CN103684525B - Signal circuit - Google Patents
Signal circuit Download PDFInfo
- Publication number
- CN103684525B CN103684525B CN201310661264.7A CN201310661264A CN103684525B CN 103684525 B CN103684525 B CN 103684525B CN 201310661264 A CN201310661264 A CN 201310661264A CN 103684525 B CN103684525 B CN 103684525B
- Authority
- CN
- China
- Prior art keywords
- transmission line
- line
- clock signal
- signal
- outermost
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention discloses a kind of signal circuit.Wherein, this circuit comprises: auxiliary transmission line, is disposed side by side on the outside of multiple signal transmssion line, for transmitting the second clock signal with clock frequency; Wherein, multiple signal transmssion line comprises the outermost transmission line adjacent with auxiliary transmission line and time outside transmission line adjacent with outermost transmission line, wherein, identical, the biased forwards or offset backward successively successively of the phase place three of the first clock signal that the phase place of second clock signal, the phase place of the first clock signal that outermost transmission line is corresponding and secondary outside transmission line are corresponding.The invention solves the technical problem that the signal quality that is positioned at the clock signal that outermost signal transmssion line transmits in the multiple signal transmssion lines be arranged side by side for transmitting with frequently multi-phase clock signal is poor.
Description
Technical field
The present invention relates to electronic circuit field, in particular to a kind of signal circuit.
Background technology
In the prior art, be positioned at outermost transmission line in the signal circuit be made up of multiple signal transmssion line and be more easily subject to inside circuit and outside interference comparatively speaking, such as, in the signal circuit such as shown in Fig. 1 (a), because any one being arranged in two middle bars transmission lines 104 and 106 all exists upper and lower two adjacent with it other signal transmssion lines, and only there are adjacent with it other signal transmssion lines in any one being arranged in outermost two bars transmission lines 102 and 108, this causes on the one hand and is positioned at the middle difference with being positioned at the capacitance profile of outermost signal transmssion line on signal transmission path, on the other hand, consider that the first clock signal that a bars transmission line transmits easily is subject to the interference of the first clock signal that other signal transmssion lines adjacent with it transmit, therefore be positioned at middle be positioned at the first clock signal that the difference of outermost signal transmssion line in signal transmission environment easily cause transmitting separately on signal transmission path suffered by impact different, enter the general performance of multiple first clock signals causing multiple signal transmssion line to export and multiple first clock signals 112 of its input, 114, 116, the difference of the general performance of 118, such as in Fig. 1 (b), first clock signal 112 of signal transmssion line 102 correspondence is relative to the first clock signal 114 of signal transmssion line 104 correspondence leading 1/4 clock cycle, 1/4 clock cycle of phase place biased forwards in other words, but the phase relation between the first clock signal exported at the output that signal transmssion line 102 and 104 is respective may can't keep above-mentioned phase relation, thus the problem causing the signal quality that is positioned at the first clock signal that outermost signal transmssion line 102 transmits poor.
For above-mentioned problem, at present effective solution is not yet proposed.
Summary of the invention
Embodiments provide a kind of signal circuit, at least to solve the poor technical problem of the signal quality that is positioned at the clock signal that outermost signal transmssion line transmits in the multiple signal transmssion lines be arranged side by side for transmitting with frequently multi-phase clock signal.
According to an aspect of the embodiment of the present invention, provide a kind of signal circuit, comprise the multiple signal transmssion lines be arranged side by side, for transmission simultaneously, there are multiple first clock signals of identical clock frequency, wherein, above-mentioned multiple signal transmssion line and above-mentioned multiple first clock signal one_to_one corresponding, wherein, foregoing circuit also comprises: auxiliary transmission line, is disposed side by side on the outside of above-mentioned multiple signal transmssion line, for transmitting the second clock signal with above-mentioned clock frequency; Wherein, above-mentioned multiple signal transmssion line comprises the outermost transmission line adjacent with above-mentioned auxiliary transmission line and time outside transmission line adjacent with above-mentioned outermost transmission line, wherein, identical, the biased forwards or offset backward successively successively of the phase place three of the first clock signal that the phase place of above-mentioned second clock signal, the phase place of the first clock signal that above-mentioned outermost transmission line is corresponding and above-mentioned outside transmission line are corresponding.
Preferably, above-mentioned auxiliary transmission line comprises the most transmitted inwards line adjacent with above-mentioned outermost transmission line and the secondary transmitted inwards line adjacent with above-mentioned most transmitted inwards line, above-mentioned, wherein, identical, the biased forwards or offset backward successively successively of the phase place of the first clock signal that the phase place of the phase place of the second clock signal that above-mentioned transmitted inwards line is corresponding, second clock signal that above-mentioned most transmitted inwards line is corresponding, the phase place of the first clock signal that above-mentioned outermost transmission line is corresponding and above-mentioned transmitted inwards line are corresponding.
Preferably, the phase difference of the second clock signal that the second clock signal that above-mentioned transmitted inwards line is corresponding is corresponding relative to above-mentioned most transmitted inwards line equals the phase difference of second clock signal corresponding to above-mentioned most transmitted inwards line first clock signal corresponding relative to above-mentioned outermost transmission line; And/or the spacing between above-mentioned transmitted inwards line and above-mentioned most transmitted inwards line equals above-mentioned most spacing between transmitted inwards line and above-mentioned outermost transmission line.
Preferably, above-mentioned time transmitted inwards line comprises the first transmission line and the second transmission line, above-mentioned most transmitted inwards line comprises the 3rd transmission line and the 4th transmission line, above-mentioned outermost transmission line comprises the 5th transmission line and the 6th transmission line, above-mentioned time outside transmission line comprises the 7th transmission line and the 8th transmission line, wherein, above-mentioned first transmission line and the 3rd transmission line are disposed side by side on the side of above-mentioned multiple signal transmssion line, wherein, above-mentioned first transmission line, above-mentioned 3rd transmission line, above-mentioned 5th transmission line, and above-mentioned 7th transmission line arranges in turn, and the second clock signal phase that above-mentioned first transmission line is corresponding, the phase place of the second clock signal that above-mentioned 3rd transmission line is corresponding, the phase place of the first clock signal that above-mentioned 5th transmission line is corresponding, and the phase place of the first clock signal corresponding to above-mentioned 7th transmission line is identical, biased forwards successively, or offset backward successively, above-mentioned second transmission line and the 4th transmission line are disposed side by side on the opposite side of above-mentioned multiple signal transmssion line, wherein, above-mentioned second transmission line, above-mentioned 4th transmission line, above-mentioned 6th transmission line, and above-mentioned 8th transmission line arranges in turn, and the second clock signal phase that above-mentioned second transmission line is corresponding, the phase place of the second clock signal that above-mentioned 4th transmission line is corresponding, the phase place of the first clock signal that above-mentioned 6th transmission line is corresponding, and the phase place of the first clock signal corresponding to above-mentioned 8th transmission line is identical, biased forwards successively, or offset backward successively.
Preferably, the phase place of each self-corresponding first clock signal of above-mentioned multiple signal transmssion line is according to from the side of above-mentioned multiple signal transmssion line to the order of opposite side successively biased forwards or offset backward.
Preferably, two of the arbitrary neighborhood in above-mentioned multiple signal transmssion line the difference of phase place between each self-corresponding first clock signal to be same preset phase poor.
Preferably, above-mentioned preset phase difference is M/N clock cycle, and wherein, M is any positive integer, and the quantity of the signal transmssion line of N included by above-mentioned multiple signal transmssion line, the above-mentioned clock cycle is corresponding with above-mentioned clock frequency.
Preferably, the spacing between two of the arbitrary neighborhood in above-mentioned multiple signal transmssion line is same preset pitch; And/or the length of each in above-mentioned multiple signal transmssion line is same preset length; And/or the shape of each in above-mentioned multiple signal transmssion line is one of following: straight line, broken line, curve.
Preferably, the phase difference of the first clock signal that the second clock signal that above-mentioned auxiliary transmission line is corresponding is corresponding relative to above-mentioned outermost transmission line equals the phase difference of the first clock signal corresponding to above-mentioned outermost transmission line first clock signal corresponding relative to above-mentioned secondary outside transmission line; And/or the spacing between above-mentioned auxiliary transmission line and above-mentioned outermost transmission line equals the spacing between above-mentioned outermost transmission line and above-mentioned outside transmission line.
Preferably, above-mentioned multiple signal transmssion line arranges on the same layer in same layer in the wafer, printed circuit board (PCB) or the same layer in ceramic circuit board; And/or each in above-mentioned multiple signal transmssion line all adopts aluminium or copper to become.
Under above-mentioned scene, because the both sides of outermost transmission line respectively exist a transmission lines, make outermost transmission line on signal transmission path, capacitance profile respectively and between the transmission line of its both sides is relative to secondary outside transmission line on signal transmission path, capacitance profile respectively and between the transmission line of its both sides is more consistent, and by second clock signal that the auxiliary transmission line in the outside being laid in outermost transmission line transmits, for outermost transmission line constructs the signal transmission environment similar with the transmission environment of secondary outside transmission line, thus in above-mentioned two, improve in multiple signal transmssion line the signal quality being positioned at the first clock signal that outermost signal transmssion line transmits, and then the technical problem that the signal quality being positioned at the clock signal that outermost signal transmssion line transmits in the multiple signal transmssion lines be arranged side by side solving for transmitting with frequently multi-phase clock signal is poor.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 (a) is the schematic diagram of a kind of signal circuit according to prior art;
Fig. 1 (b) is the schematic diagram of the signal transmitted according to a kind of signal circuit of prior art;
Fig. 2 (a) is the schematic diagram of a kind of optional signal circuit according to the embodiment of the present invention;
Fig. 2 (b) is the schematic diagram of the signal transmitted according to a kind of optional signal circuit of the embodiment of the present invention;
Fig. 3 (a) is the schematic diagram according to the optional signal circuit of the another kind of the embodiment of the present invention;
Fig. 3 (b) is the schematic diagram of the signal transmitted according to the optional signal circuit of the another kind of the embodiment of the present invention;
Fig. 4 (a) is the schematic diagram of another the optional signal circuit according to the embodiment of the present invention;
Fig. 4 (b) is the schematic diagram of the signal transmitted according to another optional signal circuit of the embodiment of the present invention;
Fig. 5 (a) is the schematic diagram of another the optional signal circuit according to the embodiment of the present invention;
Fig. 5 (b) is the schematic diagram of the signal transmitted according to another optional signal circuit of the embodiment of the present invention;
Fig. 6 (a) is the schematic diagram of another the optional signal circuit according to the embodiment of the present invention;
Fig. 6 (b) is the schematic diagram of the signal transmitted according to another optional signal circuit of the embodiment of the present invention;
Fig. 7 is the schematic diagram of another the optional signal circuit according to the embodiment of the present invention;
Fig. 8 is the schematic diagram of another the optional signal circuit according to the embodiment of the present invention.
Embodiment
Hereinafter also describe the present invention in detail with reference to accompanying drawing in conjunction with the embodiments.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
Embodiment 1
According to the embodiment of the present invention, provide a kind of signal circuit, as shown in Fig. 2 (a) He Fig. 2 (b), this circuit comprises:
1) the multiple signal transmssion lines be arranged side by side, have multiple first clock signals of identical clock frequency for transmission simultaneously, wherein, and multiple signal transmssion line and multiple first clock signal one_to_one corresponding;
2) auxiliary transmission line 202, is disposed side by side on the outside of multiple signal transmssion line, for transmitting the second clock signal 212 with this clock frequency; Wherein,
Multiple signal transmssion line comprises the outermost transmission line 102 adjacent with auxiliary transmission line 202 and time outside transmission line 104 adjacent with outermost transmission line 102, wherein, identical, the biased forwards or offset backward successively successively of the phase place three of the phase place of the phase place of second clock signal 212, the first clock signal 112 of outermost transmission line 102 correspondence and the first clock signal 114 of secondary outside transmission line 104 correspondence.
Will be clear that, one of problem to be solved by this invention is to provide circuit, transmits, wherein with the clock signal realizing having multichannel identical clock frequency simultaneously, for ease of describing, below the clock signal transmitted needed for each is designated as the first clock signal.For transmitting these the first clock signals, be similar to existing scheme, in embodiments of the present invention, the signal circuit provided can comprise the multiple signal transmssion lines be arranged side by side equally, can be such as the multiple signal transmssion lines 102 shown in Fig. 2 (a), 104 ... Deng so that one to one multiple first clock signals 112 of transmission as shown in Fig. 2 (b), 114 ... Deng.Wherein it should be noted that, below provided by the present invention in some embodiments, the clock signal corresponding with this transmission line overlying relation in the drawings shown in schematic diagram (being usually labeled as figure (b)) of the signal that a kind of overlying relation in the drawings of a transmission lines shown in schematic diagram (being usually labeled as figure (a)) of preferred signal circuit transmits with this preferred signal circuit is normally corresponding.
In existing scheme, be positioned at outermost transmission line in the signal circuit be made up of above-mentioned multiple signal transmssion line and be more easily subject to inside circuit and outside interference comparatively speaking, such as, in the signal circuit such as shown in Fig. 1 (a), because any one being arranged in two middle bars transmission lines 104 and 106 all exists upper and lower two adjacent with it other signal transmssion lines, and only there are adjacent with it other signal transmssion lines in any one being arranged in outermost two bars transmission lines 102 and 108, this causes on the one hand and is positioned at the middle difference with being positioned at the capacitance profile of outermost signal transmssion line on signal transmission path, on the other hand, consider that the first clock signal that a bars transmission line transmits easily is subject to the interference of the first clock signal that other signal transmssion lines adjacent with it transmit, therefore be positioned at middle be positioned at the first clock signal that the difference of outermost signal transmssion line in signal transmission environment easily cause transmitting separately on signal transmission path suffered by impact different, enter the general performance of multiple first clock signals causing multiple signal transmssion line to export and multiple first clock signals 112 of its input, 114, 116, the difference of the general performance of 118, such as in Fig. 1 (b), first clock signal 112 of signal transmssion line 102 correspondence is relative to the first clock signal 114 of signal transmssion line 104 correspondence leading 1/4 clock cycle, 1/4 clock cycle of phase place biased forwards in other words, but the phase relation between the first clock signal exported at the output that signal transmssion line 102 and 104 is respective may can't keep above-mentioned phase relation, thus the problem causing the signal quality that is positioned at the first clock signal that outermost signal transmssion line 102 transmits poor.
Be different from prior art, in embodiments of the present invention, at least one auxiliary transmission line can be set up on the basis of existing scheme, the outside of multiple signal transmssion line is arranged on abreast relative to multiple signal transmssion line, such as shown in Fig. 2 (a), on the basis of framework being similar to the multiple signal transmssion lines shown in Fig. 1 (a), can outside it, such as be positioned at outside outermost signal transmssion line 102 and auxiliary transmission line 202 is set abreast, wherein, it is identical with the clock frequency of the first clock signal that this auxiliary transmission line 202 can be used for transfer clock frequency, but there is another clock signal of particular kind of relationship in phase place, below for ease of statement, this another clock signal is designated as second clock signal, second clock signal 212 such as shown in Fig. 2 (b), and be designated as outermost transmission line by being positioned at outermost signal transmssion line in above-mentioned multiple signal transmssion line, a signal transmssion line adjacent inside this outermost transmission line is designated as time outside transmission line, the signal transmssion line 102 as outermost transmission line such as shown in Fig. 2 (a) and the signal transmssion line 104 as secondary outside transmission line.
In embodiments of the present invention, as shown in Fig. 2 (b), in multiple signal transmssion line, first clock signal 112 of outermost transmission line 102 correspondence leads over time the first clock signal 114 of outside transmission line 104 correspondence, correspondingly, the second clock signal 212 of auxiliary transmission line 202 correspondence leads over the first clock signal 112 of outermost transmission line 102 correspondence, and also namely the phase place three of the phase place of second clock signal 212, the phase place of the first clock signal 112 and the first clock signal 114 offsets successively backward.
Under above-mentioned scene, because the both sides of outermost transmission line 102 respectively exist a transmission lines, make outermost transmission line 102 on signal transmission path, capacitance profile respectively and between the transmission line of its both sides is relative to secondary outside transmission line 104 on signal transmission path, capacitance profile respectively and between the transmission line of its both sides is more consistent, and by second clock signal 212 that the auxiliary transmission line 202 in the outside being laid in outermost transmission line 102 transmits, for outermost transmission line 102 construct one with time similar signal transmission environment of transmission environment of outside transmission line 104, thus in above-mentioned two, improve in multiple signal transmssion line the signal quality being positioned at the first clock signal that outermost signal transmssion line transmits, and then the technical problem that the signal quality being positioned at the clock signal that outermost signal transmssion line transmits in the multiple signal transmssion lines be arranged side by side solving for transmitting with frequently multi-phase clock signal is poor.
Pass through above-described embodiment, the operation principle of technical solution of the present invention is set forth, but should not be understood as any unnecessary restriction is constituted to the present invention, such as in the some other embodiment of the present invention, first clock signal of outermost transmission line 102 correspondence also can relatively lag behind in the first clock signal of secondary outside transmission line 104 correspondence, thus the second clock signal transmitted in auxiliary transmission line 202 also should relatively lag behind in this first clock signal of outermost transmission line 102 correspondence, also be the phase place of the second clock signal that auxiliary transmission line is corresponding, the phase place of the first clock signal of outermost transmission line 102 correspondence, and the phase place three of the first clock signal of secondary outside transmission line 104 correspondence also can biased forwards successively, in addition, phase place for the first clock signal of outermost transmission line 102 correspondence is identical with time phase place of the first clock signal corresponding to outside transmission line 104, the situation of these two the first clock signal synchronizations in other words, the second clock signal transmitted in auxiliary transmission line 202 also can with these two the first clock signal synchronizations, also namely three's phase place is identical.
Particularly, in embodiments of the present invention, multiple signal transmssion line can be connected to clock signal generate equipment and one or more needs using the first clock signal as the functional unit driven between, but the present invention is not construed as limiting this, wherein, the driving force of multiple first clock signal is normally identical or close, but also can be different, the phase place of multiple first clock signal normally there are differences, but for some of them, there is the first synchronous in other words clock signal of identical phase place and adopt many circuits to carry out the execution mode transmitted respectively, the present invention is also not construed as limiting, reasonable definition can be made depending on concrete service condition by those skilled in the art.
Further, in embodiments of the present invention, auxiliary transmission line can also be multiple, such as, more auxiliary transmission line can also be laid further outside auxiliary transmission line 202 as shown in Figure 2 (a) shows, wherein, for ease of describing, most transmitted inwards line is designated as below by being positioned at of inner side relative to multiple signal transmssion line in multiple auxiliary transmission line, and the auxiliary transmission line that in multiple auxiliary transmission line, most transmitted inwards line is adjacent with this is designated as time transmitted inwards line, such as, most transmitted inwards line 202 shown in Fig. 3 (a) and time transmitted inwards line 302.
As shown in Figure 3 (b), in an embodiment of the present invention, first clock signal 112 of outermost transmission line 102 correspondence leads over time the first clock signal 114 of outside transmission line 104 correspondence, correspondingly, the second clock signal 212 of most transmitted inwards line 202 correspondence can lead over the first clock signal 112, and the second clock signal 312 of secondary transmitted inwards line 302 correspondence can lead over second clock signal 212, also namely, the phase place of second clock signal 312, second clock signal 212, first clock signal 112, first clock signal 114 offsets successively backward.
Under above-mentioned scene, on the basis setting up the optimization function mechanism of the present invention of most transmitted inwards line 202 relative to existing scheme as in the foregoing embodiment, the similar optimization function mechanism that the secondary transmitted inwards line 302 set up and the second clock signal 312 transmitted thereof apply for the second clock signal 212 that most transmitted inwards line 202 transmits can also be further advanced by, make in signals transmission, second clock signal 212 is more consistent with the signal transmission path of both the first clock signals 112, thus synchronous relative to the first clock signal 112 of second clock signal 212 can be guaranteed, leading or delayed phase relation all can be consistent to output at the input of transmission path, and then the signal quality of the first clock signal 112 that outermost transmission line 102 transmits can be guaranteed further.
Similarly, in embodiments of the present invention, except the situation described in above-described embodiment, the phase place of second clock signal 312, second clock signal 212, first clock signal 112, first clock signal 114 also can identical or biased forwards successively, this does not affect the enforcement of technical solution of the present invention and the realization of technique effect thereof, and the present invention is not construed as limiting this.
Preferably, in embodiments of the present invention, the second clock signal of secondary transmitted inwards line 302 correspondence can equal the phase difference of second clock signal relative to the first clock signal of outermost transmission line 102 correspondence of most transmitted inwards line 202 correspondence relative to the phase difference of the second clock signal of most transmitted inwards line 202 correspondence, in addition, spacing between secondary transmitted inwards line 302 and most transmitted inwards line 202 also can equal most spacing between transmitted inwards line 202 and outermost transmission line 102, with to be most transmitted inwards line 202 further with outermost transmission line 102 construct with time outside the more consistent transmission environment of transmission line 104, thus guarantee the signal quality of the first clock signal 112 that outermost transmission line 102 transmits further.
On the other hand, as shown in Figure 4 (a), in embodiments of the present invention, auxiliary transmission line can be laid in the both sides of multiple signal transmssion line simultaneously, wherein, for ease of describing, two transmitted inwards lines up and down in Fig. 4 (a) can be designated as the first transmission line 401 and the second transmission line 402 respectively, upper and lower two bars of most transmitted inwards lines are designated as the 3rd transmission line 403 and the 4th transmission line 404 respectively, upper and lower two articles of outermost transmission lines are designated as the 5th transmission line 405 and the 6th transmission line 406 respectively, upper and lower two articles outside transmission lines are designated as the 7th transmission line 407 and the 8th transmission line 408 respectively.
As shown in Figure 4 (a), in embodiments of the present invention, first transmission line 401 and the 3rd transmission line 403 can be disposed side by side on the side of multiple signal transmssion line, wherein, first transmission line 401, 3rd transmission line 403, 5th transmission line 405, and the 7th transmission line 407 arrange in turn, and second clock signal 411 phase place of the first transmission line 401 correspondence, the phase place of the second clock signal 413 of the 3rd transmission line 403 correspondence, the phase place of the first clock signal 415 of the 5th transmission line 405 correspondence, and the 7th the phase place of the first clock signal 417 of transmission line 407 correspondence identical, biased forwards successively, or offset backward successively, second transmission line 402 and the 4th transmission line 404 can be disposed side by side on the opposite side of multiple signal transmssion line, wherein, second transmission line 402, 4th transmission line 404, 6th transmission line 406, and the 8th transmission line 408 arrange in turn, and second clock signal 412 phase place of the second transmission line 402 correspondence, the phase place of the second clock signal 414 of the 4th transmission line 404 correspondence, the phase place of the first clock signal 416 of the 6th transmission line 406 correspondence, and the 8th the phase place of the first clock signal 418 of transmission line 408 correspondence identical, biased forwards successively, or offset backward successively.
By the way, be similar to the optimization function mechanism described in previous embodiment, the outermost transmission line laying respectively at multiple signal transmssion line both sides can be guaranteed, also the signal quality of i.e. the first clock signal 415 of transmitting separately of the 5th transmission line 405 and the 6th transmission line 406 and the first clock signal 416.
On basis described above, for the signal quality of the first clock signal that each raising in multiple signal transmssion line is transmitted, conforming optimization can be carried out further to the signal transmission path of each in multiple signal transmssion line and signal transmission environment, particularly, in embodiments of the present invention, the phase place of each self-corresponding first clock signal of multiple signal transmssion line is according to from the side of multiple signal transmssion line to the order of opposite side successively biased forwards or offset backward.Wherein, preferably, two of arbitrary neighborhood in multiple signal transmssion line the difference of phase place between each self-corresponding first clock signal can be consistent, such as can be a certain preset phase poor, wherein, this preset phase difference can be M/N clock cycle, wherein, M is any positive integer, and the quantity of the signal transmssion line of N included by multiple signal transmssion line, this clock cycle is corresponding with preceding clock frequency.
More preferably, in embodiments of the present invention, spacing between two of arbitrary neighborhood in above-mentioned multiple signal transmssion line can be consistent, such as can be a certain preset pitch, thus make each in multiple signal transmssion line more consistent with the electric capacity between adjacent two signal transmssion lines, in addition, the length of each in multiple signal transmssion line also can be consistent, such as can be a certain preset length, thus make multiple signal transmssion line resistance value separately more consistent, and then the loss of multiple first clock signals making it transmit is consistent substantially.It should be noted that, the present invention is to the shape of the plurality of signal transmssion line and be not construed as limiting, such as it can be straight line, also can be broken line as shown in Figure 7 or curve, generally speaking, can determine according to concrete cabling requirement, but under this scene, the shape of auxiliary transmission line should be consistent with the shape of signal transmssion line.
A more specifically embodiment of the present invention is provided, in the signal circuit provided by this embodiment below with reference to Fig. 5 (a) and Fig. 5 (b):
Multiple signal transmssion line comprises: as the 5th transmission line 405 and the 6th transmission line 406 of outermost transmission line, as the 7th transmission line 407 and the 8th transmission line 408 of secondary outside transmission line, and the signal transmssion line 501,502,503 and 504 be positioned in the middle of multiple signal transmssion line, wherein
The 5th transmission line 405 that in Fig. 5 (a), the plurality of signal transmssion line from top to bottom arranges, 7th transmission line 407, signal transmssion line 501, signal transmssion line 502, signal transmssion line 503, signal transmssion line 504, 8th transmission line 408, and the 6th transmission line 406 correspond respectively to multiple first clock signals 415 of the same frequency leggy that this circuit shown in Fig. 5 (b) will transmit, 417, 511, 512, 513, 514, 418 and 416, and the plurality of first clock signal 415, 417, 511, 512, 513, 514, the phase place of 418 and 416 offsets 1/8 clock cycle successively backward,
Multiple auxiliary transmission line comprises: as the first transmission line 401 and the second transmission line 402 of secondary transmitted inwards line, and as the 3rd transmission line 403 of most transmitted inwards line and the 4th transmission line 404, wherein,
The first transmission line 401 that in Fig. 5 (a), the plurality of auxiliary transmission line from top to bottom arranges, the 3rd transmission line 403, the 4th transmission line 404 and the second transmission line 402 correspond respectively to the second clock signal 411,413,414 and 412 shown in Fig. 5 (b), and second clock signal 411,413,414 and 412 can be respectively the copy signal of the first clock signal 418,416,415 and 417;
Wherein, the spacing comprised between two adjacent in the transmission line from top to bottom laid as shown in Figure 5 (a) of multiple signal transmssion line and multiple auxiliary transmission line is same preset pitch, and the identical length of these transmission lines is same.
Under above-mentioned scene, because each in multiple signal transmssion line is all identical with the adjacent spacing up and down between two other signal transmssion lines, and the phase relation of the first clock signal that its first clock signal transmitted is transmitted relative to adjacent two other signal transmssion lines is up and down all consistent, signal transmission path and the signal transmission environment thereof of each the first clock signal also namely transmitted in this signal circuit are all identical, thus can guarantee the signal quality of transmitted multiple first clock signals.
In the above-described embodiments, the phase difference between two adjacent in multiple signal transmssion line the first clock signals transmitted, also namely above-mentioned preset phase difference is 1/8 clock cycle, wherein, M is 1, N is 8, equals the quantity of the signal transmssion line included by multiple signal transmssion line.In some embodiments of the invention, M and N also can elect other numerical value as, such as composition graphs 6(a) and Fig. 6 (b) give M be 3 and N is 4 time situation, in this embodiment, multiple signal transmssion line may be used for transmission four clock signal, wherein, 5th transmission line 405, 7th transmission line 407, 8th transmission line 408, and the 6th transmission line 406 corresponding first clock signal 415 respectively, 417, 418 and 416, and the first clock signal 415, 417, 418 and 416 offset 3/4 clock cycle successively backward, first transmission line 401, 3rd transmission line 403, 4th transmission line 404, and the second transmission line 402 corresponding second clock signal 411 respectively, 413, 414 and 412, the plurality of second clock signal 411, 413, 414 and 412 can be respectively the first clock signal 418, 416, the copy signal of 415 and 417.
Especially, for above-mentioned multiple signal transmssion line for 2 and its first clock signal transmitted differs the situation of half clock cycle, signal transmssion line 802 and 804 in signal circuit such as shown in Fig. 8, the second clock signal that the auxiliary transmission circuit 806 and 808 set up transmits also can be respectively the copy signal of the first clock signal transmitted by signal transmssion line 804 and 802.Under this scene, for auxiliary transmission line 806, signal transmssion line 802 is outermost transmission line, signal transmssion line 804 is time outside transmission line, for auxiliary transmission line 808, signal transmssion line 804 is outermost transmission line, and signal transmssion line 802 is time outside transmission line.
Known from the above description, preferably, in embodiments of the present invention, the phase difference of the first clock signal that the second clock signal that auxiliary transmission line is corresponding is corresponding relative to outermost transmission line can equal the phase difference of the first clock signal corresponding to outermost transmission line first clock signal corresponding relative to secondary outside transmission line, in addition, the spacing between auxiliary transmission line and outermost transmission line also can equal the spacing between outermost transmission line and secondary outside transmission line.
In addition, as feasible application more of the present invention, in embodiments of the present invention, multiple signal transmssion line both can have been laid on same layer in the wafer, also can arrange on same layer in the printed circuit boards, can also be arranged on the same layer in ceramic circuit board, wherein, above-mentioned wafer, printed circuit board (PCB) and ceramic circuit board both can be single layer structure, also can be sandwich construction, and the material that above-mentioned multiple signal transmssion line adopts both can be aluminium, also can be copper, can also be other feasible metals for transmitting above-mentioned clock signal or conductor or the semi-conducting material such as nonmetal, the present invention is not construed as limiting this.
The invention provides a kind of preferred embodiment to make an explanation to the present invention further, but it should be noted that the preferred embodiment is just in order to better describe the present invention, does not form and limits improperly the present invention.
As can be seen from the above description, the present invention at least achieves following technique effect:
1) by the second clock signal of the auxiliary transmission line and transmission thereof that are arranged on the outside of outermost transmission line, for outermost transmission line constructs the signal transmission environment similar with the transmission environment of secondary outside transmission line, thus improve the signal quality being positioned at the first clock signal that outermost signal transmssion line transmits in multiple signal transmssion line;
2) by being arranged on the second clock signal of secondary transmitted inwards line in the auxiliary transmission line in the outside of outermost transmission line and transmission thereof, for the most transmitted inwards line in auxiliary transmission line constructs the signal transmission environment similar with the transmission environment of outermost transmission line, improve the signal quality of the second clock signal that most transmitted inwards line transmits, thus further increasing the signal quality of the first clock signal that outermost transmission line transmits.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a signal circuit, comprises the multiple signal transmssion lines be arranged side by side, and has multiple first clock signals of identical clock frequency for transmission simultaneously, wherein, described multiple signal transmssion line and described multiple first clock signal one_to_one corresponding, it is characterized in that, described circuit also comprises:
Auxiliary transmission line, is disposed side by side on the outside of described multiple signal transmssion line, for transmitting the second clock signal with described clock frequency; Wherein,
Described multiple signal transmssion line comprises the outermost transmission line adjacent with described auxiliary transmission line and time outside transmission line adjacent with described outermost transmission line, wherein, identical, the biased forwards or offset backward successively successively of the phase place three of the first clock signal that the phase place of described second clock signal, the phase place of the first clock signal that described outermost transmission line is corresponding and described outside transmission line are corresponding;
Wherein, the phase difference of the first clock signal that the second clock signal that described auxiliary transmission line is corresponding is corresponding relative to described outermost transmission line equals the phase difference of the first clock signal corresponding to described outermost transmission line first clock signal corresponding relative to described secondary outside transmission line.
2. circuit according to claim 1, is characterized in that, described auxiliary transmission line comprises the most transmitted inwards line adjacent with described outermost transmission line and the secondary transmitted inwards line adjacent with described most transmitted inwards line, described in, wherein,
The phase place of the phase place of the phase place of the phase place of the second clock signal that described transmitted inwards line is corresponding, second clock signal that described most transmitted inwards line is corresponding, the first clock signal that described outermost transmission line is corresponding and the first clock signal corresponding to described transmitted inwards line is identical, biased forwards or offset backward successively successively.
3. circuit according to claim 2, is characterized in that,
The phase difference of the first clock signal that the second clock signal that described in the phase difference of the second clock signal that the second clock signal that described transmitted inwards line is corresponding is corresponding relative to described most transmitted inwards line equals, most transmitted inwards line is corresponding is corresponding relative to described outermost transmission line; And/or,
Most spacing between transmitted inwards line and described outermost transmission line described in spacing between described transmitted inwards line and described most transmitted inwards line equals.
4. circuit according to claim 2, it is characterized in that, described time transmitted inwards line comprises the first transmission line and the second transmission line, described most transmitted inwards line comprises the 3rd transmission line and the 4th transmission line, described outermost transmission line comprises the 5th transmission line and the 6th transmission line, described time outside transmission line comprises the 7th transmission line and the 8th transmission line, wherein
Described first transmission line and the 3rd transmission line are disposed side by side on the side of described multiple signal transmssion line, wherein, described first transmission line, described 3rd transmission line, described 5th transmission line and described 7th transmission line arrange in turn, and the phase place of the phase place of the phase place of second clock signal phase corresponding to described first transmission line, second clock signal that described 3rd transmission line is corresponding, the first clock signal that described 5th transmission line is corresponding and the first clock signal corresponding to described 7th transmission line is identical, biased forwards or offset backward successively successively;
Described second transmission line and the 4th transmission line are disposed side by side on the opposite side of described multiple signal transmssion line, wherein, described second transmission line, described 4th transmission line, described 6th transmission line, and described 8th transmission line arranges in turn, and the second clock signal phase that described second transmission line is corresponding, the phase place of the second clock signal that described 4th transmission line is corresponding, the phase place of the first clock signal that described 6th transmission line is corresponding, and the phase place of the first clock signal corresponding to described 8th transmission line is identical, biased forwards successively, or offset backward successively.
5. circuit according to any one of claim 1 to 4, it is characterized in that, the phase place of each self-corresponding first clock signal of described multiple signal transmssion line is according to from the side of described multiple signal transmssion line to the order of opposite side successively biased forwards or offset backward.
6. circuit according to claim 5, is characterized in that, two of the arbitrary neighborhood in described multiple signal transmssion line the difference of phase place between each self-corresponding first clock signal to be same preset phase poor.
7. circuit according to claim 6, is characterized in that, described preset phase difference is M/N clock cycle, wherein, M is any positive integer, and the quantity of the signal transmssion line of N included by described multiple signal transmssion line, the described clock cycle is corresponding with described clock frequency.
8. circuit according to claim 5, is characterized in that,
Spacing between two of arbitrary neighborhood in described multiple signal transmssion line is same preset pitch; And/or,
The length of each in described multiple signal transmssion line is same preset length; And/or,
The shape of each in described multiple signal transmssion line is one of following: straight line, broken line, curve.
9. circuit according to any one of claim 1 to 4, is characterized in that,
Spacing between described auxiliary transmission line and described outermost transmission line equals the spacing between described outermost transmission line and described outside transmission line.
10. circuit according to any one of claim 1 to 4, is characterized in that,
Described multiple signal transmssion line arranges on the same layer in same layer in the wafer, printed circuit board (PCB) or the same layer in ceramic circuit board; And/or,
Each in described multiple signal transmssion line all adopts aluminium or copper to become.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310661264.7A CN103684525B (en) | 2013-12-06 | 2013-12-06 | Signal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310661264.7A CN103684525B (en) | 2013-12-06 | 2013-12-06 | Signal circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103684525A CN103684525A (en) | 2014-03-26 |
| CN103684525B true CN103684525B (en) | 2016-02-03 |
Family
ID=50320960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310661264.7A Active CN103684525B (en) | 2013-12-06 | 2013-12-06 | Signal circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103684525B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580278B (en) * | 2020-12-07 | 2023-06-09 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790905A (en) * | 2005-12-16 | 2006-06-21 | 威盛电子股份有限公司 | Transmission circuit and associated method |
| JP2007049438A (en) * | 2005-08-10 | 2007-02-22 | Renesas Technology Corp | Multiphase clock signal transmission circuit |
| CN101226511A (en) * | 2007-01-18 | 2008-07-23 | 鸿富锦精密工业（深圳）有限公司 | Signal transmission structure |
| CN101499809A (en) * | 2009-02-16 | 2009-08-05 | 北京星网锐捷网络技术有限公司 | Receiving chip circuit and communication system |
| CN201532809U (en) * | 2009-11-12 | 2010-07-21 | 宝鸡烽火电线电缆有限责任公司 | High-strength anti-interference telephone signal transmission line |
| JP2010226626A (en) * | 2009-03-25 | 2010-10-07 | Anritsu Corp | Multiplexer |
| WO2010145274A1 (en) * | 2009-10-27 | 2010-12-23 | 中兴通讯股份有限公司 | Mobile terminal and clutter signal suppressing circuit thereof |
| CN202748758U (en) * | 2012-09-07 | 2013-02-20 | 京东方科技集团股份有限公司 | Touch liquid crystal display (LCD) device, touch LCD panel and color film substrate |
-
2013
- 2013-12-06 CN CN201310661264.7A patent/CN103684525B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007049438A (en) * | 2005-08-10 | 2007-02-22 | Renesas Technology Corp | Multiphase clock signal transmission circuit |
| CN1790905A (en) * | 2005-12-16 | 2006-06-21 | 威盛电子股份有限公司 | Transmission circuit and associated method |
| CN101226511A (en) * | 2007-01-18 | 2008-07-23 | 鸿富锦精密工业（深圳）有限公司 | Signal transmission structure |
| CN101499809A (en) * | 2009-02-16 | 2009-08-05 | 北京星网锐捷网络技术有限公司 | Receiving chip circuit and communication system |
| JP2010226626A (en) * | 2009-03-25 | 2010-10-07 | Anritsu Corp | Multiplexer |
| WO2010145274A1 (en) * | 2009-10-27 | 2010-12-23 | 中兴通讯股份有限公司 | Mobile terminal and clutter signal suppressing circuit thereof |
| CN201532809U (en) * | 2009-11-12 | 2010-07-21 | 宝鸡烽火电线电缆有限责任公司 | High-strength anti-interference telephone signal transmission line |
| CN202748758U (en) * | 2012-09-07 | 2013-02-20 | 京东方科技集团股份有限公司 | Touch liquid crystal display (LCD) device, touch LCD panel and color film substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103684525A (en) | 2014-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102369581B (en) | Flexible cable and transmission system | |
| CN101378618B (en) | Printed circuit board | |
| CN107241857B (en) | A kind of printed circuit board and communication equipment | |
| CN106293168B (en) | Touch device and electrode lead setting method based on touch device | |
| CN102238810A (en) | Printed circuit board and wiring method thereof | |
| CN104244574A (en) | Pcb signal wiring structure and electronic product interface | |
| US10141250B2 (en) | Chip and electronic device | |
| CN102083277A (en) | Printed circuit board and wiring method thereof | |
| CN103188861A (en) | Printed circuit board laid with differential pairs | |
| CN106375010B (en) | A kind of fiber optic local area network CAN bus control device and networking | |
| CN105447254B (en) | A kind of chip signal transmission control unit, system and method | |
| CN107957967A (en) | Configuration through high speed serialization link | |
| CN103684525B (en) | Signal circuit | |
| CN104752851B (en) | A kind of system | |
| TWI559695B (en) | Circuit interconnect with equalized crosstalk | |
| CN101272141B (en) | Staggered logic array block architecture | |
| CN104765169A (en) | Detection circuit of array substrate and array substrate | |
| CN101841734A (en) | Back plate and back plate communication system | |
| CN105027518B (en) | Interconnection system for communication equipment | |
| US9337521B2 (en) | Crosstalk reduction in signal lines by crosstalk introduction | |
| CN102196656B (en) | Circuit layout method and layout circuit using same | |
| CN217363062U (en) | Single feeder line double MIMO 5G frequency shift system | |
| KR20100037387A (en) | Memory moduel and topology of circuit board | |
| US10566306B2 (en) | Wiring structure of glass substrate, glass substrate and display device | |
| CN106604520B (en) | Printed circuit board arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |