JP2007049438A - Multiphase clock signal transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a multiphase clock signal transmission circuit which is easy to design a wiring circuit of transmission lines for multiphase clock signals, and allows the wiring area to be more reduced. <P>SOLUTION: The multiphase clock signal transmission circuit for transmitting clock signals (CK1-CK5) of n phases (n is a natural number 2 or greater) comprises a first to n-th buffers (3a-3e), a first to n-th wirings (P1-P5), a first and second added buffers (4a, 4e), and a first and second added wirings (G5, G1). The first to n-th wirings (P1-P5) are laid adjacently parallel in circuits in the ascending or descending order of the ordinal number from the first to n-th, the first added wiring (G5) is laid adjacently to the n-th wiring (P5) parallel in a circuit at the opposite position to the (n-1)-th wiring (P4), and the second added wiring (G1) is laid adjacently to the first wiring (P1) parallel in a circuit at the opposite position to the second wiring (P2). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multi-phase clock signal transmission circuit formed on a semiconductor integrated circuit for transmitting multi-phase clock signals out of phase.

  Patent Document 1 below shows an example of wiring capable of transmitting a multiphase clock signal having an equal phase difference in a small area while suppressing signal deterioration due to coupling capacitance between clock wirings (paragraph 0015). To paragraph 0021).

JP 2002-43905 A

  In the above-mentioned Patent Document 1, as described in the paragraph 0020, a signal line of “a pair combination in which one signal transitions only during the voltage period of Lo each other” is adjacent. (For example, "S'1 / S'6" and "S'1 / S'5 / S'9" pairs), which reduces signal degradation due to coupling capacitance and transmits in a small area Configured possible wiring.

  However, in the method of the above-mentioned Patent Document 1, signal pairs having a phase difference in which activation periods hardly overlap are extracted and selected, such as signal S′1 and signal S′6, and they are adjacent to each other. It was necessary to arrange the circuit, and complicated work was necessary in designing the circuit.

  Further, as shown in FIG. 8b and FIG. 10a of Patent Document 1, a grounded wiring is introduced between the signal pairs, and the reduction of the wiring area is not necessarily sufficient.

  The present invention has been made in view of the above circumstances, and is intended to realize a multiphase clock signal transmission circuit in which the circuit design of the wiring of the multiphase clock signal transmission path is easy and the wiring area can be further reduced. is there.

  The present invention provides a first input terminal having an input terminal for receiving first to nth n-phase clock signals having different phases by (360 / n) degrees (n is a natural number of 2 or more) and an output terminal. A first n-th buffer; first to n-th wirings connected to the output terminals of the first to n-th buffers; an input terminal for receiving the first clock signal; and an output terminal. A second additional buffer having an additional buffer, an input terminal for receiving the nth clock signal, and an output terminal; a first additional wiring connected to the output terminal of the first additional buffer; A second additional wiring connected to the output terminal of the additional buffer, and the first to nth wirings are adjacently arranged in parallel in order of increasing or decreasing the ordinal number from the first to the nth. The first additional wiring is arranged in the (nth (n 1) A circuit is arranged in parallel and adjacent to the nth wiring at a position opposite to the wiring, and the second additional wiring is parallel to and adjacent to the first wiring at a position opposite to the second wiring. The multi-phase clock signal transmission circuit is arranged in the circuit.

  According to the present invention, in addition to the first to n-th buffers and the first to n-th wirings, the first and second additional buffers and the first and second additional wirings are provided. The wirings are arranged in parallel adjacently in order of increasing or decreasing the ordinal numbers from the first to the nth, and the first additional wiring is the nth wiring at a position opposite to the (n−1) th wiring. The second additional wiring is arranged in parallel adjacent to the first wiring at a position opposite to the second wiring. Therefore, in any of the first to n-th wirings, a wiring with a smaller ordinal number is arranged next to one, and a wiring with a larger ordinal number is arranged next to the other, so that the clock signal on the adjacent wiring is The influence on the clock signal on the wiring can be made equal. Thereby, it is possible to realize a multi-phase clock signal transmission circuit capable of transmitting an n-phase clock signal while suppressing signal deterioration due to coupling capacitance between clock wirings. In the present invention, the first to nth wirings are arranged in parallel adjacent to each other in order of increasing or decreasing the ordinal number, and the first and second additional wirings are adjacent to the nth and first wirings in parallel. Since it is only necessary to arrange the circuit, circuit design of the wiring of the transmission path of the multiphase clock signal becomes easy. Further, since only the first and second additional wirings need be added, a multiphase clock signal transmission circuit capable of further reducing the wiring area can be realized.

<Embodiment 1>
The present embodiment is a multi-phase clock signal transmission circuit that transmits an n-phase (n is a natural number of 2 or more) clock signal, in addition to the first to n-th buffers and the first to n-th wirings. , First and second additional buffers, and first and second additional wirings, and the first to nth wirings are adjacently arranged in parallel in order of increasing or decreasing the ordinal numbers from the first to the nth. The first additional wiring is arranged in parallel with and adjacent to the nth wiring at a position opposite to the (n-1) th wiring, and the second additional wiring is disposed at a position opposite to the second wiring. A circuit is arranged in parallel adjacent to the first wiring.

  FIG. 1 is a circuit diagram of a multiphase clock signal transmission circuit according to the present embodiment. As shown in FIG. 1, the multi-phase clock signal transmission circuit includes first to n-th n-phase multi-phase clock signals having different phases by (360 / n) degrees (in this embodiment, n = 5) A clock driver 1 that performs waveform shaping of CK1 to CK5, and an output from the clock driver 1 that is used as a clock use block (not shown) at another location on the semiconductor integrated circuit in which the clock driver 1 is formed. And a wiring part 2 for transmission.

  The clock driver 1 includes two-input NAND circuits 2a to 2e, first to fifth inversion buffers 3a to 3e, a first additional inversion buffer 4a, a second additional inversion buffer 4e, and third to fifth additional inversion buffers 4b to 4b. 4d. An enable signal EN for controlling whether or not the clock driver 1 can operate is supplied to one input terminal of each of the two-input NAND circuits 2a to 2e. Further, at the other input terminals of the two-input NAND circuits 2a to 2e, first to fifth five-phase clock signals CK1 generated by a PLL (Phase Locked Loop) circuit (not shown) or the like are provided. ~ CK5 are given respectively. The clock signals CK1 to CK5 have different phases by (360/5) = 72 degrees.

  The outputs of the two-input NAND circuits 2a to 2e are given to the input terminals of the first to fifth inversion buffers 3a to 3e, respectively. The output of the two-input NAND circuit 2a is also given to the input terminal of the first additional inverting buffer 4a, and the output of the two-input NAND circuit 2e is also given to the input terminal of the second additional inverting buffer 4e. That is, the input terminal of the first additional inverting buffer 4a is connected to the input terminal of the first inverting buffer 3a, and the input terminal of the second additional inverting buffer 4e is connected to the input terminal of the fifth inverting buffer 3e.

  The input terminals of the third to fifth additional inverting buffers 4b to 4d are also connected to the input terminals of the second to fourth inverting buffers 3b to 3d. However, the third to fifth additional inversion buffers 4b to 4d function as dummy first to third load elements that do not output any signal. The drive capacities of the first to fifth inversion buffers 3a to 3e, the first additional inversion buffer 4a, the second additional inversion buffer 4e, and the third to fifth additional inversion buffers 4b to 4d are all equal. Designed. In addition, the length, thickness, and resistivity of each wiring between each two-input NAND circuit 2a to 2e and each inverting buffer 3a to 3e, 4a to 4e are determined with respect to each two-input NAND circuit 2a to 2e and each inverting buffer. The delay times between 3a to 3e and 4a to 4e are designed to be substantially equal to each other.

  The wiring unit 2 includes first to fifth wirings P1 to P5 connected to output terminals of the first to fifth inversion buffers 3a to 3e, and a first additional terminal connected to the output terminal of the first additional inversion buffer 4a. A wiring G5 and a second additional wiring G1 connected to the output terminal of the second additional inversion buffer 4e are provided.

  In the wiring part 2, the first to fifth wirings P1 to P5 are adjacently arranged in parallel in the order of increasing the ordinal numbers from the first to the fifth. The first additional wiring G5 is arranged in parallel with the fifth wiring P5 at a position opposite to the fourth wiring P4, and the second additional wiring G1 is on the side opposite to the second wiring P2. The circuit is arranged in parallel adjacent to the first wiring P1 at the position.

  The first to fifth wirings P1 to P5, the first additional wiring G5, and the second additional wiring G1 are all wirings having substantially the same thickness, length, and resistivity on the semiconductor integrated circuit. In addition, the intervals between the wirings have almost the same dimensions. The lengths, thicknesses, and resistivity of the wirings between the inverting buffers 3a to 3e, 4a, and 4e and the wirings P1 to P5, G1, and G5 are also the same as those of the inverting buffers 3a to 3e, 4a, and 4e. The delay times between the wirings P1 to P5, G1, and G5 are designed to be substantially equal to each other.

  At the terminal portions of the first to fifth wirings P1 to P5, the transmitted clock signals are output as signals P1R to P5R to a clock use block (not shown), and the first additional wiring G5 and the second additional wiring G1 In the termination unit, the transmitted clock signal is output as signals G5R and G1R.

  FIG. 2 is a diagram illustrating clock signals applied to the first to fifth wirings P1 to P5. As shown in FIG. 2, clock signals CK1 to CK5 whose phases are delayed by 72 degrees and make a round of 360 degrees pass through the two-input NAND circuits 2a to 2e and the first to fifth inversion buffers 3a to 3e, respectively. The data is transmitted to the first to fifth wirings P1 to P5.

  The operation of the multiphase clock signal transmission circuit according to the present embodiment will be described below. First, when the clock driver is used, the enable signal EN is set to a high level. Thus, the two-input NAND circuits 2a to 2e function as inverters with respect to the clock signals CK1 to CK5. Then, the clock signals CK1 to CK5 that have passed through the two-input NAND circuits 2a to 2e are inverted again by the first to fifth inversion buffers 3a to 3e and output to the first to fifth wirings P1 to P5, respectively.

  Here, the phase of the clock signal CK2 transmitted by the second wiring P2 is shifted by ± 72 degrees from the phase of each of the clock signals CK1 and CK3 transmitted by the adjacent first wiring P1 and third wiring P3. Yes. The phase of the clock signal CK3 transmitted through the third wiring P3 is also shifted by ± 72 degrees from the phase of each of the adjacent clock signals CK2 and CK4, and the phase of the clock signal CK4 transmitted through the fourth wiring P4. However, the phase of the clock signals CK3 and CK5 on both sides is shifted by ± 72 degrees.

  Furthermore, according to the present invention, the phase of the clock signal CK1 transmitted by the first wiring P1 is also different from the phases of the clock signals CK5 and CK2 transmitted by the second additional wiring G1 and the second wiring P2 adjacent to both of them. ± 72 degrees. Further, the phase of the clock signal CK5 transmitted by the fifth wiring P5 is also shifted by ± 72 degrees from the phase of each of the clock signals CK4 and CK1 transmitted by the adjacent fourth wiring P4 and the first additional wiring G5. Yes.

  That is, in any of the first to fifth wirings P1 to P5, a wiring with a small ordinal number is arranged next to one, and a wiring with a large ordinal number is arranged next to the other, and the clocks on the adjacent wirings are arranged. The influence of the signal on the clock signal on each wiring can be made equal. Thereby, it is possible to realize a multi-phase clock signal transmission circuit capable of transmitting an n-phase clock signal while suppressing signal deterioration due to coupling capacitance between clock wirings. In the present embodiment, the first to fifth wirings P1 to P5 are adjacently arranged in parallel in order of increasing ordinal numbers, and the first and second additional wirings G5 and G1 are connected to the fifth and first wirings. Since it is only necessary to arrange the circuits adjacent to P5 and P1 in parallel, the circuit design of the wiring of the transmission path of the multiphase clock signal becomes easy. Moreover, since only the first and second additional wirings G5 and G1 need be added, a multiphase clock signal transmission circuit capable of further reducing the wiring area can be realized.

  As a result, the number of additional guard wirings required to transmit an n-phase multiphase clock signal with one period shifted into n equal parts is made two, the first and second additional wirings G5 and G1. The number of wires introduced between the signal pairs shown in FIG. 8b and FIG. 10a of the above-mentioned Patent Document 1 can be reduced. Therefore, the wiring area can be reduced. In particular, when a multiphase clock signal transmission circuit is formed in a semiconductor integrated circuit, a clock wiring and its guard wiring are formed in one upper layer and one lower layer in the semiconductor multi-layer wiring forming step, during clock operation. Since a fixed potential wiring in which the potential is fixed to the ground potential or the like is necessary, this contributes to a reduction in the area of such a fixed potential wiring.

  In the above description, the case of n = 5 (5-phase clock) is shown as an example. However, the value of n may be other than that. Further, in the circuit of FIG. 1, the first to fifth wirings P1 to P5 are arranged in parallel adjacently in order of increasing ordinal numbers from top to bottom. The fifth wirings P1 to P5 may be arranged in parallel in the order of decreasing ordinal numbers.

  In the circuit of FIG. 1, the circuit example having the enable signal EN for controlling the operation of the clock driver 1 is shown, but the enable signal EN and the two-input NAND circuits 2a to 2e are omitted and the clock signals CK1 to CK5 are omitted. A circuit configuration may be employed in which the signal is directly input to the input terminals of the first to fifth inversion buffers 3a to 3e. Further, the input clock signals CK1 to CK5 and the clock signals in the first to fifth wirings P1 to P5 may be in phase or in reverse phase.

  Therefore, generally speaking, the multi-layer clock signal transmission circuit according to the present embodiment will be described in terms of (360 / n) degrees (n is a natural number greater than or equal to 2) degrees from the first to the nth n. 1st to nth buffers (corresponding to first to fifth inversion buffers 3a to 3e in FIG. 1) each having an input terminal for receiving a phase clock signal (corresponding to clock signals CK1 to CK5 in FIG. 1) and an output terminal. ), First to nth wirings (corresponding to the first to fifth wirings P1 to P5 in FIG. 1) connected to the output terminals of the first to nth buffers, and a first clock signal (FIG. 1). A first additional buffer (corresponding to the first additional inverting buffer 4a in FIG. 1) having an input terminal receiving the clock signal CK1 and an output terminal, and an nth clock signal (clock signal CK5 in FIG. 1). Equivalent to the input end and the output A second additional buffer having an end (corresponding to the second additional inverting buffer 4e in FIG. 1) and a first additional wiring connected to the output terminal of the first additional buffer (corresponding to the first additional wiring G5 in FIG. 1) And a second additional wiring (corresponding to the second additional wiring G1 in FIG. 1) connected to the output terminal of the second additional buffer, and the first to nth wirings having the ordinal numbers from the first to the nth. In the order of increase or decrease, the circuits are arranged adjacently in parallel, and the first additional wiring is arranged in parallel adjacent to the nth wiring at a position opposite to the (n−1) th wiring, and the second The additional wiring may be arranged in parallel adjacent to the first wiring at a position opposite to the second wiring.

  When the clock signal has five or more phases, the sum of the clock signal vectors on both sides of the clock signal of interest is positive with respect to the vector of the clock signal of interest (enhance the vector of the clock signal of interest). For this reason, the signal attenuation is less than when a wiring fixed to the ground potential is arranged between the clock signal lines. For this reason, the dullness of the signals P1R to P5R at the terminal end of each wiring is reduced, and a reduction in jitter can be expected. This will be described with reference to FIGS.

  FIG. 3 is a circuit diagram used for the simulation of the multiphase clock signal transmission circuit according to the present embodiment, FIG. 4 is a circuit simulation result of the present embodiment, and FIG. 5 is a circuit simulation result of the conventional circuit.

  In FIG. 3, the upper seven stages of inverting buffers (corresponding to the second additional inverting buffer 4e, the first to fifth inverting buffers 3a to 3e and the first additional inverting buffer 4a in FIG. 1) and their connection wirings are provided. The simulation circuit, the lower five-stage inversion buffers (corresponding to the first to fifth inversion buffers 3a to 3e in FIG. 1) and the connection wiring thereof are simulation circuits of the conventional circuit.

  Note that the operating characteristics such as the delay of the inverting buffer in FIG. The clock signal is a square wave of 200 MHz (one cycle is 5 nsec), and the phase of the signal is most advanced in the second additional wiring G1 on the top. The signal in the second first wiring P1 from the top is 72 degrees behind the signal in the second additional wiring G1, and the signal in the third second wiring P2 from the top is 72 degrees behind the signal in the first wiring P1. The signal in the fourth wiring P3 fourth from the top is 72 degrees behind the signal in the second wiring P2, and the signal in the fourth wiring P4 fifth from the top is 72 degrees behind the signal in the third wiring P3. The signal in the sixth wiring P5 from the top is 72 degrees behind the signal in the fourth wiring P4, and the signal in the seventh additional wiring G5 from the top is 72 degrees in the signal from the fifth wiring P5. It is late.

  Further, the signal in the uppermost first wiring O1 in the lower five stages has the same waveform and the same phase as the signal in the first wiring P1 in the upper seven stages, and from the upper in the lower five stages. The signal in the second second wiring O1 has the same waveform and the same phase as the signal in the second wiring P2 in the upper seven stages, and the signal in the third third wiring O3 from the top in the lower five stages is the upper side. The same waveform and phase as the signal in the third wiring P3 in the seven stages, and the signal in the fourth wiring O4 fourth from the top in the lower five stages is in the fourth wiring P4 in the upper seven stages. The signal in the same waveform and phase as the signal, the signal in the lowermost fifth wiring O5 among the lower five stages has the same waveform and the same phase as the signal in the fifth wiring P5 in the upper seven stages.

  Note that, in the upper seven stages of FIG. 3, the clock wiring is configured by a 10-stage π-type RC circuit in a simulated manner. In each wiring, the distributed constant capacitance value (C between wirings) between one adjacent wiring is set to 1/20 of the total parasitic capacitance between one adjacent wiring, and the upper layer wiring in the semiconductor multilayer wiring The distributed constant capacitance value between C and the lower layer wiring (C in the π-type) was set to 1/20 of the total parasitic capacitance between the upper layer wiring and the lower layer wiring.

  Further, in the lower five stages of FIG. 3, the distributed constant capacity value (C in the π type) between the upper layer wiring and the lower layer wiring is the distributed constant capacity between one adjacent wiring in the upper seven stages. The value (C between the wirings) was doubled and equal to the sum of the distributed constant capacitance values (C in the π-type) between the upper layer wiring and the lower layer wiring in the upper seven steps. That is, a case is simulated in which both sides of each clock wiring are fixed potential wirings.

  In FIG. 4, the upper three timing charts show the waveforms of the signals P1R to P3R at the terminal portions of the first to third wirings P1 to P3 of the multiphase clock signal transmission circuit according to the present embodiment. The timing chart shows waveforms at the output terminals of the first to third inversion buffers 3a to 3c, respectively. In FIG. 5, the three timing charts in the lower stage show the first and second additional inverting buffers 4a and 4e and the first multiphase clock signal transmission circuit having the first and second additional wirings G5 and G1. The waveforms of the signals O1R to O3R at the terminal portions of the first to third wirings O1 to O3 are shown, and the upper three timing charts show the waveforms at the output ends of the first to third inversion buffers 3a to 3c, respectively.

  Comparing the waveforms of the signals P1R to P3R at the terminal portions of the first to third wirings P1 to P3 with the waveforms of the signals O1R to O3R at the terminal portions of the first to third wirings O1 to O3, the present embodiment In such a multiphase clock signal transmission circuit, the waveform is shaped like a square wave, and when the power supply voltage is Vcc, the rise time from 0.2 Vcc to 0.8 Vcc is 1.02 nsec. On the other hand, in the conventional circuit, the waveform has a shape close to a triangular wave, and the rise time from 0.2 Vcc to 0.8 Vcc is 1.26 nsec. Therefore, the signal waveform in the multiphase clock signal transmission circuit according to the present embodiment is sharper.

  Therefore, in an actual usage situation where the power supply in the clock usage block (not shown) connected to the terminal end of each wiring is shaken, the multiphase clock signal transmission circuit according to the present embodiment is more than the conventional circuit. The jitter of the received clock in the clock using block is small and considered to be excellent.

  According to the multiphase clock signal transmission circuit according to the present embodiment, in addition to the first to nth buffers and the first to nth wirings, the first and second additional buffers, and the first and second additions The first to n-th wirings are arranged in parallel adjacently in order of increasing or decreasing the ordinal number from the first to the n-th, and the first additional wiring is the (n-1) th wiring The second additional wiring is arranged in parallel and adjacent to the first wiring at a position opposite to the second wiring at a position opposite to the second wiring. . Therefore, in any of the first to n-th wirings, a wiring with a smaller ordinal number is arranged next to one, and a wiring with a larger ordinal number is arranged next to the other, so that the clock signal on the adjacent wiring is The influence on the clock signal on the wiring can be made equal. Thereby, it is possible to realize a multi-phase clock signal transmission circuit capable of transmitting an n-phase clock signal while suppressing signal deterioration due to coupling capacitance between clock wirings. In the present invention, the first to nth wirings are arranged in parallel adjacent to each other in order of increasing or decreasing the ordinal number, and the first and second additional wirings are adjacent to the nth and first wirings in parallel. Since it is only necessary to arrange the circuit, circuit design of the wiring of the transmission path of the multiphase clock signal becomes easy. Further, since only the first and second additional wirings need be added, a multiphase clock signal transmission circuit capable of further reducing the wiring area can be realized.

  Further, according to the multiphase clock signal transmission circuit according to the present embodiment, the input terminal of the first additional buffer is connected to the input terminal of the first buffer, and the input terminal of the second additional buffer is connected to the nth buffer. First to (n-2) th load elements connected to the input terminals and connected to the respective input terminals of the second to (n-1) th buffers are further provided. Accordingly, by aligning the resistance and capacitance values of the first to (n-2) th load elements with the resistance and capacitance values of the first and second additional buffers, each input of the first to nth buffers is set. The load connected to the end can be made the same, and the operating characteristics and delay characteristics of the first to nth buffers can be made uniform.

  In the above, the case where the terminal portion of the first to nth wirings is the clock receiving end of the clock use block is taken as an example, but the terminal portion of the first to nth wirings is not necessarily the clock receiving end. There is no need, and for example, there may be one or more clock lead-in locations in the middle of the first to nth wirings before reaching the termination portion. In that case, the lead-in line may be short or the wiring width and the wiring length may be equal in each phase so that the loads of all the first to n-th phases are equal at the lead-in part. Further, it is preferable to provide a clock receiving buffer or a capacitive element as a load having substantially the same resistance and capacitance in all the phase wirings at the lead-in location.

<Embodiment 2>
The present embodiment is a modification of the multiphase clock signal transmission circuit according to the first embodiment, and includes third to fifth additional inverting buffers 4b to 4d (first to third load elements) according to the first embodiment. Instead of functioning, a capacitive element is employed.

  FIG. 6 is a circuit diagram of the multiphase clock signal transmission circuit according to the present embodiment. In FIG. 6, first to third capacitive elements 4b1 to 4d1 are employed in place of the third to fifth additional inversion buffers 4b to 4d of FIG. That is, one end of the first capacitive element 4b1 as the first load element is connected to the input terminal of the second inverting buffer 3b, and the second capacitive element 4c1 as the second load element is connected to the input terminal of the third inverting buffer 3c. Are connected at one end. The input terminal of the fourth inversion buffer 3d is connected to one end of the third capacitive element 4d1 that is a third load element. A ground potential GND is applied to each of the other ends of the first to third capacitive elements 4b1 to 4d1. For the capacitances of the first to third capacitive elements 4b1 to 4d1, a value that causes a load similar to that of the third to fifth additional inversion buffers 4b to 4d may be employed.

  The circuit configuration is the same as that of FIG. 1 except that the first to third capacitive elements 4b1 to 4d1 are employed instead of the third to fifth additional inverting buffers 4b to 4d, respectively. Omitted. In the case of the n-phase, capacitive elements may be employed for all of the first to (n-2) th load elements.

  In the multiphase clock signal transmission circuit according to the present embodiment, the first to (n-2) th load elements are capacitive elements. Therefore, the first to (n-2) th load elements can be configured with a simple circuit.

  If the purpose is only to reduce jitter, the capacitive elements as the first to (n-2) th load elements are omitted, and nothing is connected to the input terminals of the second to fourth inversion buffers 3b to 3d. You may do it.

<Embodiment 3>
This embodiment is also a modification of the multiphase clock signal transmission circuit according to the first embodiment. In addition to the first and second additional wirings G5 and G1 in the first embodiment, the third and fifth additions are also made. A third additional wiring and a fourth additional wiring connected to the inverting buffers 4b and 4d are further provided, and the third additional wiring is arranged adjacent to the first additional wiring G5 in a position opposite to the fifth wiring P5. The fourth additional wiring is arranged in parallel with the second additional wiring G1 at a position opposite to the first wiring P1.

  FIG. 7 is a circuit diagram of the multiphase clock signal transmission circuit according to the present embodiment. In FIG. 7, the third additional wiring G6 and the fourth additional wiring G0 are connected to the third and fifth additional inversion buffers 4b and 4d of FIG. 1, respectively. The third additional wiring G6 is arranged in parallel with and adjacent to the first additional wiring G5 at a position opposite to the fifth wiring P5, and the fourth additional wiring G0 is opposite to the first wiring P1. The circuit is arranged in parallel adjacent to the second additional wiring G1 at the position. In FIG. 7, the circuit configuration is the same as that in FIG. 1 except that the third additional wiring G6 and the fourth additional wiring G0 are added, and thus the description of the other parts is omitted.

  In FIG. 7, the third and fifth additional inversion buffers 4b and 4d, which are dummy in FIG. 1, function as further additional buffers, and the third and fifth additional inversion buffers 4b and 4d have the third and fourth inversion buffers. Additional wirings G6 and G0 were connected. This is an example in the case of n = 5 phases, but when the value of n becomes more multiphase, it is possible to provide more additional inverting buffers and additional wirings connected to these additional inverting buffers. is there. In general, this is as follows.

  That is, first to n-th buffers (corresponding to the first to fifth inversion buffers 3a to 3e in FIG. 7) for receiving an n-phase clock signal, and a first additional inversion buffer (in FIG. In addition to the first additional inversion buffer 4a) and the second additional inversion buffer (corresponding to the second additional inversion buffer 4e in FIG. 7) that receives the nth clock signal. j is a third to (j + 1) th additional buffer having an input terminal and an output terminal each receiving a clock signal of 2 or more and [n / 2] or less (any natural number of [] is a Gaussian symbol)). 7 third additional inverting buffer 4b and a further inner buffer (not shown), and third to (j + 1) th additional wirings connected to the output terminals of the third to (j + 1) th additional buffers ( Third additional arrangement in FIG. G6 and further outside the wiring and corresponding to the (not shown)), may be provided. Furthermore, an input terminal for receiving the k-th to (n-1) -th (k is any natural number between [n / 2] +1 and (n-1)) clocks, and an output terminal, respectively. (J + 2) to (j + 2 + n−1−k) additional buffers (corresponding to the fourth additional inversion buffer 4d and further inner buffer (not shown) in FIG. 7), and (j + 2) to (j + 2 + n). -1-k) (j + 2) to (j + 2 + n-1-k) additional wirings connected to each output terminal of the additional buffer (fourth additional wiring G0 in FIG. 7 and further outside wiring (not shown)) Equivalent).

  The third to (j + 1) th additional wirings are arranged adjacent to the first additional wiring in parallel with the third to (j + 1) th ordinal numbers in the order of increasing ordinal numbers. The circuit is arranged, and the (j + 2) to (j + 2 + n−1−k) additional wirings are opposite to the first wirings in the order of decreasing ordinal numbers from the (j + 2 + n−1−k) th to the (j + 2) th. The circuit may be arranged in parallel adjacent to the second additional wiring at the position on the side.

  According to the multiphase clock signal transmission circuit according to the present embodiment, it is possible to suppress signal deterioration due to the coupling capacitance between the clock wirings for the first and second additional wirings, and to provide a more accurate multiphase clock. A signal transmission circuit can be realized.

<Embodiment 4>
This embodiment is also a modification of the multiphase clock signal transmission circuit according to the first embodiment, and a fixed potential is applied to the outside of the first and second additional wirings G5 and G1 in the first embodiment. The first and second fixed potential wirings are arranged in parallel adjacent to the first and second additional wirings G5 and G1.

  FIG. 8 is a circuit diagram of the multiphase clock signal transmission circuit according to the present embodiment. In FIG. 8, first and second fixed potential wirings 5a and 5b to which a ground potential GND as a fixed potential is applied are added outside the second and first additional wirings G1 and G5 in FIG. In FIG. 8, the circuit configuration is the same as that in FIG. 1 except that the first and second fixed potential wirings 5a and 5b are added.

  Note that such addition of the first and second fixed potential wirings is performed in the third to (j + 1) th additional buffer, the third to (j + 1) th additional wiring, and the (j + 2) th to (j + 2) th to the third embodiment described in the third embodiment. The present invention can also be applied to a multiphase clock signal transmission circuit including an (j + 2 + n−1−k) th additional buffer and (j + 2) th to (j + 2 + n−1−k) th additional wiring. That is, the first fixed potential wiring is arranged in parallel at the position opposite to the n-th wiring and adjacent to the outermost wiring among the first additional wiring or the third to (j + 1) -th additional wiring, In parallel with the second fixed potential wiring, adjacent to the outermost wiring of the second additional wiring or the (j + 2) to (j + 2 + n−1−k) additional wiring at a position opposite to the first wiring. What is necessary is just to arrange a circuit.

  According to the multiphase clock signal transmission circuit according to the present embodiment, the first and second fixed potential wirings function as guard wirings, and noise is mixed in the n-phase clock signals transmitted through the first to nth wirings. Hard to do.

1 is a circuit diagram of a multiphase clock signal transmission circuit according to a first embodiment. 6 is a diagram illustrating waveforms of clock signals applied to first to fifth wirings in the multiphase clock signal transmission circuit according to the first embodiment. FIG. FIG. 3 is a circuit diagram used for simulation of the multiphase clock signal transmission circuit according to the first embodiment. 6 is a diagram illustrating a simulation result of the multiphase clock signal transmission circuit according to the first embodiment. FIG. It is a figure which shows the simulation result of the conventional multiphase clock signal transmission circuit. FIG. 6 is a circuit diagram of a multiphase clock signal transmission circuit according to a second embodiment. FIG. 6 is a circuit diagram of a multiphase clock signal transmission circuit according to a third embodiment. FIG. 6 is a circuit diagram of a multiphase clock signal transmission circuit according to a fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock driver, 2 wiring part, 3a-3e inversion buffer, 4a-4e additional inversion buffer, P1-P5 wiring, G0, G1, G5, G6, 5a, 5b additional wiring, 4b1-4d1 capacitive element.

Claims (5)

First to n-th buffers each having an input terminal and an output terminal for receiving first to n-th n-phase clock signals having different phases by (360 / n) degrees (n is a natural number of 2 or more). When,
First to nth wirings connected to the output terminals of the first to nth buffers;
A first additional buffer having an input for receiving the first clock signal and an output;
A second additional buffer having an input terminal for receiving the nth clock signal and an output terminal;
A first additional wiring connected to the output end of the first additional buffer;
A second additional wiring connected to the output terminal of the second additional buffer,
The first to nth wirings are arranged in parallel adjacently in order of increasing or decreasing the ordinal number from the first to the nth,
The first additional wiring is arranged in parallel to be adjacent to the n-th wiring at a position opposite to the (n-1) wiring,
The second additional wiring is a multiphase clock signal transmission circuit in which a circuit is arranged in parallel and adjacent to the first wiring at a position opposite to the second wiring. The multi-phase clock signal transmission circuit according to claim 1,
The input end of the first additional buffer is connected to the input end of the first buffer;
The input terminal of the second additional buffer is connected to the input terminal of the nth buffer;
A multi-phase clock signal transmission circuit further comprising first to (n-2) th load elements connected to the input terminals of second to (n-1) th buffers. A multi-phase clock signal transmission circuit according to claim 2,
The first to (n-2) th load elements are multi-phase clock signal transmission circuits which are capacitive elements. The multi-phase clock signal transmission circuit according to claim 1,
Third to jth clock terminals each having an input terminal and an output terminal for receiving the second to jth clock signals (j is a natural number of 2 or more and [n / 2] or less ([] is a Gaussian symbol)). A (j + 1) th additional buffer;
An input terminal for receiving the k-th to (n-1) th (k is any natural number between [n / 2] +1 and (n-1)) clocks and an output terminal. (J + 2) to (j + 2 + n-1-k) additional buffers;
Third to (j + 1) th additional wiring connected to each of the output ends of the third to (j + 1) th additional buffers;
(J + 2) to (j + 2 + n−1−k) additional wirings connected to the output terminals of the (j + 2) th to (j + 2 + n−1−k) additional buffers, respectively.
The third to (j + 1) th additional wirings are arranged adjacent to the first additional wiring in the order of increasing the ordinal numbers from the third to the (j + 1) th in the position opposite to the nth wiring. Is placed in the circuit,
The (j + 2) to (j + 2 + n−1−k) additional wirings are arranged on the side opposite to the first wiring in order of decreasing ordinal numbers from the (j + 2 + n−1−k) th to the (j + 2) th. A multi-phase clock signal transmission circuit arranged in parallel at a position adjacent to the second additional wiring. A multi-phase clock signal transmission circuit according to any one of claims 1 to 4,
A first and a second fixed potential wiring to which a fixed potential is applied;
The first fixed potential wiring is arranged in parallel with the first additional wiring or the third to (j + 1) th additional wiring adjacent to the outermost wiring at a position opposite to the nth wiring. And
The second fixed potential wiring is adjacent to the outermost wiring of the second additional wiring or the (j + 2) to (j + 2 + n-1-k) additional wiring at a position opposite to the first wiring. A multi-phase clock signal transmission circuit arranged in parallel.

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