JP5240021B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5240021B2
JP5240021B2 JP2009091302A JP2009091302A JP5240021B2 JP 5240021 B2 JP5240021 B2 JP 5240021B2 JP 2009091302 A JP2009091302 A JP 2009091302A JP 2009091302 A JP2009091302 A JP 2009091302A JP 5240021 B2 JP5240021 B2 JP 5240021B2
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substrate
thin film
semiconductor element
side thin
semiconductor device
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JP2010245227A (en
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正憲 山際
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for improving reliability and lifetime. <P>SOLUTION: The semiconductor device 10 is configured such that a semiconductor element 12 is bonded to a substrate 11 by a bonding layer 13. The substrate 11 includes a substrate side thin film 15 on the bonding surface with the semiconductor element 12. Cracks 16 are formed in the bonding surface concerning the substrate side thin film 15. The substrate side thin film 15 is divided by the cracks 16 so as to be intermittently arranged. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、半導体素子と基板とが接合層によって接合された半導体装置、及びその半導体装置の製造方法に関する。   The present invention relates to a semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer, and a method for manufacturing the semiconductor device.

一般に、半導体素子（チップ）と基板を接合する際には、はんだが用いられる。このようなはんだは、半導体素子と基板との間に熱膨張係数差があるため、温度変化が加わることによって発生する応力をはんだ自身が歪むことによって緩和するというメリットを有する反面、その繰り返しによって、Coffin-Manson則（非線形材料の低サイクル疲労特性として歪と疲労寿命の関係を示す法則）で示されるように、はんだ自身に劣化が発生するというデメリットを有する。   Generally, solder is used when joining a semiconductor element (chip) and a substrate. Since such a solder has a difference in thermal expansion coefficient between the semiconductor element and the substrate, it has the merit that the stress generated by the temperature change is relaxed by distorting the solder itself, but by repetition, As indicated by the Coffin-Manson rule (a law indicating the relationship between strain and fatigue life as a low cycle fatigue property of a nonlinear material), it has a demerit that the solder itself deteriorates.

具体的には、実使用時、半導体素子の発熱によって半導体装置全体に温度変化が加わると、熱膨張係数が異なる半導体素子と基板との間に変位（伸長差）が発生し、これにより、半導体素子と基板間に存在するはんだには熱応力と熱歪が生じる。そして、半導体素子の発熱が繰り返されることによってはんだの劣化が進み、遂には疲労寿命に達してはんだにクラックが発生する。   Specifically, in actual use, when a temperature change is applied to the entire semiconductor device due to heat generated by the semiconductor element, a displacement (elongation difference) occurs between the semiconductor element having a different thermal expansion coefficient and the substrate, thereby causing the semiconductor Thermal stress and thermal strain are generated in the solder existing between the element and the substrate. Then, the heat generation of the semiconductor element is repeated, so that the deterioration of the solder progresses. Finally, the fatigue life is reached and the solder is cracked.

上記半導体装置においては、半導体素子で生じた熱の一部をはんだを介して基板側へ伝達し放熱しているが、はんだにクラックが発生すると、そのクラックによって放熱経路が遮断され、半導体素子が高温に晒されてしまうという問題点がある。   In the semiconductor device, a part of the heat generated in the semiconductor element is transmitted to the substrate side through the solder to dissipate the heat, but when a crack occurs in the solder, the heat dissipation path is blocked by the crack, and the semiconductor element There is a problem of being exposed to high temperatures.

このような問題点に対して、従来の半導体装置におけるより一層の寿命向上と、はんだが使用できないような高温で使われる次世代の半導体装置の信頼性を確保することを目的として、半導体素子と基板の接合材料の強度特性を指定することにより、半導体素子と基板間の変位を主に接合層ではなく基板側の金属で吸収するようにした構造が提案されている（例えば、特許文献１参照）。   With respect to such problems, with the aim of further improving the lifetime of conventional semiconductor devices and ensuring the reliability of next-generation semiconductor devices used at high temperatures where solder cannot be used, A structure has been proposed in which the displacement between the semiconductor element and the substrate is mainly absorbed by the metal on the substrate side rather than the bonding layer by specifying the strength characteristics of the bonding material of the substrate (see, for example, Patent Document 1). ).

すなわち、上記特許文献１では、接合層の０.２％耐力の大きさを基板金属の０.２％耐力の大きさと同じ若しくはそれ以上とすることにより、半導体素子と基板間の変位を接合層に代わって主に基板金属で受け止めることが可能となっている。そして引用文献１では、最終的な破壊を、接合層と比較して靱性が高く良好な疲労特性を示す基板金属において発生させる構造となっており、これにより、高い温度サイクル耐久性が期待できる。   That is, in the above-mentioned Patent Document 1, the displacement between the semiconductor element and the substrate is made to be equal to or greater than the 0.2% proof stress of the substrate metal by setting the 0.2% proof stress of the bonding layer to be equal to or greater than the 0.2% proof stress of the substrate metal. Instead, it can be received mainly with substrate metal. The cited document 1 has a structure in which the final fracture is generated in the substrate metal having high toughness and good fatigue characteristics as compared with the bonding layer, whereby high temperature cycle durability can be expected.

特開２００８−４１７０７号公報JP 2008-41707 A

ところで、基板や半導体素子の接合面には、通常、薄膜（メッキ層）が形成されている場合が多い。このような薄膜が形成されている場合、薄膜と基板金属は熱膨張係数が異なり、互いに熱変形挙動を拘束するため、これが要因となって基板にうねりを発生させることがある。その結果、このうねりが接合層の厚み方向での引張力となって、薄膜と接合層の界面剥離や、接合層にクラック発生を引き起こし、半導体装置の信頼性及び寿命の低下の要因となっている。   By the way, in many cases, a thin film (plated layer) is usually formed on a bonding surface of a substrate or a semiconductor element. When such a thin film is formed, the thin film and the substrate metal have different coefficients of thermal expansion and restrain the thermal deformation behavior of each other, which may cause undulation in the substrate. As a result, this undulation becomes a tensile force in the thickness direction of the bonding layer, causing interface peeling between the thin film and the bonding layer, and cracking in the bonding layer, leading to a decrease in reliability and lifetime of the semiconductor device. Yes.

本発明は、上記問題点を解消するために成されたもので、その目的は、信頼性及び寿命を向上させることが可能な半導体装置及びその製造方法を提供することにある。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of improving reliability and lifetime and a manufacturing method thereof.

上記課題を解決するために、本発明の半導体装置は、半導体素子と基板とが接合層によって接合されている。そして、本発明の半導体装置は、前記基板には前記半導体素子との接合面に基板側薄膜が設けられ、前記基板側薄膜には前記接合面の部分に亀裂が形成され、前記基板側薄膜は前記亀裂によって分割されて断続的に配置されていることを特徴としている。   In order to solve the above problems, in a semiconductor device of the present invention, a semiconductor element and a substrate are bonded by a bonding layer. In the semiconductor device of the present invention, the substrate is provided with a substrate-side thin film on a bonding surface with the semiconductor element, the substrate-side thin film is cracked at the bonding surface, and the substrate-side thin film is It is divided by the crack and is arranged intermittently.

本発明によれば、基板側薄膜に予め亀裂が形成され、基板側薄膜は亀裂によって分割されて断続的に配置されているので、半導体素子が発熱して基板の温度が上昇したとき、基板は容易に変形（伸長）することができる。これにより、基板にうねりが発生することはなく、また、うねりによって生じる接合層と薄膜との界面剥離や、接合層におけるクラック発生を防止することができ、半導体装置の信頼性及び寿命を飛躍的に向上させることが可能となる。   According to the present invention, the substrate-side thin film is previously cracked, and the substrate-side thin film is divided and intermittently disposed by the crack. Therefore, when the semiconductor element generates heat and the temperature of the substrate rises, It can be easily deformed (elongated). As a result, no undulation occurs in the substrate, and the interface peeling between the bonding layer and the thin film caused by the undulation and the generation of cracks in the bonding layer can be prevented, thereby dramatically improving the reliability and life of the semiconductor device. Can be improved.

実施例１による半導体装置の縦断面図である。1 is a longitudinal sectional view of a semiconductor device according to Example 1. FIG. 基板の平面図である。It is a top view of a board | substrate. 基板の他の例による平面図である。It is a top view by the other example of a board | substrate. 半導体素子の各部位における歪みと応力の関係を示す図である。It is a figure which shows the relationship between the distortion in each site | part of a semiconductor element, and stress. 実施例２による半導体装置の縦断面図である。6 is a longitudinal sectional view of a semiconductor device according to Example 2. FIG. 実施例３による半導体装置の縦断面図である。6 is a longitudinal sectional view of a semiconductor device according to Example 3. FIG. 実施例４による半導体装置の縦断面図である。6 is a longitudinal sectional view of a semiconductor device according to Example 4. FIG.

以下、本発明の実施例を図面に従って説明する。   Embodiments of the present invention will be described below with reference to the drawings.

《実施例１》
図１は、実施例１による半導体装置の縦断面図である。図１に示すように、半導体装置１０は基板１１と半導体素子（チップ）１２とを備え、基板１１と半導体素子１２とは接合層１３によって互いに接合されている。 Example 1
FIG. 1 is a longitudinal sectional view of a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 10 includes a substrate 11 and a semiconductor element (chip) 12, and the substrate 11 and the semiconductor element 12 are bonded to each other by a bonding layer 13.

基板１１と接合層１３は、金属材料、有機物と金属材料との複合材料、または無機物と金属材料との複合材料によって構成されている。基板１１は、基板金属１４と、基板金属１４の外表面に形成された基板側薄膜１５とによって形成されている。基板側薄膜１５はメッキ層からなっており、この基板側薄膜１５には、半導体素子１２との接合面、具体的には接合層１３と接する領域の接合面に亀裂１６が形成されている。亀裂１６は、基板側薄膜１５の厚さ方向（図の上下方向）に、つまり接合層１３に接する表面側から、基板金属１４に接する裏面側まで基板側薄膜１５を貫通して形成されている。また亀裂１６は、対向壁面がほぼ接触した状態であり、対向壁面間には隙間は存在しない。   The substrate 11 and the bonding layer 13 are made of a metal material, a composite material of an organic material and a metal material, or a composite material of an inorganic material and a metal material. The substrate 11 is formed by a substrate metal 14 and a substrate-side thin film 15 formed on the outer surface of the substrate metal 14. The substrate-side thin film 15 is made of a plated layer, and the substrate-side thin film 15 has a crack 16 formed on the bonding surface with the semiconductor element 12, specifically, the bonding surface in a region in contact with the bonding layer 13. The crack 16 is formed through the substrate-side thin film 15 in the thickness direction (vertical direction in the figure) of the substrate-side thin film 15, that is, from the surface side in contact with the bonding layer 13 to the back surface side in contact with the substrate metal 14. . The crack 16 is in a state where the opposing wall surfaces are substantially in contact, and there is no gap between the opposing wall surfaces.

図２または図３は基板１１の平面図である。亀裂１６は、図２または図３に示すような形状に形成されている。すなわち、図２においては、縦方向と横方向に直線状の亀裂１６がそれぞれ４本ずつ形成され、縦方向及び横方向の各亀裂１６は直角に交わっている。これら亀裂１６は、基板側薄膜１５のうち半導体素子１２との接合面にのみ形成されている。そして、基板側薄膜１５は各亀裂１６によって分割され、基板金属１４の表面上に断続的に配置されている。縦方向及び横方向の各亀裂１６の間隔は、基板側薄膜１５の中央部分では狭く、その外側の部分では広くなっており、これにより、連続する１つの基板側薄膜１５の大きさは半導体素子１２の中央部に近づくほど小さく形成されている。   2 or 3 is a plan view of the substrate 11. The crack 16 is formed in a shape as shown in FIG. That is, in FIG. 2, four straight cracks 16 are formed in each of the vertical direction and the horizontal direction, and the vertical and horizontal cracks 16 intersect at right angles. These cracks 16 are formed only on the bonding surface of the substrate-side thin film 15 with the semiconductor element 12. The substrate-side thin film 15 is divided by the cracks 16 and is intermittently disposed on the surface of the substrate metal 14. The interval between the cracks 16 in the vertical direction and the horizontal direction is narrow at the central portion of the substrate-side thin film 15 and wide at the outer portion thereof, whereby the size of one continuous substrate-side thin film 15 is the semiconductor element. 12 is formed smaller as it approaches the center.

また、図３においては、基板側薄膜１５のうち、半導体素子１２との接合面に円形状の３つの亀裂１６が形成され、各亀裂１６は基板側薄膜１５の中央部分を中心にした同心円状を成している。基板側薄膜１５は各亀裂１６によって分割され、基板金属１４の表面上に断続的に配置されている。各亀裂１６を呈する円は、中央部分では隣の円との間隔が狭く、その外側の部分では隣の円との間隔が広くなっており、連続する１つの基板側薄膜１５の大きさは半導体素子１２の中央部に近づくほど小さく形成されている。   In FIG. 3, three circular cracks 16 are formed on the bonding surface with the semiconductor element 12 in the substrate-side thin film 15, and each crack 16 has a concentric shape centering on the central portion of the substrate-side thin film 15. Is made. The substrate-side thin film 15 is divided by the cracks 16 and is intermittently disposed on the surface of the substrate metal 14. The circle presenting each crack 16 has a narrow interval with the adjacent circle in the central portion and a wide interval with the adjacent circle in the outer portion, and the size of one continuous substrate-side thin film 15 is a semiconductor. The closer to the center of the element 12, the smaller it is formed.

基板１１は、図１に示すように、例えば、一般的なパワーモジュールに使用されているアルミナセラミックス板１７にAl（アルミニウム）を接合したAl回路付きセラミックス絶縁基板からなっている。基板金属１４はAl回路であり、また、基板側薄膜１５はAl回路上にメッキ処理法によって形成されたNi/Agメッキ層からなっている。   As shown in FIG. 1, the substrate 11 is made of, for example, a ceramic insulating substrate with an Al circuit in which Al (aluminum) is bonded to an alumina ceramic plate 17 used in a general power module. The substrate metal 14 is an Al circuit, and the substrate-side thin film 15 is made of a Ni / Ag plating layer formed by plating on the Al circuit.

半導体素子１２は、Si（シリコン）などからなるパワー半導体デバイスとして一般的なIGBT（Insulated Gate Bipolar Transister）チップやダイオードで構成されている。そして接合層１３は、高い降伏強度の得られるCuSnはんだによって形成された合金層である。   The semiconductor element 12 is composed of an IGBT (Insulated Gate Bipolar Transistor) chip or a diode, which is a general power semiconductor device made of Si (silicon) or the like. The bonding layer 13 is an alloy layer formed of CuSn solder that provides a high yield strength.

このように構成された半導体装置１０において、動作時の半導体素子１２の自己発熱や、半導体装置１０が置かれている環境の温度変化などによって局部的に温度差が生じ、それによって、異種材接合面には熱応力が発生する。すなわち、半導体装置１０の基板１１においては、互いに異なる材料からなる、基板側薄膜１５と基板金属１４との界面に熱応力が発生する。   In the semiconductor device 10 configured as described above, a temperature difference is locally generated due to self-heating of the semiconductor element 12 during operation, a temperature change in an environment in which the semiconductor device 10 is placed, and the like. Thermal stress is generated on the surface. That is, in the substrate 11 of the semiconductor device 10, thermal stress is generated at the interface between the substrate-side thin film 15 and the substrate metal 14 made of different materials.

本実施例の半導体装置１０では、基板側薄膜１５に予め亀裂１６が形成されているので、例えば低温から高温に変化した場合でも、熱膨張係数が基板側薄膜１５よりも大きい基板金属１４は亀裂１６の直下では自由に伸びることが可能である。これにより、基板側薄膜１５と基板金属１４の界面に生じる応力や、それによって生じる基板金属１４のうねりを抑制することができる。また、接合層１３と基板側薄膜１５との界面近傍に生じる応力も低減でき、界面剥離や接合層１３におけるクラックの発生を防止することができる。その結果、半導体装置１０の信頼性向上を図ることが可能となる。   In the semiconductor device 10 of this embodiment, since the crack 16 is formed in the substrate-side thin film 15 in advance, the substrate metal 14 having a larger thermal expansion coefficient than that of the substrate-side thin film 15 is cracked even when, for example, the temperature changes from low to high. It is possible to extend freely just below 16. Thereby, the stress which arises in the interface of the board | substrate side thin film 15 and the board | substrate metal 14, and the wave | undulation of the board | substrate metal 14 produced by it can be suppressed. In addition, stress generated in the vicinity of the interface between the bonding layer 13 and the substrate-side thin film 15 can be reduced, and interface peeling and generation of cracks in the bonding layer 13 can be prevented. As a result, it is possible to improve the reliability of the semiconductor device 10.

また、本実施例の半導体装置１０では、基板金属１４がAl回路で、接合層１３がCuSnはんだの合金層であるから、０.２％耐力は接合層１３の方が基板金属１４より大きい値になっている。さらに、図４に示すように、基板金属１４がAl回路で、基板側薄膜１５がNi/Agメッキ層であるから、同一温度の下で、０.２％耐力は基板側薄膜１５の方が基板金属１４より大きい値になっている。これにより、半導体素子１２と基板１１の熱膨張係数差による変位（伸長差）を、接合層１３や基板側薄膜１５と比較して靱性が高く良好な繰返し疲労特性を有する基板金属１４の歪によって吸収させることができ、半導体装置１０の信頼性を飛躍的に向上させることが可能となる。なお、基板側薄膜１５の０.２％耐力と基板側薄膜１５の０.２％耐力を同じに設定してもよい。   Further, in the semiconductor device 10 of this embodiment, since the substrate metal 14 is an Al circuit and the bonding layer 13 is an alloy layer of CuSn solder, the 0.2% proof stress is greater in the bonding layer 13 than in the substrate metal 14. It has become. Furthermore, as shown in FIG. 4, since the substrate metal 14 is an Al circuit and the substrate-side thin film 15 is a Ni / Ag plating layer, the substrate-side thin film 15 has a 0.2% proof stress at the same temperature. The value is larger than the substrate metal 14. Thereby, the displacement (elongation difference) due to the difference in thermal expansion coefficient between the semiconductor element 12 and the substrate 11 is caused by the strain of the substrate metal 14 having high toughness and good repeated fatigue characteristics as compared with the bonding layer 13 and the substrate-side thin film 15. Therefore, the reliability of the semiconductor device 10 can be remarkably improved. Note that the 0.2% proof stress of the substrate-side thin film 15 and the 0.2% proof stress of the substrate-side thin film 15 may be set to be the same.

さらに、本実施例では、亀裂１６を図２または図３のような形状にして、半導体素子１２の中央部に近づくほど連続する１つの基板側薄膜１５の大きさが小さくなるようにしている。これは、発熱密度が高くより大きな温度差が加わる可能性のある部位が半導体素子１２の中央部だからである。仮に全ての材料が弾性挙動しか示さないとした場合、基板側薄膜１５と基板金属１４の界面近傍に働く応力は、それぞれの熱膨張係数差とそこに加わる温度差に比例すると考えられる。そのため、応力緩和を目的とした亀裂１６を入れる間隔、つまり１つの連続する基板側薄膜１５の大きさは、それぞれの熱膨張係数差とそこに生じる温度差に反比例するように設定されている。例えば、基板側薄膜１５と基板金属１４との熱膨張係数差が大きいほど、１つの連続する基板側薄膜１５の大きさは小さくなる。このように本実施例によれば、亀裂１６の具体的な位置を容易に設計することができる。   Further, in this embodiment, the crack 16 is shaped as shown in FIG. 2 or FIG. 3 so that the size of one continuous substrate-side thin film 15 becomes smaller as it approaches the center of the semiconductor element 12. This is because the portion where the heat generation density is high and a larger temperature difference may be applied is the central portion of the semiconductor element 12. If all materials exhibit only elastic behavior, the stress acting near the interface between the substrate-side thin film 15 and the substrate metal 14 is considered to be proportional to the difference in thermal expansion coefficient and the temperature difference applied thereto. For this reason, the interval at which the cracks 16 are inserted for the purpose of stress relaxation, that is, the size of one continuous substrate-side thin film 15 is set to be inversely proportional to the difference between the respective thermal expansion coefficients and the temperature difference generated there. For example, the larger the difference in thermal expansion coefficient between the substrate-side thin film 15 and the substrate metal 14, the smaller the size of one continuous substrate-side thin film 15 is. Thus, according to the present embodiment, the specific position of the crack 16 can be easily designed.

以上のように本実施例によれば、半導体装置１０の信頼性をより一層向上させることが可能である。   As described above, according to this embodiment, the reliability of the semiconductor device 10 can be further improved.

次に、半導体装置１０の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 10 will be described.

先ず、基板１１としてアルミナセラミックス板にAlを接合したAl回路付きセラミックス絶縁基板を用意し、基板金属１４としてのAl回路に、基板側薄膜１５としてのNi/Agメッキ層をメッキ処理法によって形成する。その後、基板１１の温度を例えば３００℃に上昇させることで、Al回路とNi/Agメッキ層の熱膨張係数差から生じる熱応力によって、Ni/Agメッキ層に亀裂１６を形成する。そして最後に、基板１１のNi/Agメッキ層のうち、亀裂１６を形成した箇所に半導体素子１２を実装する。   First, a ceramic insulating substrate with an Al circuit in which Al is bonded to an alumina ceramic plate is prepared as the substrate 11, and a Ni / Ag plating layer as the substrate-side thin film 15 is formed on the Al circuit as the substrate metal 14 by a plating method. . Thereafter, by raising the temperature of the substrate 11 to, for example, 300 ° C., cracks 16 are formed in the Ni / Ag plating layer due to thermal stress resulting from the difference in thermal expansion coefficient between the Al circuit and the Ni / Ag plating layer. Finally, the semiconductor element 12 is mounted on the Ni / Ag plating layer of the substrate 11 where the crack 16 is formed.

また、上記製造方法のうち、Ni/Agメッキ層の形成後に、任意の形状をした突起物をNi/Agメッキ層に当てることにより、Ni/Agメッキ層に任意の形状の亀裂１６を機械的に形成し、その後、半導体素子１２を実装するようにしてもよい。   Further, in the above manufacturing method, after the Ni / Ag plating layer is formed, a protrusion 16 having an arbitrary shape is applied to the Ni / Ag plating layer, whereby a crack 16 having an arbitrary shape is mechanically formed on the Ni / Ag plating layer. Then, the semiconductor element 12 may be mounted.

さらに、上記製造方法のうち、Ni/Agメッキ層の形成後に、基板１１の温度を例えば５００℃に上昇させることで、Al回路とNi/Agメッキ層との間に薄い金属間化合物を形成させる。そして、冷却による残留応力または押圧力によって、金属間化合物の層からNi/Agメッキ層にかけて亀裂１６を形成し、その後、半導体素子１２を実装するようにしてもよい。   Further, in the above manufacturing method, after the Ni / Ag plating layer is formed, the temperature of the substrate 11 is raised to, for example, 500 ° C., thereby forming a thin intermetallic compound between the Al circuit and the Ni / Ag plating layer. . Then, a crack 16 may be formed from the intermetallic compound layer to the Ni / Ag plating layer by residual stress or pressing force due to cooling, and then the semiconductor element 12 may be mounted.

上記の各製造方法によれば、基板側薄膜１５に亀裂１６を容易に形成することが可能となる。   According to each manufacturing method described above, the crack 16 can be easily formed in the substrate-side thin film 15.

《実施例２》
図５は、実施例２による半導体装置の縦断面図である。本実施例における半導体装置２０には、図５に示すように、半導体素子１２の底部に素子電極２１が設けられ、その素子電極２１の底面（接合面）に半導体素子側薄膜２２が形成されている。素子電極２１はAl電極であり、半導体素子側薄膜２２は素子電極２１の底面に蒸着によって形成されたTi/Ni/Ag蒸着膜である。 Example 2
FIG. 5 is a longitudinal sectional view of a semiconductor device according to the second embodiment. In the semiconductor device 20 in this embodiment, as shown in FIG. 5, an element electrode 21 is provided on the bottom of the semiconductor element 12, and a semiconductor element-side thin film 22 is formed on the bottom surface (bonding surface) of the element electrode 21. Yes. The element electrode 21 is an Al electrode, and the semiconductor element-side thin film 22 is a Ti / Ni / Ag deposited film formed on the bottom surface of the element electrode 21 by vapor deposition.

本実施例では、半導体素子側薄膜２２には、接合層１３と接する領域において、亀裂２３が形成されている。亀裂２３は、半導体素子側薄膜２２の厚さ方向（図の上下方向）に、つまり素子電極２１に接する裏面側から、接合層１３に接する表面側まで半導体素子側薄膜２２を貫通して形成されている。亀裂２３は、半導体素子側薄膜２２を接合層１３側から見たとき、直線状または円形状を成している。また亀裂２３は、対向壁面がほぼ接触した状態であり、対向壁面間には隙間は存在しない。なお、基板１１の構成は実施例１（図１）の場合と同じである。   In this embodiment, the semiconductor element side thin film 22 has a crack 23 in a region in contact with the bonding layer 13. The crack 23 is formed through the semiconductor element side thin film 22 in the thickness direction (vertical direction in the figure) of the semiconductor element side thin film 22, that is, from the back surface side in contact with the element electrode 21 to the surface side in contact with the bonding layer 13. ing. The crack 23 is linear or circular when the semiconductor element-side thin film 22 is viewed from the bonding layer 13 side. Further, the crack 23 is in a state where the opposing wall surfaces are substantially in contact with each other, and there is no gap between the opposing wall surfaces. The configuration of the substrate 11 is the same as that of the first embodiment (FIG. 1).

また、本実施例では、図４に示すように、素子電極２１がAl電極で、半導体素子側薄膜２２がTi/Ni/Ag蒸着膜であるから、同一温度の下で、０.２％耐力は半導体素子側薄膜２２の方が素子電極２１より大きい値になっている。なお、半導体素子側薄膜２２の０.２％耐力と素子電極２１の０.２％耐力を同じに設定してもよい。   In this embodiment, as shown in FIG. 4, the element electrode 21 is an Al electrode and the semiconductor element-side thin film 22 is a Ti / Ni / Ag deposited film, so that 0.2% proof stress is obtained at the same temperature. The semiconductor element side thin film 22 has a larger value than the element electrode 21. Note that the 0.2% proof stress of the semiconductor element-side thin film 22 and the 0.2% proof stress of the element electrode 21 may be set to be the same.

このように構成された半導体装置２０においては、上述したように、動作時の半導体素子１２の自己発熱や、半導体装置２０が置かれた環境の温度変化などによって局部的に温度差が生じ、これによって、半導体素子側薄膜２２と素子電極２１の界面に熱応力が発生する。   In the semiconductor device 20 configured as described above, as described above, a temperature difference is locally generated due to self-heating of the semiconductor element 12 during operation, a temperature change in an environment in which the semiconductor device 20 is placed, and the like. As a result, thermal stress is generated at the interface between the semiconductor element-side thin film 22 and the element electrode 21.

本実施例の半導体装置２０では、半導体素子側薄膜２２に予め亀裂２３が形成されているので、例えば低温から高温に変化した場合でも、半導体素子側薄膜２２より熱膨張係数の大きい素子電極２１は半導体素子側薄膜２２の亀裂２３直上で自由に伸びることが可能である。これにより、半導体素子側薄膜２２と素子電極２１の界面に生じる応力や、それによって生じる素子電極２１のうねりを抑制することができる。また、接合層１３と半導体素子側薄膜２２との界面近傍に生じる応力も低減でき、界面剥離や接合層１３におけるクラック発生を防止することができる。その結果、半導体装置２０の信頼性向上を図ることが可能である。   In the semiconductor device 20 of the present embodiment, since the crack 23 is formed in advance in the semiconductor element side thin film 22, the element electrode 21 having a larger thermal expansion coefficient than the semiconductor element side thin film 22, for example, even when the temperature changes from low temperature to high temperature. The semiconductor element-side thin film 22 can freely extend just above the crack 23. Thereby, the stress which arises in the interface of the semiconductor element side thin film 22 and the element electrode 21, and the undulation of the element electrode 21 which arises by it can be suppressed. In addition, stress generated in the vicinity of the interface between the bonding layer 13 and the semiconductor element-side thin film 22 can be reduced, and interface peeling and cracking in the bonding layer 13 can be prevented. As a result, the reliability of the semiconductor device 20 can be improved.

なお、半導体素子側薄膜２２に亀裂２３を形成するための方法としては、実施例１で説明した製造方法を利用することができる。   As a method for forming the crack 23 in the semiconductor element-side thin film 22, the manufacturing method described in the first embodiment can be used.

また、半導体素子側薄膜２２の亀裂２３に対応させて、基板側薄膜１５に亀裂を形成してもよい。   Further, a crack may be formed in the substrate-side thin film 15 so as to correspond to the crack 23 of the semiconductor element-side thin film 22.

《実施例３》
図６は、実施例３による半導体装置の縦断面図である。本実施例における半導体装置３０には、図６に示すように、図１に示した亀裂１６や図５に示した亀裂２３の代わりに、一定の幅（図において左右方向の幅）を有する溝状空間部３１，３２が形成されている。 Example 3
FIG. 6 is a longitudinal sectional view of a semiconductor device according to the third embodiment. In the semiconductor device 30 in this embodiment, as shown in FIG. 6, a groove having a certain width (width in the left-right direction in the figure) instead of the crack 16 shown in FIG. 1 and the crack 23 shown in FIG. The space portions 31 and 32 are formed.

溝状空間部３１は、基板側薄膜１５のうち半導体素子１２との接合面（第１接合面）、具体的には接合層１３と接する領域の接合面に形成されている。また溝状空間部３１は、基板側薄膜１５の厚さ方向（図の上下方向）に、つまり接合層１３に接する表面側から、基板金属１４に接する裏面側まで基板側薄膜１５を貫通して形成されている。   The groove-shaped space 31 is formed on the bonding surface (first bonding surface) with the semiconductor element 12 in the substrate-side thin film 15, specifically, on the bonding surface in a region in contact with the bonding layer 13. Further, the groove-like space 31 penetrates the substrate-side thin film 15 in the thickness direction (vertical direction in the figure) of the substrate-side thin film 15, that is, from the surface side in contact with the bonding layer 13 to the back surface side in contact with the substrate metal 14. Is formed.

溝状空間部３２は、半導体素子側薄膜２２のうち基板１１との接合面（第２接合面）、具体的には接合層１３と接する領域の接合面に形成されている。また溝状空間部３２は、半導体素子側薄膜２２の厚さ方向（図の上下方向）に、つまり素子電極２１に接する裏面側から、接合層１３に接する表面側まで半導体素子側薄膜２２を貫通して形成されている。   The groove-like space portion 32 is formed on the bonding surface (second bonding surface) with the substrate 11 in the semiconductor element side thin film 22, specifically, the bonding surface in the region in contact with the bonding layer 13. The groove-like space 32 penetrates the semiconductor element-side thin film 22 in the thickness direction (vertical direction in the figure) of the semiconductor element-side thin film 22, that is, from the back surface side in contact with the element electrode 21 to the surface side in contact with the bonding layer 13. Is formed.

また、溝状空間部３１は、基板側薄膜１５を接合層１３側から見たとき、直線状または円形状を成している。溝状空間部３２も、半導体素子側薄膜２２を接合層１３側から見たとき、直線状または円形状を成している。また、溝状空間部３１と溝状空間部３２は上下で略同じ位置に配置されている。なお、基板１１の構成は、溝状空間部３１以外の部分では実施例１（図１）の場合と同じである。   Further, the groove-like space portion 31 has a linear or circular shape when the substrate-side thin film 15 is viewed from the bonding layer 13 side. The groove-like space 32 is also linear or circular when the semiconductor element-side thin film 22 is viewed from the bonding layer 13 side. Further, the groove-like space portion 31 and the groove-like space portion 32 are arranged at substantially the same position in the upper and lower sides. The configuration of the substrate 11 is the same as that of the first embodiment (FIG. 1) except for the groove-like space portion 31.

溝状空間部３１，３２は、例えば、基板側薄膜１５又は半導体素子側薄膜２２をそれぞれ形成した後に、エッチングなどの化学的な表面処理や研磨などの機械的な処理によって形成することが可能である。また、所定部分にマスクをつけた状態で、基板金属１４又は素子電極２１の表面にメッキすることによっても、溝状空間部３１，３２を形成することができる。   The groove-like spaces 31 and 32 can be formed by, for example, chemical surface treatment such as etching or mechanical treatment such as polishing after forming the substrate-side thin film 15 or the semiconductor element-side thin film 22, respectively. is there. Alternatively, the groove-like spaces 31 and 32 can be formed by plating the surface of the substrate metal 14 or the device electrode 21 with a mask attached to a predetermined portion.

また、半導体素子１２としては、次世代の高耐熱半導体装置に搭載されるSiCチップが用いられ、また、接合層１３としては、Agナノペーストを利用した低温高耐熱接合法によって形成されるAg接合層が用いられている。   Further, as the semiconductor element 12, a SiC chip mounted on a next-generation high heat-resistant semiconductor device is used, and as the bonding layer 13, an Ag bonding formed by a low-temperature high-heat bonding method using Ag nanopaste. Layers are used.

上記構成の半導体装置３０においては、特に半導体装置３０が低温に変化した場合でも、基板側薄膜１５より熱膨張係数の大きい基板金属１４や、半導体素子側薄膜２２より熱膨張係数の大きい素子電極２１が、溝状空間部３１，３２の近傍領域で自由に収縮することが可能である。これにより、基板側薄膜１５と基板金属１４の界面に生じる応力及びうねりと、半導体素子側薄膜２２と素子電極２１の界面に生じる応力及びうねりを抑制することができる。また、接合層１３と基板側薄膜１５の界面近傍に生じる応力、及び接合層１３と半導体素子側薄膜２２の界面近傍に生じる応力も低減でき、界面剥離や接合層１３へのクラックの発生を防止できる。その結果、半導体装置３０の信頼性を向上させることが可能である。   In the semiconductor device 30 having the above configuration, even when the semiconductor device 30 changes to a low temperature, the substrate metal 14 having a larger thermal expansion coefficient than the substrate-side thin film 15 and the element electrode 21 having a larger thermal expansion coefficient than the semiconductor element-side thin film 22. However, it is possible to freely contract in the vicinity of the groove-like space portions 31 and 32. Thereby, stress and undulation generated at the interface between the substrate-side thin film 15 and the substrate metal 14 and stress and undulation generated at the interface between the semiconductor element-side thin film 22 and the element electrode 21 can be suppressed. In addition, the stress generated near the interface between the bonding layer 13 and the substrate-side thin film 15 and the stress generated near the interface between the bonding layer 13 and the semiconductor element-side thin film 22 can be reduced, preventing the occurrence of interface peeling and cracks in the bonding layer 13. it can. As a result, the reliability of the semiconductor device 30 can be improved.

本実施例における半導体装置３０では、上述したように温度変化が加わると、基板１１と半導体素子１２の熱膨張係数差から、基板１１と接合層１３との間及び半導体素子１２と接合層１３との間にそれぞれ変位（伸長差）が生じるが、この場合、基板１１側では基板側薄膜１５の溝状空間部３１が、半導体素子１２側では半導体素子側薄膜２２の溝状空間部３２が、それぞれに大きく変形する（図において左右方向の幅が拡がる）ことによって、応力緩和を実現している。   In the semiconductor device 30 in the present embodiment, when the temperature change is applied as described above, the difference between the thermal expansion coefficients of the substrate 11 and the semiconductor element 12 causes the difference between the substrate 11 and the bonding layer 13 and the semiconductor element 12 and the bonding layer 13. In this case, the groove-like space portion 31 of the substrate-side thin film 15 is formed on the substrate 11 side, and the groove-like space portion 32 of the semiconductor-element-side thin film 22 is formed on the semiconductor element 12 side. Stress relaxation is realized by largely deforming each (the width in the left-right direction is expanded in the figure).

しかし、素子電極２１と基板金属１４の厚みや若干の材質違いから、実際のそれぞれの変形量は異なることが予想される。その結果、接合層１３にも歪が発生することになり、温度変化の繰返しによって、接合層１３の上部（半導体素子側薄膜２２付近）及び下部（基板側薄膜１５付近）にクラックが入る虞がある。   However, due to the thickness of the element electrode 21 and the substrate metal 14 and slight differences in material, the actual deformation amounts are expected to be different. As a result, the bonding layer 13 is also distorted, and cracks may occur in the upper part (near the semiconductor element side thin film 22) and the lower part (near the substrate side thin film 15) of the bonding layer 13 due to repeated temperature changes. is there.

そこで本実施例では、上述したように、溝状空間部３１と溝状空間部３２を上下で略同じ位置に配置することで、接合層１３の上部及び下部に発生したクラックを上下方向に進展させるようにし、最終的にはクラックを上下で結合させる。その結果、基板１１と半導体素子１２の熱膨張係数差による変位は、素子電極２１と基板金属１４の間で上下に結合したクラックの開閉によって吸収されることになるため、接合層１３に発生する応力を大幅に減少させることができる。   Therefore, in this embodiment, as described above, the groove-like space portion 31 and the groove-like space portion 32 are arranged at substantially the same position in the vertical direction, so that the cracks generated in the upper and lower portions of the bonding layer 13 propagate in the vertical direction. And finally the cracks are bonded up and down. As a result, the displacement due to the difference in thermal expansion coefficient between the substrate 11 and the semiconductor element 12 is absorbed by the opening and closing of the cracks coupled vertically between the element electrode 21 and the substrate metal 14, and thus occurs in the bonding layer 13. Stress can be greatly reduced.

上記のように本実施例によれば、もし接合層１３にクラックが入ったとしても、そのクラックは接合層１３の上下方向にのみ形成されるので、接合層１３を介しての半導体素子１２と基板１１との結合が維持され、接合層１３における熱・電気的な特性にはほとんど影響を与えない。これにより、特に、高耐熱性をも有する半導体装置３０を実現することができる。   As described above, according to the present embodiment, even if the bonding layer 13 is cracked, the crack is formed only in the vertical direction of the bonding layer 13. Bonding with the substrate 11 is maintained, and the thermal and electrical characteristics of the bonding layer 13 are hardly affected. Thereby, in particular, the semiconductor device 30 having high heat resistance can be realized.

《実施例４》
図７は、実施例４による半導体装置の縦断面図である。本実施例における半導体装置４０においては、基板側薄膜１５及び半導体素子側薄膜２２にそれぞれ溝状空間部３１，３２が形成されているが、これら溝状空間部３１，３２は、接合層１３に近い側の幅（図において左右方向の幅）が広く、接合層１３から離れた側の幅（図において左右方向の幅）が狭くなっている。すなわち、溝状空間部３１は縦断面が逆台形を成しており、接合層１３に接する側が幅が広く、基板金属１４に接する側の幅が狭くなっている。また、溝状空間部３２は縦断面が台形を成しており、接合層１３に接する側が幅が広く、素子電極２１に接する側の幅が狭くなっている。 Example 4
FIG. 7 is a longitudinal sectional view of a semiconductor device according to the fourth embodiment. In the semiconductor device 40 according to the present embodiment, groove-like space portions 31 and 32 are formed in the substrate-side thin film 15 and the semiconductor element-side thin film 22, respectively. These groove-like space portions 31 and 32 are formed in the bonding layer 13. The width on the near side (the width in the left-right direction in the figure) is wide, and the width on the side away from the bonding layer 13 (the width in the left-right direction in the figure) is narrow. That is, the groove-like space 31 has an inverted trapezoidal vertical cross section, and the side in contact with the bonding layer 13 is wide and the side in contact with the substrate metal 14 is narrow. Further, the groove-like space portion 32 has a trapezoidal vertical cross section, and the side in contact with the bonding layer 13 is wide and the side in contact with the element electrode 21 is narrow.

上記構成によれば、溝状空間部３１，３２の近傍では接合層１３はより自由に伸縮でき、接合層１３にクラックが入りにくくなるとともに、仮に接合層１３の上部及び下部にクラックが発生しても、それらクラックは確実に上下に進展し互いに結合する。その結果、接合層１３における熱・電気的な特性にはほとんど影響を与えることがなく、高耐熱性をも有する半導体装置３０を実現することができる。   According to the above configuration, the bonding layer 13 can expand and contract more freely in the vicinity of the groove-like space portions 31 and 32, and cracks are hardly generated in the bonding layer 13, and cracks are temporarily generated in the upper and lower portions of the bonding layer 13. Even so, these cracks will surely propagate up and down and bond together. As a result, the semiconductor device 30 having high heat resistance can be realized with little influence on the thermal and electrical characteristics of the bonding layer 13.

以上、本発明の実施例を図面により詳述してきたが、上記各実施例は本発明の例示にしか過ぎないものであり、本発明は上記各実施例の構成にのみ限定されるものではない。本発明の要旨を逸脱しない範囲の設計の変更等があっても、本発明に含まれることは勿論である。   Although the embodiments of the present invention have been described in detail with reference to the drawings, each of the above embodiments is only an example of the present invention, and the present invention is not limited only to the configuration of each of the above embodiments. . Needless to say, changes in design and the like within the scope of the present invention are included in the present invention.

１０，２０，３０，４０ 半導体装置
１１ 基板
１２ 半導体素子
１３ 接合層
１４ 基板金属
１５ 基板側薄膜
１６，２３ 亀裂
２１ 素子電極
２２ 半導体素子側薄膜
３１，３２ 溝状空間部 10, 20, 30, 40 Semiconductor device 11 Substrate 12 Semiconductor element 13 Bonding layer 14 Substrate metal 15 Substrate side thin film 16, 23 Crack 21 Element electrode 22 Semiconductor element side thin film 31, 32 Grooved space

Claims (11)

半導体素子と基板とが接合層によって接合された半導体装置であって、
前記基板には前記半導体素子との接合面に基板側薄膜が設けられ、
前記基板側薄膜には前記接合面の部分に亀裂が形成され、前記基板側薄膜は前記亀裂によって分割されて断続的に配置されていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer,
The substrate is provided with a substrate-side thin film on the bonding surface with the semiconductor element,
2. A semiconductor device according to claim 1, wherein a crack is formed in the bonding surface portion of the substrate side thin film, and the substrate side thin film is divided and intermittently arranged by the crack. 半導体素子と基板とが接合層によって接合された半導体装置であって、
前記半導体素子には前記基板との接合面に半導体素子側薄膜が設けられ、
前記半導体素子側薄膜には前記接合面の部分に亀裂が形成され、前記半導体素子側薄膜は前記亀裂によって分割されて断続的に配置されていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer,
The semiconductor element is provided with a semiconductor element-side thin film on the bonding surface with the substrate,
2. A semiconductor device according to claim 1, wherein a crack is formed in the semiconductor element side thin film at a portion of the joint surface, and the semiconductor element side thin film is divided and intermittently arranged by the crack. 半導体素子と基板とが接合層によって接合された半導体装置であって、
前記基板には前記半導体素子との第１接合面に基板側薄膜が、前記半導体素子には前記基板との第２接合面に半導体素子側薄膜がそれぞれ設けられ、
前記基板側薄膜には前記第１接合面の部分に亀裂が形成され、前記基板側薄膜は前記亀裂によって分割されて断続的に配置され、
かつ前記半導体素子側薄膜には前記第２接合面の部分に亀裂が形成され、前記半導体素子側薄膜は前記亀裂によって分割されて断続的に配置されていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer,
The substrate is provided with a substrate-side thin film on a first bonding surface with the semiconductor element, and the semiconductor element is provided with a semiconductor element-side thin film on a second bonding surface with the substrate,
In the substrate-side thin film, a crack is formed in a portion of the first joint surface, and the substrate-side thin film is divided and arranged intermittently by the crack,
The semiconductor device-side thin film has a crack formed in the second bonding surface, and the semiconductor element-side thin film is divided by the crack and disposed intermittently. 前記基板側薄膜に形成された亀裂、及び前記半導体素子側薄膜に形成された亀裂は位置が互いに一致することを特徴とする請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the positions of the crack formed in the substrate side thin film and the crack formed in the semiconductor element side thin film coincide with each other. 前記亀裂に代わりに、一定の幅を有する溝状空間部を形成したことを特徴とする請求項４に記載の半導体装置。   5. The semiconductor device according to claim 4, wherein a groove-like space having a certain width is formed instead of the crack. 前記溝状空間部は、前記接合層に近い側の幅が広く、前記接合層から離れた側の幅が狭く形成されていることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the groove-like space portion is formed to have a wide width on a side close to the bonding layer and a narrow width on a side away from the bonding layer. 前記基板側薄膜及び前記半導体素子側薄膜の少なくとも一方に前記亀裂が複数形成されている場合、隣り合う亀裂間の距離は、当該各薄膜にかかる温度差、前記基板側薄膜が表面に形成された基板金属と該基板側薄膜との熱膨張係数差、及び前記半導体素子側薄膜が形成された前記半導体素子表面の素子電極と該半導体素子側薄膜との熱膨張係数差のいずれか１つ以上に基づいて決定されることを特徴とする請求項１〜４のいずれか一項に記載の半導体装置。   When a plurality of the cracks are formed in at least one of the substrate-side thin film and the semiconductor element-side thin film, the distance between adjacent cracks is the temperature difference applied to each thin film, and the substrate-side thin film is formed on the surface Any one or more of the difference in thermal expansion coefficient between the substrate metal and the substrate-side thin film, and the difference in thermal expansion coefficient between the element electrode on the surface of the semiconductor element on which the semiconductor element-side thin film is formed and the semiconductor element-side thin film The semiconductor device according to claim 1, wherein the semiconductor device is determined based on the determination. 前記基板のうち前記基板側薄膜が形成される表面の０.２％耐力の大きさは、同一温度の下で、前記基板側薄膜の０.２％耐力と同じ若しくはそれ以下に設定されていることを特徴とする請求項１〜７のいずれか一項に記載の半導体装置。   The 0.2% yield strength of the surface of the substrate on which the substrate-side thin film is formed is set to be equal to or less than the 0.2% yield strength of the substrate-side thin film at the same temperature. The semiconductor device according to claim 1, wherein: 前記半導体素子のうち前記半導体素子側薄膜が形成される表面の０.２％耐力の大きさは、同一温度の下で、前記半導体素子側薄膜の０.２％耐力と同じ若しくはそれ以下に設定されていることを特徴とする請求項１〜７のいずれか一項に記載の半導体装置。   The 0.2% yield strength of the surface of the semiconductor element on which the semiconductor element-side thin film is formed is set to be equal to or less than the 0.2% yield strength of the semiconductor element-side thin film at the same temperature. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 半導体素子と基板とが接合層によって接合された半導体装置を製造する際に、
先ず、前記半導体素子と前記基板との接合面のうち、前記半導体素子側の接合面及び前記基板側の接合面の少なくとも一方に薄膜を形成し、
次に、機械的な圧力又は熱応力によって前記薄膜に亀裂を形成することを特徴とする半導体装置の製造方法。 When manufacturing a semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer,
First, among the bonding surfaces of the semiconductor element and the substrate, a thin film is formed on at least one of the bonding surface on the semiconductor element side and the bonding surface on the substrate side,
Next, a crack is formed in the thin film by mechanical pressure or thermal stress. 半導体素子と基板とが接合層によって接合された半導体装置を製造する際に、
先ず、前記半導体素子と前記基板との接合面のうち、前記半導体素子側の接合面及び前記基板側の接合面の少なくとも一方に薄膜を形成し、
次に、熱を付加することによって、前記薄膜と前記半導体素子との間若しくは前記薄膜と前記基板との間に化合物層を成長させ、
その後、機械的な圧力又は熱応力によって、前記化合物層から前記薄膜にかけて亀裂を形成することを特徴とする半導体装置の製造方法。 When manufacturing a semiconductor device in which a semiconductor element and a substrate are bonded by a bonding layer,
First, among the bonding surfaces of the semiconductor element and the substrate, a thin film is formed on at least one of the bonding surface on the semiconductor element side and the bonding surface on the substrate side,
Next, by applying heat, a compound layer is grown between the thin film and the semiconductor element or between the thin film and the substrate,
Thereafter, a crack is formed from the compound layer to the thin film by mechanical pressure or thermal stress.
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