JP5849935B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5849935B2
JP5849935B2 JP2012258392A JP2012258392A JP5849935B2 JP 5849935 B2 JP5849935 B2 JP 5849935B2 JP 2012258392 A JP2012258392 A JP 2012258392A JP 2012258392 A JP2012258392 A JP 2012258392A JP 5849935 B2 JP5849935 B2 JP 5849935B2
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epoxy resin
semiconductor device
semiconductor element
wire
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JP2014107375A (en
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淳二 田中
淳二 田中
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Toyota Motor Corp
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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Description

本明細書で開示する技術は、半導体素子と実装部材とを樹脂部材によって封止した半導体装置と、その製造方法に関する。   The technology disclosed in this specification relates to a semiconductor device in which a semiconductor element and a mounting member are sealed with a resin member, and a manufacturing method thereof.

特許文献１には、回路基板に装着した半導体素子を樹脂で封止した半導体装置が開示されている。この半導体装置では、回路基板の部分を、低ヤング率で応力緩和能力の高いエポキシ・シリコンエラストマー樹脂組成物で封止し、その周囲を高ヤング率で応力緩和能力の低いエポキシ樹脂組成物で封止している。特許文献１の半導体装置では、半田付け等によって回路基板に熱が加わる場合において、回路基板を応力緩和能力の高い樹脂組成物で封止することにより、半導体素子に加わる応力の緩和が図られる。また、半導体素子の周囲を高ヤング率の樹脂組成物で封止することにより、半導体素子の耐久性の確保も図られる。   Patent Document 1 discloses a semiconductor device in which a semiconductor element mounted on a circuit board is sealed with a resin. In this semiconductor device, the circuit board portion is sealed with an epoxy-silicon elastomer resin composition having a low Young's modulus and high stress relaxation capability, and the periphery thereof is sealed with an epoxy resin composition having a high Young's modulus and low stress relaxation capability. It has stopped. In the semiconductor device of Patent Document 1, when heat is applied to the circuit board by soldering or the like, stress applied to the semiconductor element can be reduced by sealing the circuit board with a resin composition having high stress relaxation capability. Further, the durability of the semiconductor element can be ensured by sealing the periphery of the semiconductor element with a resin composition having a high Young's modulus.

特開平９−３２１１８２号公報Japanese Patent Laid-Open No. 9-32182

特許文献１の半導体装置では、半導体素子と回路基板が異なる二種類の樹脂層によって封止されている。そのため、回路基板に半田付けを行う等して半導体装置を使用する間に、二種類の樹脂層同士が接合面で剥離する虞がある。   In the semiconductor device of Patent Document 1, the semiconductor element and the circuit board are sealed with two different resin layers. For this reason, there is a possibility that the two types of resin layers may be peeled off at the joint surface while the semiconductor device is used by soldering the circuit board.

本明細書では、半導体素子及び実装部材を封止する樹脂部材に剥離が生じることを抑制する技術を開示する。   In this specification, the technique which suppresses that peeling arises in the resin member which seals a semiconductor element and a mounting member is disclosed.

本明細書で開示する半導体装置は、半導体素子と、半導体素子と電気的に接続可能な実装部材と、半導体素子及び実装部材を封止している樹脂部材とを備える。樹脂部材は、シリカが混入されたエポキシ樹脂であって、第１層と、第１層と重ねて形成される第２層とを有している。第２層のシリカ濃度は、第１層のシリカ濃度より低い。半導体素子は第１層内に封止されており、実装部材の少なくとも一部は第２層内に封止されており、第１層と第２層の間の境界では、第１層中のエポキシ樹脂と第２層中のエポキシ樹脂とが架橋結合している。   A semiconductor device disclosed in this specification includes a semiconductor element, a mounting member that can be electrically connected to the semiconductor element, and a resin member that seals the semiconductor element and the mounting member. The resin member is an epoxy resin mixed with silica, and includes a first layer and a second layer formed so as to overlap the first layer. The silica concentration of the second layer is lower than the silica concentration of the first layer. The semiconductor element is sealed in the first layer, at least a part of the mounting member is sealed in the second layer, and the boundary between the first layer and the second layer is in the first layer. The epoxy resin and the epoxy resin in the second layer are cross-linked.

上記の半導体装置では、第１層と第２層の間の境界では、第１層中のエポキシ樹脂と第２層中のエポキシ樹脂とが架橋結合している。即ち、上記の半導体装置では、第１層と第２層が、架橋結合によって混然一体に結合している。従って、上記の半導体装置では、半導体素子及び実装部材を封止する樹脂部材に剥離が生じることを抑制することができる。なお、上記の「境界」は、第１層の樹脂と第２層の樹脂が混然一体と結合している部分であり、「境界」のシリカ濃度は、第１層のシリカ濃度より低く、かつ、第２層のシリカ濃度よりも高くなる。この「境界」は、第１層と第２層を含む樹脂層の断面を観察することによって確認することができる。   In the semiconductor device described above, the epoxy resin in the first layer and the epoxy resin in the second layer are cross-linked at the boundary between the first layer and the second layer. That is, in the semiconductor device described above, the first layer and the second layer are mixed together by cross-linking. Therefore, in the semiconductor device described above, it is possible to suppress the peeling of the resin member that seals the semiconductor element and the mounting member. The above “boundary” is a portion where the resin of the first layer and the resin of the second layer are mixed together and the silica concentration of the “boundary” is lower than the silica concentration of the first layer, And it becomes higher than the silica concentration of the second layer. This “boundary” can be confirmed by observing the cross section of the resin layer including the first layer and the second layer.

本明細書では、半導体素子と実装部材とを樹脂部材によって封止した半導体装置を製造する新規な方法も開示する。本明細書で開示する半導体装置の製造方法では、半導体素子を、シリカが混入された第１のエポキシ樹脂基材層中に配置するとともに、実装部材の少なくとも一部を、第１のエポキシ樹脂基材層よりも低い割合でシリカが混入されているとともに第１のエポキシ樹脂基材層と重ねて配置される第２のエポキシ樹脂基材層中に配置し、コンプレッションモールドを行う。   The present specification also discloses a novel method for manufacturing a semiconductor device in which a semiconductor element and a mounting member are sealed with a resin member. In the method for manufacturing a semiconductor device disclosed in this specification, the semiconductor element is disposed in the first epoxy resin base material layer mixed with silica, and at least a part of the mounting member is disposed on the first epoxy resin base. The silica is mixed at a lower rate than the material layer, and is placed in a second epoxy resin base material layer that is placed on top of the first epoxy resin base material layer, and compression molding is performed.

上記の製造方法では、コンプレッションモールドによって成形される樹脂部材によって、半導体素子及び実装部材が封止される。コンプレッションモールドを行うため、第１のエポキシ樹脂基材層と第２のエポキシ樹脂基材層を同時に溶融及び硬化させることができる。また、第１のエポキシ樹脂基材層と第２のエポキシ樹脂基材層は、混入されているシリカの割合は異なるが、ともに母材はエポキシ樹脂基材である。そのため、成形される樹脂部材は、第１層と、第１層に比べてシリカ濃度が低い第２層とを有することとなるが、第１層と第２層との間の境界では、第１層中のエポキシ樹脂と第２層中のエポキシ樹脂とが架橋結合する。従って、上記の製造方法によって半導体装置を製造すれば、樹脂部材に剥離が生じることを抑制することができる。   In the above manufacturing method, the semiconductor element and the mounting member are sealed with the resin member formed by the compression mold. Since the compression molding is performed, the first epoxy resin base material layer and the second epoxy resin base material layer can be simultaneously melted and cured. Further, the first epoxy resin base material layer and the second epoxy resin base material layer are different in the ratio of silica mixed therein, but the base material is an epoxy resin base material. Therefore, the resin member to be molded has a first layer and a second layer having a lower silica concentration than the first layer, but at the boundary between the first layer and the second layer, The epoxy resin in the first layer and the epoxy resin in the second layer are cross-linked. Therefore, if the semiconductor device is manufactured by the above manufacturing method, it is possible to suppress the resin member from being peeled.

第１実施例の半導体装置を模式的に示す断面図。Sectional drawing which shows the semiconductor device of 1st Example typically. 第１実施例の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of 1st Example. 第１実施例の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of 1st Example. 第１実施例の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of 1st Example. 第２実施例の半導体装置を模式的に示す断面図。Sectional drawing which shows the semiconductor device of 2nd Example typically. 第３実施例の半導体装置を模式的に示す断面図。Sectional drawing which shows the semiconductor device of 3rd Example typically. 第４実施例の半導体装置を模式的に示す断面図。Sectional drawing which shows the semiconductor device of 4th Example typically.

以下に説明する実施例の主要な特徴を列記しておく。なお、以下に記載する技術要素は、それぞれ独立した技術要素であって、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。   The main features of the embodiments described below are listed. The technical elements described below are independent technical elements and exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Absent.

（特徴１）半導体装置は、半導体素子と実装部材とを電気的に接続するワイヤをさらに備えていてもよい。ワイヤと、実装部材のうちワイヤの端部と電気的に接続する部分とが第１層内に封止されていてもよい。この構成によると、半導体素子と実装部材を電気的に接続するワイヤの全体が第１層内に封止される。ワイヤが線膨張係数の異なる２つの樹脂層（第１層、第２層）に亘って封止されることがないため、温度変化によってワイヤに大きな応力が作用し、ワイヤが破断することを抑制することができる。 (Feature 1) The semiconductor device may further include a wire that electrically connects the semiconductor element and the mounting member. The wire and the portion of the mounting member that is electrically connected to the end of the wire may be sealed in the first layer. According to this configuration, the entire wire that electrically connects the semiconductor element and the mounting member is sealed in the first layer. Since the wire is not sealed across the two resin layers (first layer and second layer) with different linear expansion coefficients, large stress acts on the wire due to temperature changes, preventing the wire from breaking can do.

（特徴２）半導体装置の製造方法では、半導体素子と実装部材とを電気的に接続するワイヤと、実装部材のうちワイヤの端部と電気的に接続する部分を、第１のエポキシ樹脂基材層中に配置し、コンプレッションモールドを行ってもよい。 (Feature 2) In the method of manufacturing a semiconductor device, a wire that electrically connects a semiconductor element and a mounting member, and a portion of the mounting member that is electrically connected to an end portion of the wire You may arrange | position in a layer and perform a compression mold.

（第１実施例）
図１に示すように、本実施例の半導体装置１０は、半導体素子２０と、リードフレーム２２、２４と、ワイヤ２８と、樹脂部材４０とを備えている。 (First embodiment)
As shown in FIG. 1, the semiconductor device 10 of this embodiment includes a semiconductor element 20, lead frames 22 and 24, wires 28, and a resin member 40.

半導体素子２０は、電力用のスイッチング素子である。本実施例では、半導体素子２０に縦型のＩＧＢＴ（Insulated Gate Bipolar Transistor）を用いている。半導体素子２０は、Ｓｉ，ＳｉＣ、ＧａＮ等により形成することができる。   The semiconductor element 20 is a power switching element. In this embodiment, a vertical IGBT (Insulated Gate Bipolar Transistor) is used for the semiconductor element 20. The semiconductor element 20 can be formed of Si, SiC, GaN, or the like.

リードフレーム２４は、半導体素子２０の裏面（図１中の下側の面）の電極（図示省略）にハンダ３０を介して接続されている。リードフレーム２４は、板状の導電性部材である。リードフレーム２４は、例えばＣｕによって形成することができる。リードフレーム２４は、半導体素子２０が発生する熱を放熱する放熱板としての機能も果たす。   The lead frame 24 is connected to electrodes (not shown) on the back surface (lower surface in FIG. 1) of the semiconductor element 20 via solder 30. The lead frame 24 is a plate-like conductive member. The lead frame 24 can be formed of Cu, for example. The lead frame 24 also functions as a heat radiating plate that radiates heat generated by the semiconductor element 20.

リードフレーム２２は、半導体素子２０から離れた位置に設けられている。リードフレーム２２も、板状の導電性部材であり、例えばＣｕによって形成することができる。本実施例では、リードフレーム２２、２４が、請求項における「実装部材」の一例である。   The lead frame 22 is provided at a position away from the semiconductor element 20. The lead frame 22 is also a plate-like conductive member, and can be formed of Cu, for example. In this embodiment, the lead frames 22 and 24 are examples of “mounting members” in the claims.

ワイヤ２８は、半導体素子２０とリードフレーム２２とを電気的に接続している。ワイヤ２８は、線状の導電性部材であって、例えばＣｕによって形成することができる。図１に示すように、ワイヤ２８は、一端が半導体素子２０の表面のメインパッド又は信号パッド（図示省略）にボンディングされるとともに、他端がリードフレーム２２の表面にボンディングされている。   The wire 28 electrically connects the semiconductor element 20 and the lead frame 22. The wire 28 is a linear conductive member, and can be formed of Cu, for example. As shown in FIG. 1, one end of the wire 28 is bonded to the main pad or signal pad (not shown) on the surface of the semiconductor element 20, and the other end is bonded to the surface of the lead frame 22.

樹脂部材４０は、半導体素子２０、リードフレーム２２、２４、及び、ワイヤ２８を封止する部材である。樹脂部材４０は、シリカが混入されたエポキシ樹脂であって、第１層４２と、第１層４２の下方に重ねて形成されている第２層４４とを有している。本実施例では、樹脂部材４０は、後で説明するコンプレッションモールド法によって成形される。   The resin member 40 is a member that seals the semiconductor element 20, the lead frames 22 and 24, and the wire 28. The resin member 40 is an epoxy resin in which silica is mixed, and includes a first layer 42 and a second layer 44 formed so as to overlap the first layer 42. In this embodiment, the resin member 40 is molded by a compression molding method that will be described later.

第１層４２は、２つの層のうちの上側の層である。第１層４２は、半導体素子２０と、ワイヤ２８の一部を封止している。第１層４２は、第２層４４に比べて、混入しているシリカの濃度が高い。第１層４２は、第２層４４に比べて、ヤング率が高く、線膨張係数が低くされている。そのため、第１層４２によって封止される半導体素子２０の衝撃耐久性、耐燃性、及び、耐湿性が確保される。また、第１層４２と半導体素子２０との密着性も確保される。   The first layer 42 is an upper layer of the two layers. The first layer 42 seals the semiconductor element 20 and a part of the wire 28. The first layer 42 has a higher concentration of mixed silica than the second layer 44. The first layer 42 has a higher Young's modulus and a lower coefficient of linear expansion than the second layer 44. Therefore, the impact durability, flame resistance, and moisture resistance of the semiconductor element 20 sealed by the first layer 42 are ensured. In addition, adhesion between the first layer 42 and the semiconductor element 20 is also ensured.

第２層４４は、２つの層のうちの下側の層であり、第１層４２と重ねて形成されている。第２層４４は、リードフレーム２２、２４と、ハンダ３０と、ワイヤ２８の一部を封止している。ただし、リードフレーム２２、２４の裏面（図１の下側）は、第２層４４の裏面側に露出しており、回路基板等にハンダを介して実装可能とされている。なお、ワイヤ２８は、第１層４２と第２層４４の双方に亘って封止されている。第２層４４は、第１層４２に比べて、混入しているシリカの濃度が低い。第２層４４は、第１層４２に比べて、ヤング率が低く、線膨張係数が高くされている。そのため、リードフレーム２２、２４を他の部材にハンダ付けする際等にリードフレーム２２、２４に熱が加わる場合でも、加熱によって発生する応力を緩和しやすくなる。そのため、半導体装置１０の実装信頼性が向上する。   The second layer 44 is a lower layer of the two layers, and is formed so as to overlap the first layer 42. The second layer 44 seals part of the lead frames 22 and 24, the solder 30, and the wire 28. However, the back surfaces (lower side in FIG. 1) of the lead frames 22 and 24 are exposed on the back surface side of the second layer 44, and can be mounted on a circuit board or the like via solder. The wire 28 is sealed across both the first layer 42 and the second layer 44. The second layer 44 has a lower concentration of mixed silica than the first layer 42. The second layer 44 has a lower Young's modulus and a higher coefficient of linear expansion than the first layer 42. Therefore, even when heat is applied to the lead frames 22 and 24 when the lead frames 22 and 24 are soldered to other members, the stress generated by heating is easily relieved. Therefore, the mounting reliability of the semiconductor device 10 is improved.

第１層４２と第２層４４との間には、境界４３が存在する。境界４３のシリカ濃度は、第１層４２のシリカ濃度よりも低く、かつ、第２層４４のシリカ濃度よりも高い。境界４３では、第１層４２中のエポキシ樹脂と第２層４４中のエポキシ樹脂とが架橋結合している。即ち、本実施例の半導体装置１０では、第１層４２と第２層４４は混然一体に結合している。従って、本実施例の半導体装置１０では、使用に伴ってリードフレーム２２、２４に熱が加わる場合であっても、樹脂部材４０に剥離が生じることを抑制することができる。なお、上記境界４３は、第１層４２と第２層４４を含む樹脂層の断面を観察することによって確認することができる。   A boundary 43 exists between the first layer 42 and the second layer 44. The silica concentration at the boundary 43 is lower than the silica concentration of the first layer 42 and higher than the silica concentration of the second layer 44. At the boundary 43, the epoxy resin in the first layer 42 and the epoxy resin in the second layer 44 are cross-linked. That is, in the semiconductor device 10 of the present embodiment, the first layer 42 and the second layer 44 are mixed together. Therefore, in the semiconductor device 10 of the present embodiment, it is possible to prevent the resin member 40 from peeling even when heat is applied to the lead frames 22 and 24 with use. The boundary 43 can be confirmed by observing the cross section of the resin layer including the first layer 42 and the second layer 44.

次いで、図２〜図４を参照して、本実施例の半導体装置１０の製造方法について説明する。まず、図２に示すように、コンプレッションモールド用の下側型枠５０を用意する。下側型枠５０は、金属製の型枠であって、上面に凹部が形成されている。下側型枠５０は、予め１７０℃程度の高温に加熱されている。   Next, with reference to FIGS. 2 to 4, a method for manufacturing the semiconductor device 10 of this example will be described. First, as shown in FIG. 2, a lower mold 50 for a compression mold is prepared. The lower mold 50 is a metal mold, and has a recess formed on the upper surface. The lower mold 50 is preheated to a high temperature of about 170 ° C.

次いで、下側型枠５０の凹部内に、シリカが混入された第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２を配置する。第１のエポキシ樹脂基材６０と、第２のエポキシ樹脂基材６２とは、上下２層に配置される。図に示すように、第２のエポキシ樹脂基材６２の層が、第１のエポキシ樹脂基材６０の層よりも上側になるように配置される。第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２は、ともに粒状の樹脂基材である。第１のエポキシ樹脂基材６０の層は、第２のエポキシ樹脂基材６２の層に比べて、シリカの混入割合が高い。本実施例では、シリカは、粒状の第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２の内部に混入している。他の例では、粒状の第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２とは別の粒状シリカが混入されていてもよい。   Next, the first epoxy resin base material 60 and the second epoxy resin base material 62 mixed with silica are disposed in the recesses of the lower mold 50. The 1st epoxy resin base material 60 and the 2nd epoxy resin base material 62 are arrange | positioned at two upper and lower layers. As shown in the figure, the layer of the second epoxy resin base material 62 is disposed so as to be above the layer of the first epoxy resin base material 60. The first epoxy resin substrate 60 and the second epoxy resin substrate 62 are both granular resin substrates. The layer of the first epoxy resin base material 60 has a higher silica mixing ratio than the layer of the second epoxy resin base material 62. In this embodiment, silica is mixed inside the granular first epoxy resin base material 60 and second epoxy resin base material 62. In another example, granular silica different from the granular first epoxy resin substrate 60 and the second epoxy resin substrate 62 may be mixed.

下側型枠５０の凹部内に、第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２を配置して、所定時間（例えば３０秒）が経過すると、下側型枠５０の熱によって、第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２とが溶融し、液状になる。その結果、図３に示すように、下側型枠５０の凹部内には、第１溶湯６４と第２溶湯６６とが上下２層に形成される。下側の第１溶湯６４は、第１のエポキシ樹脂基材６０の層が溶融してできた液状層である。上側の第２溶湯６６は、第２のエポキシ樹脂基材６２が溶融してできた液状層である。   When the first epoxy resin substrate 60 and the second epoxy resin substrate 62 are arranged in the recess of the lower mold 50 and a predetermined time (for example, 30 seconds) elapses, the heat of the lower mold 50 As a result, the first epoxy resin substrate 60 and the second epoxy resin substrate 62 are melted and become liquid. As a result, as shown in FIG. 3, the first molten metal 64 and the second molten metal 66 are formed in two upper and lower layers in the recess of the lower mold 50. The lower first molten metal 64 is a liquid layer formed by melting the layer of the first epoxy resin substrate 60. The upper second molten metal 66 is a liquid layer formed by melting the second epoxy resin base material 62.

第１のエポキシ樹脂基材６０及び第２のエポキシ樹脂基材６２が溶融して第１溶湯６４と第２溶湯６６に変化する間に、図３に示す上側型枠５２を用意する。上側型枠５２は、金属製の型枠であって、下側型枠５０の凹部を閉塞可能な板状に形成されている。上側型枠５２の下面には、両面に粘着性を備える樹脂シート５４を介して、半導体素子２０、リードフレーム２２、２４、ワイヤ２８が備えられている。図３に示すように、半導体素子２０とリードフレーム２４はハンダ３０を介して予め接続されている。また、半導体素子２０とリードフレーム２２も、ワイヤ２８を介して予め接続されている。また、図３では、樹脂シート５４の下面には、半導体素子２０、リードフレーム２２、２４、ワイヤ２８が２組分備えられている。   While the first epoxy resin substrate 60 and the second epoxy resin substrate 62 are melted and changed into the first molten metal 64 and the second molten metal 66, the upper mold 52 shown in FIG. 3 is prepared. The upper mold 52 is a metal mold, and is formed in a plate shape that can close the recess of the lower mold 50. The lower surface of the upper mold 52 is provided with a semiconductor element 20, lead frames 22 and 24, and wires 28 via a resin sheet 54 having adhesiveness on both sides. As shown in FIG. 3, the semiconductor element 20 and the lead frame 24 are connected in advance via solder 30. The semiconductor element 20 and the lead frame 22 are also connected in advance via a wire 28. In FIG. 3, two sets of semiconductor elements 20, lead frames 22 and 24, and wires 28 are provided on the lower surface of the resin sheet 54.

次いで、コンプレッションモールドを行う。即ち、下面に半導体素子２０、リードフレーム２２、２４、及び、ワイヤ２８が備えられた上側型枠５２を、下側型枠５０に向けて降下させる。上側型枠５２を降下させると、上側型枠５２の下面に備えられた半導体素子２０、リードフレーム２２、２４、及び、ワイヤ２８が、第１溶湯６４内及び第２溶湯６６内に浸漬する（図４参照）。その際、半導体素子２０及びワイヤ２８の一部が、第１溶湯６４内に浸漬するとともに、リードフレーム２２、２４、ハンダ３０、及び、ワイヤ２８の一部が、第２溶湯６６内に浸漬する。   Next, compression molding is performed. That is, the upper mold 52 having the semiconductor element 20, the lead frames 22 and 24, and the wires 28 on the lower surface is lowered toward the lower mold 50. When the upper mold 52 is lowered, the semiconductor element 20, the lead frames 22, 24 and the wires 28 provided on the lower surface of the upper mold 52 are immersed in the first molten metal 64 and the second molten metal 66 ( (See FIG. 4). At that time, the semiconductor element 20 and a part of the wire 28 are immersed in the first molten metal 64, and the lead frames 22 and 24, the solder 30, and a part of the wire 28 are immersed in the second molten metal 66. .

各部材を第１溶湯６４内及び第２溶湯６６内に浸漬させた状態で、さらに、上側型枠５２を降下させる方向に付勢すると、第１溶湯６４及び第２溶湯６６に成形圧力が付加される。その状態で、所定時間（例えば１分）が経過すると、下側型枠５０の熱によって、第１溶湯６４及び第２溶湯６６がさらに加熱され、第１溶湯６４及び第２溶湯６６が硬化する。第１溶湯６４及び第２溶湯６６が硬化することにより、図４に示すように、樹脂部材４０（第１層４２及び第２層４４）が形成される。即ち、半導体素子２０及びワイヤ２８の一部が、第１層４２によって封止され、リードフレーム２２、２４、ハンダ３０、及び、ワイヤ２８の一部が、第２層４４によって封止される。また、第１層４２と第２層４４との間には、境界４３が形成される。   If each member is immersed in the first molten metal 64 and the second molten metal 66 and further energized in the direction in which the upper mold 52 is lowered, a molding pressure is applied to the first molten metal 64 and the second molten metal 66. Is done. In this state, when a predetermined time (for example, 1 minute) elapses, the first molten metal 64 and the second molten metal 66 are further heated by the heat of the lower mold 50, and the first molten metal 64 and the second molten metal 66 are cured. . As the first molten metal 64 and the second molten metal 66 are cured, the resin member 40 (the first layer 42 and the second layer 44) is formed as shown in FIG. That is, a part of the semiconductor element 20 and the wire 28 is sealed with the first layer 42, and a part of the lead frames 22, 24, the solder 30, and the wire 28 is sealed with the second layer 44. A boundary 43 is formed between the first layer 42 and the second layer 44.

その後、成形品を下側型枠５０から抜き、ダイシングを行うことにより、本実施例の半導体装置１０（図１参照）が完成する。   Thereafter, the molded product is removed from the lower mold 50 and diced to complete the semiconductor device 10 of this embodiment (see FIG. 1).

以上、本実施例の半導体装置１０とその製造方法について説明した。上記の通り、本実施例の製造方法では、コンプレッションモールドによって成形される樹脂部材４０によって、半導体素子２０及びリードフレーム２２、２４が封止される。コンプレッションモールドを行うため、第１のエポキシ樹脂基材６０の層と第２のエポキシ樹脂基材６２の層を同時に溶融及び凝固させることができる。また、第１のエポキシ樹脂基材６０の層と第２のエポキシ樹脂基材６２の層は、混入されているシリカの割合は異なるが、ともに母材はエポキシ樹脂基材である。そのため、成形される樹脂部材４０は、第１層４２と、第１層４２に比べてシリカ濃度が低い第２層４４とを有することとなる。第１層４２と第２層４４との間の境界４３では、第１層４２中のエポキシ樹脂と第２層４４中のエポキシ樹脂とが架橋結合する。従って、上記の方法によって半導体装置１０を製造すれば、樹脂部材４０に剥離が生じることを抑制することができる。   The semiconductor device 10 and the manufacturing method thereof according to the present embodiment have been described above. As described above, in the manufacturing method of the present embodiment, the semiconductor element 20 and the lead frames 22 and 24 are sealed by the resin member 40 that is molded by the compression mold. Since the compression molding is performed, the layer of the first epoxy resin substrate 60 and the layer of the second epoxy resin substrate 62 can be simultaneously melted and solidified. Further, the first epoxy resin base material 60 layer and the second epoxy resin base material 62 layer have different silica ratios, but the base material is an epoxy resin base material. Therefore, the molded resin member 40 includes a first layer 42 and a second layer 44 having a lower silica concentration than the first layer 42. At the boundary 43 between the first layer 42 and the second layer 44, the epoxy resin in the first layer 42 and the epoxy resin in the second layer 44 are cross-linked. Therefore, if the semiconductor device 10 is manufactured by the above method, it is possible to prevent the resin member 40 from being peeled off.

（第２実施例）
図５を参照して、第２実施例の半導体装置１００について、第１実施例と異なる点を中心に説明する。本実施例の半導体装置１００は、リードフレーム１２２の形状が第１実施例とは異なる。図５に示すように、本実施例のリードフレーム１２２は、その断面形状において、両端部が鉤状に曲げられた形状に形成されている。そのため、リードフレーム１２２のうち、ワイヤ２８の端部がボンディングされる部分が、第１実施例よりも上方に位置している。従って、本実施例では、第１層４２は、半導体素子２０のみならず、リードフレーム１２２のうちのワイヤ２８の端部がボンディングされる部分と、ワイヤ２８の全部をさらに封止する。本実施例では、ワイヤ２８は、第１層４２によってのみ封止されており、第１層４２と第２層４４の２層に亘って封止されることはない。そのため、本実施例の半導体装置１００によると、温度変化によってワイヤ２８に大きな応力が作用し、ワイヤ２８が破断することを抑制することができる。 (Second embodiment)
With reference to FIG. 5, the semiconductor device 100 of the second embodiment will be described focusing on differences from the first embodiment. In the semiconductor device 100 of this embodiment, the shape of the lead frame 122 is different from that of the first embodiment. As shown in FIG. 5, the lead frame 122 of the present embodiment is formed in a shape in which both end portions are bent in a hook shape in the cross-sectional shape thereof. Therefore, the portion of the lead frame 122 where the end of the wire 28 is bonded is positioned above the first embodiment. Therefore, in the present embodiment, the first layer 42 further seals not only the semiconductor element 20 but also the portion of the lead frame 122 where the end of the wire 28 is bonded and the entire wire 28. In this embodiment, the wire 28 is sealed only by the first layer 42, and is not sealed across the two layers of the first layer 42 and the second layer 44. Therefore, according to the semiconductor device 100 of the present embodiment, it is possible to prevent the wire 28 from breaking due to a large stress acting on the wire 28 due to a temperature change.

本実施例の半導体装置１００の製造方法も、基本的には第１実施例の半導体装置１０の製造方法（図２〜図４参照）と共通する。ただし、本実施例では、上側型枠５２に備えられた各部材を第１溶湯６４内及び第２溶湯６６内に浸漬させると、半導体素子２０、ワイヤ２８、及び、リードフレーム１２２のうちのワイヤ２８の端部がボンディングされる部分が第１溶湯６４内に浸漬するとともに、リードフレーム２４、ハンダ３０、及び、リードフレーム１２２の他の部分が、第２溶湯６６内に浸漬する。   The method for manufacturing the semiconductor device 100 according to the present embodiment is basically the same as the method for manufacturing the semiconductor device 10 according to the first embodiment (see FIGS. 2 to 4). However, in this embodiment, when each member provided in the upper mold 52 is immersed in the first molten metal 64 and the second molten metal 66, the wire of the semiconductor element 20, the wire 28, and the lead frame 122 is used. A portion to which the end portion of 28 is bonded is immersed in the first molten metal 64, and the lead frame 24, the solder 30, and other portions of the lead frame 122 are immersed in the second molten metal 66.

（第３実施例）
図６を参照して、第３実施例の半導体装置２００について、第１実施例と異なる点を中心に説明する。本実施例の半導体装置２００は、樹脂部材２４０の構造が第１実施例とは異なる。本実施例の樹脂部材２４０も、第１実施例の樹脂部材４０と同様に、シリカが混入されたエポキシ樹脂であるが、図６に示すように、第１層２４２、第２層２４３、第３層２４４の３層を重ねて形成した構造である点が第１実施例の樹脂部材４０とは異なる。 (Third embodiment)
With reference to FIG. 6, the semiconductor device 200 of the third embodiment will be described focusing on differences from the first embodiment. The semiconductor device 200 of the present embodiment is different from the first embodiment in the structure of the resin member 240. Similarly to the resin member 40 of the first embodiment, the resin member 240 of this embodiment is also an epoxy resin mixed with silica, but as shown in FIG. 6, the first layer 242, the second layer 243, the second layer It differs from the resin member 40 of the first embodiment in that it has a structure in which three layers of three layers 244 are overlapped.

第１層２４２は、３つの層のうちの一番上側の層である。第１層２４２は、半導体素子２０と、ワイヤ２８の一部を封止している。第１層２４２のシリカ濃度は、３つの層のうち最も高い。そのため、第１層２４２は、３つの層のうち、最もヤング率が高く、最も線膨張係数が低い。   The first layer 242 is the uppermost layer of the three layers. The first layer 242 seals the semiconductor element 20 and a part of the wire 28. The silica concentration of the first layer 242 is the highest of the three layers. Therefore, the first layer 242 has the highest Young's modulus and the lowest linear expansion coefficient among the three layers.

第２層２４３は、３つの層のうちの上から２番目の層である。第２層２４３は、ハンダ３０と、ワイヤ２８の一部を封止している。第２層２４３のシリカ濃度は、第３層２４４のシリカ濃度に比べて高いが、第１層２４２のシリカ濃度に比べて低い。そのため、第２層２４３は、３つの層のうち、２番目にヤング率が高く、２番目に線膨張係数が低い。   The second layer 243 is the second layer from the top of the three layers. The second layer 243 seals the solder 30 and a part of the wire 28. The silica concentration of the second layer 243 is higher than the silica concentration of the third layer 244, but is lower than the silica concentration of the first layer 242. Therefore, the second layer 243 has the second highest Young's modulus among the three layers, and the second lowest coefficient of linear expansion.

第３層２４４は、３つの層のうちの一番下側の層である。第３層２４４は、リードフレーム２２、２４を封止している。第３層のシリカ濃度は、３つの層のうち最も低い。そのため、第３層２４４は、３つの層のうち、最もヤング率が低く、最も線膨張係数が高い。   The third layer 244 is the lowest layer of the three layers. The third layer 244 seals the lead frames 22 and 24. The silica concentration of the third layer is the lowest of the three layers. Therefore, the third layer 244 has the lowest Young's modulus and the highest linear expansion coefficient among the three layers.

第１層２４２と第２層２４３との間には、境界２４５が存在する。境界２４５のシリカ濃度は、第１層２４２のシリカ濃度よりも低く、かつ、第２層２４３のシリカ濃度よりも高い。境界２４５では、第１層２４２中のエポキシ樹脂と第２層２４３中のエポキシ樹脂とが架橋結合し、混然一体に結合している。   A boundary 245 exists between the first layer 242 and the second layer 243. The silica concentration at the boundary 245 is lower than the silica concentration of the first layer 242 and higher than the silica concentration of the second layer 243. At the boundary 245, the epoxy resin in the first layer 242 and the epoxy resin in the second layer 243 are cross-linked and bonded together.

同様に、第２層２４３と第３層２４４との間にも、境界２４６が存在する。境界２４６のシリカ濃度は、第２層２４３のシリカ濃度よりも低く、かつ、第３層２４４のシリカ濃度よりも高い。境界２４６では、第２層２４３中のエポキシ樹脂と第３層２４４中のエポキシ樹脂とが架橋結合し、混然一体に結合している。   Similarly, a boundary 246 exists between the second layer 243 and the third layer 244. The silica concentration at the boundary 246 is lower than the silica concentration of the second layer 243 and higher than the silica concentration of the third layer 244. At the boundary 246, the epoxy resin in the second layer 243 and the epoxy resin in the third layer 244 are cross-linked and bonded together.

上記の通り、本実施例の半導体装置２００では、上記の３つの層（第１層２４２、第２層２４３、第３層２４４）によって各部材を封止している。第１層２４２、第２層２４３、第３層２４４の順に、混入するシリカ濃度が漸次低くなっているため、シリカ濃度の異なる２層（第１層４２、第２層４４）の樹脂部材４０で各部材を封止する場合に比べて、各層間に生じる応力をより小さくすることができる。各層間に大きな応力が生じにくくなるため、各層の剥離をより効果的に抑制することができる。   As described above, in the semiconductor device 200 of this embodiment, each member is sealed by the three layers (first layer 242, second layer 243, and third layer 244). Since the silica concentration to be mixed is gradually decreased in the order of the first layer 242, the second layer 243, and the third layer 244, the resin member 40 of two layers (first layer 42 and second layer 44) having different silica concentrations. As compared with the case of sealing each member, the stress generated between the layers can be made smaller. Since it becomes difficult to generate a large stress between each layer, peeling of each layer can be more effectively suppressed.

本実施例の半導体装置２００の製造方法も、基本的には第１実施例の半導体装置１０の製造方法（図２〜図４参照）と共通する。ただし、本実施例では、下側型枠５０の凹部内に、シリカの混入割合の異なる３種のエポキシ樹脂基材を３層に重ねて配置する点が第１実施例とは異なる。このときに３層に重ねて配置したエポキシ樹脂基材が、半導体装置２００を形成した際に、第１層２４２、第２層２４３、第３層２４４を形成する。   The manufacturing method of the semiconductor device 200 of this embodiment is also basically the same as the manufacturing method of the semiconductor device 10 of the first embodiment (see FIGS. 2 to 4). However, this embodiment is different from the first embodiment in that three types of epoxy resin base materials having different silica mixing ratios are arranged in three layers in the concave portion of the lower mold 50. At this time, when the semiconductor device 200 is formed by the epoxy resin base material disposed so as to overlap the three layers, the first layer 242, the second layer 243, and the third layer 244 are formed.

（第４実施例）
図７を参照して、第４実施例の半導体装置３００について、第１実施例と異なる点を中心に説明する。本実施例の半導体装置３００も、樹脂部材３４０の構造が第１実施例とは異なる。本実施例の樹脂部材３４０も、第１実施例の樹脂部材４０と同様に、シリカが混入されたエポキシ樹脂であるが、図７に示すように、第１層３４２、第２層３４４の形状が第１実施例の樹脂部材４０とは異なる。 (Fourth embodiment)
With reference to FIG. 7, a semiconductor device 300 according to the fourth embodiment will be described focusing on differences from the first embodiment. Also in the semiconductor device 300 of this embodiment, the structure of the resin member 340 is different from that of the first embodiment. Similarly to the resin member 40 of the first embodiment, the resin member 340 of the present embodiment is an epoxy resin mixed with silica, but as shown in FIG. 7, the shapes of the first layer 342 and the second layer 344 are the same. Is different from the resin member 40 of the first embodiment.

本実施例では、第１層３４２は、半導体素子２０、ハンダ３０、及び、ワイヤ２８のうち半導体素子２０と接続する側の端部の周囲のみを封止している。第１層３４２は、リードフレーム２２及びワイヤ２８の他の部分を封止していない。第１層３４２は、半導体素子２０とハンダ３０の周囲のみを封止する略半球形状に形成されている。第１層３４２のシリカ濃度は、第２層３４４のシリカ濃度よりも高い。   In the present embodiment, the first layer 342 seals only the periphery of the end portion of the semiconductor element 20, the solder 30, and the wire 28 on the side connected to the semiconductor element 20. The first layer 342 does not seal the lead frame 22 and other portions of the wire 28. The first layer 342 is formed in a substantially hemispherical shape that seals only the periphery of the semiconductor element 20 and the solder 30. The silica concentration of the first layer 342 is higher than the silica concentration of the second layer 344.

第２層３４４は、第１層３４２の周囲、リードフレーム２２、及び、ワイヤ２８の他の部分を封止している。第２層３４４のシリカ濃度は、第１層３４２のシリカ濃度よりも低い。   The second layer 344 seals the periphery of the first layer 342, the lead frame 22, and other portions of the wire 28. The silica concentration of the second layer 344 is lower than the silica concentration of the first layer 342.

本実施例でも、第１層３４２と第２層３４４との間には、境界３４３が存在する。境界層３４３のシリカ濃度は、第１層３４２のシリカ濃度よりも低く、かつ、第２層３４４のシリカ濃度よりも高い。境界３４３では、第１層３４２中のエポキシ樹脂と第２層３４４中のエポキシ樹脂とが架橋結合している。   Also in this embodiment, a boundary 343 exists between the first layer 342 and the second layer 344. The silica concentration of the boundary layer 343 is lower than the silica concentration of the first layer 342 and higher than the silica concentration of the second layer 344. At the boundary 343, the epoxy resin in the first layer 342 and the epoxy resin in the second layer 344 are cross-linked.

本実施例の半導体装置３００でも、第１実施例の半導体装置３００と同様の作用効果を発揮することができる。   The semiconductor device 300 according to the present embodiment can also exhibit the same effects as the semiconductor device 300 according to the first embodiment.

本実施例の半導体装置３００を製造する場合は、第１実施例のようなコンプレッションモールド法によらなくてもよい。本実施例では、シリカ濃度の異なる２種類の液状エポキシ樹脂を用いて、ポッティング法によって第１層３４２及び第２層３４４を形成する。   When manufacturing the semiconductor device 300 of the present embodiment, it is not necessary to use the compression molding method as in the first embodiment. In this embodiment, the first layer 342 and the second layer 344 are formed by potting using two types of liquid epoxy resins having different silica concentrations.

以上、本明細書に開示の技術の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。例えば、以下の変形例を採用してもよい。   As mentioned above, although the specific example of the technique disclosed by this specification was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, the following modifications may be adopted.

（変形例１）上記の実施例では、樹脂部材４０（２４０、３４０）は、半導体素子２０と、リードフレーム２２、２４を封止している。これには限られず、樹脂部材４０（２４０、３４０）は、半導体素子２０に加えて、半導体素子２０が装着された回路基板の少なくとも一部を封止してもよい。本変形例では、回路基板が「実装部材」の一例である。 (Modification 1) In the above embodiment, the resin member 40 (240, 340) seals the semiconductor element 20 and the lead frames 22, 24. The resin member 40 (240, 340) may seal at least a part of the circuit board on which the semiconductor element 20 is mounted in addition to the semiconductor element 20. In the present modification, the circuit board is an example of a “mounting member”.

（変形例２）上記の実施例では、樹脂部材４０（２４０、３４０）は、シリカ濃度の異なる２層構造（又は３層構造）を有している。これには限られず、樹脂部材は、シリカ濃度の異なる４層以上の層を有していてもよい。 (Modification 2) In the above embodiment, the resin member 40 (240, 340) has a two-layer structure (or a three-layer structure) with different silica concentrations. The resin member is not limited to this, and the resin member may have four or more layers having different silica concentrations.

また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

１０：半導体装置
２０：半導体素子
２２、２４：リードフレーム
２８：ワイヤ
３０：ハンダ
４０：樹脂部材
４２：第１層
４３：境界
４４：第２層
５０：下側型枠
５２：上側型枠
５４：樹脂シート
６０：第１のエポキシ樹脂基材
６２：第２のエポキシ樹脂基材
６４：第１溶湯
６６：第２溶湯
１００：半導体装置
１２２：リードフレーム
２００：半導体装置
２４０：樹脂部材
２４２：第１層
２４３：第２層
２４４：第３層
２４５：境界
２４６：境界
３００：半導体装置
３４０：樹脂部材
３４２：第１層
３４３：境界
３４４：第２層 10: Semiconductor device 20: Semiconductor element 22, 24: Lead frame 28: Wire 30: Solder 40: Resin member 42: First layer 43: Boundary 44: Second layer 50: Lower mold 52: Upper mold 54: Resin sheet 60: first epoxy resin base material 62: second epoxy resin base material 64: first molten metal 66: second molten metal 100: semiconductor device 122: lead frame 200: semiconductor device 240: resin member 242: first Layer 243: Second layer 244: Third layer 245: Boundary 246: Boundary 300: Semiconductor device 340: Resin member 342: First layer 343: Boundary 344: Second layer

Claims (4)

半導体装置であって、
半導体素子と、
半導体素子と電気的に接続可能な実装部材と、
半導体素子及び実装部材を封止している樹脂部材と、を備え、
樹脂部材は、シリカが混入されたエポキシ樹脂であって、第１層と、第１層と重ねて形成される第２層とを有しており、
第２層のシリカ濃度は、第１層のシリカ濃度より低く、
半導体素子は第１層内に封止されており、
実装部材の少なくとも一部は第２層内に封止されており、
第１層と第２層の間の境界では、第１層中のエポキシ樹脂と第２層中のエポキシ樹脂とが架橋結合している、
ことを特徴とする半導体装置。 A semiconductor device,
A semiconductor element;
A mounting member electrically connectable to the semiconductor element;
A resin member sealing the semiconductor element and the mounting member,
The resin member is an epoxy resin mixed with silica, and has a first layer and a second layer formed to overlap the first layer,
The silica concentration of the second layer is lower than the silica concentration of the first layer,
The semiconductor element is sealed in the first layer,
At least a part of the mounting member is sealed in the second layer,
At the boundary between the first layer and the second layer, the epoxy resin in the first layer and the epoxy resin in the second layer are cross-linked,
A semiconductor device. 半導体素子と実装部材とを電気的に接続するワイヤをさらに備え、
ワイヤと、実装部材のうちワイヤの端部と電気的に接続する部分とが第１層内に封止されている、
ことを特徴とする請求項１に記載の半導体装置。 A wire that electrically connects the semiconductor element and the mounting member;
The wire and the portion of the mounting member that is electrically connected to the end of the wire are sealed in the first layer.
The semiconductor device according to claim 1. 半導体素子と実装部材とを樹脂部材によって封止した半導体装置を製造する方法であって、
半導体素子を、シリカが混入された第１のエポキシ樹脂基材層中に配置するとともに、実装部材の少なくとも一部を、第１のエポキシ樹脂基材層よりも低い割合でシリカが混入されているとともに第１のエポキシ樹脂基材層と重ねて配置される第２のエポキシ樹脂基材層中に配置し、コンプレッションモールドを行う、
ことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a semiconductor element and a mounting member are sealed with a resin member,
The semiconductor element is disposed in the first epoxy resin base material layer mixed with silica, and at least a part of the mounting member is mixed with silica at a lower rate than the first epoxy resin base material layer. And placing it in the second epoxy resin base material layer that is placed on top of the first epoxy resin base material layer, and performing a compression molding.
A method for manufacturing a semiconductor device. 半導体素子と実装部材とを電気的に接続するワイヤと、実装部材のうちワイヤの端部と電気的に接続する部分を、第１のエポキシ樹脂基材層中に配置し、コンプレッションモールドを行う、
ことを特徴とする請求項３に記載の半導体装置の製造方法。 A wire that electrically connects the semiconductor element and the mounting member, and a portion of the mounting member that is electrically connected to the end of the wire are disposed in the first epoxy resin base material layer, and compression molding is performed.
The method of manufacturing a semiconductor device according to claim 3.
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