JP5239939B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to data reading from a semiconductor memory, and more particularly to a semiconductor memory having a burst read function.

  Burst read, which continuously reads out a series of data stored in a memory area in a conventional flash memory, is an operation of continuously reading stored data in synchronization with a clock input from the outside. A flash memory whose access time operates asynchronously with respect to an external input clock requires a configuration for outputting data in synchronization with the external input clock.

  When data is read from a memory element constituting the memory area of the flash memory, a time (access time) required for reading the first data corresponding to the instruction from the memory element after the read command is input has elapsed. Waiting time occurs. Therefore, by setting the number of wait cycles indicating the waiting time from when a burst read command indicating burst read is input to the flash memory until the first data corresponding to the command is output, the flash memory, Synchronize with an external device that reads data stored in the flash memory. This wait cycle is referred to as first latency. The first latency is determined by a minimum integer including a real number calculated by (access time) / (period of external input clock). Therefore, it is necessary to set the first latency according to the period of the external input clock.

In addition, in a flash memory that performs a burst read command, a plurality of data is read by one read operation, and a plurality of new data is read while a plurality of read data is being output. Outputting.
The flash memory has an address boundary, and the address boundary depends on the configuration of the memory cell array (configuration of word lines and bit lines) and the configuration of the sense amplifier that controls the read data. Data cannot be read from the memory cell array at a time across the address boundary, and the data before the address boundary and the data after the address boundary are read in two steps with the address boundary as a boundary. Become.

Since the number of valid data before the address boundary (data to be burst output to the outside) differs depending on the start address of a series of data to be read, it is necessary to output the valid data read before the address boundary depending on the burst read command. The time may be shorter than the time (access time) required for reading data after the address boundary, and in this case, a wait cycle for waiting for completion of data reading occurs. Hereinafter, this wait cycle is referred to as a word boundary wait cycle.
In the flash memory, a data output waiting time occurs in a burst read due to a word boundary wait cycle that occurs at the first address boundary at the start of reading. At the subsequent address boundaries, while the read data is being output, the next data to be output is read out and prepared for output, so the data is continuously output without causing a word boundary wait cycle. Output.

  For example, in the semiconductor memory described in Patent Document 1, a first latency of 5 cycles from when a burst read command is input to when the first read data is output occurs, and then data read following the first address boundary is read. A word boundary wait cycle occurs to wait for completion, and the output of the read data is interrupted during the word boundary wait cycle, that is, until the reading of data across the first address boundary is completed.

JP 2007-80410 A

As described above, when a word boundary wait cycle occurs during burst reading, semiconductor memory outputs invalid data so that an external device reading data from the semiconductor memory does not read invalid data. It is necessary to inform that it is correct data. Therefore, the semiconductor memory outputs a ready signal RDY or the like for indicating whether or not the output data is valid data, and notifies the external device that reads the data that valid data is being output. Data transmission using handshaking is performed.
An interface circuit of an external device that reads data from a semiconductor memory becomes complicated because of handshaking, and the circuit scale increases, which hinders speedup.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory in which valid data is continuously output in synchronism with a clock without being interrupted by a first address boundary in a burst read operation. .

  In order to solve the above problems, the present invention provides a semiconductor memory having a burst read function for sequentially outputting data stored in continuous memory areas of a provided memory cell array in synchronization with an input clock signal. When the burst read command is input, the number of clock cycles required to output the first data read from the memory area from the start address to the first address boundary included in the burst read command; When a wait cycle is set according to a preset first latency, the cycle count unit that counts the set wait cycle in synchronization with the clock signal, and when the burst read command is input, 1 data read from the memory area and the first The second data stored immediately after the dress boundary is continuously read from the memory area, and when the count of the cycle count unit is completed, the first data and the second data are A cycle control unit that starts output to the outside in successive clock cycles in synchronization with a clock signal, and the address boundary is included in one reading of the data depending on the configuration of the memory cell array. This is a semiconductor memory characterized in that it is an address boundary that cannot.

  In the present invention described above, the cycle count unit may include a first latency counter that counts the first latency in synchronization with the clock signal, the number of cycles of the first latency, and the first data A boundary latency counter that counts the timing at which the data corresponding to the burst read is output to the outside in synchronization with the clock signal based on the number of cycles required for output, the first latency counter and the boundary latency The counter is operated in order, the wait cycle from when the burst read command is input until the output of data corresponding to the command is started is counted, and the value counted by the boundary latency counter is the first When outputting data When the number of cycles required is equal to or greater than the number of cycles corresponding to the time for reading the second data from the memory area, the number of cycles required to output the first data is “0”. If the number of cycles is less than the number of cycles for reading the data, the difference between the number of cycles required to output the first data and the number of cycles corresponding to the time for reading the second data from the memory area And

  In the invention described above, the first latency is set according to a period of the clock signal and a data read time of the memory cell array.

  Further, the present invention is characterized in that, in the above-described invention, the boundary latency counter is set with the boundary latency according to a lower bit of an address included in the burst read instruction.

  According to this invention, in the semiconductor memory, the cycle count unit calculates and sets a wait cycle corresponding to the start address specified by the input burst read command, and the cycle control unit sets the read data according to the wait cycle. Control the output. The wait cycle set in accordance with the start address is the number of cycles required for reading the first read data and the second read data in burst read, and the first data and second data to be output are After the preparation, the first data is output. That is, the cycle count unit sets a wait cycle corresponding to the number of cycles required for reading data read for the second time immediately after the address boundary and the wait cycle required until the first data to be read first can be output. Count the wait cycle. The cycle control unit starts reading the first data and the second data while the cycle count unit is counting the wait cycle, and prepares the data to be output, thereby preparing the first address boundary. When outputting the data stored before and after, it becomes possible to output the data continuously in synchronization with the clock without interrupting the data.

It is a schematic block diagram which shows the structure of the semiconductor memory in this embodiment. It is the schematic block diagram which showed the structure of the burst control part in the embodiment. 7 is a timing chart showing an outline of a burst read operation when the lower 4 bits of the start address in the embodiment are “14”. 6 is a timing chart showing an outline of a burst read operation when the lower 4 bits of the start address in the embodiment are “6”. It is a figure which shows the number of effective data and the total number of wait cycles until the output start of data with respect to each value of the lower 4 bits of the start address in the same embodiment.

  Hereinafter, a semiconductor memory and an operation of the semiconductor memory according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a block is assumed to be 16 words and a reading unit is assumed to be 8 words. The semiconductor memory 100 is characterized in that the first latency and the word boundary wait cycle are collectively counted as a wait cycle between the time when burst read is input and the time when data is output, and the wait cycle is counted. In the meantime, data to be output is prepared by reading data before and after the first address boundary, and after the start of data output, the data is continuously output in every clock cycle.

FIG. 1 is a schematic block diagram showing the semiconductor memory 100 according to the present embodiment.
The semiconductor memory 100 includes memory banks 7-0, 7-1,..., 7-n including an input buffer 1, an address latch 2, a burst control unit 3, an address control unit 4, a row decoder 5, and a memory cell array 6. , Column decoder 8, sense amplifier / sense data latch 9, enable control unit 10, 2-word data latch 12-0 to 12-3, 8-word data latch 11, page selector 13, output latch 14, data selector 15 includes a data output control unit 16 and a ready output control unit 17.
The address boundary of the semiconductor memory 100 is every 16 words. One word is 16-bit data. In the semiconductor memory 100, the burst read command includes an external address indicating the start address of burst read and an address valid signal ADVB indicating that the external address is valid. Further, the memory banks 7-0, 7-1,..., 7-n have the same configuration, and hereinafter, any one of the memory banks 7-0, 7-1,. When all are shown as a representative, it is called a memory bank 7.

  The enable control unit 10 performs processing such as waveform shaping and outputs a chip enable signal CEB and an output enable signal OEB input from the outside. Here, when both the “L” level chip enable signal CEB and the “L” level output enable signal OEB are input, the enable control unit 10 becomes “H” in which the input buffer 1 is activated. The chip selection signal CS at the level and the output selection signal OS at the “H” level to be activated are output to the burst controller 3.

The input buffer 1 performs processing such as waveform shaping on the address valid signal ADVB, the external clock signal, and the external address signal (for example, A0 to A22) input from the outside. The input buffer 1 outputs an address valid signal ADVS, an internal clock signal CLK, an address latch signal ALAT, and an address AD from the input signal.
Here, the input buffer 1 generates the address valid signal ADVS from the external clock signal and the address valid signal ADVB when the “H” level chip selection signal CS indicating the activated state is input from the enable control unit 10. The input external clock signal is output as the internal clock signal CLK, the input external address signal is output as the address AD, and the address AD is latched in the address latch 2 based on the input address valid signal ADVS. An address latch signal ALAT is output.

The address latch 2 latches the address AD input from the input buffer 1 at a timing indicated by the address latch signal ALAT output from the input buffer 1.
The burst control unit 3 uses the latch address LAD input from the address latch 2 as the start address (start address, start address) of burst read, and the upper bits of the start address (A0 to A22) as the burst address BAD. Output to. Here, the upper bits of the head address are the upper bits excluding the lower 3 bits when reading 8 word units, and the lower 4 bits are omitted when reading 16 word units. Upper bit. Further, when burst reading is performed, the burst control unit 3 increments the burst address BAD by “1” in synchronization with the internal clock at a later-described timing, and outputs it as a new burst address BAD.
The burst controller 3 generates and outputs the word data latch signals DL0 to DL3, the page control signal PC, and the wait signal WAIT in synchronization with the internal clock signal CLK, and further performs initial settings such as the start of power supply. Depending on the access mode (burst access mode that outputs data continuously in synchronization with the external clock signal or random access mode that outputs data of 1 word without synchronizing with the external clock signal) The synchronous / asynchronous select signal SEL is generated and output. In addition, when the value of the lower 4 bits of the start address is “2 to 7”, the burst control unit 3 sets the 16 word boundary signal to “H” level, accesses a block different from the start address, and crosses the address boundary. To “L” level.

The address control unit 4 selects and decodes either the burst address BAD or the latch address LAD input from the burst control unit 3 and outputs the row address RAD to the row decoder 5 provided in each memory bank 7. The column address CAD is output to the column decoder 8. Here, the address control unit 4 selects the burst address BAD when the access mode is the burst access mode, and selects the latch address LAD when the access mode is the random access mode.
Further, when the address control unit 4 detects a change in the selected burst address BAD or latch address LAD, after the time (access time) required to read data from the memory bank 7 has elapsed, the latch control of “H” level is performed. The signal LC is output to the sense amplifier / sense data latch 9 to cause the sense amplifier / sense data latch 9 to latch the data output from the column decoder 8. Here, the access time corresponds to the time required for processing by the row decoder 5, the memory cell array 6, the column decoder 8, and the sense amplifier / sense data latch 9.

  The memory bank 7 includes a row decoder 5 and a memory cell array 6. The memory cell array 6 is formed by arranging a plurality of memory cells (memory elements) in a matrix. The memory cell is divided into blocks for each readout line of M × N (M and N are integers, for example, M is 2 and N is 8). I can't access it. The row decoder 5 decodes the row address RAD input from the address control unit 4 and selects a memory cell (for example, in units of 8 words, 1 word = 16 bits) in the memory area indicated by the row address RAD in the memory cell array 6. To do.

The column decoder 8 decodes the column address CAD input from the address control unit 4, selects data output from any one of the memory banks 7-0, ..., 7-n, The selected data is output to the sense amplifier / sense data latch 9.
The sense amplifier / sense data latch 9 latches data output from the column decoder 8 in response to a latch control signal LC input from the address control unit 4. Here, the sense amplifier / sense data latch 9 latches data in accordance with the start address as follows.
When the lower 4 bits of the start address are “0 to 1”, the sense amplifier / sense data latch 9 latches the data corresponding to the lower 4 bits of the address “0 to 7” from the read block, and starts. When the lower 4 bits of the address are “2-3”, the data corresponding to the lower 4 bits of the address “2-9” is latched from the block to be read, and the lower 4 bits of the start address is “4-5”. ”Latches the data corresponding to the lower 4 bits of the address“ 4 to 11 ”from among the blocks to be read, and from the read block when the lower 4 bits of the start address is“ 6 to 7 ”. When the lower 4 bits of the address latch data corresponding to “6 to 13” and the lower 4 bits of the start address is “8 to 15”, the address is added from the block to be read. Scan the lower 4 bits of the latches the data corresponding to the "8-15".

  The 8-word data latch 11 includes 2-word data latches 12-0 to 12-3. The 2-word data latches 12-0 to 12-3 latch data having a 2-word width (32-bit width), respectively, according to the word data latch signals DL0 to DL3 output from the burst control unit 3. Here, the sense amplifier data SAD [31: 0] (SAD0) of the sense amplifier data SAD [127: 0] output from the sense amplifier / sense data latch 9 is input to the 2-word data latch 12-0. The The sense amplifier data SAD [63:32] (SAD1) of the sense amplifier data SAD [127: 0] output from the sense amplifier / sense data latch 9 is input to the 2-word data latch 12-1. . The sense amplifier data SAD [95:64] (SAD2) of the sense amplifier data SAD [127: 0] output from the sense amplifier / sense data latch 9 is input to the 2-word data latch 12-2. . The sense amplifier data SAD [127: 96] (SAD3) of the sense amplifier data SAD [127: 0] output from the sense amplifier / sense data latch 9 is input to the 2-word data latch 12-3. .

When the lower 4 bits of the address corresponding to the data to be read are “0 to 1”, the value of the lower 4 bits of the address corresponds to “0 to 1” in the 2-word data latch 12-0 in the burst read operation. For example, “D0, D1” is latched, and data corresponding to the value of the lower 4 bits of the address “2-3”, for example, “D2, D3” is latched in the 2-word data latch 12-1. The 2-word data latch 12-2 latches data corresponding to the value of the lower 4 bits of the address "4-5", for example, "D4, D5", and the 2-word data latch 12-3 Data corresponding to the value of the lower 4 bits of the address corresponding to “6-7”, for example, “D6, D7” is latched.
When the lower 4 bits of the address corresponding to the data to be read are “2 to 3” In the burst read operation, the value of the lower 4 bits of the address corresponds to “8 to 9” in the 2-word data latch 12-0. Data, for example, “D8, D9” is latched, and data corresponding to the value of the lower 4 bits of the address “2-3”, for example, “D2, D3” is latched in the 2-word data latch 12-1. The 2-word data latch 12-2 latches data corresponding to the value of the lower 4 bits of the address "4-5", for example, "D4, D5", and the 2-word data latch 12-3 Data corresponding to the value of the lower 4 bits “6-7”, for example, “D6, D7” is latched.

When the lower 4 bits of the address corresponding to the data to be read are “4 to 5” In the burst read operation, the value of the lower 4 bits of the address corresponds to “8 to 9” in the 2-word data latch 12-0. Data, for example, “D8, D9” is latched, and data corresponding to the value of the lower 4 bits of the address “10-11”, for example, “D10, D11” is latched in the 2-word data latch 12-1. The 2-word data latch 12-2 latches data corresponding to the value of the lower 4 bits of the address "4-5", for example, "D4, D5", and the 2-word data latch 12-3 Data corresponding to the value of the lower 4 bits “6-7”, for example, “D6, D7” is latched.
When the lower 4 bits of the address corresponding to the data to be read are “6 to 7” In the burst read operation, the value of the lower 4 bits of the address corresponds to “8 to 9” in the 2-word data latch 12-0. Data, for example, “D8, D9” is latched, and data corresponding to the value of the lower 4 bits of the address “10-11”, for example, “D10, D11” is latched in the 2-word data latch 12-1. The 2-word data latch 12-2 latches data corresponding to the value of the lower 4 bits of the address "12 to 13", for example, "D12, D13", and the 2-word data latch 12-3 Data corresponding to the value of the lower 4 bits “6-7”, for example, “D6, D7” is latched.

  When the lower 4 bits of the address corresponding to the data to be read are “8 to 15” In the burst read operation, the value of the lower 4 bits of the address corresponds to “8 to 9” in the 2-word data latch 12-0. Data, for example, “D8, D9” is latched, and data corresponding to the value of the lower 4 bits of the address “10-11”, for example, “D10, D11” is latched in the 2-word data latch 12-1. The 2-word data latch 12-2 latches data corresponding to the value of the lower 4 bits of the address "12 to 13", for example, "D12, D13", and the 2-word data latch 12-3 Data corresponding to the value of the lower 4 bits “14 to 15”, for example, “D14, D15” is latched.

The page selector 13 selects one word from the 8-word width data input from the 8-word data latch 11 according to the page control signal PC output from the burst control unit 3, and outputs it as page data PD [15: 0]. To do.
The output latch 14 stores the page data PD [15: 0] output from the page selector 13 in synchronization with the internal clock signal CLK, for example, in synchronization with the rising edge of the internal clock signal CLK.
The data selector 15 selects one word-width data output from the output latch 14 and the page selector 13 based on the synchronous / asynchronous select signal SEL output from the burst control unit 3. The data selector 15 selects and outputs the data output by the output latch 14 when the access mode is the burst access mode, and the page data PD [15 output by the page selector 13 when the access mode is the random access mode. : 0] and output.

  The data output control unit 16 selects whether or not to output the data output from the data selector 15 as output data OUT [15: 0] by the output control signal OPC input from the burst control unit 3. Here, when the output control signal is at the “H” level, the data output control unit 16 outputs the data output from the data selector 15 as output data OUT [15: 0] to the output terminal, and outputs the output control signal. When the signal OPC is at “L” level, the output is set to high impedance.

  The ready output control unit 17 calculates a logical product of the output control signal OPC input from the burst control unit 3 and the wait signal WAIT, and outputs the logical product from the output terminal to the outside as the ready signal RDY in the next clock cycle. Here, when the ready signal RDY is at “H” level, it indicates that valid output data OUT [15: 0] is being output. When the ready signal RDY is at “L” level, invalid output data is output. It indicates that OUT [15: 0] is being output.

  Next, FIG. 2 is a schematic block diagram showing the configuration of the burst control unit 3. The burst control unit 3 includes a valid data register writing unit 38, a first latency register 31, a valid data register 32, a latency counter writing unit 37, a data counter writing unit 39, a boundary counter writing unit 40, a cycle counting unit 51, And the cycle control part 52 is provided. Here, the cycle count unit 51 includes an address counter 33, a first latency counter 34, a data counter 35, and a 16-word boundary counter 36 (boundary latency counter). The cycle control unit 52 includes an address change detection unit 41, a page latch signal generation unit 42, a page control signal generation unit 43, and a wait signal generation unit 44, and receives data from the instruction after a burst read command is input. Count the number of cycles until the output of.

In the burst controller 3, the first latency register 31 is a register that stores a value obtained by subtracting “1” from the number of first latency wait cycles input from the outside. The writing to the first latency register 31 is performed by a control circuit (not shown) at a timing before burst reading or the like is actually performed. Hereinafter, a value obtained by subtracting “1” from the number of wait cycles of the first latency is referred to as a weight count initial value.
The number of wait cycles due to the first latency is set to a time for reading data from the asynchronous memory bank 7, that is, a waiting time until the memory access is completed when reading the data. In burst read, the number of clock cycles from the first clock valid edge at which a burst read command is input to the valid edge of the clock at which data output starts or data output is determined is set.

The valid data register 32 stores a value obtained by subtracting “1” from the number of valid data to be output among the data read from the memory bank 7. Hereinafter, a value obtained by subtracting “1” from the number of valid data is referred to as a data count initial value.
The address counter 33 stores the upper bits excluding the lower 3 bits of the latch address LAD input from the address latch 2 in synchronization with the input internal clock signal CLK and outputs it as a burst address BAD. In addition, the address counter 33 has a case where the count value of the first latency counter 34 is “1”, the count value of the first latency counter 34 is “0”, and the count value of the data counter 35 is “0” or “ In the case of “8”, the burst address BAD is incremented by “1” in synchronization with the input internal clock signal CLK. That is, the address counter 33 increments the count value when the first data read related to the burst read operation is completed and when there is no valid data held in the read 8-word data latch 11.

  The first latency counter 34 counts the clock cycles of the first latency. This is also used to count the number of clock cycles corresponding to the access time of the first memory access at the start of burst reading. In the first latency counter 34, the initial value of the wait count stored in the first latency register 31 is written as the initial value. The first latency counter 34 decrements “1” until the count value becomes “0” in synchronization with the rising edge of the input internal clock signal CLK.

  The data counter 35 counts the number of data to be output in a block (in units of 16 words) including the data held by the 8-word data latch 11, and operates in synchronization with the input internal clock signal CLK. . In addition, the data counter initial value stored in the valid data register 32 is written in the data counter 35 as an initial value. The data counter 35 decrements the count value by “1” in synchronization with the input internal clock signal CLK. In the present embodiment, 16-word data is read at a time and the read data is held in the 8-word data latch 11 and the sense amplifier / sense data latch 9, so that values of 0 to 15 can be stored. Thus, the counter has a 4-bit width, and when “0” is decremented, “15” is set. That is, the count value of the data counter 35 is “15” → “14” →… → “1” → “0” → “15” →… → “1” → “0” → “15” →. The value from “15” to “0” is repeated.

The 16-word boundary counter 36 is written in synchronization with the rising edge of the input internal clock signal CLK when the initial value is written in the boundary counter writing unit 40 and the count value of the first latency counter 34 is “0”. Decrement “1” until the value becomes “0”.
The latency counter writing unit 37 reads the wait count initial value stored in the first latency register 31 in synchronization with the falling of the address latch signal ALAT signal, and counts the read wait count initial value to the first latency counter 34. Write as the initial value.

  The valid data register writer 38 starts calculating the data count initial value at the start of burst reading or when the data counter writer 39 described later reads the data count initial value from the valid data register 32. The data count initial value calculated when the calculation is completed is written in the valid data register 32. The valid data register writing unit 38 calculates a value (data count initial value) obtained by subtracting “1” from the number of valid data, and writes the calculation result in the valid data register 32.

The data counter writing unit 39 reads and reads the data count initial value stored in the valid data register 32 in synchronization with the rising edge of the internal clock signal CLK when the address valid signal ADVB is “L” level. The data count initial value is written to the data counter 35 as a count value.
The boundary counter writing unit 40 writes the initial value of the 16-word boundary counter 36 in synchronization with the rising of the input internal clock signal CLK when the address valid signal ADVB is at “L” level. Here, the initial value that the boundary counter writing unit 40 writes to the 16-word boundary counter 36 is the number of valid data among the data read the second time when the value indicated by the lower 4 bits of the start address is 0-7. This is a value subtracted from the initial value of the wait count stored in the latency register 31. When the value indicated by the lower 4 bits of the start address is 8 to 15, the number of valid data in the first read data is set to the first latency. This is a value obtained by subtracting from the weight count initial value stored in the register 31. If the subtraction result is a negative value, the boundary counter writing unit 40 writes “0” to the 16-word boundary counter 36 as an initial value.

  Whether or not a word boundary wait cycle occurs depends on the number of valid data included in the data read the second time when the value indicated by the lower 4 bits of the start address is 0 to 7, and the lower 4 bits of the start address When the indicated value is 8 to 15, since it depends on the number of valid data included in the first read data, the boundary counter writing unit 40 calculates the number of wait cycles corresponding to the number of valid data to obtain 16 words The initial value of the boundary counter 36 is used.

The address change detection unit 41 detects a change in the burst address BAD, generates and outputs an address transition signal ATD that is a one-shot pulse signal.
The page latch signal generation unit 42 causes the 8-word data latch 11 to latch the word data read from the memory cell array 7 and latched in the sense amplifier / sense data latch 9 by the output word data latch signals DL0 to DL3. Take control. The 2-word data latch 12-0 outputs latched data when the word data latch signal DL0 is at "L" level, and sense amplifier sense when the word data latch signal DL0 is at "H" level. SAD [31: 0] input from the data latch 9 is output.

Further, the page latch signal generation unit 42 changes from “H” level to “H” level in synchronization with the rising of the internal clock signal CLK to which the word data latch signals DL0 to DL3 are input when the following condition 1 or condition 2 is satisfied. Transition to the “L” level. Condition 1 is that the count value of the first latency counter 34 is “1”. Condition 2 is that the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “0” or “8”.
In addition, when the following condition 3 or condition 4 is satisfied, the page latch signal generation unit 42 starts from the “L” level in synchronization with the rising edge of the internal clock signal CLK to which the word data latch signals DL0 to DL3 are input. Transition to the “H” level. Condition 3 is that the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 are both “0”, and the count value of the data counter 35 is “1” or “9”. Condition 4 is that an “L” level address valid signal ADVB is input.

  However, when the 16 word boundary signal is “H” level and the lower 4 bits of the address are “2 to 7”, the page latch signal generation unit 42 changes from “L” level to “H” of the word data latch signal DL0. If the 16-word boundary signal is “H” level and the lower 4 bits of the address are “4-7” without transition to the level, the word data latch signal DL1 changes from “L” level to “H” level. When the 16 word boundary signal is “H” level and the lower 4 bits of the address are “6-7”, the transition of the word data latch signal DL2 from “L” level to “H” level is not performed. Do not do.

  The page control signal generation unit 43 outputs a page control signal PC to 13 and controls the page selector 13 to select any one word from the 8-word data output from the 8-word data latch 11. The page control signal generation unit 43 has a page selection counter with a 3-bit width, and reads the lower 3 bits of the start address as the initial value of the page selection counter. When the sum of the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 becomes “1” or less, the page control signal generation unit 43 selects a page in synchronization with the rising edge of the input internal clock signal CLK. Increment the counter by "1". The page control signal generation unit 43 determines one word to be selected by the page selector 13 according to the count value of the page selection counter. The page control signal generator 43 generates WLD [15: 0], WLD [31:16], and WLD [47 according to the count values “0”, “1”, “2”,. : 32],..., WLD [127: 112] is selected and page control signals PC “P0”, “P1”, “P2”,..., “P7” are output to control the page selector 13. For example, when the count value of the page selection counter is “6”, the page control signal generation unit 43 outputs one word of WLD [111: 96] corresponding to the seventh lower order of the 8-word data WLD [127: 0]. The page control signal PC “P6” to be selected is output.

The wait signal generation unit 44 sets the wait signal WAIT to the “H” level in synchronization with the falling edge of the address latch signal ALAT. Further, when the count value of the 16-word boundary counter 36 is “1”, the wait signal generation unit 44 sets the wait signal WAIT to the “L” level in synchronization with the rising edge of the input internal clock signal CLK.
Further, the wait signal generation unit 44 outputs an output when the “H” level output control signal OC is input and both the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 become “0”. An output control signal OPC of “H” level indicating that output data OUT [15: 0] is output from the terminal is output.

(Operation 1 of Semiconductor Memory 100)
Hereinafter, the burst reading operation of the semiconductor memory 100 will be described with reference to FIGS. 3 and 4, the access mode is the burst access mode and the first latency is 6 cycles as an example.
FIG. 3 is a timing chart showing an outline of the burst read operation when the lower 4 bits of the start address are “14”.
In one clock cycle from time t100, the input buffer 1 receives an external address signal whose lower 4 bits indicate “4”. Further, the input buffer 1 raises the address latch signal ALAT when the input address valid signal ADVB transits from the “H” level to the “L” level, and at the rise of the internal clock signal CLK that follows the rise. The address latch signal ALAT falls in synchronization.

  In one clock cycle from time t101, an external address “14” is input from the outside, and an “L” level address valid signal ADVB indicating that the external address is a valid value is input. When the “L” level address valid signal ADVB is input, the input buffer 1 sets the address latch signal ALAT to the “H” level to put the address latch 2 in the through state.

The address counter 33 stores (A22 to A3) excluding the lower 3 bits of the latch address LAD output from the address latch 2 as an initial value in synchronization with the rising edge of the internal clock signal CLK, and bursts the stored address. The address BAD is output to the address control unit 4.
The address control unit 4 detects a change in the burst address BAD output from the address counter 33, decodes the burst address BAD, outputs the row address RAD to the row decoder 5 included in each of the memory banks 7, and the column address CAD. “C8” is output to the column decoder 8.

At time t101, the latency counter writing unit 37 reads the wait count initial value “5” stored in the first latency register 31, writes it in the first latency counter 34, and stores it. The wait signal generation unit 44 sets the wait signal WAIT to the “H” level in synchronization with the falling edge of the address latch signal ALAT.
When the “L” level address valid signal ADVB is input, the page latch signal generation unit 42 sets the word data latch signals DL0 to DL3 to the “H” level in synchronization with the rising edge of the internal clock signal CLK. Further, the page control signal generation unit 43 stores the lower 3 bits “110” of the start address as the initial value of the page selection counter, and outputs the corresponding page control signal PC of “P6”.
Further, in one clock cycle from time t101, the address valid signal ADVB input from the outside becomes “H” level. That is, the input external address becomes an invalid value.

At time t101, when the address valid signal ADVB is “L” level, the boundary counter writing unit 40 sets “3” ((first latency) to the 16-word boundary counter 36 in synchronization with the rising edge of the internal clock signal CLK. The number of cycles) -1)-(the number of valid data in the data read for the second time)) is written and stored.
When the address valid signal ADVB is at “L” level, the data counter writing unit 39 writes and stores “1” (the number of valid data−1) in the data counter 35 in synchronization with the rising edge of the internal clock signal CLK.
At time t102, the first latency counter 34 decrements the count value in synchronization with the internal clock signal CLK to change the count value from “5” to “4”. Thereafter, until time t106, it is decremented in synchronization with the rising edge of the internal clock signal CLK (“4” → “3” → “2” → “1” → “0”).

  In one clock cycle from time t104, the address control unit 4 senses the latch control signal LC at the “H” level because the access time has elapsed since the row address RAD and the column address CAD “C8” are output. Output to amplifier / sense data latch 9. The sense amplifier / sense data latch 9 receives the “H” level latch control signal LC and enters the through state. The 8-word data “D8-D15” selected by the column decoder 8 is transferred to the 8-word data latch 11. Output. This data “D8-D15” is 8-word data selected from the data read from the memory bank 7 by the column decoder 8 using the column address CAD “C8”.

  The 8-word data latch 11 receives the sense amplifier data SAD [127: 0] “D8-D15” input from the sense amplifier / sense data latch 9 when the word data latch signals DL0 to DL3 are “H”. The data WLD [127: 0] is output to the page selector 13. Further, the page selector 13 receives the data “8” from the 8-word data WLD [127: 0] “D8-D15” in response to the page control signal PC of “P6” that selects the sixth word from the lower order output from the burst control unit 3. D14 "is selected and output. The data selector 15 selects data that changes in synchronization with the internal clock signal CLK output from the output latch 14 based on the synchronous / asynchronous select signal SEL output from the burst control unit 3, and selects the select data SD [15: 0. ], The data “D14” is output to the data output control unit 16. At this time, since the “L” level output control signal OPC is input from the burst control unit 3 to the data output control unit 16, the output is in a high impedance state and invalid data is output.

  At time t105, the address control unit 4 sets the latch control signal LC to the “L” level in synchronization with the rising edge of the internal clock signal CLK. The output latch 14 latches the page data PD [15: 0] “D14” output from the page selector 13 in synchronization with the rising edge of the internal clock signal CLK.

At time t106, the address counter 33 is in a state where 8-word data read by the first memory access is held in the 8-word data latch 11, that is, when the count value of the first latency counter 34 is “1”. In addition, the stored address is incremented by “1” in synchronization with the rising edge of the internal clock signal CLK, and is output as a burst address BAD indicating the address where the data to be read next (in units of 8 words) is stored.
The address control unit 4 detects a change in the burst address BAD output from the address counter 33, decodes the burst address BAD, outputs the row address RAD to the row decoder 5 included in each of the memory banks 7, and “C16”. Is output to the column decoder 8.

  At time t106, when the count value of the first latency counter 34 is “1”, the page latch signal generation unit 42 outputs the 2-word data latch signals DL3 to DL0 to “L” in synchronization with the rising edge of the internal clock signal CLK. To the level.

  At time t107, when the count value of the first latency counter 34 is “0”, the 16-word boundary counter 36 decrements the count value by “1” in synchronization with the rising edge of the internal clock signal CLK and sets the count value to “2”. Update to

  At time t108, when the count value of the first latency counter 34 is “0”, the 16-word boundary counter 36 decrements the count value by “1” in synchronization with the rising edge of the internal clock signal CLK and sets the count value to “1”. Update to

At time t109, when the count value of the 16-word boundary counter 36 is “1”, the wait signal generation unit 44 sets the wait signal WAIT to the “L” level in synchronization with the rising edge of the internal clock signal CLK.
When the sum of the counter value of the first latency counter 34 and the counter value of the 16-word boundary counter 36 is “1” or less, the page control signal generation unit 43 increments the counter value from “6”. The page control signal PC is updated from “P6” to “P7” according to the page selection counter. Thereafter, the page control signal generator 43 decrements the count value by “1” every time the internal clock signal CLK rises, and sets the page control signal PC corresponding to the counter value of the page selection counter to “P7”, “P0”, .. Are output to the page selector 13.

When both the count value of the first latency counter 34 and the count value of the 16 word boundary counter 36 are “0”, the wait signal generation unit 44 outputs the “H” level output control signal OPC to the data output control unit 16. Output to the ready output control unit 17.
The page selector 13 receives the page control signal PC of “P7” from the page control signal generation unit 43, and the eighth data “D15” from the lower order of the data “D15-D8” input from the 8-word data latch 11. Are output as page data PD [15: 0].
The data output control unit 16 receives the data “D14” held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Are output to the outside as output data OUT [15: 0].

Further, in one clock cycle from time t109, the address control unit 4 has passed the access time after outputting the row address RAD and the column address CAD “C16”. Therefore, the latch control signal LC at the “H” level. Is output to the sense amplifier / sense data latch 9. The sense amplifier / sense data latch 9 receives the “H” level latch control signal LC and enters the through state. The 8-word data “D16-D23” selected by the column decoder 8 is transferred to the 8-word data latch 11. Output. This data “D16-D23” is 8-word data selected from the data read from the memory bank 7 by the column decoder 8 by the column address CAD “C16”.
When the count value of the first latency counter 34 is “0”, the 16-word boundary counter 36 decrements the count value by “1” in synchronization with the rising edge of the internal clock signal CLK and updates the count value to “0”. .

At time t110, the output latch 14 latches the page data PD [15: 0] “D15” output from the page selector 13 in synchronization with the rising edge of the internal clock signal CLK. The data output control unit 16 receives the data “D15” held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Are output to the outside as output data OUT [15: 0].
The data counter 35 decrements the count value by “1” and updates the count value to “0” when both the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 are “0”. To do. Thereafter, the data counter 35 decrements the count value by “1” every time the internal clock signal CLK rises.
The address control unit 4 sets the latch control signal LC to the “L” level in synchronization with the rising edge of the internal clock signal CLK, and causes the sense amplifier / sense data latch 9 to latch the read data “D16-D23”.

When both the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 are “0” and the count value of the data counter 35 is “1”, the page latch signal generation unit 42 Data latch signals DL0-DL3 are set to "H" level, and 8-word data latch 11 is set to the through state. The 8-word data latch 11 outputs the data “D16-D23” input from the sense amplifier / sense data latch 9 to the page selector 13.
The page selector 13 selects the first data “D16” from the lower order from the data “D16-D23” input as 8-word data by the page control signal “P0” input from the page control signal generator 43. , Data “D16” is output as page data PD [15: 0].

At time t111, the output latch 14 latches the page data PD [15: 0] “D16” output from the page selector 13 in synchronization with the rising edge of the internal clock signal CLK. The data output control unit 16 receives the data “D16” held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Are output to the outside as output data OUT [15: 0].
The address counter 33 sets the burst address BAD to “1” in synchronization with the internal clock signal CLK when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “0”. Increment and update, and output the updated burst address BAD to the address control unit 4.
The address control unit 4 detects a change in the burst address BAD output from the address counter 33, decodes the burst address BAD, outputs the row address RAD to the row decoder 5 included in each of the memory banks 7, and “C24”. Is output to the column decoder 8.

The page latch signal generation unit 42 sets the word data latch signals DL0 to DL3 to the “L” level when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “0”. Then, the 8-word data latch 11 latches the data “D16-D23”.
The page selector 13 changes the data “D17” from the 8-word data WLD [127: 0] “D16-D23” in response to the change of the page control signal PC output from the page control signal generator 43 to “P1”. Select and output.

From time t112 to time t114, the output latch 14 latches and outputs the page data PD [15: 0] sequentially output by the page selector 13 in synchronization with the rising edge of the internal clock signal CLK (“D17” → “D18” → “D19”).
The data output control unit 16 sequentially outputs data held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Data OUT [15: 0] is output to the outside (“D17” → “D18” → “D19”).
The page selector 13 changes the 8-word data WLD [127: 0] “D16-D23” to the data “D18”, “D19”, and the like in accordance with the change of the page control signal PC output from the page control signal generator 43. Select “D20” in order and output.

  In one clock cycle from time t114, the address control unit 4 senses the latch control signal LC at the “H” level because the access time has elapsed since the row address RAD and the column address CAD “C16” are output. Output to amplifier / sense data latch 9. The sense amplifier / sense data latch 9 receives the “H” level latch control signal LC and enters the through state. The 8-word data “D16-D23” selected by the column decoder 8 is transferred to the 8-word data latch 11. Output. The data “D24-D31” is 8-word data selected from the data read from the memory bank 7 by the column decoder 8 using the column address CAD “C24”.

At time t115, the address control unit 4 sets the latch control signal LC to the “L” level in synchronization with the rising edge of the internal clock signal CLK.
Further, from time t115 to time t117, the page selector 13 changes the 8-word data WLD [127: 0] “D16-D23” in accordance with the change of the page control signal PC output from the page control signal generation unit 43. Data “D21”, “D22”, and “D23” are selected in this order and output.
The output latch 14 latches and outputs the page data PD [15: 0] sequentially output by the page selector 13 in synchronization with the rising edge of the internal clock signal CLK (“D20” → “D21” → “D22”). .
The data output control unit 16 sequentially outputs data held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Data OUT [15: 0] (“D20” → “D21” → “D22”).

At time t118, the output latch 14 latches and outputs the page data PD [15: 0] “D23” output from the page selector 13 in synchronization with the rising edge of the internal clock signal CLK. The data output control unit 16 receives the data “D23” held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Are output to the outside as output data OUT [15: 0].
The page latch signal generation unit 42 sets the word data latch signals DL0 to DL3 to the “H” level when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “9”. Then, the 8-word data latch 11 is set to the through state. The 8-word data latch 11 outputs the sense amplifier data SAD [127: 0] “D24-D31” input from the sense amplifier / sense data latch 9 to the page selector 13 as 8-word data WLD [127: 0].
The page selector 13 responds to the page control signal PC “P0” output by the page control signal generation unit 43, and the first data “D24” from the lower order of the 8-word data WLD [127: 0] “D16-D23”. Are output as page data PD [15: 0].

  At time t119, the output latch 14 latches the page data PD [15: 0] “D24” output from the page selector 13 in synchronization with the rising edge of the internal clock signal CLK. The data output control unit 16 receives the data “D24” held in the output latch 14 via the data selector 15 when the “H” level output control signal OPC is input from the wait signal generation unit 44. Are output to the outside as output data OUT [15: 0].

The address counter 33 sets the burst address BAD to “1” in synchronization with the internal clock signal CLK when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “8”. Increment and update, and output the updated burst address BAD to the address control unit 4.
The address control unit 4 detects a change in the burst address BAD output from the address counter 33, decodes the burst address BAD, outputs the row address RAD to the row decoder 5 included in each of the memory banks 7, and "C32" Is output to the column decoder 8.

The page latch signal generation unit 42 sets the word data latch signals DL0 to DL3 to the “L” level when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “8”. Then, the 8-word data latch 11 latches the data “D24-D31”.
The page selector 13 receives the second word from the lower part of the 8-word data WLD [127: 0] “D16-D23” in response to the page control signal PC output from the page control signal generator 43 changing to “P1”. The data “D25” is selected and output.

(Operation 2 of Semiconductor Memory 100)
Next, FIG. 4 is a timing chart showing an outline of the burst read operation when the lower 4 bits of the start address are “6”.
The operations different from those of the semiconductor memory 100 shown in FIG. 3 are the calculation of the 16 word boundary counter value by the boundary counter writing unit 40, the change of the 16 word boundary signal, and the change of the word data latch signals DL0 to DL2. is there. This difference is because the value of the lower 4 bits of the start address corresponds to “2-7”.
In FIG. 4, since the start address is different from that in FIG. 3, the initial value of the data counter 35, the column address CAD, and the read data “D8-13, D6-7” corresponding to the start address “A6”. However, the timing at which the signal changes is the same except for the 16-word boundary signal and the 8-word data latch 11 controlled by the word data latch signals DL0 to DL2.
In the following, only the difference in signal change timing from FIG. 3 will be described.

At time t200, when the value of the lower 4 bits of the latch address LAD input from the address latch 2 is included in “2-7”, the burst control unit 3 sets the 16-word boundary signal to the “H” level. When the address valid signal ADVB is “L” level, the boundary counter writing unit 40 sets “3” (((first latency cycle number) −1) to the 16-word boundary counter 36 in synchronization with the rising edge of the internal clock signal CLK. -(The number of valid data among the data read first time)) is stored.
At time t210, the page latch signal generation unit 42 determines that both the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 are “0” and the count value of the data counter 35 is “9”. Yes, when the 16-word boundary signal is at "L" level, the word data latch signal DL3 is set to "H" level, and only the 2-word data latch 12-3 is set to the through state. The 8-word data latch 11 receives the data “D8-D13” held in the 2-word data latches 12-0 to 12-2 and the data “D14-D15” input from the sense amplifier / sense data latch 9. Output to the page selector 13.
At time t211, the page latch signal generation unit 42 sets the word data latch signal DL3 to “L” when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “8”. ", The 8-word data latch 11 latches the data" D8-D15 ".
At time t218, the burst controller 3 sets the 16-word boundary signal to “L” when the count value of the first latency counter 34 is “0” and the count value of the data counter 35 is “1”. .

As described above, the semiconductor memory 100 determines the number of clock cycles required for the word boundary wait cycle from the start address by the boundary counter writing unit 40, and operates the first latency counter 34 and the 16 word boundary counter 36 in order to count. Then, the cycle control unit 52 controls to output data to the outside after both the count value of the first latency counter 34 and the count value of the 16-word boundary counter 36 become “0”. That is, when reading data, the semiconductor memory 100 calculates the number of cycles required for the first latency generated from the start address and the word boundary wait cycle, and spends the data to be output delayed by the calculated number of cycles. This prevents the occurrence of a word boundary wait cycle after the start of data output.
Thereby, the semiconductor memory 100 can output data without generating a word boundary wait cycle due to waiting for completion of data reading in the burst reading operation.
By eliminating the clock cycle in which valid data is continuously output and invalid data is output, an external device that receives data from the semiconductor memory 100 outputs data in the exchange of data with the semiconductor memory. Since it is not necessary to determine whether or not the stored data is valid, the handshake circuit relating to data transmission / reception can be simplified, and the data transfer speed can be increased.

  As described above, the semiconductor memory 100 operates, that is, when a burst read command is input, a cycle required to output the read data from the start address to the first address boundary included in the burst read command; The count values of the first latency counter 34 and the 16-word boundary counter 36 are set in accordance with a preset first latency cycle. At this time, the latency counter writing unit 37 writes the count value to the first latency counter 34, and the boundary counter writing unit 40 writes the count value to the 16-word boundary counter 36, so that the data corresponding to the burst read command is externalized. Sets the wait cycle until the output to is started.

  In addition, when a burst read command is input via the address control unit 4, the cycle control unit 52 continuously reads the read data from the start address to the first address boundary from the memory bank 7, The read data up to the address boundary is latched by the 8-word data latch 11 and the data stored immediately after the address boundary is read and latched by the sense amplifier / sense data latch 9. Further, when both the count values of the first latency counter 34 and the 16 word boundary counter 36 become “0”, the cycle control unit 52 starts outputting data corresponding to the burst read command and latches it in the 8-word data latch 11. When the valid data to be output to the 8-word data latch 11 is lost, the data latched in the sense amplifier / sense data latch 9 is latched in the 8-word data latch 11 and the subsequent Are read from the memory bank 7 and latched by the sense amplifier / sense data latch 9. Thereafter, the cycle control unit 52 latches the data read from the memory bank 7 in the order of the sense amplifier / sense data latch 9 and the 8-word data latch 11 in a continuous clock cycle in synchronization with the internal clock signal CLK. The data is output to the outside in order.

The boundary counter writing unit 40 can read data immediately after the first address boundary while outputting the data read up to the first address boundary to the outside in a continuous clock cycle in synchronization with the internal clock signal CLK. In other words, the number of cycles required to output the data read up to the first address boundary to the outside (the first cycle number) is determined by reading the data stored immediately after the first address boundary from the memory bank 7. If the number of cycles required for latching by the 8-word data latch 11 (second cycle number) is exceeded, “0” is written to the 16-word boundary counter 36 as the count value.
On the other hand, the boundary counter writing unit 40 can read the data immediately after the first address boundary while outputting the data read up to the first address boundary to the outside in a continuous clock cycle in synchronization with the internal clock signal CLK. If not, that is, if the first cycle number is smaller than the second cycle number, the difference between the first cycle number and the second cycle number is written in the 16-word boundary counter 36 as a count value.
In addition, the latency counter writing unit 37 sets the number of clock cycles corresponding to the time (access time) required for reading the first data corresponding to the instruction from the memory element after the burst read instruction is input to the first latency counter 34. Is written as a count value.

FIG. 5 is a diagram showing the number of valid data and the total number of wait cycles until the start of data output, for each value of the lower 4 bits of the start address. The total number of wait cycles is shown for each case where the first latency is “2” to “8” (indicated as wait2,..., Wait8 in the figure).
“1st” is the number of words of valid data in the first block read before the first 16-word boundary, and “2nd” is valid data in the second block read before the first 16-word boundary. Is the number of words.
“Before boundary” is the number of valid data words in the block before the first 16 word boundary, that is, the sum of “1st” and “2nd”.
As shown in FIG. 5, when the first latency is 6 cycles and the lower 4 bits of the start address are “14” (FIG. 3), the total number of wait cycles is 8 cycles. When the first latency is 6 cycles and the lower 4 bits of the start address are “6” (FIG. 4), the total number of wait cycles is 8 cycles.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor memory 1 ... Input buffer, 2 ... Address latch, 3 ... Burst control part 4 ... Address control part, 5 ... Row decoder, 6 ... Memory cell array 7, 7-0, 7-1, 7-n ... Memory bank DESCRIPTION OF SYMBOLS 8 ... Column decoder, 9 ... Sense amplifier and sense data latch 10 ... Enable control part, 11 ... 8 word data latch 12-0 ... 2 word data latch 12-1 ... 2 word data latch 12-2 ... 2 word data latch 12 -3 ... 2 word data latch 13 ... Page selector, 14 ... Output latch, 15 ... Data selector 16 ... Data output control unit, 17 ... Ready output control unit 31 ... Fast latency register, 32 ... Valid data register 33 ... Address counter, 34 ... First latency counter 35 ... Data counter, 36 ... 16 Boundary counter 37 ... Latency counter writing unit, 38 ... Valid data register writing unit 39 ... Data counter writing unit, 40 ... Boundary counter writing unit 41 ... Address change detection unit, 42 ... Page latch signal generation unit 43 ... Page control signal generation unit, 44 ... wait signal generation unit 51 ... cycle count unit, 52 ... cycle control unit BAD ... burst address, LAD ... latch address AD ... address, RAD ... row address, CAD ... column address CLK ... internal clock Signal ADVB ... Address valid signal, ALAT ... Address latch signal

Claims (4)

A semiconductor memory having a burst read function for sequentially outputting data stored in a continuous memory area of a provided memory cell array in synchronization with an input clock signal,
When the burst read command is input, the number of clock cycles required to output the first data read from the memory area from the start address corresponding to the burst read command to the first address boundary is set in advance. A cycle cycle unit configured to set a wait cycle according to the first latency and to count the set wait cycle in synchronization with the clock signal;
When the burst read command is input, the reading of the first data from the memory area and the reading of the second data stored immediately after the first address boundary are continuously performed. A cycle control unit configured to start outputting data to the outside in successive clock cycles in synchronization with the clock signal when the cycle count unit finishes counting; ,
With
The address boundary is
A semiconductor memory, which is an address boundary that cannot be included in one reading of the data due to the configuration of the memory cell array. The cycle count unit
A first latency counter that counts the first latency in synchronization with the clock signal;
Based on the number of cycles of the first latency and the number of cycles required to output the first data, boundary latency for counting the timing of outputting the data corresponding to the burst read to the outside in synchronization with the clock signal A counter,
With
The first latency counter and the boundary latency counter are operated in order to count the wait cycle from when the burst read command is input until the output of data corresponding to the command is started,
The value counted by the boundary latency counter is:
When the number of cycles required to output the first data is equal to or greater than the number of cycles corresponding to the time for reading the second data from the memory area, the number is 0, and the first data is output. When the number of cycles required for reading the second data is smaller than the number of cycles for reading the second data, the number of cycles required for outputting the first data and the cycle corresponding to the time for reading the second data from the memory area The difference with the number,
The semiconductor memory according to claim 1. The semiconductor memory according to claim 2, wherein the first latency is set according to a cycle of the clock signal and a data read time of the memory cell array. 4. The semiconductor memory according to claim 2, wherein the boundary latency counter is set with the boundary latency according to a lower bit of an address included in the burst read instruction. 5.

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