JP5226920B2 - Display panel drive circuit - Google Patents

Description

BACKGROUND OF THE INVENTION
The present invention relates to a display panel driving circuit, related to a driving circuit of a display device using a display panel, in particular made of self-luminous element such as an organic electroluminescence element.

  An organic electroluminescence (hereinafter referred to as EL) element is known as a self-luminous element for realizing a thin display device with low power consumption. FIG. 4 is a diagram showing a schematic configuration of such an EL element. As shown in the figure, the EL element has at least one layer composed of an electron transport layer, a light emitting layer, a hole transport layer, etc. on a transparent substrate 100 composed of a glass plate or the like on which a transparent electrode 101 is formed. The organic functional layer 102 and the metal electrode 103 are laminated.

FIG. 5 is an equivalent circuit that electrically shows the characteristics of the EL element. As shown in the figure, the EL element can be replaced by a capacitive component C and a diode characteristic component E coupled in parallel to the capacitive component.
Here, when a positive voltage is applied to the anode of the transparent electrode 101 and a negative voltage is applied to the cathode of the metal electrode 103 to apply a direct current between the transparent electrode and the metal electrode, charges are accumulated in the capacitive component C. At this time, when the barrier voltage or emission threshold voltage specific to the EL element is exceeded, current starts to flow from the electrode (the anode side of the diode component E) to the organic functional layer serving as the light emitting layer, and the organic function has an intensity proportional to this current. Layer 102 emits light.

FIG. 6 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix. In the figure, an ELDP 10 as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line, and an array that intersects each of the cathode lines B _{1 to} B _n. is the m anode lines (transparent electrodes) a ₁ to a _m are formed. EL elements E _{11 to} E _nm having the above-described structure are formed at the intersections of the cathode lines B _{1 to} B _n and the anode lines A _{1 to} Am. Each of these EL elements E _{11 to} E _nm serves as one pixel as the ELDP 10.

The light emission control circuit 1 converts the input image data for one screen (n rows, m columns) into pixel data groups D _{11 to} D D corresponding to the respective pixels of the ELDP 10, that is, the EL elements E _{11 to} E _nm. These are converted to _nm , and these are sequentially supplied to the anode line drive circuit 2 line by line as shown in FIG. For example, the pixel data D _{11 to} D _nm are m data bits that specify whether or not light emission is performed for each of the EL elements E _{11 to} E _nm belonging to the first display line of the ELDP 10. When the logic level is “1”, “light emission” is indicated, and when the logic level is “0”, “non-light emission” is indicated.

Further, as shown in FIG. 7, the light emission control circuit 1 scans each of the first display line to the nth display line of the ELDP 10 in order in synchronization with the supply timing of the pixel data for each row. A line selection control signal is supplied to the cathode line scanning circuit 3. First, the anode line drive circuit 2 extracts all the data bits of the logic level “1” designating “light emission” from the m data bits in the pixel data group. Next, the anode line belonging to "columns" corresponding to the data bits each and the extracted selected all from among the anode lines A ₁ to A _m, connects the constant current source only to the selected anode line, predetermined A pixel driving current i is supplied.

The cathode line scanning circuit 3 selectively selects a cathode line corresponding to the display line indicated by the scanning line selection control signal from the cathode lines B _{1 to} B _n and sets the cathode line to the ground potential. A predetermined high potential Vcc is applied to each of the other cathode lines. Note that the high potential Vcc is set to be approximately the same value as the voltage across the EL element when the EL element emits light with a desired luminance (voltage determined based on the amount of charge to the parasitic capacitance C).

  At this time, a light emission driving current flows between the “column” to which the constant current source is connected by the anode line drive circuit 2 and the display line set to the ground potential by the cathode line scanning circuit 3. The EL element formed so as to cross the display line and the “column” emits light according to the light emission drive current. On the other hand, since no current flows between the display line set to the high potential Vcc by the cathode line scanning circuit 3 and the “column” to which the constant current source is connected, the display line and the “column” are crossed. The EL element thus formed remains non-light emitting.

When the above operation is performed based on each of the pixel data groups D _{11 to} D _1m , D _{21 to} D _2m ,..., D _{n1 to} D _nm , the input image data is displayed on the ELDP 10 screen. A light emission pattern corresponding to one field, that is, an image is displayed.

Problems to be solved by the invention

  Here, in recent years, in order to realize a large display panel, it is necessary to increase the number of display lines, that is, the number of cathode lines B, and increase the number of anode lines A to increase the definition of the screen. It was. Therefore, as the number of each of these anode lines A and cathode lines B increases, the circuit scale of each of the anode line drive circuit 2 and the cathode line scanning circuit 3 also increases. Therefore, when both are integrated into an IC, the yield associated with the increase in chip area increases. There is concern about deterioration. Therefore, it has been considered to construct each of the anode line drive circuit 2 and the cathode line scanning circuit 3 with a plurality of IC chips.

  However, when the anode line drive circuit 2 is constructed of a plurality of IC chips, the amount of light emission drive current to be supplied to the anode lines may differ between the IC chips due to manufacturing variations and the like. Therefore, there is a problem that areas having different luminances are formed on the ELDP 10 screen due to the difference in the light emission drive current. A technique for solving this is described in Japanese Patent Laid-Open No. 2001-42827.

FIG. 8 is a diagram showing a schematic configuration of an EL display device described in the publication. In the figure, an ELDP 10 ′ as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n for carrying the first display line to the nth display line and the cathode lines B _{1 to} B _n. Arranged 2m anode wires (transparent electrodes) A _{1 to} A _2m are formed. EL elements E _{1,1 to} E _{n, 2m} having the structure shown in FIG. 4 are formed at the intersections of the cathode lines B _{1 to} B _n and the anode lines A _{1 to} A _2m . Each of these EL elements E _{1,1 to} E _{n, 2m} serves as one pixel as the ELDP 10 ′.

As shown in FIG. 9, the light emission control circuit 1 ′ supplies a scanning line selection control signal for sequentially scanning each of the first display line to the n-th display line of the ELDP 10 ′ to the cathode line scanning circuit 30. The cathode line scanning circuit 30 selectively selects a cathode line corresponding to the display line indicated by the scanning line selection control signal from the cathode lines B _{1 to} B _n of the ELDP 10 ′ and grounds it to the ground potential. A predetermined high potential Vcc is applied to each of the other cathode lines.

Further, the light emission control circuit 1 ′ converts the input image data for one screen (n rows, 2m columns) into pixels of the ELDP 10 ′, that is, pixels corresponding to the EL elements E _{1,1 to} E _{n, 2m.} Data D _{1,1 to} D _{n, 2m} is converted and divided into data belonging to the first column to the m-th column and data belonging to the m + 1-th column to the second m-th column. At this time, the pixel data D _{1, 1} a grouping of pixel data belonging to the first column to m-th column in each display line _{~D 1, m, D 2,1 ~D} 2, m, D 3,1 ˜D _{3, m} ,..., And D _{n, 1 to} D _{n, m} are sequentially set as first drive data GA _1-m as shown in FIG. To supply. At the same time, the light emission control circuit 1 ′ has pixel data D _{1, m + 1 to} D _1,2m , D _{2, m} obtained by grouping pixel data belonging to the _{(m + 1) -th} column to the (2m) _-th column for each display line. _{+1 ~D 2,2m, D 3, m} + 1 ~D 3,2m, ..., and _{D n, m + 1 ~D n} , the _2m respectively, as shown in Figure 9, the second drive Data GB _1-m is sequentially supplied to the second anode line drive circuit 22.

Each of the first drive data GA _1-m and the second drive data GB _1-m is sequentially sent in synchronization with the scanning line selection control signal as shown in FIG. It is supplied to each of the drive circuit 21 and the second anode line drive circuit 22. At this time, the first drive data group GA _1-m refers to whether or not light emission is performed for each of the m EL elements belonging to the first column to the m-th column of each display line of the ELDP 10 ′. These are m data bits that specify The second drive data group GB _1-m is whether or not light emission is performed for each of the m EL elements belonging to the (m + 1) -th column to the second m-th column of each display line of the ELDP 10 ′. M data bits for designating. For example, when such a data bit is a logical level “1”, light emission is performed, whereas when it is “0”, light emission is not performed.

FIG. 10 is a diagram showing an internal configuration of each of the first anode line drive circuit 21 and the second anode line drive circuit 22 as a drive circuit. Each of the first anode line drive circuit 21 and the second anode line drive circuit 22 is constructed in two different IC chips. In the figure, a first anode line drive circuit 21 includes a reference current control circuit RC, a control current output circuit CO, a switch block SB, and transistors Q _{1 to} Q _m and resistors R ₁ to R as m current drive sources. consisting of R _m.

The emitter of the transistor Q _b in the reference current control circuit RC is connected to a predetermined voltage V _BE through the resistor R _r, the collector of the transistor Q _a is connected to its base and collector. A predetermined reference potential V _REF and the emitter potential of the transistor Q _a are input to the operational amplifier OP, and the output potential is input to the base of the transistor Q _a . The emitter of the transistor Q _a is grounded to the earth potential via a resistor R _p. The configuration given above, so that the reference current _{I REF (= V REF / R} p) flows between the collector-emitter of the transistor Q _a.

A pixel drive potential V _BE is applied to the emitters of the transistors Q _{1 to} Q _m via the resistors R _{1 to} Rm, respectively, and the base of the transistor Q _b is connected to each base. At this time, the resistance values of the resistors R _r and R _{1 to} R _m are the same, and the transistors Q _{1 to} Q _m , Q _a and Q _b have the same characteristics. . Therefore, the reference current control circuit RC and the transistors Q _{1 to} Q _m constitute a current mirror circuit (hereinafter referred to as a current mirror), and between the emitters and collectors of the transistors Q _{1 to} Q _m , A light emission drive current i having the same current value as the reference current I _REF flows and is output.

The switch block SB is provided with _m switching elements S _{1 to} S _m for leading the light emission drive current i output from each of the transistors Q _{1 to} Q _m to the output terminals X _{1 to} X _m , respectively. ing. At this time, in the switch block SB of the first anode line drive circuit 21, the switching elements S _{1 to} S according to the logic levels of the first drive data GA _{1 to} GA _m supplied from the light emission control circuit 1 ′. _m Each is independently controlled on / off. For example, when the first drive data GA ₁ is at the logic level “0”, the switching element S ₁ is turned off. On the other hand, when the first drive data GA ₁ is at the logic level “1”, the switching element S ₁ is turned on. The light emission drive current i supplied from Q1 is derived to the output terminal X1. When the first drive data GA _m is at the logic level “0”, the switching element S _m is turned off, and when it is at the logic level “1”, it is turned on and supplied from the transistor Q _m . to derive the light emission drive current i to the output terminal X _m. In this way, the light emission drive current i output from each of the transistors Q _{1 to} Q _m is supplied to the anode of the ELDP 10 ′ through the output terminals X _{1 to} X _m as shown in FIG. supplied to each of the lines a ₁ to a _m.

The pixel drive potential V _BE is applied to the emitter of the transistor Q ₀ in the control current output circuit CO via the resistor R 0, and the base of the transistor Q _b in the reference current control circuit RC is connected to the base thereof. . In this case, the resistance value of the resistor R0 is the same as the resistance R _r of the reference current control circuit RC, further, the transistor Q ₀ has a respective transistor Qa and Qb in the reference current control circuit RC, having the same characteristics It is. Therefore, the transistor Q ₀ in the control current output circuit CO and the reference current control circuit RC form a current mirror, and between the emitter and collector of the transistor Q ₀ , the current amount is the same as the reference current IREF. Current flows. Control current output circuit CO is such current and the control current ic, supplied to the input terminal I _in the second anode line drive circuit 22 through the output terminal I _out of this. That is, anode lines A ₁ to A each supplies light emission drive current i and the same currents of _m of the first anode line drive circuit 21 is ELDP10 'is supplied as a control current ic to the second anode line drive circuit 22 It is.

The second anode line drive circuit 22 includes a drive current control circuit CC, a switch block SB, and transistors Q _{1 to} Q _m and resistors R _{1 to} R _m as m current drive sources. The collector and base of the transistor Qc in the drive current control circuit CC is connected to the input terminal I _in, its emitter is grounded to the earth potential via the resistor R _Q1. Therefore, the control current ic that is output from the first anode line drive circuit 21, the collector of the transistor Q _c via its input I _in - flows between the emitter.

In addition, the pixel drive potential V _BE is applied to the emitter of the transistor Q _e through the resistor R _S in the drive current control circuit CC, and the collector of the transistor Q _d is connected to the base and collector thereof. Base of such transistor Q _d are respectively connected to the collector and base of the transistor Q _c, the emitter thereof is grounded to a ground potential via the resistor R _Q2. At this time, the transistor Q _{0 of} the first anode line drive circuit 21 and each of the transistors Q _c , Q _d , and Qe are transistors having the same characteristics, and further the resistance R ₀ in the first anode line drive circuit 21. And the resistance R _S has the same resistance value. Therefore, the same current and the control current ic supplied from the first anode line drive circuit 21 flows between the collector-emitter of the transistor Q _d.

Further, the pixel drive potential VBE is applied to the emitters of the transistors Q _{1 to} Q _m in the second anode line drive circuit 22 via the resistors R _{1 to} R _m, respectively. The base of the transistor Q _e is connected. At this time, the resistance values of the resistors RS and R _{1 to} R _m are the same, and the transistors Q _{1 to} Q _m , Qd, and Qe have the same characteristics. Therefore, the drive current control circuit CC and the transistors Q _{1 to} Q _m form a current mirror, and the first anode line drive circuit 21 is connected between the emitters and collectors of the transistors Q _{1 to} Q _m. A light emission drive current i having the same amount of current as the supplied control current 1c flows and is output respectively. That is, the light emission drive current i output from each of the transistors Q _{1 to} Q _m of the second anode line drive circuit 22 by the drive current control circuit CC is the same as the light emission drive current output from the first anode line drive circuit 21. Therefore, the current amount is adjusted.

The switch block SB is provided with _m switching elements S _{1 to} S _m for leading the light emission drive current i output from each of the transistors Q _{1 to} Q _m to the output terminals X _{1 to} X _m , respectively. ing. At this time, in the switch block SB of the second anode line drive circuit 22, the switching elements SI to Sm are independent according to the logic levels of the second drive data GB1 to GBm supplied from the light emission control circuit 1 ′. Thus, on / off control is performed.

For example, when the second drive data GB ₁ is at the logic level “0”, the switching element S ₁ is turned off, whereas when the second drive data GB ₁ is at the logic level “1”, the transistor is turned on. The light emission drive current i supplied from Q ₁ is derived to the output terminal X ₁ . When the second drive data GB _m is at the logic level “0”, the switching element S _m is turned off, and when it is at the logic level “1”, it is turned on and supplied from the transistor Q _m . Thus to derive the light emission drive current i to the output terminal X _m, the transistors Q ₁ to Q _m light emission drive current i output from each of the second anode line drive circuit 22, respective output terminals X ₁ to X _m As shown in FIG. 8, the anode lines A _{m + 1 to} A _2m of the ELDP 10 ′ are supplied to the anode lines.

As described above, in the drive circuit described in the above publication, in addition to the current source (transistors Q _{1 to} Q _m ) for generating the light emission drive current, the light emission drive current is supplied to the anode line drive circuit. A drive current control circuit CC that maintains a current amount corresponding to the input control current and a control current output circuit CO that outputs the light emission drive current itself as a control current are provided. Here, when the anode line of the display panel is divided and driven by a plurality of anode line drive circuits constructed in individual IC chips, the first anode line drive circuit is a second anode line drive circuit. Controls the amount of light emission drive current to be output on the basis of the light emission drive current actually output. Therefore, even if there is a variation in characteristics between the IC chips (as anode line drive circuits), the amount of light emission drive current output from each IC chip is substantially the same. Can be obtained.

  In the technique described in the above-mentioned publication, when a reference current is passed from the first anode line drive circuit 21 configured by an IC chip to the second anode line drive circuit 22 configured by another IC chip, A mirror is used. For this reason, when current variation occurs in the current mirror, output current varies among a plurality of IC chips. As a result, there is a disadvantage that uniform light emission luminance cannot be obtained on the display panel.

  The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to reduce the current variation generated in the current mirror, and to reduce the variation in the reference current among a plurality of IC chips. To provide a display panel driving circuit that can be eliminated.

Means for solving the problem

[Means for Solving the Problems]
A display panel driving circuit according to an aspect of the present invention operates with a plurality of reference current sources each generating a reference current, and a reference current provided corresponding to the plurality of reference current sources and provided from the corresponding reference current source A plurality of IC chips each including a current mirror circuit, and a plurality of cathode lines each carrying a plurality of display lines, and a plurality of anode lines arranged crossing each of the plurality of cathode lines. A plurality of self-light-emitting elements forming a display panel are formed at each of intersections of the plurality of cathode lines and the plurality of anode lines, and a drive current for driving the plurality of self-light-emitting elements is supplied to the current mirror circuit. by synchronizing signal synchronized with a display panel driving circuit for supplying to the plurality of anode lines generated, the scan line selection signal by, From among the serial plurality of cathode lines, the timing of switching the cathode lines corresponding to the display line indicated by the scan line selection signal, the plurality of reference current sources corresponding relationship between the plurality of reference current source and the plurality of IC chips It is characterized by including switching means for performing switching control so that these are sequentially used.

Further , when the number of the IC chips is N, the switching means has a duty ratio 1 / N in which a high level period is 1 / N in a period of making a round using the plurality of reference current sources in order. The electrical connection state between the plurality of reference current sources and the plurality of IC chips may be switched and controlled by the synchronization signal . The self-luminous element may be composed of an electroluminescent element.

  In short, a plurality of IC chips have their own current sources, and by switching control so that the current sources of each IC chip are used in order, each IC chip is the average of all the chips over a long period of time. It operates with a large current. That is, rather than using the reference current of the main IC chip as in the prior art, a plurality of IC chips can operate with an average current.

Next, embodiments of the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
FIG. 1 is a diagram showing a configuration of a main part in an embodiment of a display panel driving circuit according to the present invention. In the figure, a case where there are two IC chips is shown.

As shown in the figure, inside the first anode line drive circuit 21 which is an IC chip, a current source I _org1 for outputting a reference current for the current mirror and the current source I _{org1 are} outputted. And a switching circuit SW1 having a reference current I _cm1 as one input. The reference current I _cm1 is also input to the switching circuit SW2 in the second anode line drive circuit 22 that is an IC chip.

In addition, in the anode line drive circuit 22, a current source I _org2 that outputs a reference current for the current mirror and a switching circuit SW2 that has a reference current I _cm2 output from the current source I _org2 as one input. And are provided. The reference current I _cm12 is also input to the switching circuit SW1 in the anode line drive circuit 21.
Assume that the internal circuit 22-1 in the anode line drive circuit 21 and the internal circuit 22-2 in the anode line drive circuit 22 have the same configuration as the anode line drive circuit 22 in FIG. That is, the internal circuits 22-1 and 22-2 both have a current mirror circuit, and a drive current for driving the display panel is generated by the current mirror circuit.

Of the reference current I _cm1 and the reference current I _cm2 , one selected by the switching circuit SW1 is input to the internal circuit 22-1 as the reference current I _ref1 . Similarly, the reference current I _ref2 selected from the reference current I _cm1 and the reference current I _cm2 by the switching circuit SW2 is input to the internal circuit 22-2.
The switching circuits SW1 and SW2 are controlled by a synchronization signal 200 synchronized with the scanning line selection signal. The switching circuit SW1 and the switching circuit SW2 are _subjected to switching control so that different ones of the reference current I _cm1 and the reference current I _cm2 are selected. That is, the output currents from the current source I _org1 and the current source I _org2 are switched by a switching circuit that is _turned on and off by an external synchronization signal 200 and is time-division controlled (averaged over time).

By doing so, current is alternately sent to the internal circuit, and the currents averaged by the anode line drive circuits 21 and 22 are used internally. By performing the time-division control switch, the reference current I _ref1, the reference current I _ref2 to the anode line drive circuits 21 and 22, current source I _org1, the reference current I _cm1 and the reference current I from the current source I _org2 Time average with _cm2 . Therefore, the reference current I _ref1 and the reference current I _ref2 are equal. Specifically, the average current is obtained by switching control so that the current source I _org1 and the current source I _org2 of the anode line drive circuits 21 and 22 are alternately switched at a duty ratio of ½ (50%). Can do. By driving the display panel using the averaged current in this way, the variation in the reference current can be eliminated, and uniform light emission luminance can be obtained on the display panel.

FIG. 2 is a timing chart showing the operation of the switching circuit. The figure shows a reference current I _ref1 to the anode line drive circuit 21, a reference current I _ref2 to the anode line drive circuit 22, and a scanning line selection signal. As shown in the figure, switching control of the switching circuits SW1 and SW2 is performed at the timing of switching the cathode line. By performing in this way the switching control, the current source alternately and the current I _{cm @ 2} which is the output of the current I _cm1 and current source I _org2 which is the output of I _org1, the reference current I _ref1, anode line drive circuit 21 as I _ref2 , 22. For this reason, the current is averaged and supplied to a plurality of anode line drive circuits. Therefore, even if there are variations in the current output from each of the plurality of IC chips (anode line drive circuits), when viewed over a long period of time, each IC chip operates with an averaged current and eliminates variations in the reference current. Can do. Therefore, particularly homogeneous light emission luminance can be obtained on the display panel, accompanied by the switching control, the switching operation of the cathode ray current be carried out in a period in which the OFF state, the reference current I _ref1 and the reference current I _ref1 Noise can be minimized. Accordingly, adverse effects such as flickering of the display screen can be suppressed, and better image display can be performed.

Here, a configuration example of the switching circuit is shown in FIG. The switching circuits SW1 and SW2 shown in the figure include two analog switches to which the currents I _cm1 and I _cm2 output from the corresponding reference current sources I _ref1 and I _ref2 are input, respectively. ing. The switching circuit SW1 is composed of analog switches SW11 and SW12. Both of these analog switches SW11 and SW12 are configured by an N-type MOS (Metal Oxide Semiconductor) transistor and a P-type MOS transistor having a common source and drain. The gates of the N-type MOS transistor and the P-type MOS transistor serve as switching control terminals, and on / off is controlled by signals inverted from each other. The outputs of the analog switches SW11 and SW12 are combined into one and become the above-described reference current _Iref1 .

Similarly, the switching circuit SW2 includes analog switches SW21 and SW22. These analog switches SW21 and SW22 are both constituted by an N-type MOS transistor and a P-type MOS transistor having a common source and drain. The gates of the N-type MOS transistor and the P-type MOS transistor serve as switching control terminals, and on / off is controlled by signals inverted from each other. The outputs of the analog switches SW21 and SW22 are integrated into the reference current I _ref2 described above. In the same figure, an inverter INV for inverting the synchronization signal 200 described above is provided. This inverter INV is constituted by, for example, a well-known CMOS (Complementary Metal Oxide Semiconductor) inverter circuit.

  The synchronization signal 200 is directly input to the N-type MOS transistor of the analog switch SW11 and the P-type MOS transistor of the analog switch SW12, whereas the P-type MOS transistor of the analog switch SW11 and the N-type MOS transistor of the analog switch SW12 are The synchronization signal 200 is logically inverted by the inverter INV and input. Therefore, the analog switch SW11 is turned on when the synchronization signal 200 is at a high level, and the analog switch SW12 is turned on when the synchronization signal 200 is at a low level.

  On the other hand, the synchronization signal 200 is directly input to the P-type MOS transistor of the analog switch SW21 and the N-type MOS transistor of the analog switch SW22, whereas the N-type MOS transistor of the analog switch SW21 and the P-type MOS transistor of the analog switch SW22 are input. The synchronization signal 200 is input to the inverter after being logically inverted by the inverter INV. Therefore, the analog switch SW22 is turned on when the synchronization signal 200 is at a high level, and the analog switch SW21 is turned on when it is at a low level.

In such a configuration, when the synchronization signal 200 is at a high level, the analog switches SW11 and SW22 are turned on. At this time, current I _cm1 is output as a current I _ref1, current I _{cm @ 2} is output as a current I _ref2. On the other hand, when the synchronization signal 200 is at a low level, the analog switches SW12 and SW21 are turned on. At this time, current I _{cm @ 2} is output as a current I _ref1, current I _cm1 is output as a current I _ref2.

Therefore, if the synchronization signal has a duty ratio of 1/2 (50%), the current I _cm1 and the current I _cm2 are averaged and output as the current I _ref1 and the current I _ref2 . Therefore, even if there are variations in the current output from each of the plurality of IC chips, when viewed in a long time, each IC chip operates with an averaged current, and variations in the reference current can be eliminated. Accordingly, uniform light emission luminance can be obtained on the display panel.

  By the way, in the prior art, the same current is distributed from one master IC chip (internal current source) to another slave IC chip (see FIG. 10). In this conventional configuration, the variation in current as a whole product is determined by the reference current of the master current source. When the variation of the master current is plus or minus 10%, even if the current is distributed to the slave without any error, it does not improve from the variation of 10% as a whole. On the other hand, in the present invention, since the IC chips as current sources are sequentially switched, even if the variation of each current source is 10%, it is averaged. The variation is 10 / √N. Therefore, the variation in current is 10% or less. In other words, the display luminance variation of the organic EL panel product is determined by the variation of the master reference current in the case of the conventional technology, whereas in the present invention, the variation of the current source incorporated in each IC chip to be used is determined. Since the average is obtained, the luminance variation as a panel product can be improved.

  Although the case where two IC chips are used has been described above, the same effect can be obtained by switching the current in the same manner even when more IC chips are used. For example, when three IC chips are used, one analog switch in FIG. 3 is added for each IC chip, and switch switching control is performed by a synchronization signal having a pulse duty ratio of 1/3 (about 33%) in each IC chip. By doing so, the current applied to the IC chip may be averaged. That is, when the number of IC chips is N, the electrical connection state between the reference source flow source and the IC chip is controlled by switching with a pulse having a duty ratio of 1 / N.

  As described above, by switching the correspondence relationship (electrical connection state) between the IC chip and the reference current source at a predetermined period, the current applied to each IC chip is averaged, and the variation in output current between the IC chips is reduced. be able to.

Effect of the invention

  As described above, according to the present invention, the same current is not supplied to a plurality of IC chips, but is averaged and supplied, so that even if the currents output from the plurality of IC chips vary, it takes a long time. In other words, each IC chip operates with an averaged current, and variations in the reference current can be eliminated. Therefore, there is an effect that uniform light emission luminance can be obtained on the display panel.

  It is a figure which shows the structure of the principal part of the display panel drive circuit by this invention.   2 is a timing chart showing switching timing of a switching circuit in the display panel drive circuit of FIG. 1.   It is a figure which shows the structural example of a switching circuit.   It is a figure which shows schematic structure of an EL element.   It is a figure which shows the equivalent circuit which shows the characteristic of EL element electrically.   It is a figure which shows schematic structure of the EL display apparatus which displays an image using the EL display panel formed by arranging a plurality of EL elements in a matrix.   It is a figure which shows the supply timing of pixel data and a scanning line selection signal.   It is a figure which shows the case where an anode wire drive circuit is constructed | assembled with two IC chips.   It is a figure which shows the supply timing of the pixel data by a light emission control circuit, and a scanning line selection control signal.   It is a figure which shows the internal structural example of an anode line drive circuit.

DESCRIPTION OF SYMBOLS 1 Light emission control circuit 2 Anode line drive circuit 3 Cathode line scanning circuit 10 ELDP
21 and 22 Anode line drive circuit 22-1 and 22-2 Internal circuit 30 Cathode line scanning circuit 100 Transparent substrate 101 Transparent electrode 102 Organic functional layer 103 Metal electrode 200 Synchronization signal INV Inverter SW1, SW2 Switching circuit SW11, SW12
SW21, SW22 Analog switch

Claims (3)

A plurality of reference current sources each generating a reference current; and a plurality of IC chips each including a current mirror circuit provided corresponding to the plurality of reference current sources and operated by a reference current supplied from the corresponding reference current source; the a, a plurality of cathode lines responsible for each of a plurality of display lines, a plurality of self-luminous elements constituting the display panel the plurality of cathode lines each plurality of which are crossed to sequence the anode line is formed , are formed in each of intersections of the plurality of cathode lines and the plurality of anode lines, the driving current for driving a plurality of self-luminous element and generated by the current mirror circuit supplies to the plurality of anode lines a display panel driving circuit, a synchronizing signal synchronized with the scanning line selection signal, from among the plurality of cathode lines, indicated by the scan line selection signal At the timing of switching the cathode lines corresponding to the display line, comprise a switching means for switching control so the correspondence relationship between the plurality of reference current source and the plurality of IC chips will use in order to the plurality of reference current source A display panel driving circuit.
When the number of the IC chips is N, the switching means uses the plurality of reference current sources in order and makes a cycle of a high level in a period of one cycle, and the duty ratio is 1 / N. 2. The display panel driving circuit according to claim 1, wherein an electrical connection state between the plurality of reference current sources and the plurality of IC chips is controlled by a synchronization signal.
  The display panel driving circuit according to claim 1, wherein the self-luminous element is configured by an electroluminescence element.

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