JP5102418B2 - Display panel drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display panel drive circuit, and more particularly to a display panel drive circuit comprising self-luminous elements such as organic electroluminescent elements.
[0002]
[Prior art]
An organic electroluminescence (hereinafter referred to as EL) element is known as a self-luminous element for realizing a thin display device with low power consumption. A display device using this EL element and its driving circuit are described in JP-A-2001-42821.
[0003]
FIG. 5 is a diagram showing a schematic configuration of such an EL element. As shown in the figure, the EL element has at least one layer composed of an electron transport layer, a light emitting layer, a hole transport layer, etc. on a transparent substrate 100 composed of a glass plate or the like on which a transparent electrode 101 is formed. The organic functional layer 102 and the metal electrode 103 are laminated.
FIG. 6 is a diagram showing an equivalent circuit that electrically shows the characteristics of the EL element. As shown in the figure, the EL element can be replaced by a capacitive component C and a diode characteristic component E coupled in parallel to the capacitive component C. Here, when a positive voltage is applied to the anode of the transparent electrode 101 and a negative voltage is applied to the cathode of the metal electrode 103 to apply a direct current between the transparent electrode and the metal electrode, charges are accumulated in the capacitive component C. At this time, when the barrier voltage or light emission threshold voltage specific to the EL element is exceeded, current starts to flow from the electrode (the anode side of the diode component E) to the organic functional layer serving as the light emitting layer, and the organic functional layer has an intensity proportional to this current. 102 emits light.
[0004]
FIG. 7 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of the EL elements are arranged in a matrix. In the figure, an ELDP 10 serving as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line, and an array that intersects each of the cathode lines B _{1 to} B _n. is the m anode lines (transparent electrodes) a ₁ to a _m are formed. To each of the intersecting portions of the cathode lines B ₁ .about.B _n and anode lines A ₁ ~A _m (n × _m pieces), EL elements E ₁₁ to E _nm having the above structure is formed. Each of the EL elements E _{11 to} E _nm bears one pixel as the ELDP 10.
[0005]
The light emission control circuit 1 converts input image data for one screen (n rows, m columns) into pixel data D _{11 to} D _nm corresponding to each pixel of the ELDP 10, that is, each of the EL elements E _{11 to} E _nm. These are converted, and these are sequentially supplied to the anode line drive circuit 2 for each row as shown in FIG. For example, the pixel data D _{11 to} D _nm are m data bits that specify whether or not light emission is performed for each of the EL elements E _{11 to} E _nm belonging to the first display line of the ELDP 10. When the logic level is “1”, “light emission” is indicated, and when the logic level is “0”, “non-light emission” is indicated.
[0006]
Further, as shown in FIG. 8, the light emission control circuit 1 should sequentially scan each of the first display line to the nth display line of the ELDP 10 in synchronization with the supply timing of the pixel data for each row. A scanning line selection signal is supplied to the cathode line scanning circuit 3. First, the anode line drive circuit 2 extracts all data bits of the logic level “1” designating “light emission” from the m data bits in the pixel data group. Next, the anode line A ₁ selects all from among to A _m, connects the constant current source only to the selected anode lines, a predetermined pixel drive currents belonging to the "column" corresponding to the data bits each obtained by this extraction i is supplied.
[0007]
The cathode line scanning circuit 3 selectively selects a cathode line corresponding to the display line indicated by the scanning line selection signal from the cathode lines B _{1 to} B _n and sets the cathode line to the ground potential. A predetermined high potential V _CC is applied to each of the cathode lines. The high potential V _CC is set to substantially the same value as the voltage across the EL element when the EL element emits light with a desired luminance (voltage determined based on the amount of charge to the parasitic capacitance C).
[0008]
At this time, a light emission driving current flows between the “column” to which the constant current source is connected by the anode line drive circuit 2 and the display line set to the ground potential by the cathode line scanning circuit 3. The EL elements formed so as to intersect the display line and the “column” emit light according to the light emission drive current. On the other hand, no current flows between the display line set to the high potential V _CC by the cathode line scanning circuit 3 and the “column” to which the constant current source is connected. The EL elements formed to intersect do not emit light.
[0009]
Above operation is the pixel data _{D 11 ~D 1m, D 21 ~D} 2m, ..., when implemented on the basis of the respective D _n1 to D _nm, On the screen of ELDP10, the input image data A light emission pattern corresponding to one field, that is, an image is displayed.
[0010]
[Problems to be solved by the invention]
In recent years, it has become necessary to increase the number of display lines, that is, the cathode lines B and increase the number of anode lines A to increase the definition of the screen in order to realize a large display panel. Therefore, as the number of each of these anode lines A and cathode lines B increases, the circuit scale of each of the anode line drive circuit 2 and the cathode line scanning circuit 3 also increases. There is concern about deterioration. Therefore, it is conceivable to construct each of the anode line drive circuit 2 and the cathode line scanning circuit 3 with a plurality of IC chips.
[0011]
For example, as shown in FIG. 9, it is conceivable to construct the anode line drive circuit 2 with two IC chips 2a and 2b. When constructing this way the anode line drive circuit 2 in the two IC chips 2a and 2b, as shown in Figure 10, from the anode lines A ₁ to the anode line A _N driven in IC chip 2a, an anode It made from line a _{N + 1} to the anode line a _m to be driven by the IC chip 2b. In the figure, “1” to “N−1”, “N”, “N + 1”, and “N + 2” to “m” are attached as current output to each pixel element, that is, drive output channel numbers. ing.
[0012]
By the way, when the anode line drive circuit 2 is constructed with a plurality of IC chips, there may be a difference in the value of the light emission drive current to be supplied to the anode line between the IC chips due to manufacturing variations and the like. Therefore, due to such a difference in the light emission drive current, regions having different luminances are formed on the ELDP 10 screen, and in particular, there is a disadvantage that the luminance step on the boundary impairs the image quality.
[0013]
The present invention has been made to solve the above-described drawbacks of the prior art, and an object of the present invention is to provide a display panel driving circuit capable of suppressing image quality degradation when an anode line drive circuit is constructed with a plurality of IC chips. Is to provide.
[0014]
[Means for Solving the Problems]
The display panel drive circuit according to claim 1 of the present invention includes a plurality of first and second IC chips, and a plurality of drive outputs belonging to a drive output group of the first and second IC chips, and a plurality of display lines. For driving a plurality of self-luminous elements constituting a display panel in which a cathode line and a plurality of anode lines which are first and second drive line groups arranged to intersect each of the plurality of cathode lines are formed a corresponding drive line of the driving lines belonging to the first and second drive line groups, a display panel driving circuit for applying respectively a first drive output belonging to the drive output unit of the first IC chip When a second drive output belonging to the drive output unit of the second IC chip as input, either of the first and second drive output, the scanning line selection signal, said plurality At the same timing as the cathode lines from among the cathode lines corresponding to the display line indicated by the scan line selection signal is selected, and select switch, drive lines belonging to the selected drive output to the first driving line group A switching circuit for supplying a drive line adjacent to the second drive line group.
[0015]
A display panel driving circuit according to a second aspect of the present invention is the display panel driving circuit according to the first aspect, wherein the switching circuit is formed in the first IC chip.
According to a third aspect of the present invention, in the display panel drive circuit according to the first or second aspect, the second IC chip has a dummy drive output that does not correspond to the drive lines constituting the second drive line group. The dummy drive output is input to the switching circuit as the second drive output.
[0016]
The display panel driving circuit according to a fourth aspect of the present invention is characterized in that, in any one of the first to third aspects, the plurality of self-luminous elements constituting the display panel are electroluminescent elements. In short, in the present invention, a dummy drive output is provided, and the original drive output in the adjacent IC chip is switched at a predetermined cycle and applied to the drive line. Variation can be suppressed. Therefore, when the anode line drive circuit is constructed with a plurality of IC chips, the luminance step in the two display areas having different luminances on the display becomes gradual due to the difference in the current driving ability between the IC chips, and the image quality is improved. Deterioration can be suppressed. If the switching circuit is formed in the IC chip, it is not necessary to prepare a new space for mounting the switching circuit.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.
FIG. 1 is a diagram showing a configuration of a main part of an embodiment of a display panel driving circuit according to the present invention. As shown in the figure, the display panel driving circuit according to the present embodiment includes a first IC chip 2a and a second IC chip 2b.
[0018]
The first IC chip 2a has drive outputs of channel numbers 1 to N + 1. The drive output of the channel numbers 1 to N-1 is supplied to the anode line A ₁ ~A _N-1, the pixel elements are driven to their corresponding anode lines A ₁ ~A _N-1.
On the other hand, the second IC chip 2b has drive outputs of channel numbers N to m. The drive output of the channel number N + 2 to m is supplied to the anode line A _{N + 2} ~A _m, pixel elements corresponding to those anode lines A _{N + 2} ~A _m are driven.
[0019]
In addition to the drive output of the channel number N of the first IC chip 2a, the drive output of the channel number N of the second IC chip 2b is input to the switching circuit SW1 in the first IC chip 2a. In the switching circuit SW1, and outputs the two drive output alternatively, are given to the anode line A _N.
That is, the switching circuit SW1 has a channel number N drive output belonging to the drive output group (channel numbers 1 to N + 1) of the IC chip 2a and a channel number N belonging to the drive output group (channel numbers N to m) of the IC chip 2b. of an input and a drive output, by switching these two drive output in a predetermined period, the second driving line group of anode line belonging to the first is a drive line group anode lines a ₁ ~ anode line a _N giving the anode line a _N which is disposed adjacent to one anode line a _{N +1 ~} anode line a _m. The drive output of the channel number N of the IC chip 2b, the _second-anode lines A _{N +1} is driven line group anode lines A each constituting the _m anode lines dummy drive output that does not correspond to the (drive line) d2 It is.
[0020]
Similarly, in addition to the drive output of channel number N + 1 of the second IC chip 2b , the drive output of channel number N + 1 of the first IC chip 2a is input to the switching circuit SW2 in the second IC chip 2b. . In the switching circuit SW2, these two drive outputs are alternatively output and given to the anode line AN + 1.
That is, the switching circuit SW2 has a channel number N + 1 drive output belonging to the drive output group (channel numbers N to m) of the IC chip 2b and a channel number N + 1 belonging to the drive output group (channel numbers 1 to N + 1) of the IC chip 2a. The two driving outputs are switched at a predetermined cycle, and the first driving line group among the anode lines belonging to the anode line A _{N +1} to the anode line Am that is the second driving line group. A given anode line A1 to an anode line AN + 1 is provided adjacent to the anode line AN + 1. The drive output of channel number N + 1 of the IC chip 2a is a dummy drive output d1 that does not correspond to each anode line (drive line) constituting the anode line A1 to the anode line AN that is the first drive line group.
[0021]
As described above, in the switching circuits SW1 and SW2, in addition to the original drive output in the IC chip, the dummy drive output from another adjacent IC chip is also input, and the two drive outputs are switched at a predetermined cycle. Time-division control is performed by giving the anode wire. The IC chips 2a and 2b are provided with dummy outputs at both ends. The dummy output in one IC chip 2a is input to the other IC chip 2b. The dummy output input from the IC chip 2b is input to the IC chip 2a.
[0022]
Since the switching circuits SW1 and SW2 are formed inside the IC chips 2a and 2b, it is only necessary to add the wirings S1 and S2, and it is not necessary to prepare a new mounting space.
FIG. 2 is a timing chart showing drive switching timing by this drive circuit. In the figure, provided to the anode line A _N, the ratio between the drive output of the drive output and the IC chip 2b of the IC chip 2a (hereinafter, referred to as the switching ratio) is an example of the case of 2: 1 is shown .
[0023]
When the cathode lines B ₁ , B ₂ , B ₃ , and B ₄ are sequentially selected by the scanning line selection signal shown in the same drawing, the drive output of the IC chip 2a or 2b is given to each anode line. The anode line A _N-1 is given the drive output of the channel number N-1 of the IC chip 2a, and the anode line A _{N + 2} is given the drive output of the channel number N + 2 of the IC chip 2b.
[0024]
For the anode line A _N , the drive output of channel number N of the IC chip 2a and the drive output of channel number N of the IC chip 2b (dummy drive output) are alternatively given at a predetermined cycle. In this example, after a period in which the drive output of the channel number N of the IC chip 2a is given twice, a period in which the drive output of the channel number N of the IC chip 2b is given once. That is, the switching ratio between the IC chip 2a and the IC chip 2b is 2: 1.
[0025]
For the anode line A _{N + 1} , the drive output of the channel number N + 1 of the IC chip 2b and the drive output of the channel number N + 1 of the IC chip 2a (dummy drive output) are alternatively given at a predetermined cycle. It is done. In this example, after a period in which the driving output of the channel number N of the IC chip 2b is given twice, a period of giving the driving output of the channel number N in the IC chip 2a occurs once. That is, the switching ratio between the IC chip 2a and the IC chip 2b is 1: 2.
[0026]
However, the switching cycle is not limited to that shown in the figure, and switching may be performed at a cycle according to another switching ratio.
Here, the relationship between the channel number of the anode line and the output current will be described with reference to FIG. The figure shows the case where the switching ratio in the switching circuit is 1: 1, the case where it is 2: 1, and the case where switching is not performed. The solid line connecting black circles in the figure, if not to switch, the change between the channels of the output current and the anode lines A _{N + 1} channel of the output current of the anode lines A _N is abrupt. Therefore, such a luminance step deteriorates image quality.
[0027]
On the other hand, the solid line connecting the double circles in the figure shows the case where the switching ratio is 1: 1, and the output current of the channel of the anode line A _N and the output current of the channel of the anode line A _{N + 1} . There is almost no change between. The change between the output current of the channel of the anode line A _{N + 1} and the output current of the channel of the anode line A _{N + 2} , and the change of the anode line A _N-1 and the anode line A _N are not changed. Smaller than the change between line A _N and anode line A _{N + 1} .
[0028]
Dashed line connecting the white circles in the figure, in the case where the switching ratio 2: 1, the channel of the anode line A _N-1 of the anode lines from the channel A _N, through the channel of the anode line A _{N + 1,} the anode line The change in the output current up to the A _{N + 2} channel is gradual. For this reason, the level | step difference of a brightness | luminance is smaller than the case where a switching ratio is set to 1: 1.
When an anode line drive circuit is constructed with a plurality of IC chips, there is a difference in the value of the light emission drive current to be supplied to the anode line between the IC chips due to manufacturing variations, etc., and there are areas with different brightness on the screen. I can do it. Even in such a case, by changing the drive output of the IC chip at a predetermined cycle and giving it to the drive line at the boundary of the two drive line groups, the luminance change on the boundary between the regions having different luminance becomes smooth. The image quality is not impaired.
[0029]
Here, a configuration example of the switching circuit SW1 provided corresponding to the anode line A _N is shown in FIG. The switching circuit SW1 shown in the figure includes two analog switches 21 and 22 to which a current output from the channel number N of the corresponding IC chip is input. The analog switches 21 and 22 are both constituted by an N-type MOS (Metal Oxide Semiconductor) transistor and a P-type MOS transistor having a common source and drain. The gates of the N-type MOS transistor and the P-type MOS transistor serve as switching control terminals, and on / off is controlled by signals inverted from each other.
[0030]
In addition, the figure includes a counter 20 that provides an output pulse 200 to the gate that is the switching control terminal, and an inverter INV that inverts the output pulse 200. Note that the inverter INV is constituted by, for example, a known CMOS (Complementary Metal Oxide Semiconductor) inverter circuit.
[0031]
The output pulse 200 of the counter 20 is directly input to the N-type MOS transistor of the analog switch 21 and the P-type MOS transistor of the analog switch 22, whereas the P-type MOS transistor of the analog switch 21 and the N-type MOS of the analog switch 22 are input. An output pulse 200 is logically inverted by an inverter INV and input to the transistor. Therefore, when the output pulse 200 of the counter 20 is at a high level, the analog switch 21 is turned on and the analog switch 22 is turned off. On the other hand, when the output pulse 200 of the counter 20 is at a low level, the analog switch 21 is turned off and the analog switch 22 is turned on.
[0032]
A clock CLK synchronized with a scanning line selection signal (see FIG. 2) is input to the counter 20, and a count operation is performed by the clock CLK. Then, an output pulse 200 having a duty ratio corresponding to the above-described ratio is generated by the counting operation. By controlling the on / off state of the analog switches 21 and 22 by the output pulse 200, the analog switches 21 and 22 are alternatively turned on.
[0033]
That is, as shown in FIG. 5B, when the output pulse 200 from the counter 20 that receives the clock CLK is applied to the analog switches 21 and 22, the analog switch 22 is turned on. The ratio to the period in which the analog switch 21 is turned on is 2: 1. As a result, the anode line A _N is provided with the drive output of the channel number N of the IC chip 2a and the drive output of the channel number N of the IC chip 2b in a ratio of 2 to 1. Similarly, the switching circuit SW2 provided corresponding to the anode line A _{N + 1} may be configured using two analog switches and a counter.
[0034]
Although the case where two IC chips are used has been described above, the present invention is not limited to this, and it is obvious that the present invention can be applied to a case where more IC chips are used. Also in this case, a dummy drive output that does not correspond to each drive line corresponding to the IC chip is provided, and the original drive output in the adjacent IC chip is switched in a predetermined cycle in the same manner as described above, so that the drive line To give. By doing so, the luminance step between the two display areas having different luminances on the display becomes gentle due to the difference in current drive capability between the IC chips, and the deterioration of the image quality is suppressed.
[0035]
Further, the case where one dummy drive output is provided for each adjacent IC chip has been described above. However, the present invention is not limited to this, and the present invention can also be applied to the case where a plurality of dummy drive outputs are provided for each. Is clear. A plurality of dummy drive outputs corresponding to each drive line corresponding to the IC chip are provided, and the original plurality of drive outputs in the adjacent IC chip are switched in a predetermined cycle in the same manner as described above and given to the drive lines. That's fine. By changing the switching ratio for each of the plurality of drive outputs, the brightness difference between the two display areas with different brightness on the display becomes more gradual due to the difference in current drive capability between the IC chips, and the image quality deteriorates. It is suppressed.
[0036]
Further, the case where the pixel element constituting the display panel is an EL element has been described above. However, it is obvious that the present invention can be applied to a case where the pixel element is other than that.
[0037]
【Effect of the invention】
As described above, the present invention provides a plurality of anode line drive circuits by providing a dummy drive output, switching the original drive output in the adjacent IC chip at a predetermined cycle, and applying it to the drive line. When this IC chip is constructed, the difference in current driving ability between the IC chips makes the luminance step in the two display areas having different luminance on the display gentle so that deterioration of image quality can be suppressed. .
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a main part of an embodiment of a display panel driving circuit according to the present invention.
FIG. 2 is a timing chart showing drive switching timing by the display panel drive circuit of FIG. 1;
FIG. 3 is a diagram showing a relationship between a channel number of an anode line and an output current.
4A is a diagram illustrating a configuration example of a switching circuit, and FIG. 4B is a timing chart illustrating an operation of the switching circuit of FIG.
FIG. 5 is a diagram showing a schematic configuration of an EL element.
FIG. 6 is a diagram showing an equivalent circuit that electrically indicates the characteristics of an EL element.
FIG. 7 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix.
FIG. 8 is a diagram illustrating the supply timing of pixel data and a scanning line selection signal.
FIG. 9 is a diagram showing a case where an anode line drive circuit is constructed with two IC chips.
FIG. 10 is a diagram illustrating a correspondence relationship between a drive output of an anode line drive circuit and an anode line.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Light emission control circuit 2a, 2b IC chip 2 Anode line drive circuit 3 Cathode line scanning circuit 20 Counter 21, 22 MOS transistor 100 Transparent substrate 101 Transparent electrode 102 Organic functional layer 103 Metal electrode 200 Output pulse SW1, SW2 Switching circuit

Claims (4)

A drive output that includes the first and second IC chips and belongs to the drive output group of the first and second IC chips is arranged so as to intersect with each of the plurality of cathode lines that carry a plurality of display lines and each of the plurality of cathode lines. drive belonging to the first and second of said first and second drive line group for driving the plurality of self-luminous elements constituting the display panel in which a plurality of anode lines are formed a drive line group which is Display panel drive circuits which are respectively given to corresponding drive lines of the lines, the first drive output belonging to the drive output group of the first IC chip and the first output belonging to the drive output group of the second IC chip. 2 of the drive output and input, the first and one of the second drive output, the scanning line selection signal, the display line indicated by the scan line selection signal from among the plurality of cathode lines In the same timing as cathode ray corresponding is selected, switched and selected, are disposed adjacent to the second drive line group among the drive lines belonging to the selected drive output to the first driving line group A display panel driving circuit comprising a switching circuit for supplying a driving line.   The display panel driving circuit according to claim 1, wherein the switching circuit is formed in the first IC chip.   The second IC chip has a dummy drive output that does not correspond to the drive lines constituting the second drive line group, and the dummy drive output is input to the switching circuit as the second drive output. 3. The display panel driving circuit according to claim 1, wherein the display panel driving circuit is a display panel driving circuit.   The display panel driving circuit according to claim 1, wherein the plurality of self-luminous elements constituting the display panel are electroluminescent elements.

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