JP5217598B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device.

As a semiconductor laser element, one having a semiconductor mesa portion on an n-type InP substrate and a semi-insulating buried layer on a side surface of the semiconductor mesa portion is known (for example, see Non-Patent Document 1). . In this semiconductor laser device, the semiconductor mesa portion has an n-type InP buffer layer, an active layer, and a p-type InP cladding layer in order on the surface of the n-type InP substrate. The buried layer is a semi-insulating InP layer doped with Fe.
"Reliability and Degradation Behaviors of Semi-InsuratingFe-Doped InP Buried Heterostructure Lasers Fabricated by RIE and MOVPE", Hiroyasu Mawatari et al., Journal of Lightwave Technology, Vol. 15, No. 3, March 1997, p534-537.

  In the semiconductor laser device described above, since the p-type InP cladding layer and the buried layer are in contact with each other, Zn which is a dopant of the p-type cladding layer and Fe of the buried layer diffuse to each other, and Resistance decreases. Also, electrons trapped in the buried layer and holes in the p-type InP cladding layer are recombined to form a current leak path. Such a current leak path causes a decrease in efficiency of current injection into the active layer.

  It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device that can improve current injection efficiency into an active layer by preventing formation of a current leak path.

  A semiconductor light emitting device according to the present invention includes a p-type InP substrate, a semiconductor mesa portion having a p-type buffer layer, an active layer, and an n-type cladding layer in order on the surface of the substrate, an n-type block layer, And a semi-insulating buried layer. The n-type block layer is located between the exposed surface of the InP substrate and the buried layer, and between the p-type buffer layer and the buried layer.

  In the manufacturing method of the present invention for suitably manufacturing this semiconductor light emitting device, a) a semiconductor mesa portion including a p-type buffer layer, an active layer, and an n-type cladding layer is formed on the surface of a p-type InP substrate. And b) depositing an n-type semiconductor layer on the exposed surface of the p-type InP substrate and the side surface of the semiconductor mesa portion; and c) depositing on the side surface of the semiconductor mesa portion so as to expose the side surface of the active layer. selectively etching the n-type semiconductor layer; and d) forming a semi-insulating buried layer on the n-type semiconductor layer and on the side of the semiconductor mesa portion after the etching step. Yes.

  According to this manufacturing method, mutual diffusion between the dopant of the p-type InP substrate and the dopant of the buried layer can be prevented, and a semiconductor light emitting device with reduced leakage current can be provided. In addition, since the n-type block layer is formed by deposition and selective etching of the n-type semiconductor layer, a block layer having a suitable shape can be formed. Furthermore, contact between the n-type block layer and the n-type cladding layer can be prevented.

  In the manufacturing method of the present invention, it is preferable that the n-type semiconductor layer is an n-type InP layer, and the etching is performed using an etchant containing hydrochloric acid and acetic acid in the selective etching step. This etching solution is suitable for selective etching of the n-type InP layer deposited on the side surface of the semiconductor mesa portion.

  In the manufacturing method of the present invention, in the step of depositing, the distance between the exposed surface of the p-type InP substrate and the surface of the n-type semiconductor layer is such that the exposed surface of the p-type InP substrate and the bottom surface of the active layer. The n-type semiconductor layer is preferably grown so as to be equal to the distance between them. By making the surface of the n-type semiconductor layer and the bottom surface of the active layer flush with each other, it becomes possible to prevent contact between the n-type semiconductor layer and the n-type cladding layer, and in addition, the buried layer and the p-type The contact area with the buffer layer can be minimized.

  The manufacturing method of the present invention further includes a step of performing wet etching so as to expose a (111) plane of the p-type InP substrate between the step of forming the semiconductor mesa portion and the step of depositing. Is preferred. On the (111) plane of the substrate, the dimensions of the semiconductor layer to be grown can be controlled well. Therefore, by forming the n-type semiconductor layer on the (111) plane, the dimension of the n-type semiconductor layer can be easily controlled, and in particular, the thickness of the n-type semiconductor layer can be easily controlled.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor light-emitting device which can improve the current injection efficiency to an active layer by preventing formation of a current leak path is provided.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a flowchart of a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention. In the present manufacturing method shown in FIG. 1, first, in step S1, a semiconductor mesa portion is formed on a p-type InP substrate.

  FIG. 2 is a cross-sectional view showing a product generated in the process of forming the semiconductor mesa portion. As shown in FIG. 2A, in step S1, a p-type semiconductor layer 12a, a semiconductor layer 14a, a first n-type semiconductor layer 16a, and a first n-type semiconductor layer 16a are sequentially formed on the surface 10a of the p-type InP substrate 10. Two n-type semiconductor layers 18a are formed. In one example, the p-type semiconductor layer 12a, the semiconductor layer 14a, the first n-type semiconductor layer 16a, and the second n-type semiconductor layer 18a are formed by an organic metal vapor phase epitaxy (OMVPE) method. Grown up.

The p-type InP substrate 10 is doped with Zn, for example. In one example, the impurity concentration of the InP substrate 10 is about 1 × 10 ¹⁸ cm ⁻³ , and the thickness of the InP substrate 10 is 350 μm.

The p-type semiconductor layer 12a becomes the p-type buffer layer 12 in the semiconductor mesa portion M. In one example, the p-type semiconductor layer 12a is a p-type InP layer and is doped with Zn. In one example, the p-type semiconductor layer 120 is formed so that its impurity concentration is about 1 × 10 ¹⁸ cm ⁻³ and its thickness is 550 nm.

  The semiconductor layer 14a becomes the active layer 14 in the semiconductor mesa portion M. In one example, the semiconductor layer 14a has, for example, a plurality of well layers and a plurality of barrier layers stacked alternately so as to have a multiple quantum well structure. The well layer constituting this quantum well structure is made of InGaAsP, and has a band gap wavelength of 1.6 μm and a thickness of 5 nm. The barrier layer is made of InGaAsP, and has a band gap wavelength of 1.25 μm and a thickness of 10 nm. At this time, the emission wavelength from the semiconductor layer 14a is 1.55 μm. The thickness of the semiconductor layer 14a is 224 nm.

The first n-type semiconductor layer 16a becomes the n-type cladding layer 16 in the semiconductor mesa portion M. In one example, the first n-type semiconductor layer 16a is an n-type InP layer, and is doped with Si. In one example, the first n-type semiconductor layer 16a is formed so that its impurity concentration is about 1 × 10 ¹⁸ cm ⁻³ and its thickness is 2000 nm.

The second n-type semiconductor layer 18 a becomes the cap layer 18 in the semiconductor mesa portion M. In one example, the second n-type semiconductor layer 18a is an n-type InGaAs layer and is doped with Si. In one example, the second n-type semiconductor layer 18a is formed so that its impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ and its thickness is 200 nm.

Next, as shown in FIG. 2B, in step S1, a mask 20 is formed. The mask 20 is formed on the second n-type semiconductor layer 18a and on the portion that becomes the semiconductor mesa portion M. The mask 20 is formed, for example, by depositing about 2 μm of a SiO ₂ film on the surface of the second n-type semiconductor layer 18a and patterning the film by photolithography.

Subsequently, as shown in FIG. 2C, in step S <b> 1, the semiconductor mesa portion M is formed by etching the portion not covered with the mask 20 from the upper side. For this etching, for example, RIE (Reactive Ion Etching) can be used. In one example, RIE is performed using a mixed gas of CH ₄ and _{H 2,} the flow rate of CH ₄ gas and _{H 2} gas are both 25 sccm. In one example, the etching rate of RIE etching is 1.8 μm / h, and etching with a depth of 3.6 to 3.7 μm is performed. By the process S1 for forming the semiconductor mesa portion M as described above, a product 22 shown in FIG. 2C is generated.

  In the manufacturing method, a surface etching step S2 is then performed. FIG. 3 is a cross-sectional view showing a product generated in the surface etching process. In this surface etching step S2, wet etching is performed in order to remove residual carbon in the semiconductor mesa portion M caused by RIE methane gas. In one example, in step S2, concentrated sulfuric acid is used and etching is performed for 2 minutes.

  Thereafter, in the surface etching step S2, further wet etching is performed in order to remove the crystal damage layer of the semiconductor mesa portion M and to expose the (111) plane of the p-type InP substrate 10. In one example, a mixed solution containing 150 cc of hydrochloric acid, 150 cc of acetic acid, 60 cc of hydrogen peroxide, and 150 cc of water is used as an etching solution, and etching is performed for 30 seconds.

  Through the above surface etching step S2, the product 24 is generated, the surface 10b of the p-type InP substrate 10 is exposed, and the (111) plane is provided. In one example, the amount by which the p-type InP substrate 10 is etched in the thickness direction by the surface etching step S2 is about 100 nm.

Next, in this manufacturing method, step S3 for depositing an n-type semiconductor layer is performed. FIG. 4 is a cross-sectional view showing a product generated by a process of depositing an n-type semiconductor layer. In this step S3, the n-type semiconductor layer 26 is deposited on the surface 10b of the n-type InP substrate 10 and on the side surface of the semiconductor mesa portion M, and a product 28 is generated. In one example, in step S3, an InP layer containing Si as a dopant is deposited at a height of 1.2 to 1.3 μm. The impurity concentration in the InP layer is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

  The n-type semiconductor layer 26 can be grown by, for example, a metal organic chemical vapor deposition (OMPVE) method. In the growth by the OMVPE method, for example, trimethylindium (TMIn) and phosphine (PH3) can be used as raw materials, and monosilane (SiH4) can be used as a dopant raw material. In one example, the growth temperature is 620 ° C., the growth rate is 2 μm / h, and the growth time is 35-40 minutes.

  The n-type semiconductor layer 26 includes a first portion 26 a deposited on the surface 10 b of the p-type InP substrate 10 and a second portion 26 b deposited on the side surface of the semiconductor mesa portion M. The first portion 26a is a portion that becomes a block layer. The thickness of the first portion 26 a, that is, the distance between the surface 10 b of the p-type InP substrate 10 and the surface 26 c of the first portion 26 a is determined by the bottom surface 14 b of the active layer 14 and the surface 10 b of the p-type InP substrate 10. Is preferably smaller than the distance between. For example, the difference between these two distances is preferably 0.2 to 0.3 μm or less. This is because the current leak path is eliminated by eliminating the contact between the n-type semiconductor layer 26 and the n-type cladding layer 16 after the subsequent selective etching. Note that the contact between the semi-insulating buried layer embedded later and the p-type buffer layer 12 is not a problem as long as the contact area is small. This is because the resistance of the p-type semiconductor is smaller than that of the n-type semiconductor.

  More preferably, these two distances are equal, and the bottom surface 14b of the active layer 14 and the surface 26c of the first portion 26a are flush with each other. Here, the thickness of the first portion 26a can be controlled as follows. That is, the difference between the measurement distance between the surface 10b of the p-type InP substrate 10 and the surface (upper surface) of the cap layer 18 and the design distance from the bottom surface 14b of the active layer 14 to the surface (upper surface) of the cap layer 18 is calculated. Ask. According to this difference, the thickness of the first portion 26a can be controlled by adjusting the growth condition by the OMPVE method, that is, the growth time.

  Next, in this manufacturing method, a selective etching step S4 is performed. FIG. 5 is a cross-sectional view showing a product generated by the selective etching process. In this step S4, as shown in FIG. 5, the second portion 26b (see FIG. 4) of the n-type semiconductor layer 26 deposited on the side surface of the semiconductor mesa portion M is selectively etched, thereby producing the product 30. Is generated.

  For example, in step S4, wet etching is performed for 45 seconds using an etching solution containing 60 cc of hydrochloric acid, 300 cc of acetic acid, and 60 cc of water. This etching solution etches the (011) plane and the (111) plane of the Si-doped InP layer that is the n-type semiconductor layer 26, but does not etch the (100) plane. Therefore, the second portion 26b deposited on the side surface of the semiconductor mesa portion M can be selectively removed by the etching solution.

  Next, in this manufacturing method, a buried layer forming step S5 is performed. FIG. 6 is a cross-sectional view showing a product generated by the buried layer forming step. As shown in FIG. 6, in step S <b> 5, semi-insulating buried layers 32 are formed on the n-type semiconductor layer 26 and on both sides of the semiconductor mesa portion M, and a product 34 is generated.

In one example, the buried layer 32 is an InP layer doped with Fe, and the impurity concentration is about 1.5 × 10 ¹⁸ cm ⁻³ . The buried layer 32 is grown by, for example, the OMVPE method. In this OMVPE method, for example, trimethylindium (TMIn) and phosphine (PH3) can be used as raw materials, and ferrocene (C10H10Fe) can be used as a dopant raw material. In one example, the growth temperature for this OMVPE growth is 620 ° C. and the growth rate is 2 μm / h. In order to cover the side portion of the semiconductor mesa portion M, the thickness of the buried layer 32 is 2.5 μm, and the growth time is about 1 hour 15 minutes to 1 hour 20 minutes.

  Next, in this manufacturing method, a mask removal step S6 is performed. FIG. 7 is a cross-sectional view showing a product generated by the mask removing process. As shown in FIG. 7, in step S6, the mask 20 is removed and a product 36 is generated. In one example, the mask 20 is removed using hydrofluoric acid.

Next, in this manufacturing method, the protective film forming step S7 is performed. FIG. 8 is a cross-sectional view showing a product generated by the protective film forming step. As shown in FIG. 8A, in step S <b> 7, first, the surface protective film 38 is formed on the cap layer 18 and the buried layer 32. For example, the surface protective film 38 is a SiO ₂ film.

  In step S7, as shown in FIG. 8B, the protective film 38 above the semiconductor mesa portion M is removed, an opening 38a is formed, the upper surface of the cap layer 18 is exposed, and the product 40 is generated.

  Subsequently, in this manufacturing method, electrode formation process S8 is performed. FIG. 9 is a cross-sectional view showing a product (semiconductor light emitting device) generated by the electrode forming step. As shown in FIG. 9, in step S8, the upper surface electrode 42 and the lower surface electrode 44 are formed. The upper surface electrode 42 is an n-type electrode, and in one example, is an electrode containing AuGe. The upper surface electrode 42 is formed in the opening 38a (see FIG. 8). The lower surface electrode 44 is a p-type electrode, and in one example, is an electrode containing AuZn. The lower surface electrode 44 is formed on the back surface of the p-type InP substrate 10. Thus, the semiconductor light emitting element 46 is produced | generated by forming the upper surface electrode 42 and the lower surface electrode 44. FIG.

  According to the manufacturing method described above, mutual diffusion between the dopant of the p-type InP substrate 10 and the dopant of the buried layer 32 can be prevented, and a semiconductor light emitting device with reduced leakage current can be provided.

  Further, since the n-type block layer 26 (26a) is formed by depositing an n-type semiconductor layer by a growth method such as OMVPE method and selective etching, a block layer having a suitable shape can be formed. That is, it is possible to form a block layer whose thickness is suitably controlled. Furthermore, the contact between the n-type block layer 26 and the n-type cladding layer 16 can be prevented, and current leakage can be prevented. Therefore, the current injection efficiency into the active layer can be improved by preventing the formation of a current leak path.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the materials and dimensions of each layer described above, conditions of each process, and the like are merely examples, and those skilled in the art can appropriately change them.

3 is a flowchart of a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention. It is sectional drawing which shows the product produced | generated in the process of forming a semiconductor mesa part. It is sectional drawing which shows the product produced | generated in a surface etching process. It is sectional drawing which shows the product produced | generated by the process of depositing an n-type semiconductor layer. It is sectional drawing which shows the product produced | generated by a selective etching process. It is sectional drawing which shows the product produced | generated by a buried layer formation process. It is sectional drawing which shows the product produced | generated by a mask removal process. It is sectional drawing which shows the product produced | generated by a protective film formation process. It is sectional drawing which shows the product (semiconductor light emitting element) produced | generated by an electrode formation process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... p-type InP substrate, 10a, 10b ... surface of p-type InP substrate, 12 ... p-type buffer layer, 14 ... active layer, 16 ... n-type cladding layer, 18 ... cap layer, M ... semiconductor mesa part, 18 ... Cap layer, 20 ... mask, 26 ... n-type semiconductor layer (block layer), 32 ... semi-insulating buried layer, 38 ... surface protective film, 42 ... upper surface electrode, 44 ... lower surface electrode.

Claims (3)

forming a semiconductor mesa portion including a p-type buffer layer, an active layer, and an n-type cladding layer on the surface of the p-type InP substrate;
depositing an n-type semiconductor layer on the exposed surface of the p-type InP substrate and the side surface of the semiconductor mesa portion;
Selectively etching the n-type semiconductor layer deposited on the side surface of the semiconductor mesa portion to expose the side surface of the active layer;
After the etching step, forming a semi-insulating buried layer on the n-type semiconductor layer and on the side of the semiconductor mesa portion, and
The n-type semiconductor layer is an n-type InP layer;
In the selective etching step, wet etching is performed using an etching solution containing hydrochloric acid and acetic acid,
The p-type buffer layer is doped with Zn,
The semi-insulating buried layer is an InP layer doped with Fe,
The side surface of the semiconductor mesa portion formed in the step of forming the semiconductor mesa portion has a (011) plane,
In the step of depositing the n-type semiconductor layer, a first distance between the exposed surface of the p-type InP substrate and the surface of the n-type semiconductor layer is set to be equal to the exposed surface of the p-type InP substrate. The thickness of the n-type semiconductor layer is controlled to be smaller than a second distance between the bottom surface of the active layer and a difference between the first distance and the second distance is 0.3 μm or less. Done by
A method for manufacturing a semiconductor light emitting device. The (111) plane of the p-type InP substrate is formed in a region where the surface of the p-type InP substrate and the side surface of the semiconductor mesa portion intersect between the step of forming the semiconductor mesa portion and the step of depositing. The manufacturing method of Claim 1 which further includes the process of performing wet etching so that it may expose. In the step of forming the semiconductor mesa portion, after forming the semiconductor stack including the p-type buffer layer, the active layer, and the n-type cladding layer, a mask is formed on the upper surface of the semiconductor stack, and RIE etching is performed. The semiconductor mesa portion is formed by etching the semiconductor stack.
The manufacturing method of Claim 1 or 2 .

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