JP5201641B2 - 重複オペランドを使用したsimdの内積演算 - Google Patents
重複オペランドを使用したsimdの内積演算 Download PDFInfo
- Publication number
- JP5201641B2 JP5201641B2 JP2010524899A JP2010524899A JP5201641B2 JP 5201641 B2 JP5201641 B2 JP 5201641B2 JP 2010524899 A JP2010524899 A JP 2010524899A JP 2010524899 A JP2010524899 A JP 2010524899A JP 5201641 B2 JP5201641 B2 JP 5201641B2
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- Japan
- Prior art keywords
- source register
- vector
- subset
- vector elements
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30109—Register structure having multiple operands in a single register
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/854,630 US8631224B2 (en) | 2007-09-13 | 2007-09-13 | SIMD dot product operations with overlapped operands |
| US11/854,630 | 2007-09-13 | ||
| PCT/US2008/071327 WO2009035774A1 (en) | 2007-09-13 | 2008-07-28 | Simd dot product operations with overlapped operands |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010539593A JP2010539593A (ja) | 2010-12-16 |
| JP2010539593A5 JP2010539593A5 (enExample) | 2011-09-15 |
| JP5201641B2 true JP5201641B2 (ja) | 2013-06-05 |
Family
ID=40452385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010524899A Expired - Fee Related JP5201641B2 (ja) | 2007-09-13 | 2008-07-28 | 重複オペランドを使用したsimdの内積演算 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8631224B2 (enExample) |
| JP (1) | JP5201641B2 (enExample) |
| KR (1) | KR101482540B1 (enExample) |
| WO (1) | WO2009035774A1 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8595467B2 (en) * | 2009-12-29 | 2013-11-26 | International Business Machines Corporation | Floating point collect and operate |
| US8478969B2 (en) * | 2010-09-24 | 2013-07-02 | Intel Corporation | Performing a multiply-multiply-accumulate instruction |
| JP5528976B2 (ja) * | 2010-09-30 | 2014-06-25 | 株式会社メガチップス | 画像処理装置 |
| WO2013101018A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Dot product processors, methods, systems, and instructions |
| US9355061B2 (en) | 2014-01-28 | 2016-05-31 | Arm Limited | Data processing apparatus and method for performing scan operations |
| GB2523805B (en) * | 2014-03-06 | 2021-09-01 | Advanced Risc Mach Ltd | Data processing apparatus and method for performing vector scan operation |
| GB2553783B (en) | 2016-09-13 | 2020-11-04 | Advanced Risc Mach Ltd | Vector multiply-add instruction |
| US10049082B2 (en) * | 2016-09-15 | 2018-08-14 | Altera Corporation | Dot product based processing elements |
| GB2560159B (en) * | 2017-02-23 | 2019-12-25 | Advanced Risc Mach Ltd | Widening arithmetic in a data processing apparatus |
| GB2563878B (en) * | 2017-06-28 | 2019-11-20 | Advanced Risc Mach Ltd | Register-based matrix multiplication |
| US11334319B2 (en) * | 2017-06-30 | 2022-05-17 | Intel Corporation | Apparatus and method for multiplication and accumulation of complex values |
| US11294679B2 (en) | 2017-06-30 | 2022-04-05 | Intel Corporation | Apparatus and method for multiplication and accumulation of complex values |
| US11409525B2 (en) * | 2018-01-24 | 2022-08-09 | Intel Corporation | Apparatus and method for vector multiply and accumulate of packed words |
| US10642620B2 (en) | 2018-04-05 | 2020-05-05 | Apple Inc. | Computation engine with strided dot product |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0375868A (ja) * | 1989-08-17 | 1991-03-29 | Sony Corp | 行列データ乗算装置 |
| JPH04242861A (ja) * | 1990-12-28 | 1992-08-31 | Sony Corp | 内積演算回路 |
| JPH05267992A (ja) * | 1992-03-18 | 1993-10-15 | Sony Corp | フイルタ回路 |
| US5721892A (en) * | 1995-08-31 | 1998-02-24 | Intel Corporation | Method and apparatus for performing multiply-subtract operations on packed data |
| JP3790307B2 (ja) * | 1996-10-16 | 2006-06-28 | 株式会社ルネサステクノロジ | データプロセッサ及びデータ処理システム |
| US6094637A (en) | 1997-12-02 | 2000-07-25 | Samsung Electronics Co., Ltd. | Fast MPEG audio subband decoding using a multimedia processor |
| US6230253B1 (en) * | 1998-03-31 | 2001-05-08 | Intel Corporation | Executing partial-width packed data instructions |
| US6477203B1 (en) * | 1998-10-30 | 2002-11-05 | Agilent Technologies, Inc. | Signal processing distributed arithmetic architecture |
| JP2000322235A (ja) * | 1999-05-07 | 2000-11-24 | Sony Corp | 情報処理装置 |
| JP3940542B2 (ja) * | 2000-03-13 | 2007-07-04 | 株式会社ルネサステクノロジ | データプロセッサ及びデータ処理システム |
| US6857061B1 (en) * | 2000-04-07 | 2005-02-15 | Nintendo Co., Ltd. | Method and apparatus for obtaining a scalar value directly from a vector register |
| JP3935678B2 (ja) * | 2001-01-31 | 2007-06-27 | 富士通株式会社 | Simd積和演算方法、積和演算回路、および、半導体集積回路装置 |
| US6901422B1 (en) | 2001-03-21 | 2005-05-31 | Apple Computer, Inc. | Matrix multiplication in a vector processing system |
| US6898691B2 (en) | 2001-06-06 | 2005-05-24 | Intrinsity, Inc. | Rearranging data between vector and matrix forms in a SIMD matrix processor |
| US7103756B2 (en) * | 2002-09-30 | 2006-09-05 | Hewlett-Packard Development Company, L.P. | Data processor with individually writable register subword locations |
| US7275147B2 (en) * | 2003-03-31 | 2007-09-25 | Hitachi, Ltd. | Method and apparatus for data alignment and parsing in SIMD computer architecture |
| US6847313B2 (en) | 2003-06-30 | 2005-01-25 | Intel Corporation | Rational sample rate conversion |
| GB2409061B (en) | 2003-12-09 | 2006-09-13 | Advanced Risc Mach Ltd | Table lookup operation within a data processing system |
| US8332452B2 (en) | 2006-10-31 | 2012-12-11 | International Business Machines Corporation | Single precision vector dot product with “word” vector write mask |
-
2007
- 2007-09-13 US US11/854,630 patent/US8631224B2/en not_active Expired - Fee Related
-
2008
- 2008-07-28 JP JP2010524899A patent/JP5201641B2/ja not_active Expired - Fee Related
- 2008-07-28 KR KR20107007865A patent/KR101482540B1/ko not_active Expired - Fee Related
- 2008-07-28 WO PCT/US2008/071327 patent/WO2009035774A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009035774A1 (en) | 2009-03-19 |
| KR20100075494A (ko) | 2010-07-02 |
| KR101482540B1 (ko) | 2015-01-14 |
| US20090077345A1 (en) | 2009-03-19 |
| US8631224B2 (en) | 2014-01-14 |
| JP2010539593A (ja) | 2010-12-16 |
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