JP5186841B2 - Storage element manufacturing method and storage device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a manufacturing method, and a storage device of a storage element for storing information through change in electrical characteristics of the storage layer.

  In an information device such as a computer, a DRAM (Dynamic Random Access Memory) having a high-speed operation and a high density is widely used as a RAM (Random Access Memory). However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI (Large Scale Integration) or signal processing used in an electronic device. The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

  Therefore, for example, flash memories, FeRAM (Ferroelectric Random Access Memory) (ferroelectric memory), MRAM (Magnetoresistive Random Access Memory) (magnetic memory element), etc., are non-volatile memories whose information does not disappear even when the power is turned off. Proposed. In the case of these memories, it is possible to keep the written information for a long time without supplying power.

  However, the various nonvolatile memories described above have advantages and disadvantages. Flash memory has a high degree of integration, but is disadvantageous in terms of operation speed. FeRAM is limited in microfabrication for high integration and has a problem in the manufacturing process. MRAM has a problem of power consumption.

  Therefore, a new type of storage element has been proposed that is particularly advantageous for the limit of microfabrication of the memory element. This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. In this memory element, when a voltage is applied between two electrodes by including a metal contained in the ionic conductor in one of the two electrodes, the metal contained in the electrode is contained in the ionic conductor. By diffusing as ions, electrical characteristics such as resistance value or capacitance of the ion conductor change. For example, Patent Document 1 and Non-Patent Document 1 describe the configuration of a memory device using this characteristic. In particular, Patent Document 1 proposes a configuration in which the ionic conductor is made of a solid solution of chalcogenide and metal. ing. Specifically, it is made of a material in which Ag (silver), Cu (copper), or Zn (zinc) is dissolved in AsS, GeS, GeSe, and either one of the two electrodes has Ag, Cu, or Zn is contained.

  However, in the above-described memory element having a structure in which Ag or the like is included in the upper electrode or the lower electrode and a Ge—S or Ge—Se amorphous chalcogenide material is sandwiched between the electrodes, the chalcogenide thin film is crystallized due to a temperature rise. There was a problem. When crystallization occurs in this way, the characteristics of the material change with the crystallization, and the part that originally retains data in a high resistance state becomes a low resistance state in a high temperature environment or during long-term storage. Problems such as change occur. Therefore, a memory element having a structure in which a rare earth oxide film is inserted between the electrode and the ion conductor as a barrier layer that restricts the movement of ions between the ion conductor and the electrode has been proposed (for example, Patent Document 2).

  Thus, in a memory element having a rare earth oxide film as a barrier layer, when a recording voltage higher than a threshold voltage is applied, these metals are ionized from an electrode layer containing a metal element such as Cu, Ag, Zn, and the like. Then, it diffuses into the rare earth oxide film and precipitates by being combined with electrons on the other electrode side, or stays diffused inside the rare earth oxide film. Then, a current path containing a large amount of these metal elements is formed inside the rare earth oxide film, or a large number of defects due to the metal elements are formed inside the rare earth oxide film, thereby reducing the resistance value of the rare earth oxide film. Become.

In addition, by applying a voltage having a polarity opposite to that described above, the metal element such as Cu constituting the current path or impurity level formed in the rare earth oxide film is ionized again and moves in the rare earth oxide film. Returning to the electrode layer side, the resistance value of the rare earth oxide film is increased. It has been reported that the memory element based on the resistance change of the rare earth oxide film has excellent characteristics particularly in a high temperature environment and long-term data retention stability.
Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104) JP 2005-197634 A

However, in such a memory element, when the area is reduced to 4,000 nm ² or less, it is very difficult to reduce the thickness of the rare earth oxide film according to the scaling measurement.

The present invention has been made in view of the above problems, its object is also miniaturized, without forming a rare earth oxide film, a manufacturing method of the stable writing and erasing operations can be easily realized memory element and An object of the present invention is to provide a method for manufacturing a storage device using the same.

The method for manufacturing a memory element according to the present invention includes at least one of Si (silicon) , Zr (zirconium) , Al (aluminum) , Ti (titanium), and Cr (chromium) on the first electrode together with an ion conductive material. After the memory layer including the metal element and the second electrode are formed in this order to produce the memory element, the initializing pulse in the erasing direction with respect to the first electrode and the second electrode is performed before the first write operation. A voltage is applied to form an oxide layer or nitride layer of the metal element in the vicinity of the interface of the memory layer with the first electrode or the second electrode.

Manufacturing method of a storage device of the present invention has a memory layer, a plurality of storage elements for storing information through change in electrical characteristics of the storage layer, of selectively voltage or current to the plurality of storage elements pulses And at least one metal element of Si, Zr, Al, Ti, and Cr together with an ion conductive material on the first electrode. After the memory element is formed by forming the memory layer and the second electrode in this order, an initializing pulse voltage is applied to the first electrode and the second electrode in the erasing direction before the first write operation to store the memory element. An oxide layer or nitride layer of the metal element is formed in the vicinity of the interface between the first electrode and the second electrode of the layer .

In the production method of the production method or the storage device of the storage device of the present invention, before the first write operation, reset voltage pulse is applied to the erasing direction with respect to the first electrode and the second electrode, the first storage layer 1 At least one oxide layer or nitride layer of the above metal elements (Si, Zr, Al, Ti and Cr) is formed as a high resistance layer in the vicinity of the interface with the electrode or the second electrode.

In the memory element or the memory device manufactured by such a method, it is in the “positive direction” (for example, the first electrode side is a negative potential and the second electrode side is a positive potential) with respect to the element in the initial state (high resistance state). When a voltage or current pulse is applied, a conduction path of a metal element is formed on the first electrode side, and a low resistance state is obtained. When a voltage pulse is applied to the element in the low resistance state in the “negative direction” (for example, the first electrode side is a positive potential and the second electrode side is a negative potential), the metal conduction path is oxidized. It dissolves in the ionized layer and changes to a high resistance state.

According to the method for manufacturing the memory element or the method for manufacturing the memory device of the present invention, the initialization pulse voltage is applied in the erasing direction before the first writing, so that the rare earth oxide film is not formed in the memory layer. The high resistance layer can be easily formed, and miniaturization is facilitated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a memory element according to an embodiment of the present invention. Note that the memory element 1 illustrated in FIG. 1 represents a state after initialization, whereas FIG. 3C illustrates a state before initialization after the element is manufactured. The storage element 1 is formed on a vertical wiring structure, for example. That is, an insulating layer 12 is formed on the wiring layer 11, and a groove 13 reaching the wiring layer 11 is provided in the insulating layer 12. A lower electrode 14 is embedded in the groove 13. An interlayer insulating film 15 having an opening 16 is formed on the insulating layer 12 and the lower electrode 14, and a part of the lower electrode 14 is exposed. A memory layer 17 is formed on the lower electrode 14 and the interlayer insulating film 15, and an upper electrode 18 is formed on the memory layer 17.

  For the lower electrode 14 and the upper electrode 18, for example, W (tungsten), WN (tungsten nitride), Cu (copper), Al (aluminum), Mo (molybdenum), Ta (tantalum), Si (silicon), Zr ( Zirconium) and silicide can be used. In the present embodiment, the lower electrode 14 is composed of, for example, a WZrNb layer, and the upper electrode 18 is composed of a stacked structure (Zr / Al layer) of a Zr layer and an Al layer.

The insulating layer 12 is formed of, for example, TEOS-SiO ₂ , and the interlayer insulating film 15 is formed of, for example, SiO ₂ or SiN. The film thickness of the interlayer insulating film 15 is a thickness that can prevent current leakage from the lower electrode 14 when a driving voltage is applied, for example, 8 nm. The opening 16 provided in the interlayer insulating film 15 narrows the current flowing between the lower electrode 14 and the upper electrode 18 and has an area of, for example, 400 nm ² .

  The memory layer (ionization layer) 17 contains an ionizable metal element together with the ion conductive material. Examples of the ion conductive material include S (sulfur), Se (selenium), and Te (tellurium) (chalcogenide element), and these elements may be used alone or in combination of two or more. Examples of the metal element include Cu (copper), Ag (silver), Ge (germanium), and Zn (zinc). In addition, in the present embodiment, as the metal element constituting the high resistance layer 19, For example, any one of Si, Zr, Al, Ti (titanium) and Cr (chromium) is added. Specifically, the memory layer 17 is a CuGeTeSi layer having a thickness of 30 nm, for example.

  A high resistance layer 19 is provided at the interface between the memory layer 17 and the lower electrode 14 and in the vicinity thereof. The high resistance layer 19 is formed in the direction of erasing information with respect to the upper electrode 18 and the lower electrode 14 before the first write operation after a memory element is manufactured as described later (see FIG. 3C). Preferably, it is formed by applying an initialization pulse voltage having a pulse width of 10 μs or more, and is composed of an oxide layer or a nitride layer of Si, Zr or Al, or a combination thereof. Are different. The high resistance layer 19 may be formed in the vicinity of the upper electrode 18 side. The high resistance layer 19 has a characteristic that the resistance value decreases when a voltage pulse or a current pulse is applied during writing of information.

  In the memory element 1 of the present embodiment, when a predetermined voltage pulse or current pulse is applied from a power source (pulse applying means) (not shown) via the lower electrode 14 and the upper electrode 18, the electrical characteristics of the memory layer 17, For example, the resistance value changes, whereby information is stored, erased, and further read. The storage device of the present invention can be configured by arranging a large number of such storage elements 1, for example, in a matrix.

  Next, a method for manufacturing the memory element 1 will be described with reference to FIGS.

First, as shown in FIG. 2A, an insulating layer 12 made of TEOS-SiO ₂ is formed on the wiring layer 11, and then an opening is formed on the insulating layer 12 as shown in FIG. A resist (photosensitive resin) layer 20 having 20A is formed.

  Next, as shown in FIG. 2C, using the resist layer 20 as a mask, for example, RIE (Reactive Ion Etching) method, IM (Ion Milling) method, wet etching method, etc. Thus, the insulating layer 12 is selectively removed until the wiring layer 11 is exposed, and the groove 13 is formed. Next, the resist layer 20 is removed. Examples of the resist layer 20 include a photoresist for an exposure apparatus using ultraviolet rays and an EB (Electron Beam) resist for electron beam drawing using an electron beam.

  Next, as shown in FIG. 3A, the lower electrode 14 made of WZrNb is formed on the inside of the groove 13 by, for example, depositing by the CVD method and performing a flattening process by, for example, a resist etch back method. Next, as shown in FIG. 3B, an interlayer insulating film 15 made of, for example, SiO 2 is formed by, eg, CVD. Subsequently, the openings 16 are selectively formed by, for example, any one of the above etching methods.

  Subsequently, as shown in FIG. 3C, a storage layer 17, for example, a CuGeTeSi film having a thickness of 30 nm is formed by DC magnetron sputtering. Next, a laminated film (Zr / Al layer) is formed as the upper electrode 18 by, for example, a CVD method. In this state, the high resistance layer 19 is not formed in the memory layer 17.

  Next, initialization of the memory element 1 which is a feature of the present embodiment will be described with reference to FIGS. Here, initialization refers to the formation of the above-described device (FIG. 3C), and then applying a predetermined voltage between the lower electrode 14 and the upper electrode 18 to thereby form the lower electrode 14 or upper portion in the memory layer 17. This refers to the step of forming the high resistance layer 19 in the vicinity of the interface of the electrode 18. The initialization is performed using, for example, the initialization circuit shown in FIG.

  In this initialization circuit, a selection transistor (NMOS transistor) 2 and a switch 3 are arranged in series with respect to the storage element 1. The upper electrode 18 of the memory element 1 is connected to the terminal 8 through the source line 5, and the lower electrode 14 is connected to one end of the selection transistor 2. The other end of the selection transistor 2 is connected to the terminal 9 via the switch 3 and the bit line 6. The gate portion of the selection transistor 2 is connected to the terminal 10 through the word line 4. Each of the terminals is connected to an external pulse voltage source so that a pulse voltage can be applied from the outside. An ammeter 7 is arranged in parallel with the switch 3 so that the current flowing through the circuit can be measured when the switch 3 is in the open state.

  FIG. 5 shows an initialization voltage waveform applied to each of the terminals 8, 9, and 10. When the switch 3 is closed, an initialization voltage is applied to the terminal 9 with a pulse width capable of forming the high resistance layer 19. For example, the initialization voltage pulse width Pinit is 10 ms, and the initialization voltage Vinit is 2.1V. A gate voltage Vginit is applied to the terminal 10 with a gate pulse width Pginit surrounding the initialization voltage pulse width Pinit. At this time, the gate voltage Vginit is a voltage at which the transistor operates normally. For example, the gate pulse width Pginit is 13 ms, and the gate voltage Vginit is 3.0V. Terminal 8 is maintained at 0V.

  In the present embodiment, when an initialization voltage is applied in such an erasing direction, an electric field is generated between the upper electrode 18 and the lower electrode 14. Therefore, conductive ions distributed in the memory layer 17, for example, Cu ions are attracted to the upper electrode 18 side, and a region where the Cu density is lowered is generated on the lower electrode 14 side. On the other hand, for example, oxygen present in either the interface of the lower electrode 14 or the interface of the memory layer 17 in the interlayer insulating film 15 is attracted to the lower electrode 14 side. Therefore, for example, Si and O in the memory layer 17 react in the region where the Cu density is low (opening 16). As a result, a silicon oxide layer (high resistance layer 19) is formed in the opening 16 as shown in FIG.

  Here, as described above, oxygen necessary for forming the high resistance layer 19 (silicon oxide layer) exists in either the interface of the lower electrode 14 or the interface of the memory layer 17 in the interlayer insulating film 15. It only has to be. Further, the interlayer insulating film 15 may be formed of a nitride such as silicon nitride (SiN). When the interlayer insulating film 15 is formed of nitride, a nitride layer (or nitrided oxide layer) is formed as the high resistance layer 19 instead of the silicon oxide layer.

  The memory element 1 that has been initialized is written, erased, and read by applying a pulse voltage having a waveform as shown in FIGS. 6A to 6C, for example. First, for example, a positive potential (+ potential) is applied to the upper electrode 18, and a positive voltage is applied to the memory element 1 so that the lower electrode 14 side becomes negative. As a result, conductive ions such as Cu ions are conducted from the memory layer 17 and are combined with electrons on the lower electrode 14 side and deposited, thereby forming a low resistance Cu current path reduced to a metallic state in the high resistance layer 19. As a result, the resistance value is lowered.

After that, when the positive voltage is removed and the voltage applied to the memory element 1 is eliminated, the resistance value is kept low. Thus, information is written (FIG. 6A). When used in a storage device that can be recorded only once, so-called PROM, it is completed only by the writing process. On the other hand, an erasing process is necessary for application to a erasable storage device, so-called RAM or EEPROM, etc. In the erasing process, for example, a negative potential (−potential) is applied to the upper electrode 18, A negative voltage is applied to the memory element 1 so that the lower electrode 14 side is positive. As a result, Cu in the current path formed in the high resistance layer 19 is oxidized and ionized and dissolved in the memory layer 17 or combined with Te to form a compound such as Cu ₂ Te or CuTe. Then, the current path due to Cu disappears or decreases, and the resistance value increases.

  After that, when the negative voltage is removed and the voltage applied to the memory element 1 is eliminated, the resistance value is kept high. As a result, the information is erased (FIG. 6B). By repeating such a process, information can be written to and erased from the memory element 1 repeatedly.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  To read out the written information, the switch 3 is opened, and the ammeter 7 is turned on by applying a voltage pulse (FIG. 6C) smaller than the threshold voltage at which the resistance value of the memory element 1 changes. This is done by detecting the value of the flowing current.

  Specific examples will be described below.

Example 1
The device of Example 1 having the cross-sectional structure shown in FIG. 3C was manufactured by the above manufacturing method and initialization method. The insulating layer 12 using a TEOS-SiO ₂ layer. WZrNb was used for the lower electrode 14 and its shape was a cylindrical shape with a radius of 150 nm. As the interlayer insulating film 15, a SiO ₂ film having a thickness of 8 nm was used. At this time, the opening of the lower electrode 14 was 400 nm ² . For the memory layer 17, a CuGeTeSi film having a thickness of 30 nm was used. A Zr / Al film was used for the upper electrode 18.

  Subsequently, the device was initialized by the above initialization method. That is, the switch 3 of the above circuit was closed, and a gate voltage of 3.0 V with a pulse width of 13 ms was applied to the terminal 10, a voltage of 0 V was applied to the terminal 8, and an initialization voltage of 2.1 V was applied to the terminal 9. At this time, five kinds of initialization voltage pulse widths Pinit of 100 ns, 1 μs, 10 μs, 100 μs, and 10 ms were applied to the terminal 9, and devices were produced for the respective pulse widths.

  Initialization was performed under the above conditions, and a high resistance layer 19 was formed in the opening 16 between the interlayer insulations 15. Here, a silicon oxide film having a thickness of 3 nm was formed on the device to which the initialization voltage having a pulse width of 10 ms was applied.

(Examples 2, 3, and 4)
As Examples 2 to 4, three types of devices having different compositions of the interlayer insulating film 15 and the memory layer 17 from Example 1 were manufactured. Each composition is as follows.
(Example 1; the storage layer is CuGeTeSi, the interlayer insulating film is SiO ₂ )
Example 2; the storage layer is CuTeZrAl, and the interlayer insulating film is SiO ₂
Example 3; the storage layer is CuTeZrSi, and the interlayer insulating film is SiO ₂
Example 4; the storage layer is CuTeZrAl, and the interlayer insulating film is SiN

  The above-described initialization was performed on each example, and five types of devices having different initialization voltage pulse widths Pinit were produced for each example.

(Characteristic evaluation)
The device was measured for electrical characteristics. For this measurement, the voltage waveform shown in FIG. 6A was applied using the circuit shown in FIG. Specifically, the switch 3 was opened and the following voltages were applied to each terminal. That is, the terminal 9 has a read voltage of 0.1 V with a pulse width of 50 ns, the terminal 10 has a gate voltage (power supply voltage VDD) of 3.0 V with a pulse width of 200 ns, and the terminal 8 has a voltage of 0.1 V, respectively. Applied.

FIG. 7 shows the result. The initialization voltage pulse width Pinit in the case of using the memory layer 17 containing any one of the metal elements (Si, Zr, Al) and the interlayer insulating film 15 made of SiO ₂ or SiN is used. And the element resistance after initialization. The horizontal axis represents the initialization voltage pulse width Pinit (s), and the vertical axis represents the element resistance value (Ω) after initialization.

  According to this, the same change was shown in all the examples. The resistance value of the device to which the pulse width Pinit of 100 ns was applied was about 15 kohm. When the pulse width Pinit was increased to 1 μs, the resistance value was about 22 kohms, and no significant change was observed. However, by increasing the pulse width Pinit to 10 μs, the resistance value becomes about 7 Mohm, indicating a remarkable increasing tendency. Thereafter, by increasing the pulse width Pinit to 100 μs and 1 ms, the resistance values showed a gradual increasing tendency of 20 Mohm and 36 Mohm, respectively.

  From the above results, it was found that in any of the examples, when the initialization voltage was applied, the resistance of the element increased. In particular, by performing initialization with an initialization voltage pulse width Pinit of 10 μs or more, the element resistance becomes a high resistance of 1 Mohm or more, for example, about 15 kohm at a pulse width of 100 ns. In other words, the resistance of the element can be increased by performing initialization without using a rare earth oxide film as in the prior art.

  Here, all the devices of Examples 1 to 3 have different compositions of the memory layer 17, but the device resistances of these devices with respect to the initialization voltage pulse width Pinit show similar changes. That is, even if the composition of the memory layer 17 is different, a similar oxide film is formed. Therefore, if any one of the above metal elements (Si, Zr, Al) is contained in the memory layer 17, the metal element is combined with oxygen to form a similar oxide film (high resistance layer 19). Can do. Although not shown in the embodiments, Ti and Cr other than Si or the like can similarly form a high resistance layer.

  The devices of Example 2 and Example 4 are different in the composition of the interlayer insulating film 15, but the device resistance of these devices with respect to the initialization voltage pulse width Pinit shows the same change. That is, even when the interlayer insulating film 15 is made of SiN as in the fourth embodiment, the high resistance layer 19 is formed. Therefore, the interlayer insulating film 15 is not limited to a silicon oxide film, and may be a silicon nitride film.

(Repeated characteristic evaluation)
Next, the resistance change at the time of writing and erasing during the repetitive operation was measured.

  With respect to the device of Example 1 described above (initialization voltage pulse width Pinit 10 ms), the resistance change (repetitive characteristics) during the write and erase operations during the repetitive operation was measured. In the repetitive operation, the write operation and the erase operation were alternately repeated 10,000 times, and the resistance value was measured for each write and erase operation. In this measurement, the repetitive operation is started from the write operation.

  The repeated measurement was performed using the circuit shown in FIG. 4, and the applied voltage at each operation was as follows.

  At the time of the write operation, the switch 3 is closed as shown in FIG. 6A, the terminal 9 has a write voltage pulse width Pw of 5 ns and a write voltage Vw of 3.0 V, and the terminal 8 has a write voltage Vw of 3.0 V. The gate potential Vgw at the time of writing of 1.3 V was applied to the terminal 10 with a gate pulse width Pgw of 125 ns.

  At the time of the erase operation, the switch 3 is closed as shown in FIG. 6B, the terminal 9 has an erase voltage pulse width Pe of 1 ns and an erase voltage Ve of 1.7 V, the terminal 8 has a potential of 0 V, and the terminal 10 has Is a gate pulse width Pge of 125 ns, and a gate voltage Vge of 3.0 V was applied thereto.

  At the time of reading, the switch 3 is opened as shown in FIG. 6C, the terminal 9 has a pulse width of 50 ns and a reading voltage of 0.1 V, the terminal 8 has a reading voltage of 0.1 V, and the terminal 10 has A power supply voltage VDD of 3.0 V was applied. At this time, the resistance value of the element was measured using the ammeter 7 based on the current flowing through the memory element 1 and the applied voltage (read voltage).

  The result is shown in FIG. The horizontal axis in FIG. 8 represents the number of repeated operations (times), and the vertical axis represents resistance (Ω). The resistance value at the time of writing (at the time of low resistance) is about 10 kohm, but the resistance value at the time of erasing (at the time of high resistance) is about 10 Mohm. That is, there is a read resistance margin of about 3 digits between writing and erasing. Therefore, it can be seen that the resistance change switching characteristic is stable and the memory characteristic is good. Further, the resistance value fluctuates due to the number of repetitive operations in both writing and erasing. That is, it also has highly reliable memory characteristics.

  Subsequently, an initialization process was performed on the device of Example 1 with the initialization voltage pulse width Pinit set to 10 ns, 100 ns, 1 μs, and 10 μs. Thereafter, the above repeated characteristics were measured for each device. In addition, devices that were not initialized were also measured at the same time. Here, the number of repetitions was 1000. At the time of measurement, the write and erase pulse widths were 10 ns and 100 ns, and the measurement was performed for each write and erase pulse width.

  FIGS. 9A, 9B to 13A, 13B show the repetitive characteristics of devices having different initialization voltage pulse widths Pinit. FIG. 9 shows the result when the pulse width Pinit is 10 μs, and similarly shows the result of 1 μs in FIG. 10, 100 ns in FIG. 11, and 10 ns in FIG. In each figure, (A) shows a write and erase pulse width of 10 ns, and (B) shows a 100 ns pulse width.

  When the initialization is not performed, the switching characteristics are not exhibited at all when the write and erase pulse width is 10 ns, and the erase resistance gradually increases but the variation is large at 100 ns. As the initialization pulse width is gradually increased, the erase resistance in the repetitive operation increases. When the initialization voltage pulse width is 10 μs, the write / erase pulse width is 10 ns, the write / erase resistance margin is one digit or more, and the write / erase pulse width is 100 ns, which shows a very stable and good switching characteristic of about three digits. It became so.

  This is because when the memory layer 17 does not have a rare earth oxide film as in the memory element 1 of the present embodiment, an initialization voltage is applied in the erasing direction from a state where writing and erasing are not performed at all. A region where the Cu density is lowered due to movement of Cu ions distributed in the memory layer 17 is generated, or another element is combined with oxygen to form an oxide film in the region where the density is lowered. Therefore, it is considered that the high resistance layer 19 (see FIG. 1) is generated. In the case where the memory layer 17 does not have a rare earth oxide film, in order to exhibit more stable switching characteristics, it is necessary to stably form the high resistance region. For this purpose, the initialization voltage pulse width is 10 μs or more. It is preferable that

  As described above, in this embodiment (example), since the initialization voltage pulse is applied from the outside after the memory element 1 is formed, the region (opening 16) in contact with the lower electrode 14 of the memory layer 17. ), A high resistance layer 19 is formed, and the resistance at the time of erasing (high resistance) can be increased. As a result, stable resistance change switching characteristics can be exhibited, and good memory characteristics can be obtained. Further, since it is formed in accordance with the opening 16, the high resistance layer 19 and the memory element 1 can be easily miniaturized.

  In addition, when the initialization voltage pulse width Pinit is set to 10 μs or more, it is possible to obtain better memory characteristics by having a read resistance margin of about three digits.

Further, since the high resistance layer 19 is formed by replacing a part of the memory layer 17 (contact region with the lower electrode 14), a thin film is formed with respect to a minute region (for example, the opening 16 of 400 nm ² ). Even when (for example, a film thickness of 3 nm) is formed, a thin film can be formed with high accuracy without using a special thin film technique.

It is sectional drawing of the memory element which concerns on one embodiment of this invention. It is sectional drawing showing the manufacturing method of the said element for every process. FIG. 3 is a diagram illustrating a process following FIG. 2. It is a block diagram of a circuit for performing initialization and measurement of electrical characteristics. It is a wave form diagram showing the terminal voltage application method at the time of initialization. It is a wave form diagram showing the terminal voltage application method at the time of characteristic evaluation. It is a characteristic view showing the measurement result of resistance value measurement for each example. 6 is a characteristic diagram showing measurement results of repetition characteristics of Example 1. FIG. It is a characteristic view showing the measurement result of the repetition characteristic when the initialization voltage pulse width is 10 μs. It is a characteristic view showing the measurement result of the repetition characteristic when the initialization voltage pulse width is 1 μs. It is a characteristic view showing the measurement result of the repetition characteristic when the initialization voltage pulse width is 100 ns. It is a characteristic view showing the measurement result of the repetition characteristic when the initialization voltage pulse width is 10 ns. It is a characteristic view showing the measurement result of the repetition characteristic when there is no initialization.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Wiring layer, 12 ... Insulating layer, 13 ... Groove, 14 ... Lower electrode, 15 ... Interlayer insulating film, 16 ... Opening part, 17 ... Memory layer, 18 ... Upper electrode, 19 ... High resistance layer.

Claims (6)

A method of manufacturing a storage element having a storage layer, wherein information is written or erased by a change in electrical characteristics of the storage layer,
A storage layer including, on the first electrode, at least one metal element of Si (silicon), Zr (zirconium), Al (aluminum), Ti (titanium), and Cr (chromium) together with an ion conductive material, and After forming the second electrode in this order and manufacturing the memory element,
Before the first write operation, an initialization pulse voltage is applied to the first electrode and the second electrode in the erasing direction, and the metal element is disposed in the vicinity of the interface of the memory layer with the first electrode or the second electrode. form of oxide layer or nitride layer
Manufacturing method of the serial憶素Ko. The memory layer does not include a rare earth oxide layer
A method for manufacturing a memory element according to claim 1. The memory layer contains at least one of Cu (copper), Ag (silver), Ge (germanium), and Zn (zinc).
A method for manufacturing a memory element according to claim 1. The ion conductive material of the memory layer is at least one of S (sulfur), Se (selenium), and Te (tellurium).
A method for manufacturing a memory element according to claim 1. It shall be the least 10μs pulse width of the reset voltage pulse
Method for manufacturing a memory element according to 請 Motomeko 1. A plurality of storage elements having a storage layer and storing information according to a change in electrical characteristics of the storage layer; and pulse applying means for selectively applying voltage or current pulses to the plurality of storage elements. A storage device manufacturing method comprising:
A storage layer including, on the first electrode, at least one metal element of Si (silicon), Zr (zirconium), Al (aluminum), Ti (titanium), and Cr (chromium) together with an ion conductive material, and After forming the second electrode in this order and manufacturing the memory element,
Before the first write operation, an initialization pulse voltage is applied to the first electrode and the second electrode in the erasing direction, and the metal element is disposed in the vicinity of the interface of the memory layer with the first electrode or the second electrode. Form an oxide or nitride layer
A method for manufacturing a storage device.

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