JP5180261B2 - Game machine - Google Patents

Description

  The present invention relates to an electronic game machine incorporating a computer device, and is particularly suitably applied to a ball game machine and a spinning game machine.

  In a spinning machine such as a slot machine, when a player inserts a medal into a medal slot and operates a start lever, the rotation of the rotating reel is started accordingly. When the player presses the stop button to stop the rotating reel, when the symbols are aligned on the effective stop line, a payout medal corresponding to the symbol is paid out. Of the winning symbols, the Big Bonus (BB) symbol is particularly valuable. When the BB symbol is won internally and the player aligns the BB symbol on the active line, a big bonus game is started. After that, the winning probability of the small role symbol is maintained at a very high level. The number of dividend medals can be expected.

  However, in actuality, whether or not a big hit state is determined in advance by an internal lottery process executed at the time of operating the start lever, and the player can align the symbols won by the lottery process on the active line. Dividend medals are paid out.

  In the internal lottery process, the output value of the random number generation circuit is used as a random number value RND for jackpot determination, and it is determined whether or not it is a big hit state by comparing this with the jackpot lottery value Hit. Here, the random number generation circuit generally includes a counter that is updated at a high speed and a latch that holds a count value of the counter based on a start lever signal or the like.

JP 2008-1113914 A

  However, in the case of the random number generation circuit configured as described above, the timing at which the count value of the counter coincides with the value of the big hit lottery value Hit occurs repeatedly regardless of how fast the update speed of the counter is increased. It will be. For this reason, there are concerns about illegal acts such as operating a start lever aiming at a big hit timing using an illegal instrument called a sensory device.

  Here, there are various proposals for suppressing fraud. For example, in the configuration of the prior art document 1, complicated software processing is essential, and the control burden on the CPU increases.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine that can eliminate illegal activities without increasing the control burden on the CPU.

In order to achieve the above object, the present invention executes a lottery process for comparing a random value generated by a random number generation circuit at a predetermined timing during a game with a predetermined lottery value, thereby providing a gaming state advantageous to the player. a gaming machine having a CPU for determining whether or not to generate the random number generating circuit, an oscillator for outputting a count clock in succession, with receiving a count clock from the oscillating unit, the continuation of Protection level time is configured to have a gate circuit receiving the operation control signal CPU-generated to vary randomly each time, while the counting operation Ru is stopped by supplying the count clock is interrupted during prohibition level of the operation control signal, operation the authorization level when the control signal, and a counter for repeating a counting operation by being supplied with counting clock, the output data of the counter unit at the predetermined timing turbulent Receiving a latch portion for holding a value, and an output unit for outputting the random number the latch portion is held in accordance with an instruction from the CPU to the CPU, the operation control signal CPU-generated transition from disable level to allow Level A delay circuit that increases the duration of the prohibition time generated by the CPU by sometimes adopting a circuit configuration in which the capacitor is charged via a resistor is configured .

  According to the present invention described above, illegal activities can be eliminated without increasing the control burden on the CPU.

It is a front view of the slot machine which concerns on an Example. FIG. 2 is a right side view (a) and a plan view (b) of the slot machine of FIG. 1. It is the figure which illustrated the front panel of the slot machine from the back. It is an internal front view of the main body case of the slot machine. FIG. 2 is a block diagram showing a circuit configuration of the slot machine of FIG. 1. It is a block diagram which shows the circuit structure of a main control board. It is a circuit diagram which shows a random number generation circuit. It is a circuit diagram which shows another random number generation circuit. It is a time chart explaining operation | movement of a random number generation circuit. It is a circuit diagram which shows the internal circuit of IC used for a random number generation circuit. It is a flowchart explaining the main process in a main control part, and a timer interruption process. It is a circuit diagram which shows the flowchart explaining a part of main process, and an additional circuit. It is a flowchart explaining another Example.

  Hereinafter, the present invention will be described in more detail based on examples. 1 to 4 illustrate a slot machine SL according to an embodiment. In this slot machine SL, a rectangular box-shaped main body case 1 and a front panel 2 fitted with various game members are connected via a hinge 3 so that the front panel 2 can be opened and closed with respect to the main body case 1. (FIG. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. A front view is shown.

  As shown in FIG. 4, a symbol rotating unit 4 including three rotating reels 4 a to 4 c is disposed in the approximate center of the main body case 1, and a medal payout device 5 is disposed below the symbol rotating unit 4. On each of the rotating reels 4a to 4c, a BB symbol, an RB symbol, various fruit symbols, a replay symbol, and the like are drawn. The medal payout device 5 is provided with a medal hopper 5a for storing medals, a payout motor MO, a medal payout control board 55, a payout relay board 63, a payout sensor (not shown), and the like. Here, the medal is derived from the payout opening 5b toward the front of the drawing based on the rotation of the payout motor MO. Note that medals stored exceeding the limit amount are configured to fall into the auxiliary tank 6 through the overflow portion 5c.

  A power supply board 62 is arranged adjacent to the medal payout device 5, a main control board 50 is arranged above the symbol rotation unit 4, and a rotating drum setting board 54 is arranged adjacent to the main control board 50. ing. In addition, inside the symbol rotating unit 4, a rotating LED relay substrate 58 and a rotating relay substrate 57 are provided, and an external concentrated terminal plate 56 is disposed adjacent to the symbol rotating unit 4.

  As shown in FIG. 1, a liquid crystal display unit 7 is disposed on the upper portion of the front panel 2, and three display windows 8a to 8c corresponding to the rotating reels 4a to 4c are disposed on the lower portion thereof. Through the display windows 8a to 8c, about 3 symbols can be seen in the rotational direction of each of the rotating reels 4a to 4c, and a total of 9 symbols in the horizontal direction and 2 in the diagonal direction. Becomes a virtual stop line.

  On the left side of the display window 8a, an LED group 9 indicating a gaming state is provided. Below that, a payout display unit 10 for displaying the number of medals to be paid out as a gaming result, and the number of medals in a credit state are displayed. The storage number display part 11 to display is provided.

  In the center of the front panel 2 in the vertical direction, a medal insertion slot 12 for inserting medals is provided, and adjacent thereto, a return button 13 for returning medals filled in the medal insertion slot 12 is provided. Also, a credit check button 14 for paying out a credit medal, an insertion button 15 for artificially inserting one credit medal in place of inserting a medal into the medal slot 12, and a credit medal in a pseudo manner A maximum loading button 16 for loading three sheets is provided.

  Below these game members, a start lever 17 for starting the rotation of the rotating reels 4a to 4c and stop buttons 18a to 18c for stopping the rotating reels 4a to 4c are provided. In addition, below the front panel 2, a horizontally long tray 19 for storing medals and a medal outlet 20 communicating with the payout port 5b of the payout device 5 are provided. Speakers SP are arranged on the left and right sides of the medal outlet 20.

  As shown in FIG. 3, on the back side of the front panel 3, a medal sorting device 21 that sorts medals inserted into the medal slot 12, and medals that are determined to be inappropriate by the medal sorting device 21 A return passage 22 that guides the vehicle 20 is provided. A substrate case 23 that houses the effect control board 51, the effect interface board 52, the liquid crystal control board 61, and the like is disposed on the upper back side of the front panel 3. A game relay board 53 that relays signals between the various game members shown in FIG. 1 and the main control board 50 is provided on the medal sorting device 21.

  FIG. 5 is a block diagram illustrating a circuit configuration of the slot machine SL according to the embodiment. As shown in the figure, this slot machine SL realizes an effect operation based on a main control board 50 that controls the operation of various game members including the rotating reels 4a to 4c and a control command received from the main control board 50. The control board 51 and a power supply board 62 that converts an alternating voltage (24V) into a direct voltage (5V, 12V, 24V) and supplies them to each part of the apparatus are mainly configured.

  The main control board 50 outputs, to the effect control board 51, control commands for realizing the sound effect by the speaker SP, the lamp effect by the LED lamp or the cold cathode ray tube discharge tube, and the symbol effect by the liquid crystal display unit 7. doing. The effect control board 51 is connected to the liquid crystal control board 61 through the effect interface board 52, and the liquid crystal control board 61 realizes a design effect in the liquid crystal display (LCD) unit 7.

  The effect control board 51 realizes lamp effects in various LEDs and cold cathode ray tube discharge tubes via the LED board 59, the inverter board 60, and the rotary LED drive board 58 together with the effect interface board 52. In addition, the effect control board 51 drives the speaker SP through the effect interface board 52 to realize an audio effect.

  The main control board 50 is connected to various game members of the slot machine through the game relay board 53. Specifically, the start switch of the start lever 17, the stop switch of the stop buttons 18a to 18c, the input switch of the input buttons 15 and 16, the liquidation switch of the checkout button 14, and the photointerrupters PH1 and PH2 constituting the input number determination unit 21d The blocker solenoid 31 constituting the inserted medal return unit 21c and the various LED elements 9 to 11 are connected.

  Various output signals including a start switch signal LV from the start lever 17 and stop switch signals STP1 to STP3 from the stop buttons 18a to 18c are input to the main control board 50 via the game relay board 53. Is done. Various control signals output from the main control board 50 are supplied to the corresponding game members via the game relay board 53.

  Further, the main control board 50 is connected to the three stepping motors for rotating the rotating reels 4a to 4c and the index sensor for detecting the reference position of the rotating reels 4a to 4c via the rotating relay board 57. Has been. Then, by rotating or stopping the stepping motor, the rotating operation of the rotating reels 4a to 4c and the stopping operation at the target position are realized.

  The main control board 50 is also connected to the medal payout device 5 through the payout relay board 63. The medal payout device 5 is provided with a medal payout control board 55, a medal payout sensor, and a payout motor MO. The medal payout control board 55 is based on a control command from the main control board 50. Is rotated to pay out a predetermined amount of medals. The main control board 50 is configured to grasp the number of medals paid out based on the output of the medal payout sensor SE.

  In addition, the main control board 50 is also connected to the external concentration terminal board 56 and the rotary setting board 54. The external concentrated terminal board 56 is connected to, for example, the hall computer HC, and the main control board 50 outputs the number of inserted medals and the number of paid out medals through the external concentrated terminal board 56. Further, the rotating drum setting board 54 outputs a setting key signal indicating a setting value set by the staff using the setting key.

  Here, the set value defines the winning probability of the lottery process executed on the gaming machine in six stages from setting 1 to setting 6, and is appropriately set based on the sales strategy of the gaming hall. . For example, a gaming machine set to the highest rank is most advantageous to the player because the expected value of the number of medals to be paid out is the highest level.

  FIG. 6 illustrates the circuit configuration of the main control board 50. As illustrated, the main control board 50 includes a one-chip microcomputer 64, an I / O port circuit 65 for inputting / outputting 8-bit parallel data, a random number generation circuit 66 for generating a random number value RND by a hardware configuration, and an effect control board. An interface circuit with an external substrate such as 51 and an oscillation circuit OSC that outputs a counting clock Φ of about 8 MHz are mainly configured.

  Here, the one-chip microcomputer 64 incorporates a CTC (Counter / Timer Circuit) 64b, an interrupt controller 64c, an input port 64d, an output port 64e, etc., in addition to the Z80 equivalent CPU core 64a, ROM, RAM, and the like. ing.

  The CTC 64b is a circuit in which an 8-bit counter and a timer are integrated, and adds a periodic interrupt, a pulse output creation function (bit rate generator) and a time measurement function to the Z80 system. Therefore, in this embodiment, a timer interrupt (FIG. 11B) is applied to the Z80 CPU 64a at a time interval τ of about 1.5 mS using the CTC 64b.

  As an interface circuit, an interface circuit 67 with a power supply circuit, an interface circuit 68 with a game relay board 53, a rotary motor driving circuit 69, an effect control board and an interface circuit 70 with 51 are provided. Yes. When the power is shut off, a voltage drop interrupt is applied to the Z80 CPU 64a through the interface circuit 67. Note that the rotating motor driving circuit 69 is a circuit that generates a driving signal for the stepping motors of the rotating reels 4 a to 4 c, and the interface circuit 70 is an 8-bit parallel port for outputting a control command to the effect control board 51. It is.

  As shown in the figure, the interface circuit 68 is supplied with output signals such as a start switch signal LV and stop switch signals STP1 to STP3. The start switch signal LV is supplied to the random number generation circuit 66 via the I / O port circuit 65, and other signals are input to the input port of the one-chip microcomputer via the I / O port circuit 65. 64d.

  The random number generation circuit 66 is a circuit that counts the count clock Φ supplied from the oscillation circuit OSC and outputs a random number value RND to the input port 64 d of the one-chip microcomputer 64. However, the random number generation circuit 66 according to the present embodiment receives the operation inhibition pulse CTL from the output port 64e of the one-chip microcomputer 64 in addition to the start switch signal LV, and realizes an intermittent counting operation.

  That is, unlike the normal random number generation circuit, the continuous counting operation is not repeated based on the counting clock Φ, but the counting operation of the random number generation circuit 66 is stopped in the interval where the operation prohibiting pulse CTL is at the prohibiting level. ing. Therefore, the big hit timing at which the count value (random number value RND) of the counter matches the value of the big win lottery value Hit occurs irregularly, and even if a sensory device or the like is used, the illegal game cannot be made successful.

  The operation prohibiting pulse CTL is output from the output port 64e to the random number generation circuit 66 at the end of one game operation completed by, for example, medal payout (see ST18 in FIG. 11 (a)). The random number generation circuit 66 supplies the start switch signal LV ″ having a waveform shape to the input port 64 d of the one-chip microcomputer 64.

  FIG. 7 is a circuit diagram illustrating in detail the random number generation circuit 66 that exhibits the above function. The illustrated random number generation circuit 66 includes an input unit Fi having a low-pass filter function, a signal acquisition unit 25 that acquires a start switch signal LV logically inverted at the input unit Fi, and two 8-bit counters 26L and 26H in cascade connection. And a counting unit 26 that generates a random number value RND.

  The output values LOW and HI of the lower counter 26L and the upper counter 26H in the counting unit 26 are 16-bit random numbers RND as a whole. As shown in the figure, each counter 26L, 26H is connected to an input port 64d of the one-chip microcomputer 64, and a 16-bit random number value RND is acquired every 8 bits. The input port 64d is also supplied with a waveform-shaped start switch signal LV ″, and the one-chip microcomputer 64 grasps the ON operation of the start lever 17 based on the start switch signal LV ″, and each time The game operation is started.

<Input unit Fi>
The input unit Fi is provided with a low-pass filter composed of a resistor R and a capacitor C. Therefore, noise superimposed on the signal line from the start lever 17 is eliminated, and only the original start switch signal LV bar is logically inverted by the Schmitt trigger type NOT gate G and output.

<Signal acquisition unit 25>
The signal acquisition unit 25 is configured by two D-type flip-flops 25a and 25b connected in series, and a count clock Φ output from the oscillation circuit OSC is supplied to each clock terminal CLK. Although the D flip-flop is not particularly limited, in this embodiment, SN74HC74 (TI) is used, and the data of the D input terminal is transferred to the Q output terminal at the rising edge of the count clock Φ (8 MHz in the embodiment). Is output. Accordingly, as shown in FIGS. 9A to 9D, the start switch signal LV corresponding to the player's start lever operation is adjusted in pulse width in the flip-flop 25a in synchronization with the count clock Φ. Above (LV ′), it is further delayed by one clock (1/8 μS) of the count clock (LV ″) and output from the flip-flop 25b.

  Therefore, even if the input terminal of the flip-flop 25a is turned on for a moment due to noise that has passed through the input unit Fi, the signal acquisition unit 25 does not malfunction. The signal acquisition unit 25 reacts when receiving noise having a pulse width of 2/8 μS or more. However, in the one-chip microcomputer 64 that receives the start switch signal LV ″, the start switch signal LV is spaced at a predetermined time interval (for example, 1 μS). Since the level of "" is checked a plurality of times and the start switch signal LV "is maintained at the same level, the process proceeds to the subsequent processing, so that no problem occurs.

<Counter 26>
The counting unit 26 of the present embodiment is composed of two SN74HC590A (8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS: TI) 26L and 26H. As shown the equivalent circuit in FIG. 10, each 8-bit counter, and 2 ^octal counter CT, and 8-bit latch La, and the 8-bit output register Ro is incorporated. Then, the rising edge of the count clock supplied to a clock terminal CCLK, the counter value of 2 ^octal counter CT is updated.

In this embodiment, the clock terminal CCLK of the lower counter 26L, counting the clock Φ is counting clocks Φ bar is phase-inverted is supplied to the internal 2 ^octal counter CT of the carry signals (ripple carry) RCO is higher counter 26H is supplied to the clock terminal CCLK. Therefore, the counting section 26 of the present embodiment, as a ^whole, functions as a ^{two hexadecimal} counter, circulating in the numerical range of 0000h to FFFFh (H indicates a hexadecimal number).

The counter value of 2 ^octal counter CT at the rising edge of the latch signal of the latch clock terminal RCLK, is held in the 8-bit latch La, the output value of the 8-bit latch La, the control signal of the control terminal OE is at L level Is output from the output register Ro. When the control signal of the control terminal OE is at the H level, the output terminal of the output register Ro is in a high impedance state (HiZ).

In the present embodiment, the output (LV ″) of the flip-flop 25b is supplied to each latch clock terminal RCLK of the lower counter 26L and the upper counter 26H. Therefore, at the rising edge of the start switch signal LV ″, two two the counter value of the ^octal counter CT is respectively held in the two 8-bit latches La. FIG. 9D and FIG. 9G illustrate the relationship. The counter value (16-bit length) M incremented from M−1 is the value of the output LV ″ of the D-type flip-flop 25b. It indicates that the data is acquired by the 8-bit latch La of the lower counter 26L and the upper counter 26H at the rising edge.

In the present invention, a start switch signal LV to the ON state at a random timing, in synchronization while shaping the waveform to count clocks [Phi, in synchronization with the count clock [Phi the count clock [Phi bar is phase-inverted 2 ^hex The counter is updated. Therefore, the counter value of each 2 ^octal counter CT is the timing latched by the 8-bit latch La, counter update operation has been completed reliably, for example, of being updated to M-1 → M not There is no possibility that a stable counter value is latched. If the counter is updated in synchronization with the count clock Φ, an unreasonable counter value during the update may be latched.

Incidentally, each of the counters 26L and 26H constituting the counting unit 26 is provided with an operation prohibiting terminal CCKEN. Then, the voltage of the operation prohibition terminal CCKEN is the is H level, the counting operation is prohibited, regardless of the voltage change of the clock terminal CCLK, the counter value of 2 ^hexadecimal counter CT is not changed. FIG. 9 (f) and FIG. 9 (g) show this relationship. In the section where the voltage of the operation inhibition terminal CCKEN is at the H level, the counter value remains N + 1 regardless of the supply of the count clock Φbar. Indicates no change.

  As shown in the circuit diagram of FIG. 7, the operation prohibiting pulse CTL is output from the output port 64e of the one-chip microcomputer 64, and this is logically inverted by the NOT gate G6 and supplied to the operation prohibiting terminal CCKEN. As described above, in this embodiment, the operation prohibiting pulse CTL at the prohibiting level is repeatedly output at the timing of step ST18 in FIG. 11A, so that the counting operation of the count 26 is predetermined at the end of each game. By prohibiting only the time, the intermittent counting operation of the random number generation circuit 66 is realized.

  In order to realize the intermittent counting operation, it is not always necessary to adopt the circuit configuration of FIG. 7, and it is preferable to adopt the circuit configuration of FIG. In the circuit configuration of FIG. 8, an operation prohibiting pulse CTL having a prohibition level is supplied to one input terminal of the NAND gate G1, and at the end of each game, the counting operation is prohibited and an intermittent counting operation is realized. The

  By the way, in the operation prohibition period of the counting operation, the count value of the counting unit 26 maintains a constant value. Therefore, if the operation prohibition period is too long, the uniformity of random number generation may be hindered. Therefore, the operation inhibition section T (pulse width of the operation inhibition pulse CTL) is preferably short to some extent, and should be set to 50 mS or less, more preferably 1 mS or less.

  In addition, even when the operation prohibiting pulse CTL is output, if the timer interrupt processing with the interrupt period τ is started, the actual operation prohibiting section T ′ is compared with the design value T of the pulse width of the operation prohibiting pulse CTL. Thus, T ′ = T + n * t, and the interrupt count n takes an indefinite value of 0, 1, 2,... (Changes ± 1) in relation to the design value T of the pulse width and the interrupt cycle τ. . Moreover, since the execution processing time t of the interrupt processing program is slightly different every time for each interrupt processing (however, t <τ), the actual operation prohibited section T ′ is further randomized in this sense.

  Next, the control operation realized by the one-chip microcomputer 64 (hereinafter referred to as the main control unit 50) of the main control board 50 will be described. FIG. 11 is a flowchart for explaining a control program executed by the main control unit 50. The control program of the main control unit 50 includes an infinite loop main process (FIG. 11 (a)) that is started when the power is turned on, and a timer interrupt process (FIG. 11 (b)) that is started by a scheduled interrupt from the CTC. It is comprised.

  First, the main process of FIG. 11A will be described. When the power is turned on, after the initial process (ST1), the CPU is set in an interrupt enabled state and the work area of the RAM is cleared (ST2).

  When the process of step ST2 is completed, the medal insertion process for the medal actually inserted from the medal insertion slot 12 and the medal actually inserted by pressing the insertion buttons 15 and 16 is performed (ST3). . In the medal insertion process (ST3), a medal inserted or pseudo inserted by the player is detected, the number of inserted medals is determined, and when the start lever 17 is turned on, the subroutine process is terminated. As described with reference to FIG. 7, when the start lever 17 is turned on, the start switch signal LV changes to H level, and the count value at that moment is output in the counters 26L and 26H of the counter unit 26. It is held and stored in a register (see FIGS. 7 and 10).

  Subsequent to such a medal insertion process (ST3), a random number acquisition process (ST4) is executed. Specifically, the one-chip microcomputer 64 changes the chip select signals CS0 and CS1 to the L level and acquires the counter value held in the counting unit 26 of the random number generation circuit 66 via the input port 64d. This is stored as a random number value RND (numerical range: 0 to 65535) at a corresponding address in the RAM.

  Next, an internal lottery process is executed based on the stored random number value RND (ST5). Specifically, the random number value RND and the big hit lottery value Hit are compared to determine whether or not the big hit state (BB symbol win). In addition, not only whether or not the big bonus (BB) symbol is won, it is determined whether or not the other regular bonus (RG) symbol, fruit symbol, and replay symbol are successful.

  When the internal lottery process (ST5) with the random number value RND is completed in this way, next, preparation work for rotating the rotating reels 4a to 4c is performed, and the rotation control of the rotating reels 4a to 4c by timer interruption is possible. After that, when the stop buttons 18a to 18c are pushed, a rotating cylinder stop process for stopping the corresponding rotating reels 4a to 4c is performed (ST8).

  In this spinning cylinder stop process, stop control is executed so as to follow the result of the internal lottery process (ST5). That is, as a result of the internal lottery process (ST5), if there is any internal winning state, the symbols of the rotating reels 4a to 4c are aligned so as to match the winning result on condition that the player performs an appropriate stop operation. However, if the timing at which the player presses the stop button or the order of the stop operation is inappropriate, the player is stopped in a lost state pattern. As a result, the small winning combination (per fruit symbol) is wasted, but the bonus winning (BB, RB) is carried over after the next game.

  When all the rotating reels 4a to 4c are stopped in this way, it is determined whether or not the winning symbols are aligned on the effective line (ST9), and the required number of medals are paid out (ST10).

  Then, a necessary process is executed by managing the game digest number of RT (replay time) (ST11). Next, it is determined whether or not the player is in the replay winning state (ST12). If the player is in the replay winning state, a re-game operation start process (ST15) is executed. If it is not in the replay winning state, it is determined whether or not the bonus game is currently in progress (RB operation or RB operation is in progress). If the bonus game is in progress, the corresponding processing is executed.

  On the other hand, if the determination in step ST13 is NO, it is determined whether or not the bonus symbol is aligned (ST14). If the bonus symbol is aligned, a bonus game start process (ST17) is executed.

  In either case, after outputting the operation prohibiting pulse CTL in the interrupt enabled state, the process proceeds to step ST2 (ST18). FIG. 12A is a flowchart specifically showing this output process. First, an appropriate fixed value is set to the variable CT for determining the pulse width (ST31), and an operation prohibiting pulse of the prohibiting level (L level) is output (ST32).

  Thereafter, the variable CT is decremented to zero until the operation prohibition section of the counting unit 66 is secured (ST33 to ST34), and then the operation prohibition pulse of the permission level (H level) is output and the processing ends. (ST35).

  In order to slightly randomize the operation prohibition section of the counting unit 66 for each gaming machine, a time constant circuit shown in FIG. The illustrated time constant circuit is composed of a delay unit 32 and a randomizing unit 33.

  The delay unit 32 includes a NOT gate G3 that receives the operation inhibition pulse OP, an N-channel MOS transistor T1, a resistor R1, a capacitor C1, a NOT gate G4, and a NAND gate G5. The delay unit 32 as a whole constitutes a delay circuit for the operation inhibition pulse OP, and the delay time is defined by the time constants of the resistor R1 and the capacitor C1. Then, the delayed operation prohibiting pulse OP and the non-delayed operation prohibiting pulse OP are supplied to the NAND gate G5, thereby generating a negative logic pulse having a predetermined width. As shown in FIG. 12 (c-2), the output of the NAND gate G5 becomes L level for a predetermined time from the rising edge at which the operation prohibiting pulse OP returns to the steady level, and at other timings, the output is constantly at the H level. To maintain.

  On the other hand, the randomizing unit 33 that receives the output of the NAND gate G5 includes a resistor R and a capacitor C. The randomizing unit 33 is a simple charging circuit in which the capacitor C is charged by the power supply voltage Vcc. However, the charging time constant (R * C) is increased by using low-precision products as the resistor R and the capacitor C. It is configured to vary from one gaming machine to another.

  Then, when the output of the NAND gate G5 maintains the L level, the charge of the capacitor C is discharged. After that, when the output of the NAND gate G5 returns to the H level, the path of the power supply voltage Vcc → resistance R → capacitor C. The capacitor C is charged and becomes H level after a predetermined time. Therefore, during the charging time until the discharged capacitor C is recharged, the operation prohibiting pulse CTL bar becomes H level, and the counting operation of the counting unit 26 is prohibited (see FIG. 12 (c-2)). .

  As described above, the resistance value of the resistor R and the capacitance of the capacitor C are configured so that each value varies from element to element. Therefore, the operation prohibited section also varies from game machine to game machine. It can be surely prevented. In addition, by using the time constant circuit, the pulse width of the operation prohibiting pulse OP can be set to the minimum value that can be processed by software (see the broken line portion), so there is an advantage that other game controls are not hindered.

  When the operation prohibiting terminal CCKEN of the counting unit 26 is used as in the circuit configuration of FIG. 7, the operation prohibiting pulse CTL bar is supplied via the NOT gate G6, but as in the circuit configuration of FIG. When the NAND gate G1 is used, the operation prohibiting pulse CTL is supplied as it is (see FIG. 12 (c-3)).

  In addition, it is not always necessary to separately provide the delay unit 32 and the randomizing unit 32. For simplicity, as shown in FIG. 12 (c-4), the resistor R1 and the capacitor C1 of the delay unit 32 are random. It is sufficient because the conversion unit 33 is configured.

  By the way, in order to more reliably randomize the pulse width of the operation prohibiting pulse CTL, it is preferable to employ the program processing of FIG. In this embodiment, as a random value, for example, the random value RND acquired in step ST4 is used (ST30), and an appropriate mask value is AND-operated to limit a numerical range and determine a pulse width. CT is determined randomly (ST31).

  Next, the operation prohibiting pulse CTL at the prohibiting level is output (ST32), and the decrement processing is repeated until the variable CT becomes zero (ST33, ST34). When the decremented variable CT becomes zero, an operation prohibiting pulse CTL at a permission level is output and the process is terminated (ST35). In this embodiment, during the processing time of steps ST33 to ST34, the passage of the counting pulse Φ is blocked by the NAND gate G1, or the operation inhibiting terminal CCKEN is at the H level and the counting unit 26 is in the operation inhibiting state. Therefore, the occurrence timing of the big hit cycle becomes random, and illegal games can be eliminated. Needless to say, the value acquired in step ST30 is not limited to the random value RND as long as it is a random value.

<Timer interrupt processing>
Next, the timer interrupt process shown in FIG. 11B will be described. This timer interrupt process is started at a constant time interval τ based on a maskable interrupt signal (timer signal) from the CTC inside the one-chip microcomputer 64.

  When a timer interruption occurs, the CPU register is saved (ST21), and then port input processing is performed (ST22). In the port input process, signals from all switches arranged in the slot machine, such as a start switch, a stop switch, a stored medal switch, a clearing switch, and a door switch, are input through the I / O port circuit 65. The start switch signal LV ″ is input via the random number generation circuit 66 and is acquired on condition that the signal LV ″ at the same level is detected continuously a plurality of times.

  Next, in order to keep track of the current positions of the three rotary reels 4a to 4c, a rotating rotation control process is executed (ST23). The main control unit 50 can grasp the current position of each of the rotating reels 4a to 4c based on the input timing of the input signal from the index sensor and the number of drive pulses supplied to the stepping motor thereafter. Note that in the rotation rotation control process (ST23), the start-up process and stop process of the rotating reels 4a to 4c are also performed. Is generated.

  When the rotation rotation control process (ST23) is completed, the periodic update process is executed (ST24). In the scheduled update process, various software timer values for managing the game operation are updated by the decrement process (−1).

  Subsequently, one byte of the control command is output to the effect control unit 51 (ST25). Since one control command is 2 bytes long, one control command is transmitted by two successive timer interrupts. The control command indicates the game state of the main control unit 50, and the game state including the operation of the start lever 17 and the stop buttons 18a to 18c is notified to the effect control unit 51 by the control command. . Upon receiving such a control command, the production control unit 51 performs a control operation to turn on the LED lamp or generate a sound effect.

  Next, a medal information output process is executed, and for example, a medal insertion signal and a medal payout signal, each of which is a 1-bit signal, are output to the external concentration terminal board 56 (ST26). From this medal insertion signal and payout signal, the hall computer HC can grasp the number of medals inserted into each slot machine SL and the number of medals paid out from each slot machine SL. Further, the main control unit 50 outputs drive data for driving each LED lamp group to the game relay board 53 and the rotary relay board 57 (ST27).

  Thereafter, after determining the presence / absence of an abnormality such as a medal payout sensor or a door opening sensor (ST28), the saved register is restored and the interrupt process is completed (ST29).

  Although the embodiments of the present invention have been specifically described above, the specific description is not particularly intended to limit the present invention and can be appropriately changed.

  For example, the number of times of control for temporarily stopping the counting operation of the random number generation circuit 66 is not necessarily limited to once for each game, and may be once for several games, or may be a stop control for a plurality of times for one game. good. In any case, the stop control of the counting operation of the random number generation circuit 66 is performed at an appropriate timing at which there is no possibility of acquiring a random value (a random number is acquired and then a predetermined number of medals are inserted in the next game to acquire a random number. In such a case, the random number generation function can be achieved without any problem.

  When the operation prohibiting pulse CTL is output to each game a plurality of times, the output timing includes, for example, when a inserted medal is detected, when a stored medal is detected, when a stop switch is operated, when a medal to be paid out is detected, etc. Illustrated. For example, every time a medal to be paid out is detected, stop control for temporarily stopping the count operation is executed alone or in combination with other stop control.

  FIG. 13 is a flowchart for explaining an embodiment in which an operation prohibiting pulse is output when a medal is paid out. This flowchart shows in detail the medal payout process (ST10) executed in the main control unit 50.

  In the medal payout process (ST10), it is determined whether or not the medal payout number to be paid out to the player is 0 (SS10). If the medal payout number is not 0, the number of credits reaches an upper limit (for example, 50). Executes the payout process by increasing the number of credits (SS11 to SS13).

  On the other hand, when the number of credits reaches the upper limit value or reaches the upper limit value in this way, the medal payout signal PAY is set to the ON level (L level) (SS15). As a result, the payout motor MO of the medal payout device 5 starts rotating to start paying out medals.

  When the medal payout operation is started, it is next determined whether or not the payout sensor SE (FIG. 5) detects the medal payout (SS16), and waits for a predetermined waiting time until the medal payout is detected ( SS19). If the medal payout is detected, the payout number is subtracted (SS17), the operation prohibiting pulse CTL is output (SS18), and the same operation is repeated until the remaining payout number becomes zero. Note that, for example, the process of FIG. 12A is executed when the operation prohibiting pulse CTL is output.

  On the other hand, if the payout sensor SE does not detect the payout of medals even after the predetermined standby time is exceeded, it is considered that the medal hopper 5a is empty, and an abnormality notification process to that effect is executed (SS20). If opening / closing of the door sensor is detected, it is assumed that the replenishment process by the staff has been completed, the error notification process is canceled, and the process returns to step SS15.

  If such processing is repeated, the remaining payout number will eventually become 0 (SS13), so that the medal payout signal PAY is set to OFF level and the payout motor MO of the medal payout device 5 is stopped to complete the processing (SS14). ). Therefore, in this embodiment, since the operation prohibiting pulse CTL is intermittently output for the number of medals to be paid out, the counting operation of the counting unit 26 is prohibited an indefinite number of times at irregular timings, and the crime prevention function is enhanced.

  It should be noted that the stop control of the counting operation of the random number generation circuit 66 does not necessarily correspond to medal detection, and may be any timing that does not have a possibility of acquiring a random value as described above.

66 Random number generation circuit ST5 Lottery processing OSC Oscillation unit Φ Count clock CT Counter unit La Latch unit Ro Output unit 28 Prohibition unit

Claims (1)

A CPU for executing a lottery process for comparing a random number generated by a random number generation circuit at a predetermined timing during a game with a predetermined lottery value to determine whether or not to generate a gaming state advantageous to the player is provided. A gaming machine, wherein the random number generation circuit is
An oscillation unit that continuously outputs a counting clock;
In addition to receiving a count clock from the oscillating unit, the circuit includes a gate circuit that receives an operation control signal generated by the CPU so that the duration of the prohibition level changes randomly each time . while counting is Ru is stopped by supply is interrupted, when permission level of the operation control signal, and a counter for repeating a counting operation by being supplied with counting clock,
A latch unit that holds the output data of the counter unit as a random value at the predetermined timing;
An output unit that outputs a random number value held by the latch unit to the CPU based on an instruction from the CPU;
A delay circuit that increases the duration of the inhibition time generated by the CPU by adopting a circuit configuration that receives the operation control signal generated by the CPU and charges the capacitor via a resistor at the transition from the inhibition level to the authorization level. And
Gaming machine characterized in that it is configured to have a.

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