JP6572611B2 - Game machine - Google Patents

Description

  It relates to gaming machines.

  A spinning machine (slot machine) is a multi-row game machine in which a plurality of symbols are arranged on the outer periphery when a game start instruction device (start lever) is operated after a predetermined number of game medals have been inserted. The cylinder (reel) rotates, and as a result of stopping the rotation using a rotation stop device (stop button) for stopping the rotation, a combination of predetermined symbols (for example, “777” on the effective line) )), The game type is generally shifted to a special gaming state that is more profitable for the player than the normal gaming state {the gaming state in which the lottery probability of the winning combination is higher than in the normal state}. is there. Here, in the slot machine, there may be a case where an image for production for enhancing the fun of the game is displayed on a display such as a liquid crystal in a form synchronized with the rotation operation and the stop operation of the reel. In many cases, when a stop button or the like is operated, a game result is predicted and enjoyed while comparing a design displayed on the reel with an image for performance displayed on the display.

  In addition, the pachinko game machine has a symbol called “special symbol” variably displayed on the display section such as 7-segment when the game ball enters the start opening (start chucker). Is in a specific mode (for example, “7”), a special game state that is more profitable for the player than the normal game state {contents that a special winning opening (attacker) that is normally closed is opened under predetermined conditions] Is a type that shifts to the so-called “digipachi” (conventional “first-class gaming machine”). Here, in order to reduce the burden of display control of special symbols that are directly linked to the interests of the player, in addition to the aforementioned “special symbols”, it is referred to as “decorative symbols” for the purpose of enhancing the fun of the game. The symbol to be displayed may be variably displayed on a display such as a liquid crystal having a size larger than that of the display unit in a form synchronized with the variation of the special symbol. And when the change of the special symbol is started, the decorative symbol also starts to change accordingly, and when the special symbol stops in a specific mode (for example, “7”), the decorative symbol also changes to the predetermined mode (for example, “777”). And many things are comprised so that a player can recognize clearly that transfer to a special game was decided because the decoration design stopped in the predetermined mode.

  Such a mechanism is common to many game machines of this type, but the program capacity for controlling the operation of the game machine is to prevent mixing of illegal programs (guaranteeing the validity of the program provided by the machine manufacturer). The upper limit of the capacity is strictly regulated from the viewpoint, and in addition to the program for implementing the gaming specification, the gaming machine is cheated (for example, for the slot of the game medium and the outlet) Many programs for preventing illegal acts are also implemented to protect against unauthorized access to obtain game media by unauthorized means.

JP2011-147675A

  However, at present, a program for implementing the game playability specification and a program for preventing fraud are often mixed on the ROM, and as a result, it is difficult to verify the legitimacy of these programs. There is a problem of becoming.

The gaming machine according to this aspect is
In the ROM area,
A first control area in which the program is stored;
A first data area in which data is stored;
A second control area in which the program is stored;
A second data area where data is stored,
Have
In the RAM area,
A first information storage area for storing processing result data by a program stored in the first control area;
A second information storage area for storing processing result data by a program stored in the second control area;
A first stack area where data stored in a register can be saved;
A second stack area in which data stored in the register can be saved;
Have
At least after the return from power-off, the processing result data stored in the first information storage area, the processing result data stored in the second information storage area, the data saved in the first stack area, and An error detection based on the data saved in the second stack area is performed,
When executing the program stored in the second control area, the address information stored in the stack pointer is stored in the second information storage area, and the stack pointer corresponds to the second stack area. When storing specific address information and finishing the program stored in the second control area, the address information stored in the second information storage area can be stored in the stack pointer. A gaming machine characterized by the above.

  According to the gaming machine according to the present aspect, there is an effect that it becomes easy to verify the validity of the program for implementing the gameability specification and the program for preventing fraud.

FIG. 1 is a perspective view of a rotating type gaming machine according to the present embodiment. FIG. 2 is a perspective view of a state in which the door of the spinning cylinder type gaming machine according to the present embodiment is opened. FIG. 3 is a perspective view of the inside of the medal slot in the spinning cylinder game machine according to the present embodiment. FIG. 4 is a front view and a top view of the medal payout device in the spinning cylinder type gaming machine according to the present embodiment. FIG. 5 is an overall electrical configuration diagram of the swivel type gaming machine according to the present embodiment. FIG. 6 is an electrical configuration diagram relating to the main control chip of the spinning cylinder gaming machine according to the present embodiment. FIG. 7 is a memory map configuration diagram of the main control chip in the rotating game machine according to the present embodiment. FIG. 8 is a main flowchart on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 9 is a flowchart of the setting change device control process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 10 is a flowchart of the game progress control process (first sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 11 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 12 is a flowchart of the game progress control process (third sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 13 is a flowchart of the non-recoverable error process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 14 is a flowchart of a medal insertion error detection process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 15 is a flowchart of the medal payout error detection process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 16 is a flowchart of the insertion / withdrawal error detection process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 17 is a flowchart of the timer interruption process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 18 is a flowchart of the medal insertion check process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 19 is a flowchart of a medal payout check process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 20 is a flowchart of the input / withdrawal error check processing on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 21 is a flowchart of the power-off process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 22 is a main flowchart (first sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 23 is a main flowchart (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 24 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 25 is a flowchart of a medal insertion error detection process on the main control board side in the spinning-reel game machine according to the second embodiment. FIG. 26 is a flowchart of a medal payout error detection process on the main control board side in the spinning cylinder game machine according to the second embodiment. FIG. 27 is a flowchart of the insertion / withdrawal error detection process on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 28 is a flowchart of the game progress control process (third sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 29 is a flowchart of non-recoverable error processing on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 30 is a flowchart of timer interruption processing on the main control board side in the spinning-reel game machine according to the second embodiment. FIG. 31 is a flowchart of a power-off process on the main control board side in the spinning cylinder game machine according to the second embodiment. FIG. 32 is a list of basic specifications in the rotary type gaming machine according to the third embodiment. FIG. 33 is a list of reel arrangements in the rotary type gaming machine according to the third embodiment. FIG. 34 is a list of small role appearance rates in the rotary type gaming machine according to the third embodiment. FIG. 35 is a symbol combination list 1 in the rotary type gaming machine according to the third embodiment. FIG. 36 is a symbol combination list 2 in the rotary type gaming machine according to the third embodiment. FIG. 37 is a list of condition devices 1 in the rotating game machine according to the third embodiment. FIG. 38 is a list of condition devices 2 in the rotating game machine according to the third embodiment. FIG. 39 is a list of condition devices 3 in the swivel type gaming machine according to the third embodiment. FIG. 40 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning cylinder game machine according to the third embodiment. FIG. 41 is a flowchart of the process of adding the number of games at the time of winning on the main control board side in the spinning-reel game machine according to the third embodiment. FIG. 42 is a flowchart of push-sequence navigation control processing on the main control board side in the spinning cylinder game machine according to the third embodiment. FIG. 43 is a flowchart of the reel rotation start preparation process on the main control board side in the spinning cylinder type gaming machine according to the third embodiment. FIG. 44 is a flow chart of an ART lottery execution process on the main control board side in the rotating game machine according to the third embodiment. FIG. 45 is a flowchart of the process for adding the number of winning games on the main control board side in the spinning-reel game machine according to the third embodiment. FIG. 46 is a flowchart of the gaming state transition control process on the main control board side in the spinning cylinder type gaming machine according to the third embodiment. FIG. 47 is a game state transition diagram on the main control board side in the rotating game machine according to the third embodiment. FIG. 48 is a flowchart of timer interruption processing on the main control board side in the spinning-reel game machine according to the third embodiment. FIG. 49 is a flowchart of the first test signal output process on the main control board side in the spinning cylinder game machine according to the third embodiment. FIG. 50 is a flowchart of a second test signal output process on the main control board side in the spinning cylinder game machine according to the third embodiment. FIG. 51 is a flowchart of a signal control process when there is a push order navigation on the main control board side in the rotating type gaming machine according to the third embodiment. FIG. 52 is a flowchart of a signal control process when no push order navigation is performed on the main control board side in the spinning cylinder type gaming machine according to the third embodiment. FIG. 53 is a list of operation mode information in the rotating game machine according to the third embodiment. FIG. 54 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 55 is a flowchart of push-sequence navigation control processing on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 56 is a flowchart of the first test signal output process on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 57 is a flowchart of a second test signal output process on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 58 is a flowchart of the operation mode information control process on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 59 is a flowchart of a signal control process when there is a push order navigation on the main control board side in the rotating game machine according to Modification 1 from the third embodiment. FIG. 60 is a flowchart of signal control processing when no push order navigation is performed on the main control board side in the spinning-reel game machine according to Modification 1 from the third embodiment. FIG. 61 is a list of operation mode information in the rotating game machine according to the first modification from the third embodiment. FIG. 62 is a flowchart of the game progress control process (second sheet) on the main control board side in the rotating game machine according to Modification 2 from the third embodiment. FIG. 63 is a flowchart of timer interrupt processing on the main control board side in the spinning-reel game machine according to Modification 2 from the third embodiment. FIG. 64 is a flowchart of signal control processing when there is a push order navigation on the main control board side in the spinning-reel game machine according to Modification 2 from the third embodiment. FIG. 65 is a flowchart of signal control processing when no push order navigation is performed on the main control board side in the spinning-reel game machine according to Modification 2 from the third embodiment. FIG. 66 is an operation mode information list in the rotating game machine according to Modification 2 from the third embodiment. FIG. 67 is a flowchart of main processing on the main control device side on the main control board side in the spinning cylinder game machine according to the fourth embodiment. FIG. 68 is a flowchart of the setting change device control process on the main control board side in the spinning cylinder type gaming machine according to the fourth embodiment. FIG. 69 is a flowchart of a RAM initialization process without a setting change on the main control board side in the spinning cylinder game machine according to the fourth embodiment. FIG. 70 is a flowchart of a RAM initialization process with a setting change on the main control board side in the spinning cylinder game machine according to the fourth embodiment. FIG. 71 is a flowchart of the game progress control process (first sheet) on the main control board side in the spinning cylinder type gaming machine according to the fourth embodiment. FIG. 72 is a flowchart of the game progress control process (third sheet) on the main control board side in the spinning cylinder type gaming machine according to the fourth embodiment. FIG. 73 is a flowchart of the second test signal output process on the main control board side in the spinning cylinder type gaming machine according to the fourth embodiment. FIG. 74 is an example of second test signal output information on the main control board side in the swivel game machine according to the fourth embodiment. FIG. 75 is a flowchart of a power-off process on the main control board side in the spinning cylinder game machine according to the fourth embodiment. FIG. 76 is a flowchart of timer interruption processing on the main control board side in the spinning-reel game machine according to the fourth embodiment. FIG. 77 is a flowchart of a first test signal output process on the main control board side in the spinning cylinder type gaming machine according to the fourth embodiment. FIG. 78 is an example of processing when calling the second ROM area on the main control board side in the spinning cylinder type gaming machine according to the fifth embodiment. FIG. 79 is a stack area image view on the main control board side in the spinning cylinder game machine according to the fifth embodiment. FIG. 80 is a flowchart of the first and second main processes on the main control board side in the spinning cylinder game machine according to the sixth embodiment. FIG. 81 is a flowchart of first interrupt processing on the main control board side in the spinning-reel game machine according to the sixth embodiment. FIG. 82 is a flowchart of second interrupt processing on the main control board side in the spinning-reel game machine according to the sixth embodiment. FIG. 83 is an image A of main processing on the main control board side in the spinning cylinder type gaming machine according to the sixth embodiment. FIG. 84 is an interrupt image diagram A during the setting of the first stack on the main control board side in the spinning cylinder type gaming machine according to the sixth embodiment. FIG. 85 is an image diagram A of an interrupt during setting of the second stack on the main control board side in the spinning cylinder game machine according to the sixth embodiment. FIG. 86 is a flowchart of the first and second main processes on the main control board side in the spinning cylinder game machine according to the seventh embodiment. FIG. 87 is a flowchart of the first interrupt process on the main control board side in the spinning-reel game machine according to the seventh embodiment. FIG. 88 is a flowchart of the second interrupt process on the main control board side in the spinning-reel game machine according to the seventh embodiment. FIG. 89 is a main process image diagram B on the main control board side in the spinning cylinder type gaming machine according to the seventh embodiment. FIG. 90 is an interrupt image diagram B during the setting of the first stack on the main control board side in the spinning-reel game machine according to the seventh embodiment. FIG. 91 is a second stack setting interrupt image view B on the main control board side in the spinning-reel game machine according to the seventh embodiment. FIG. 92 is a flowchart of the first and second main processes on the main control board side in the spinning cylinder type gaming machine according to the eighth embodiment. FIG. 93 is a flowchart of the first interrupt process on the main control board side in the spinning-reel game machine according to the eighth embodiment. FIG. 94 is a flowchart of second interrupt processing on the main control board side in the spinning-reel game machine according to the eighth embodiment. FIG. 95 is an image C of main processing on the main control board side in the spinning cylinder type gaming machine according to the eighth embodiment. FIG. 96 is an image C of an interrupt during the first main process on the main control board side in the spinning-reel game machine according to the eighth embodiment. FIG. 97 is a second main processing interrupt image diagram C on the main control board side in the spinning-reel game machine according to the eighth embodiment. FIG. 98 is a flowchart of the first and second main processing on the main control board side in the spinning cylinder type gaming machine according to the ninth embodiment. FIG. 99 is a flowchart of the first interrupt process on the main control board side in the spinning-reel game machine according to the ninth embodiment. FIG. 100 is a flowchart of the second interrupt process on the main control board side in the spinning-reel game machine according to the ninth embodiment. FIG. 101 is a main process image diagram D on the main control board side in the spinning cylinder type gaming machine according to the ninth embodiment. FIG. 102 is an image diagram D of an interrupt during the first main processing on the main control board side in the spinning cylinder type gaming machine according to the ninth embodiment. FIG. 103 is an interrupt image diagram D during the second main process on the main control board side in the spinning cylinder type gaming machine according to the ninth embodiment. FIG. 104 is a flowchart of the first and second main processes on the main control board side in the spinning cylinder game machine according to the tenth embodiment. FIG. 105 is a flowchart of the first interrupt process on the main control board side in the spinning-reel game machine according to the tenth embodiment. FIG. 106 is a flowchart of second interrupt processing on the main control board side in the spinning-reel game machine according to the tenth embodiment. FIG. 107 is a flowchart of the first and second main processes on the main control board side in the spinning cylinder type gaming machine according to the eleventh embodiment.

  First, the meaning of each term in this specification will be described. “Random number” is a random number used in a lottery (lottery by an electronic computer) to determine some game content in a spinning-type game machine, and includes a pseudo-random number in addition to a random number in a narrow sense (for example, as a random number) Is a hard random number, and a soft random number as a pseudo-random number). For example, a so-called “basic random number” that affects the outcome of the game, specifically, a “winning random number” associated with the transition of a special game or a winning combination can be cited. “CPU” is synonymous with what is well known in the art, and is not limited to the architecture (CISC, RISC, number of bits, etc.) used, processing performance, or the like. “Power interruption (power interruption)” means that the power supply voltage supplied to the gaming machine falls below a certain level regardless of whether the power switch provided on the gaming machine is operated or not. This also includes shutting down the power supply due to unforeseen circumstances such as unit damage or power outages. “ROM” is synonymous with what is well known in the art, and physically retains information (for example, “1” for a device configuration that conducts when a current for reading data is applied, It will be “0” if the device configuration is not.) RAM is synonymous with what is well known in the art, and electrically holds information (for example, when a current for reading data is applied, “1” is stored if it is stored, and it is not stored. It is generally “0.” In general, backup power is supplied to some or all of the data stored in the RAM when the power is interrupted). The “game state” is, for example, a special game state in which a game medal can be easily acquired and advantageous to the player (so-called jackpot game, such as a bonus game, a type 1 BB, a type 2 BB, or the like) ), The re-game probability variation game state (RT state) in which the re-game win rate is higher (or lower) than the normal game state in which the re-game win rate is a predetermined value, and the winning combination is awarded For example, an AT (assist time) state in which the stop order of the reels can be notified, an ART (assist replay time) state in which the RT state and the AT state are combined, and the like. Further, even in the normal game state, there are a high-probability normal game state, a low-probability normal game state, and the like that have different lottery probabilities for transition to the RT state, AT state, and ART state. In addition, there is no problem even if the game states are combined {in addition, these game states and functions (for example, a lottery to shift to the AT state, an output of a notification instruction related to the stop order of reels, etc.) control the game progress. There is no problem even if all are mounted on the main control board side}.

  The following embodiment is based on the assumption of a revolving game machine (so-called slot machine), but is not limited to this, and other game machines (for example, pachinko game machines, sparrow balls, arrangements) It is also within the range when applied to a ball, etc., that is, with a microcomputer chip (chip equipped with a CPU, ROM, RAM) for controlling the progress of the game, and for operating a program on the microcomputer chip It is a technology that can be applied. Note that this embodiment is merely an example, the location and function of each means, the order of each step regarding various processes, the timing of flag on / off, the name of the means responsible for each step, etc. It is not limited to the following aspects. In addition, the above-described embodiments and modified examples should not be understood as being limited to being applied to specific items, and may be in any combination. For example, it should be understood that a modification example of an embodiment is a modification example of another embodiment, and even if one modification example and another modification example are described independently, there is the modification example. It should be understood that a combination of the modified example and another modified example is also described.

  Prior to the detailed description of the present invention, a simple configuration according to the present invention will be described.

  Among the swivel type gaming machines according to the present invention, a configuration in which the first RAM area (or register area) can be updated and referred to by the processing of the CPUC 100 based on the program code arranged in the second ROM area (this book) Embodiment) will be described in detail.

  Among the swivel type gaming machines according to the present invention, the second RAM area can be referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area, and is arranged in the second ROM area. A configuration in which the first RAM area can be referred to in the processing of the CPUC 100 based on the program code is described in detail in the second embodiment.

  Among the spinning-type gaming machines according to the present invention, any condition device information is executed as condition device information to be executed in the second program area and related to a signal output to the test substrate and output to the first test substrate. The identification value (small role identification value, bonus identification value) relating to the timing of outputting is temporarily stored in the first RAM area by processing in the first program area, and the push order executed in the first program area A configuration for controlling the output signal to the second test board based on the push order navigation by the display device D270 will be described in detail in (third embodiment).

  Among the swirl type gaming machines according to the present invention, the identification value relating to which condition device information is output as the condition device information to be output to the first test board based on the third embodiment The (small role identification value, bonus identification value) is temporarily stored in the register area by processing in the second program area, and the second test area is transferred to the second test board regardless of the push order navigation in the first program area. The configuration for controlling the output signal will be described in detail in (Modification 1 from the third embodiment).

  Of the spinning cylinder type gaming machine according to the present invention, based on the modified example 1 from the third embodiment and as operation mode information to be output to the second test board, information on the reel to be stopped, that is, in the reel stop order. A configuration for transmitting such information to the second test board with a single output will be described in detail in (Modification 2 from the third embodiment).

  Based on the third embodiment, the RAM initialization range is determined and the RAM is cleared at the time of power interruption recovery, and the range related to the first ROM / RAM area is the first ROM / RAM area. A configuration in which the range of the second ROM / RAM area is executed by the process of the second ROM / RAM area will be described in detail in the fourth embodiment.

  Of the swivel type gaming machine according to the present invention, the address of the stack pointer when the process of the second ROM area is called while the process of the first ROM area is being executed, and the first ROM area after the process of the second ROM area is finished It is determined whether or not the address of the stack pointer when returning to the caller of the file matches, and only when it matches, it is determined that the processing in the second ROM area has been executed normally. This will be described in detail in (Fifth Embodiment).

  Of the swivel-type gaming machine according to the present invention, a configuration in which processing of the first ROM / RAM area and processing of the second ROM / RAM area are separated by using two stack areas (sixth embodiment) This will be described in detail.

  Of the swivel type gaming machine according to the present invention, a configuration in which the timing of saving or returning the registers is made different will be described in detail in (Seventh embodiment) based on the sixth embodiment.

  Based on the sixth embodiment, the first ROM / RAM area processing and the second ROM / RAM area processing are prohibited by prohibiting an interrupt when calling the second ROM area, based on the sixth embodiment. A configuration for carving will be described in detail in (Eighth Embodiment).

  Of the swivel-type gaming machine according to the present invention, a configuration in which the timing of saving or returning the registers is different will be described in detail in the ninth embodiment based on the eighth embodiment.

  Of the swirl type gaming machine according to the present invention, a configuration in which the timing of saving or returning the registers is made different will be described in detail in the tenth embodiment based on the sixth embodiment.

  Based on the sixth embodiment, the first ROM / RAM area processing and the second ROM / RAM area processing are prohibited by prohibiting an interrupt when calling the second ROM area, based on the sixth embodiment. The configuration for carving will be described in detail in (Eleventh Embodiment).

(This embodiment)
Here, before describing each component, the feature (outline) of the spinning-rotor type gaming machine P according to the present embodiment will be described. Hereinafter, each element will be described in detail with reference to the drawings.

  First, with reference to FIG. 1 (FIG. 2 for a part of the configuration), the basic structure on the front side of the rotary type gaming machine according to the present embodiment will be described. First of all, the swing type gaming machine P mainly includes a front door (also referred to as a front door), a back box (also referred to as a cabinet and a base body), a reel unit installed in the back box, a hopper device, a power supply unit, and a main control. It is composed of a substrate M (a substrate on which the main control chip C is mounted). Hereinafter, these will be described in order.

  Next, the front door DU of the swing type gaming machine P includes a decorative lamp unit D150 and a medal tray D230. First, the decorative lamp unit D150 has a light-emitting source that emits light in accordance with the progress of the game of the rotary game machine P. Further, a door switch D80 capable of detecting the open / closed state of the front door DU is provided. Further, the front door DU is provided with a key hole D260, and a key (door key) that matches the shape of the key hole D260 is inserted into the key hole D260 {in addition, twisted in a predetermined direction (for example, clockwise)} The front door DU can be opened. Further, in the present embodiment, an error state (a door opening error, which will be described later) can be canceled by inserting the door key into the keyhole D260 {plus twisting in a predetermined direction (for example, counterclockwise)}. It is configured. Next, the medal tray D230 is a tray for game medals (or simply called medals) released from the discharge port D240.

  Next, the front door DU includes a mechanism for enabling visual recognition of the game state, a mechanism for enabling input of game media, a mechanism for operating the reel unit, and the like. Specifically, the reel window D160, the insertion number display lamp D210, the operation state display lamp D180, the special game state display apparatus D250, the payout number display apparatus D190, and the credit number display apparatus are provided as mechanisms for making the gaming state visible. D200, a push order display device D270, an ART counter value display device D280, and the like are attached. Further, as a mechanism for enabling the insertion of game media and inputting the number of bets (the number of bets), a medal insertion slot D170, a bet button D220, and a mechanism for enabling the payout of the inserted game media are settled. Button D60 is attached. As a mechanism for operating the reel unit, a start lever D50 and a stop button D40 are attached. Hereinafter, each element will be described in detail.

<Mechanism to make game state visible>
Next, the reel window D160 is a transparent member formed of a synthetic resin or the like that constitutes a part of the front door DU, and is configured so that the reel unit installed in the gaming machine frame can be seen through the reel window D160. ing. In addition, the insertion number indicator lamp D210 is constituted by an LED, and is configured so that the same number of LEDs as the number of medals currently bet (to insert a game medal necessary for starting one game) are lit. Has been. Further, the operation state indicator lamp D180 is constituted by an LED, and is configured to be turned on / off according to the current operation state (medal acceptance / non-acceptance state, re-game winning state, game start wait state, etc.). The special game state display device D250 is configured by a 7-segment display, and is configured to display the total number of payouts paid out during the special game. In addition, it is good also as a structure which does not provide the special game state display apparatus D250, and when it is comprised in that way, it is comprised so that a player may be in special game by displaying so that the total of the said number of payouts may be displayed in effect display apparatus S40. The total number of payouts paid out can be recognized, and a user-friendly gaming machine can be obtained. Further, the payout amount display device D190 is configured by a 7-segment display, and is configured to display the number of game medals currently being paid out. The credit amount display device D200 is configured by a 7-segment display, and is configured to display the total number of medals (credit number) stored in the gaming machine as medals held by the player. Further, the push order display device D270 is a condition device {a so-called push order small role that may be won depending on the reel stop order (the stop order of the left stop button D41, middle stop button D42, right stop button D43). In a game in which a profit rate (the number of payouts, the subsequent RT state, etc.) attached to the player can be different when the winning combination is different is generally established} The reel stop order that is most advantageous to the player can be notified. In addition, the ART counter value display device D280 indicates the number of games that can stay in an ART state (details will be described later) that is guaranteed when a game progresses according to the push order navigation display displayed on the push order display device D270. It is configured so that it can be displayed. It should be noted that the push order display device D270 may also be used as the payout number display device D190, and if not used, the payout number display device D190 will display the total number of medals paid out by winning in the ART state to be described later ( Or a net increase number) may be displayed.

<Mechanism to enable input of game media>
Next, the medal slot D170 is a slot for game medals, and the game medal inserted into the slot is guided to the inside of the gaming machine frame in a situation where medals can be received. In addition, an insertion acceptance sensor D10s, a first insertion sensor D20s, and a second insertion sensor D30s are provided inside the gaming machine frame as sensors for detecting the insertion of medals. When it is determined that the guided game medal is normally inserted, the inserted medal is detected as a bet. Further, the bet button D220 is configured to be operable by the player, and configured to bet a stored medal (credit medal). Further, the settlement button D60 is configured to be operable by the player, and by this operation, the stored medal (credit medal) and / or the bet medal can be paid back to the player. ing. Note that the game medals paid out by operating the settlement button D60 are configured to be paid out to the discharge port D240.

<Mechanism for operating reel unit>
Next, the start lever D50 is configured to be operable by the player, and is configured to be able to start the operation of the reel unit by the operation. The stop button D40 includes a left stop button D41, a middle stop button D42, and a right stop button D43 that can be operated by the player. By operating each stop button, the operation of the reel unit can be stopped sequentially. It is configured.

  Next, the reel unit of the rotating type gaming machine P includes a reel M50 and a drive source (stepping motor or the like) of the reel M50. The reel M50 includes a left reel M51, a middle reel M52, and a right reel M53. Here, each reel part is formed of a synthetic resin or the like, and a plurality of symbols are drawn on the outer periphery (on the reel band) of the reel part. And based on operation of each stop button in the start lever D50 and the stop button D40, it is comprised so that rotation operation and stop operation | movement of each reel part are enabled. Although not shown, an LED (hereinafter also referred to as a reel backlight) is provided inside the left reel M51, the middle reel M52, and the right reel M53, and when the LED is lit, the reel portion It is configured so that the light transmitted through the outer periphery can be visually recognized as if the outer periphery of the reel portion is lit.

<Other mechanisms>
In addition, inside and outside the gaming machine frame of the swing type gaming machine P, as a mechanism for enhancing the interest of the game, an effect display device S40 for displaying effects such as a notice effect and a background effect, various lighting modes Are provided with an LED lamp S10 that can be turned on, a speaker S20 that can output sound, and an upper panel D130 and a lower panel D140 that are members formed of synthetic resin or the like.

  Next, FIG. 2 is a perspective view showing an internal configuration of the rotating game machine P with the front door DU opened. An effect display device S40 is attached to the upper part on the back side of the front door DU. A reel window D160 is provided substantially at the center of the front door DU, and a door substrate D described later is provided below the reel window D160. In addition, the door board D receives input signals such as the stop button D40, the start lever D50, and the settlement button D60 described above. A speaker S20 is provided below the door substrate D.

  Although details will be described later, an insertion acceptance sensor D10s serving as a path for game medals inserted from the medal insertion slot D170 is provided in the vicinity of the door substrate D, and below the insertion reception sensor D10s, A coin shooter D90 and the like for guiding a game medal to the discharge port D240 are provided. The insertion acceptance sensor D10s has a function of selecting game medals inserted from the medal insertion slot D170 mainly on the basis of dimensions, and accepting only game medals conforming to the standard dimensions. The selected medal (or other foreign matter) is returned to the discharge port D240 by the blocker D100. If the player inserts a game medal before operating the start lever D50 (in a state where the insertion of the game medal is valid), the game medal is selected by the insertion acceptance sensor D10s, and only those satisfying the standard are selected. A medal that does not satisfy the standard and is inserted into the hopper H40 is returned to the discharge port D240 through the coin shooter D90. On the other hand, when a game medal is inserted after the start lever D50 is operated (in a state where the insertion of the game medal is not valid), the inserted game medal passes through the coin shooter D90, and the discharge port D240. Returned to. In addition, a sensor for medal insertion, which will be described in detail later, is provided inside the insertion acceptance sensor D10s (the back of the flow path), and when a game medal that has been received satisfying the dimensional standard passes, the first insertion sensor D20s. The signal is detected by the second input sensor D30s and the signal is supplied to the main control board M to be described later.

  A main control board M, which will be described later, that controls the entire game is stored above the reel M50, and behind the reel M50, each reel (left reel M51, middle reel M52, right reel M53) is driven. For this purpose, a later-described rotor substrate K is stored. Further, on the left side of the reel M50, a sub-control board S (to be described later) that controls various effects performed using the effect display device S40 shown in FIG. 1, the LED lamp S10, the speaker S20, and the like is stored. . In addition, the main control board M has a setting key switch M20 used for executing a setting change device control process (to change settings), which will be described later, and a setting / reset that can execute setting value change, error cancellation, and the like. A setting door switch M10 for determining opening / closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30, and the like is connected. The setting key switch M20, the setting / reset button M30, and the setting door switch M10 are not shown, but they may be provided at appropriate positions on the main control board M (ie, the front door). If the DU is not opened, it may be in a position where it is difficult to access artificially).

  Below the reel M50, there are provided a hopper H40 for collecting inserted game medals and a medal payout device H for paying out game medals, and a power supply board for supplying power to the entire revolving game machine P E is stored. The game medals paid out from the medal payout device H pass through the coin shooter D90 and are paid out from the discharge port D240. Further, on the front surface of the power supply board E, there is also provided a power switch E10 for turning on the power of the swivel type gaming machine P.

  Next, FIG. 3 is a perspective view showing a path (selector) of game medals inserted into the medal insertion slot D170 inside the spinning cylinder type game machine. A game medal inserted into the medal slot D170 first passes through the slot acceptance sensor D10s. The insertion acceptance sensor D10s is a mechanical double sensor, and when the game medal passes, it turns on when the two protruding mechanisms are pressed, and the game medal can normally pass through the passage. Become. Also, with such a configuration, when a foreign object that is not a game medal (for example, one having a smaller diameter than the game medal) is inserted, the two protruding mechanisms are not pressed. Such medals cannot be maintained in the standing state, and therefore cannot pass through the passage (the medals fall down) and are paid back to the discharge port D240. In addition, the insertion acceptance sensor D10s is configured to be able to determine that there is an error even when the on-time continues for a predetermined time or longer (as a result, the blocker D100 can be turned off). .

  When a game medal normally passes through the blocker D100, it passes through the first insertion sensor D20s and the second insertion sensor D30s immediately after the passage. The throwing sensors (first throwing sensor D20s and second throwing sensor D30s) are composed of two sensors (adjacently arranged at an interval smaller than the standard diameter of the game medal), and each sensor is turned on. -Various errors (to be described later) are monitored by monitoring the OFF state (the order in which the combination of ON / OFF of the first input sensor D20s and the second input sensor D30s transitions) and the ON / OFF time. , Inserted medal retention error, inserted medal backflow error, etc.).

  Next, FIG. 4 is a front view and a perspective view of the medal payout device H in the spinning cylinder type gaming machine. The medal payout device H is operated with the checkout button in the state where credits (game medals stored electronically inside the gaming machine) or bets (medals inserted to start the game) exist. It is activated when a game medal is paid out by winning or winning. In operation, first, the hopper motor H80 is driven to rotate the disk H50 about the disk rotation axis H50a. The game medal in the medal payout device H flows down from the game medal outlet H60 toward the discharge port D240 by displacing the discharge urging means H70 by the rotation. The payout sensors (the first payout sensor H10s and the second payout sensor H20s) are composed of two sensors, and the ON / OFF status of each sensor (the ON / OFF state of the first payout sensor H10s and the second payout sensor H20s). The order of transition of the combination of off, etc.) and the on / off time are monitored to detect various errors (payout medal retention error, etc., which will be described later). More specifically, for example, when the game medal outlet H60 normally passes, the first payout sensor H10s = off and the second payout sensor H20s = off due to the displacement of the discharge biasing means H70. 1 payout sensor H10s = off / second payout sensor H20s = off → first payout sensor H10s = on / second payout sensor H20s = off → first payout sensor H10s = on / second payout sensor H20s = on → first payout Sensor H10s = on / second payout sensor H20s = off → first payout sensor H10s = off / second payout sensor H20s = off, so that when a movement contrary to this sensor state transition is detected It is possible to exemplify the configuration of an error.

  Next, referring to the block diagram of FIG. 5, an electrical schematic configuration of the rotating game machine P according to the present embodiment will be described. First, in the spinning-type game machine according to the present embodiment, a sub-control board S, a door board D, a spinning board K, a power board E, a relay board IN, A setting door switch M10, a setting key switch M20, a setting / reset button M30, and the like are connected to be able to exchange data. The solid line portion in the figure shows the movement related to the exchange of data, and the broken line portion in the figure shows the power supply route. The power supply route is not limited to this, and for example, power may be supplied from the power supply board E to the relay board IN and the door board D without going through the main control board.

  The main control board M is a board that governs the progress of the entire game performed in the rotating game machine P. A main control chip C is mounted on the main control board M, and a CPU C 100, a built-in ROM C 110, a built-in RAM C 120, and the like are mounted on the main control chip C so as to be able to exchange data with each other via a bus ( The illustration and details will be described later). The main control board M receives a signal indicating that the start lever D50 or the like has been operated from the door board D mounted on the front door DU, and receives the sub-control board S, the door board D, and the rotating board. By outputting a control command (or control signal) toward K or the like, the operation of these various substrates is controlled.

  Similarly to the main control board M described above, the sub control board SC is also mounted on the sub control board S. The sub control chip SC is provided with a CPU, ROM, RAM, etc. Are connected so as to be able to exchange data with each other. In addition, various LED lamps S10, a speaker S20, an effect display device S40, a rotating backlight S30, and the like are connected to the sub-control board S. Here, the spinning backlight S30 is a light that is provided inside each of the left reel M51, the middle reel M52, and the right reel M53, and illuminates the pattern drawn on the surface of the reel from the back side. The sub-control board S analyzes the control command received from the main control board M, and outputs various drive signals to the various LED lamps S10, the speaker S20, the effect display device S40, the rotary backlight S30, etc. The production of.

  On the door substrate D, the above-described insertion acceptance sensor D10s, first insertion sensor D20s, second insertion sensor D30s, stop button D40 for stopping the rotating reel M50, start for starting the rotation of the reel M50. Lever D50, paid game medals (credits) and payment buttons D60 for paying out inserted game medals and ending the game, various display panels D70 for displaying the game status (the above-mentioned input number display lamps) D210, operation state display lamp D180, special game state display device D250, payout number display device D190 is a collection of display devices such as credit number display device D200), determination of opening / closing of front doors, error cancellation, and set value The door switch D80 for executing the change of the game medal (or other determined to be incompatible after being inserted) Blocker D100 or the like for refund foreign matter) in the outlet D240 is connected. The door substrate D is connected to the main control substrate M described above so as to exchange data. For this reason, when a start lever D50, a stop button D40, a settlement button D60, etc. provided on the front door DU are operated, a signal related to the operation is supplied to the main control board M via the door board D. It has become. Further, a signal that the insertion acceptance sensor D10s detects the passage of the game medal is also supplied to the main control board M through the door board D.

  In addition, a rotating motor K10 for rotating the reel M50, a rotating sensor K20 for detecting the rotational position of the reel M50, and the like are connected to the rotating substrate K. The spinning board K can stop the reel M50 at the determined stop position by driving the spinning motor K10 while detecting the rotational position of the reel M50 by the spinning sensor K20. Yes. Further, in the spinning cylinder type gaming machine of the present embodiment, a so-called step motor (stepping motor) is used as the spinning cylinder motor K10. In the step motor, 504 steps are set as the number of steps for one rotation of the reel M50. Each reel (left reel M51, middle reel M52, right reel M53) has a predetermined number of symbols (for example, 21 symbols) with a substantially uniform size, and the number of steps corresponding to one symbol is set. 24 steps (= 21/504) are set. There is no problem even if the number of steps and the number of symbols per reel are changed.

  The medal payout device H is connected to the main control board M via the relay board IN, and pays out a predetermined number (for example, 10) of game medals based on a control signal from the main control board M. Perform the action The medal payout device H includes a first payout sensor H10s and a second payout sensor H20s for determining whether or not a medal has been paid out normally and measuring the number of game medals paid out, and a disk H50. A hopper motor H80 for rotation is connected.

  These various control boards and the power consumed by the boards are supplied from a power supply board E (a board for controlling the presence or absence of power supply by the power switch E10). In FIG. 5, a state in which power is supplied from the power supply board E is indicated by a broken-line arrow. As shown in the figure, power is directly supplied from the power supply board E to the main control board M and the sub-control board S, and various boards (door board D, rotor board K, relay board IN) Electric power is supplied via the main control board M. A predetermined amount (for example, 100 V) of AC voltage is supplied to the power supply board E, and this electric power is converted into a DC voltage of a specified voltage and then supplied to each control board and board.

  In addition, the main control board M has a setting key switch M20 used for executing a setting change device control process (to change settings), which will be described later, and a setting / reset that can execute setting value change, error cancellation, and the like. A setting door switch M10 for determining opening / closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30, and the like is connected.

<Example of basic circuit configuration of main controller>
Next, a configuration example of the main control chip C of the main control board M will be described with reference to FIG.

  First, the main control chip C shown in FIG. 6 includes a CPU C100, built-in ROMC110 (first ROM area C111, second ROM area C112), built-in RAMC120 (first RAM area C121, second RAM area C122), external bus control circuit C190, parallel. In addition to the input port C130, address decoding circuit C150, timer circuit C170, counter circuit C180, reset control circuit C220, interrupt control circuit C160, clock circuit C210, random number generation circuit C140, verification block C230, specific information C240, arithmetic circuit C250 Are all connected to each other via an internal bus C200.

  Hereinafter, details of each of the above-described units will be described.

  First, the CPUC 100 executes various numerical calculations, information processing, control processing, and the like according to programs and data in the built-in ROMC 110 and the built-in RAMC 120. The built-in ROMC 110 stores control programs and various data. The built-in RAMC 120 temporarily stores data. Further, the built-in ROMC 110 and the built-in RAMC 120 hold addresses and data as a set, and uses are divided by address ranges. The main applications are a program area and a data area. Details of this point will be described later in the description of a memory map.

  The external bus control circuit C190 includes an IO request terminal (XIORQ terminal), a memory request terminal (XMREQ terminal), a read signal terminal (XRD terminal), a write signal terminal (XWR terminal), and a 16-bit width address output terminal (A0 terminal to A15 terminal) and data input / output terminals (D0 terminal to D7 terminal) which are input / output terminals having an 8-bit width. In the present embodiment, among these, the data input / output terminals (D0 terminal to D7 terminal) are used for data output to each drive circuit (for example, the rotating board K via the relay board IN) and each peripheral control circuit (for example, the terminal board). , Used for data input from various sensors and various operation members via the door substrate D). The data input / output destinations of the data input / output terminals (D0 terminal to D7 terminal) are the address signal output from the address output terminals (A0 terminal to A15 terminal) and the chip select signal output from the address decode circuit C150. Use to switch.

  The parallel input port C130 has four input terminals (P0 terminal to P3 terminal). As for these input terminals (P0 terminal to P3 terminal), for example, any one of the input terminals is connected to the start lever D50, and as a latch signal for causing the CPU C 100 to acquire the random number generated by the random number generation circuit C140, It outputs to the random number generation circuit C140.

  The address decoding circuit C150 has a predetermined number (for example, 14) of output terminals (XCS0 terminal to XCS13 terminal). The output terminals (XCS0 terminal to XCS13 terminal) are connected to the peripheral control circuit outside the main control chip C, and are output from the data input / output terminals (D0 terminal to D7 terminal) of the external bus control circuit C190. It is used to output a chip select signal or the like for switching the data transmission destination.

  The timer circuit C170 is used for time measurement. The timer circuit C170 outputs a time-out signal to the counter circuit C180 when the set measurement time has passed. On the other hand, the counter circuit C180 is used for measuring the number of times of rising (or falling) of various signals. Signals measured by the counter circuit include a system clock of the main control chip C, a timeout signal from the timer circuit, a memory read / write signal, a memory request signal, an external input / output signal, an interrupt response signal, and the like. It can be measured.

  The reset control circuit C220 has two terminals, a system reset input terminal (XSRST terminal) and a reset output terminal (XRSTO terminal). This system reset input terminal (XSRST terminal) is connected to a voltage monitoring circuit (a circuit for monitoring voltage, not shown). When a system reset signal (for example, a signal at an L level for a predetermined time) is input from the system reset input terminal (XSRST terminal), the reset control circuit C220 sends this system reset signal to the internal circuit of the main control chip C. In addition to outputting, a reset signal (for example, a rising signal from L level to H level) is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the main control chip C. In this case, the main control chip C executes a process called system reset and initializes each circuit. An example of executing the system reset is when the power is turned on.

  In addition, the reset control circuit C220 includes a watchdog timer C222 and an out-of-designated area travel prohibition circuit C221. When the watchdog timer C222 times out, or when the CPU C100 refers to an address outside the predetermined range (runs outside the designated area), the reset control circuit C220 is connected to the circuit inside the main control chip C. Either system reset signal or user reset signal is output. Whether to output a system reset signal or a user reset signal depends on the setting of a program area (details will be described later) in the built-in ROMC 110. Further, a reset signal is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the main control chip C.

  The main control chip C can execute either the above-described system reset or a process called user reset depending on the setting.

  The traveling outside the designated area means that the program is operating unexpectedly. In this case, the CPUC 100 operates with a code that should not be handled as a program. Such a situation may be caused by some sort of fraud other than a so-called runaway state due to a program mistake. In this case, normal operation can be restored by any one of the system reset and user reset processes described above. Further, when the watchdog timer C222 times out, there are a case where the CPUC100 cannot perform the originally designed operation due to a runaway due to a program mistake or a voltage drop. Also in this case, it is configured to be able to return to normal operation by any one of the above system and user reset processes.

  The interrupt control circuit C160 generates an interrupt in order to appropriately execute processing according to an external input or a change in an internal state. This interrupt process includes, for example, a process executed when an external input (signal from a sensor) is received. In the present embodiment, timer interrupt processing executed in response to an interrupt request from the timer circuit is executed. The interrupt control circuit C160 includes an internal information register C161. The internal information register C161 includes an abnormality in the cycle of the external clock (count clock) that determines the random number update cycle by the random number generation circuit C140, and the update of the random number. In addition, information on the reset factor of the user reset that occurred immediately before is stored.

  The clock circuit C210 receives an external clock (24 MHz clock in this example) input from a crystal oscillator (not shown) via an external clock input terminal (EX terminal) with a predetermined frequency division ratio (for example, 1/2). The divided system clock (12 MHz clock in this example) is supplied to each circuit in the main control chip C. The system clock is output to a peripheral control circuit outside the main control chip C via a system clock output terminal (CLKO terminal).

  The random number generation circuit C140 uses the clock signal (count clock) for updating the random number, and holds the updated random number in the random number register when the random number latch signal is received. In this embodiment, an external clock signal input from a crystal oscillator via an external clock input terminal (RCK terminal) is divided by a predetermined frequency division ratio (for example, 1/2) and used as this count clock. However, the clock signal in the main control chip C can also be used, and in this case, a crystal oscillator is not necessary. The value held in the random number register can be read and used as a random number. Note that when a random number is read from the random number register, an allowable state in which the random number register is allowed to latch the next random number can be set.

  The verification block C230 executes a security check that is an authenticity check as to whether or not the main control chip C is a legitimate product that has passed the type approval. It is configured to be able to transmit to or receive from the external terminal plate.

  The unique information C240 stores a unique identification number written when the main control chip C is manufactured, and the identification number cannot be rewritten. The arithmetic circuit C250 is a circuit that executes four arithmetic operations and logical operations.

<Memory map>
Next, an example of the memory map of the main control chip C shown in FIG. 6 will be described using FIG. The memory map shows an address space from “0000H” to “FFFFH”. Among these, the built-in ROMC 110 is assigned to the space from “0000H” to “27FFH”, and the register area built in each circuit in the main control chip C is assigned to the space from “2800H” to “28FFH”. The internal RAMC 120 is allocated to the space from “F000H” to “F2FFH”, and the XCS decode area (the given machine language is interpreted as an internal representation) in the space from “FDD0H” to “FDFBH”. (Decoding area) is allocated. By causing the CPUC 100 to execute an instruction to access these addresses, it is possible to execute access to the corresponding hardware.

  The built-in ROMC 110 has a first ROM area that is an area that mainly controls the progress of the game, and a second ROM area that is an area that mainly controls processing different from the normal progress of the game such as errors. The first ROM area is assigned to the space from “0000H” to “1FFFH”, and the second ROM area is assigned to the space from “2000H” to “27FFH”. Note that the first ROM area is configured to have a larger capacity than the second ROM area (in other words, the data capacity that exists in the first ROM area and is accessed by the CPUC 100 exists in the second ROM area, and the CPUC100 Configured to be larger than the data capacity accessed from

  The first ROM area stores a first control area in which program code (instruction code set for the CPUC 100) is stored, and program data used by the program (read by processing of the CPUC 100 based on the program code). First data area, an area for storing various identification information (company name, date of manufacture, model name, etc.), and various settings used when operating the main control chip C (operation of the random number generation circuit C140) A program management area in which settings, operation settings of the watchdog timer C222, etc.) are stored. In the figure, the memory map image in the first ROM area is illustrated, but the number of bytes in each area and the presence / absence of an unused area are merely examples.

  The second ROM area stores a second control area in which program codes (instruction code sets for the CPUC 100) are stored, and program data used by the program (read by processing of the CPUC 100 based on the program codes). The second control area is configured to have a capacity smaller than that of the first control area (in other words, the CPUC100 exists in the second control area. The program code capacity accessed from the first control area is smaller than the program code capacity accessed from the CPUC 100), and the second data area is configured to have a smaller capacity than the first data area. (In other words, it exists in the second data area and is accessed from the CPUC 100. Program data capacity is smaller than the program data capacity to be accessed from there to the first data area CPUC100).

  On the other hand, the built-in RAMC 120 is a first RAM area which is an area mainly storing information based on the progress of the game, and a second RAM area which is an area storing information mainly based on processing different from normal progress of the game such as an error related. And a stack area that is used when the program needs to store data internally, and a first RAM area is allocated to the space from “F000H” to “F1FFH”. The second RAM area is allocated to the space from “F200H” to “F2C9H”, and the stack area is allocated to the space from “F2CAH” to “F2FFH” (however, the number of bytes in each area is merely an example) ).

  The first RAM area has a first work area that is a work area for temporarily storing information related to the progress of the game, and the second RAM area temporarily stores information related to errors and the like. And a checksum area that is a work area for performing error detection of information temporarily stored in the first RAM area and the second RAM area. The first RAM area is configured to have a larger capacity than the second RAM area. In this embodiment, only the second RAM area is included in the checksum area (the first RAM area is not included), and the checksum area includes both the first RAM area and the second RAM area ( It is configured to manage a checksum (total of information temporarily stored in both sides). In this embodiment, as will be described later, when calculating the checksum, including the unused area, the calculation is not limited to this. The checksum may be calculated for the work area and the second work area. In addition, the method of performing error detection is not limited to the method of performing checksum check, and a method of performing other methods (for example, parity check) may be used. This is an area for storing information for error detection (for example, parity bits, etc.) required when using the technique.

  It should be noted that there is no problem even if the address of the area in which various kinds of identification information (company name, manufacturing date, model name, etc.) are stored is after the address of the internal RAM. In addition, although there is no problem if the address that is an unused area is changed, it is preferable to provide an unused area between the first data area and the second control area. That is, in the case of the memory map configuration as shown in FIG. 7, the program code that exists in the first control area and is accessed from the CPUC 100, and the program code that exists in the second control area and is accessed from the CPUC 100 are: Since they are arranged apart from each other on the memory map (with discontinuous addresses) and an unused area is sandwiched between them, the location of both program codes on the program source code or dump list can be viewed visually. It can be clearly separated (the same can be said when an unused area is sandwiched between them).

  Here, the ROM mounted on the main control board M may be configured not to provide an unused area (an unfilled area) in order to prevent a program or the like modified by an illegal act from being written. It is preferable (for example, all unused areas are filled with zeros, and used areas are filled in young addresses and written). In addition, in order to prevent the first control area and the first data area from referring to data that is not normally referred to due to noise or fraudulent behavior, unused data (for example, in a gaming machine with different specifications) It is preferable not to provide data to be used or data used only for testing at the development stage. In addition, the first control area, the first data area, the second control area, the second data area, the first work area, and the second work area are arranged in a young address and used in the area (in the area). (For example, “0010H” to “0050H” in the first control area in the range of “0000H” to “0FA7H” are not used as unused areas). It is preferable to do. In this example, all the bits in the unused area are “0”, and any bit other than the unused area is “1” (not “0”). ing).

  Next, FIGS. 8 to 31 are flowcharts showing a flow of general processing performed by the main control board M in the present embodiment. First, in the flowchart showing the flow of these processes, when the CPUC 100 executes a process based on the program code and program data arranged in the first ROM area, or the processing result is stored in a register (register register) in the CPUC100. (Processing in the first ROM / RAM area) when the processing result is stored (updated) in the area) or the first RAM area, or the processing result is referred to by the CPUC 100 based on the program code arranged in the first ROM area. As indicated by a dotted line, it is described that the CPU C 100 executes the process “based on data in the first ROM / RAM area”. Further, in the flowchart showing the flow of these processes, when the CPUC 100 executes a process based on the program code and program data arranged in the second ROM area, or the process result is stored in a register (register register) in the CPUC100. (Processing in the second ROM / RAM area) when the processing result is stored (updated) in the area) or the second RAM area, or the processing result is referred to by the CPUC 100 based on the program code arranged in the second ROM area. As indicated by a dotted line, it is described that the CPU C 100 executes the process “based on data in the second ROM / RAM area”.

  The flowchart is mainly composed of processing steps (illustrated by rectangles), judgments (illustrated by diamonds), flow lines (arrows), terminals indicating start / end / return, etc. (illustrated by rounded rectangles). ing. Moreover, when the details are illustrated in another flowchart among the processing steps, those referring to the other flowchart are illustrated as a subroutine (illustrated by a rectangle in which the left and right lines are double lines). . Here, in the development stage of gaming machines, gaming machines with different specifications are also developed at the same time, but in this example, a subroutine ( (Subroutines that are not normally used) are not left behind, and processing related to unused subroutines that are not normally executed due to noise or fraudulent actions is prevented from being executed.

  And it is a case not following these movements. For example, when the second RAM area is updated or referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area, or conversely, the second ROM area When the first RAM area is updated or referred to in the processing of the CPUC 100 based on the program code arranged in (1), the update / reference destination is specified (or these) Even if it follows the movement, it may be noted as necessary for clarity). It should be noted that, when the processing movements in the embodiment described below are conceptually summarized, the following cases are obtained.

  <Operation 1> The program data arranged in the first ROM area (particularly the first data area) is processed by the CPUC 100 based on the program code arranged in the first ROM area (particularly the first control area). It is read or arranged in the second ROM area (particularly the second data area) by the processing of the CPUC 100 based on the program code arranged in the second ROM area (particularly the second control area). Program data is read out. However, depending on the processing of the CPUC 100 based on the program code arranged in the first ROM area (particularly, the first control area), the program data arranged in the second ROM area (particularly the second data area) is read. Depending on the processing of the CPUC 100 based on the program code arranged in the second ROM area (particularly the second control area), the program arranged in the first ROM area (particularly the first data area) Data is not read out.

  <Operation 2> The first RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and program data arranged in the first ROM area. Further, the second RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and program data arranged in the second ROM area.

  <Operation 3> The processing of the CPUC 100 based on the program code arranged in the second ROM area can be executed by a calling instruction (for example, a CALL instruction called mnemonic) in the program code arranged in the first ROM area. The CPUC 100 based on the program code arranged in the first ROM area cannot be executed by a calling instruction (for example, a CALL instruction called mnemonic) in the program code arranged in the second ROM area. That is, the program code arranged in the first ROM area and the program code arranged in the second ROM area are in a master-slave relationship, and a call instruction in the program code arranged in the main first ROM area. Only then is there a state in which the processing of the CPUC 100 based on the program code arranged in the secondary second ROM area can be executed.

  <Operation 4> When there is a call instruction in the program code arranged in the main first ROM area and the processing of the CPUC 100 based on the program code arranged in the subordinate second ROM area is executed, When the CPUC 100 executes the process based on the program code arranged in the slave second ROM area, information stored at the time when the call instruction is issued (for example, information in the register area) is referred to. Alternatively, after the processing of the CPUC 100 based on the program code arranged in the subordinate second ROM area is executed, the processing returns to the processing of the CPUC100 based on the program code arranged in the main first ROM area. When executing the processing of the CPUC 100 based on the program code arranged in the main first ROM area, information stored at the time of return (for example, information in the register area) is referred to.

  <Operation 5> In the above <Operation 4>, when the information in the register area is not referred to, <Operation 5-1> Processing result of the CPUC 100 based on the program code arranged in the main first ROM area Is stored in the first RAM area, and the processing result stored in the first RAM area can be referred to and updated when the CPUC 100 executes the process based on the program code arranged in the secondary ROM area. (Refer to the updated first RAM area when the process of the CPUC 100 is restored based on the program code arranged in the main first ROM area) <Operation 5-2> Main first ROM area The processing result of the CPUC 100 based on the program code arranged in is stored in the first RAM area, and the slave When executing the processing of the CPUC 100 based on the program code arranged in the second ROM area, the processing result stored in the first RAM area can be referred to and is arranged in the subordinate second ROM area. The processing result of the CPUC 100 based on the program code is stored in the second RAM area, and is stored in the second RAM area when the processing of the CPUC 100 based on the program code arranged in the main first ROM area is restored. It is possible to refer to the processing results that have been made available.

  Based on the above assumption (premise for explanation), a general flow of processing performed by the main control board M will be explained. <Operation 1> to <Operation 3> described above > Is an indispensable premise, while <Action 4> and <Action 5> are determined by the implementation method of how the processing results in the CPUC 100 are inherited between program codes in a master-slave relationship. Since it is a premise that can be selected, even if only one of <Operation 4> and <Operation 5> is exemplified in the following processing flow, it can be replaced with the other. It supplements beforehand.

  First, FIG. 8 is a flowchart showing a flow of processing executed for the first time by the CPUC 100 of the main control board M after turning on the power of the rotating game machine P (or at the time of system reset or user reset). . In this case, generally, the program code is executed in order from the program code arranged at the address (that is, the first control area) of 0000H in the built-in ROMC 110. Note that, depending on the configuration of the main control chip C on the main control board M, the above-described security check is executed after turning on the power of the spinning machine P (or at the time of system reset or user reset). In some cases, it can be assumed that the program code for executing the security check is configured to be executed first, but even in such a configuration, the program code is arranged in the first control area shown in the present embodiment. (In addition, even if the initial address of the built-in ROMC 110 is not 0000H, it does not change to the overall configuration of the above-described memory map = each address.) Only deviate as appropriate). In the present embodiment, backup power is supplied to the built-in RAMC 120 so that data stored in the built-in RAMC 120 is retained even when the power is turned off.

<Processing in the first ROM / RAM area>
First, after turning on the power of the revolving game machine P in step 1000, the CPUC 100 sets a timer interrupt based on the data in the first ROM / RAM area in step 1002 (here, the type of timer interrupt) In the subsequent processing, when a timer interrupt is started, a flowchart related to timer interrupt processing described later is periodically executed). Next, in step 1004, the CPUC 100 executes the function setting of the main control chip C based on the data in the first ROM / RAM area. Next, in step 1006, the CPUC 100 calls a power-off recovery process for the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 1008, the CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the checksum area based on the data in the first ROM / RAM area. Next, in step 1010, the CPUC 100 checks the first RAM and the second RAM based on the data in the first ROM / RAM area (for example, the calculated checksum and the checksum data held in the checksum area). Based on the above, it is checked whether or not the data stored in the built-in RAMC 120 is correctly held by the power-off / power-off recovery), and the power-off recovery data is generated (the result of the check and the processing at the time of power-off in Step 1800 And is stored in the second RAM area). Next, in Step 1012, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to Step 1014.

<Processing in the first ROM / RAM area>
Next, in step 1014, the CPUC 100 confirms the switch states of the door switch D80, the setting door switch M10, and the setting key switch M20 based on the data in the first ROM / RAM area. Next, in step 1016, the CPUC 100 refers to the data in the first ROM / RAM area and determines whether any of the door switch D80, the setting door switch M10, and the setting key switch M20 is OFF. In the case of Yes in Step 1016, in Step 1018, the CPUC 100 calls the non-setting change initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to Step 1022. On the other hand, in the case of No in step 1016, in step 1020, the CPUC 100 calls the setting change initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1030.

<Processing in the second ROM / RAM area>
Next, in step 1022, the CPUC 100 turns on / off the power-off processing completion flag in the first RAM (turned on in step 1904) and the checksum state of all RAMs (based on the data in the second ROM / RAM area). With reference to the check result in step 1010), it is determined whether or not the power-off recovery data in the second RAM is normal. In the case of Yes in step 1022, in step 1026, the CPUC 100 sets a backup error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area. On the other hand, in the case of No in step 1022, in step 1028, based on the data in the second ROM / RAM area, the CPUC 100 sets the initialization range of the first RAM and the second RAM to the unused RAM range (shown in the box outside the figure). The unused area in the 1RAM area and the unused area in the second RAM area are determined and set (for example, set in the register area), and the process proceeds to step 1036.

  On the other hand, after the processing in step 1020, in step 1030, based on the data in the second ROM / RAM area, the CPUC 100 turns on / off the power-off processing completion flag in the first RAM (turned on in step 1904) and all With reference to the checksum state of the RAM (check result in step 1010), it is determined whether or not the power-off recovery data in the second RAM is normal. In the case of Yes in step 1030, in step 1032 the CPUC 100 determines and sets the initialization range of the first RAM and the second RAM to all ranges except the set value in the RAM based on the data in the second ROM / RAM area. (For example, set in the register area), the process proceeds to step 1036. The set value is stored at the top address of the first RAM area. On the other hand, in the case of No in step 1030, in step 1034, based on the data in the second ROM / RAM area, the CPUC 100 determines and sets the initialization range of the first RAM and the second RAM to all the ranges of the RAM (for example, , Set in the register area), and go to Step 1036.

  Next, in step 1036, the CPUC 100 executes initialization of only the second RAM area within the determined initialization range based on the data in the second ROM / RAM area. Next, in step 1038, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1040.

<Processing in the first ROM / RAM area>
Next, in Step 1040, the CPUC 100 executes initialization of only the first RAM area within the initialization range determined in Step 1028, Step 1032 or Step 1034 based on the data in the first ROM / RAM area. Next, in step 1041, the CPUC 100 determines whether any of the door switch D80, the setting door switch M10, and the setting key switch M20 is OFF based on the data in the first ROM / RAM area. In the case of Yes in Step 1041, in Step 1042, the CPUC 100 calls the setting value check process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to Step 1044. On the other hand, in the case of No in step 1041, in step 1100, the CPUC 100 executes a setting change device control process (also referred to as a setting change process), which will be described later, based on the data in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
Next, in step 1044, the CPUC 100 refers to the first RAM area based on the data in the second ROM / RAM area, and the data related to the set value in the first RAM area is within the normal range (in this example, 1 to 1). 6) It is determined whether or not. In the case of Yes in Step 1044, in Step 1046, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to Step 1050. On the other hand, in the case of No in step 1044, in step 1048, the CPUC 100 sets a setting value error display (for example, displayed on the payout number display device D190) based on the data in the second ROM / RAM area. (For example, set in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1050, the CPUC 100 restores the stack pointer based on the data related to the stack pointer saved in the power-off process (step 1902) based on the data in the first ROM / RAM area. Next, in step 1052, the CPUC 100 reads the input port based on the data in the first ROM / RAM area. Next, in step 1054, the CPUC 100 starts the timer interrupt set in step 1002 based on the data in the first ROM / RAM area. Next, in step 1056, the CPUC 100 turns off the power-off processing completion flag in the flag area in the first ROM / RAM area, and returns to the processing at the time of power-off according to the returned stack pointer.

  Although not shown, it is preferable that the initial value (value at the start of processing) of the temporary storage area (RAM area or the like) mounted on the main control board M is not a value at which a special game is executed. (In order to prevent a special game from being erroneously executed when a process for determining whether or not to execute a special game is executed due to noise or fraud immediately after the program processing is started). Although not shown, when a random number such as a winning random number is stored in the RAM area of the main control board M, a dedicated storage area is secured, and the byte storing information related to the random number is stored in the byte. It is preferable to configure to store only the information related to the random number (not to store other information such as various timer values) (when operating other data stored in the same 1 byte, due to noise etc. To prevent rewriting of information related to random numbers).

<Processing in the first ROM / RAM area>
Next, FIG. 9 is a flowchart of the setting change device control process according to the subroutine of step 1100 in FIG. First, in step 1102, the CPUC 100 sets a stack pointer based on the data in the first ROM / RAM area (initialized with the start address of the process). Next, in step 1118, the CPUC 100 starts a timer interrupt based on the data in the first ROM / RAM area. Next, in step 1120, the CPUC 100 refers to the data in the first ROM / RAM area, and determines whether or not the set value in the first RAM area is within the normal range (1 to 6 in this example). . In the case of Yes in Step 1120, in Step 1122, the CPUC 100 sets a predetermined value (for example, 1 = value that is most disadvantageous for the player) as a setting value based on the data in the first ROM / RAM area, and Step 1124. Migrate to On the other hand, also in the case of No in step 1120, the process proceeds to step 1124. Next, in step 1124, based on the data in the first ROM / RAM area, the CPUC 100 displays on the error display LED (not shown) that the setting changing device is operating, and sets the setting display LED (not shown). The value is displayed and the process proceeds to step 1126.

  Next, in step 1126, the CPUC 100 determines whether or not the setting / reset button M30 has been switched from OFF to ON based on the data in the first ROM / RAM area. In the case of Yes in step 1126, in step 1128, the CPUC 100 adds 1 to the current set value based on the data in the first ROM / RAM area (if the added set value exceeds 6, the setting is made. The value becomes 1), and the process proceeds to Step 1130. In the case of No in step 1126, the process proceeds to step 1130. Next, in step 1130, the CPUC 100 determines whether or not the start lever D50 has been switched from OFF to ON based on the data in the first ROM / RAM area. In the case of Yes in step 1130, in step 1132, the CPUC 100 determines whether or not the setting key switch M20 has been switched from on to off based on the data in the first ROM / RAM area. If No in step 1132, the process in step 1132 is looped. On the other hand, in the case of Yes in step 1132, in step 1134, based on the data in the first ROM / RAM area, the CPUC 100 displays on the error display LED (not shown) that the operation of the setting change device has ended, and displays the setting display. The display of the set value of the LED (not shown) is erased, and the process proceeds to a game progress control process in step 1200. In the case of No in step 1130, the process proceeds to step 1126.

<Processing in the first ROM / RAM area>
Next, FIG. 10 is a flowchart of the game progress control process (first sheet) according to the subroutine of step 1200 in FIG. First, in step 1202, the CPUC 100 sets a stack pointer based on the data in the first ROM / RAM area (initialized with the start address of the process). Next, in step 1204, the CPUC 100 sets data in the first RAM area necessary for the game (for example, an upper limit number of bets, an effective line for winning, etc.) based on the data in the first ROM / RAM area. Next, in step 1206, the CPUC 100 sets a gaming state in the game (for example, during a normal game, during a big hit game, during a replay probability variation game, during an AT game, etc.) based on the data in the first ROM / RAM area. To do. Next, in step 1208, the CPUC 100 determines whether or not the medal payout device H is full of game medals based on the data in the first ROM / RAM area. Specifically, a subtank (not shown) for storing medals overflowing from the medal payout device H is provided, and a determination is made based on current conduction / non-conduction by a plurality of full detection sensors provided in the subtank (via the medal). If the current is conducted, it is determined to be full). If Yes in step 1208, the process proceeds to step 1218.

  On the other hand, in the case of No in step 1208, in step 1210, the CPUC 100 turns on the medal full error flag based on the data in the first ROM / RAM area (for example, turns on the medal full error flag area in the first RAM area). Update with a value equivalent to Next, in step 1212, the CPUC 100 displays an error number corresponding to the medal full error with a 7-segment LED (for example, a storage display LED or an acquired number LED) based on the data in the first ROM / RAM area. Next, in step 1214, the CPUC 100 refers to the data in the first ROM / RAM area to determine whether or not the medal full error has been canceled (for example, the current through the sub tank is non-conductive and the setting / reset button M30 is Whether or not it has been pressed). In the case of Yes in step 1214, in step 1216, the CPUC 100 turns off the medal full error flag based on the data in the first ROM / RAM area (for example, this corresponds to turning off the medal full error flag area in the first RAM area). Update with the value), and go to Step 1218. On the other hand, in the case of No in step 1214, the process proceeds to step 1212. Next, in step 1218, the CPUC 100 permits the medal insertion acceptance based on the data in the first ROM / RAM area (the insertion operation is automatically executed in the next game of the replay). The process proceeds to (the process of step 1220). Here, in Step 1218, the blocker D100 is turned on (process formed by the medal flow path). Specifically, when a re-game player is established in the previous game, the blocker D100 is turned on on the condition that the current storage number (credit) is less than a predetermined value (50 in this example). Run. In other words, when the current storage number (credit) is a predetermined value, the ON process of the blocker D100 is not executed. On the other hand, when the re-game combination is not established in the previous game, the blocker D100 is turned on uniformly. With this configuration, even when a re-game is established, if the number of stored credits (credits) has not reached a predetermined value, a game medal can be inserted. Replays that are difficult to understand as replays when you are staying in an RT state with a high game probability (replays that appear to be small roles: bell-bell-bell on the invalid line, or cherry on the left reel stops The player can play the game with a good rhythm (without a sense of incongruity) even when the symbol combination) is stopped.

<Processing in the first ROM / RAM area>
Next, FIG. 11 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in FIG. First, in step 1220, the CPUC 100 determines whether or not a game medal is bet and no credit exists based on the data in the first ROM / RAM area. In the case of Yes in step 1220, in step 1221 the CPUC 100 satisfies the setting display conditions based on the data in the first ROM / RAM area (for example, the door switch D80, the setting door switch M10, and the setting key switch M20 are It is determined whether or not the condition is satisfied if all are turned on. In the case of Yes in step 1221, in step 1222, the CPUC 100 sets the setting display LED (not shown, but the payout number display device D190, the credit number display device D200, the insertion number display light D210 based on the data in the first ROM / RAM area. The setting value may be displayed on the screen, and the process proceeds to step 1221. In the case of No in Step 1220 or Step 1221, in Step 1224, the CPUC 100 executes management related to game medal insertion and settlement based on the data in the first ROM / RAM area. Next, in step 1225, the CPUC 100 confirms the number of game medals that can be accepted based on the data in the first ROM / RAM area. Next, in step 1226, the CPUC 100 determines whether or not the blocker D100 is on based on the data in the first ROM / RAM area. In the case of Yes in step 1226, in step 1227, the CPUC 100 determines whether or not the first input sensor D20s or the second input sensor D30s is on based on the data in the first ROM / RAM area (first input). When the sensor D20s or the second insertion sensor D30s is turned on, it is determined that one game medal has been received). In the case of Yes in step 1227, in step 1228, the CPUC 100 calls the medal insertion error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1400.

<Processing in the second ROM / RAM area>
Next, in step 1400, the CPUC 100 executes medal insertion error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1229, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1230.

<Processing in the first ROM / RAM area>
Next, in step 1230, the CPUC 100 determines whether or not the first input sensor D20s and the second input sensor D30s are off based on the data in the first ROM / RAM area (the first input sensor D20s or the first input sensor D20s). When the first insertion sensor D20s and the second insertion sensor D30s are turned off after the second insertion sensor D30s is turned on, the received one game medal passes through the first insertion sensor D20s and the second insertion sensor D30s. judge). In the case of Yes in step 1230, in step 1231, the CPUC 100 determines that one normal game medal has been inserted based on the data in the first ROM / RAM area. Although not shown, after step 1231, the CPUC 100 determines that the credit is the upper limit (50 in this example) and the maximum bet (3 in this example) based on the data in the first ROM / RAM area. ) Is determined, and if the determination is Yes, the blocker D100 is controlled to be off (a state where no medal flow path is formed). In the case of No in step 1230, the process proceeds to step 1228, and in the case of No in step 1226 or step 1227, the process proceeds to step 1232.

  Next, in Step 1232, the CPUC 100 determines whether or not the settlement button D60 has been operated based on the data in the first ROM / RAM area. In the case of Yes in Step 1232, in Step 1233, the CPUC 100 determines whether or not there is a remaining number of credits or a betting game medal based on the data in the first ROM / RAM area. In the case of Yes in step 1233, in step 1234, the CPUC 100 turns on when a hopper drive flag (a flag in the first RAM area and the hopper motor H80 is driven) based on the data in the first ROM / RAM area. (Flag) is turned on, and one game medal is paid out. Next, in step 1236, the CPUC 100 refers to the data in the first ROM / RAM area and determines whether or not the first payout sensor H10s or the second payout sensor H20s is ON (the first payout sensor H10s or When the second payout sensor H20s is turned on, it is determined that a payout operation for one game medal is being performed). In the case of Yes in step 1236, in step 1238, the CPUC 100 calls a medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1450. Here, although not explicitly shown in the flowchart, only the remaining number of credits is to be settled when the previous game was a re-game player.

<Processing in the second ROM / RAM area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1240, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1247.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 1236, in step 1241, the CPUC 100 has passed a predetermined time (for example, 5 seconds) after driving the hopper (after the processing timing in step 1234) based on the data in the first ROM / RAM area. It is determined whether or not. Specifically, whether or not a situation in which it is determined that a medal has not been paid out has continued for a predetermined period of time despite transmission of a hopper drive signal to the hopper motor H80 (the hopper motor H80 is rotating). Determine whether or not. In the case of Yes in step 1241, in step 1242, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM / RAM area (for example, equivalent to turning on the medal empty error flag area in the first RAM area). Update with the value you want). Next, in step 1244, the CPUC 100 executes a medal empty error display based on the data in the first ROM / RAM area. Next, in step 1245, the CPUC 100 determines whether or not the medal empty error has been canceled based on the data in the first ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). If YES in step 1245, in step 1246, the CPUC 100 turns off the medal empty error flag in the flag area in the first ROM / RAM area (for example, turns off the medal empty error flag area in the first RAM area). Update to the corresponding value), and the process proceeds to step 1247. On the other hand, if No at step 1245, the process proceeds to step 1244.

<Processing in the first ROM / RAM area>
Next, in step 1247, the CPUC 100 determines whether or not the first payout sensor H10s and the second payout sensor H20s are off based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the first payout sensor H10s and the second payout sensor H20s are turned off after the two payout sensors H20s are turned on, it is determined that the payout operation of one game medal on which the payout operation has been performed is completed. In the case of Yes in step 1247, in step 1248, the CPUC 100 turns off the hopper driving flag based on the data in the first ROM / RAM area, and proceeds to step 1233. If step 1241 or step 1247 is No, the process proceeds to step 1236.

  On the other hand, in the case of No in step 1232 or step 1233, in step 1249, the CPUC 100 calls the input / exit error detection processing in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1500.

<Processing in the second ROM / RAM area>
Next, in step 1500, the CPUC 100 executes a loading / dispensing error detection process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1250, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1251.

<Processing in the first ROM / RAM area>
Next, in step 1251, the CPUC 100 determines that the start lever D50 is valid based on the data in the first ROM / RAM area (for example, a prescribed number of game medals for starting the game are inserted), and Then, it is determined whether or not the start lever D50 has been operated. In the case of Yes in step 1251, in step 1252, the CPUC 100 executes a process of obtaining a random number and turning off the blocker D100 based on data in the first ROM / RAM area, and then performing a setting value check process for the second ROM area. Call and go to step 1253.

<Processing in the second ROM / RAM area>
Next, in step 1253, the CPUC 100 determines whether or not the set value in the first RAM area is within the normal range (1 to 6 in this example) based on the data in the second ROM / RAM area. In the case of Yes in step 1253, in step 1254, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to the next process (process in step 1257). On the other hand, in the case of No in step 1253, in step 1256, the CPUC 100 sets a setting value error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 12 is a flowchart of the game progress control process (third sheet) according to the subroutine of step 1200 in FIG. First, in step 1257, the CPUC 100 starts an internal lottery (lottery for determining a winning combination in the game) based on the data in the first ROM / RAM area. Next, in step 1258, the CPUC 100 starts rotation of all reels (reel M50) based on the data in the first ROM / RAM area, and proceeds to step 1260. Next, in step 1260, the CPUC 100 makes a pull-in point creation request (request to determine the stop positions of the rotating left reel M51, middle reel M52, and right reel M53 based on the data in the first ROM / RAM area. It is determined whether or not there has been a request as appropriate depending on the stop order and the stop position of the other reels. In the case of Yes in Step 1260, in Step 1261, the CPUC 100 creates a pull-in point based on the data in the first ROM / RAM area, and proceeds to Step 1262. On the other hand, also in the case of No in step 1260, the process proceeds to step 1262. Next, in step 1262, the CPUC 100 executes a reel stop acceptability check based on the data in the first ROM / RAM area. Next, in step 1263, the CPUC 100 determines whether or not any stop button (left stop button D41, middle stop button D42, right stop button D43) has been operated based on the data in the first ROM / RAM area. To do. In the case of Yes in step 1263, in step 1264, the CPUC 100, based on the data in the first ROM / RAM area, corresponds to the operated stop button (for example, the left stop button D41 corresponds to the left reel M51). Is determined, and the process proceeds to step 1265. On the other hand, also in the case of No in step 1263, the process proceeds to step 1265. Next, in step 1265, the CPUC 100 executes an all reel stop check process based on the data in the first ROM / RAM area. Next, in step 1266, the CPUC 100 determines whether or not all the reels (the left reel M51, the middle reel M52, and the right reel M53) are stopped based on the data in the first ROM / RAM area. In the case of Yes in step 1266, in step 1267, the CPUC 100 calls the display determination check process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1268. If No in step 1266, the process proceeds to step 1260.

<Processing in the second ROM / RAM area>
Next, in step 1268, the CPUC 100 compares the symbol stop position data in the first RAM with the internal established combination stop position data based on the data in the second ROM / RAM area. Next, in step 1269, the CPUC 100 refers to the data in the second ROM / RAM area and determines whether or not the displayed symbol combination is normal (the winning combination determined by the internal lottery is determined). Is determined to be abnormal). In the case of Yes in step 1269, in step 1500, the CPUC 100 executes a loading / dispensing error detection process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1270, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1274. On the other hand, in the case of No in step 1269, in step 1272, the CPUC 100 sets a display determination error display based on the data in the second ROM / RAM area (for example, in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1274, the CPUC 100 executes a game medal payout process by winning based on the data in the first ROM / RAM area. Next, in step 1275, the CPUC 100 determines whether or not there has been a prize for paying out a game medal based on the data in the first ROM / RAM area {the game medal acquired by winning the prize is the maximum number of credits (this example) Then, when 50) is exceeded, game medals are paid out}. In the case of Yes in step 1275, in step 1276, based on the data in the first ROM / RAM area, the CPUC 100 turns on when the hopper driving flag (the flag in the first RAM area and the hopper motor H80 is being driven). (Flag) is turned on, and one game medal is paid out. Next, in step 1277, the CPUC 100 determines whether or not the first payout sensor H10s or the second payout sensor H20s is on based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the two payout sensor H20s is turned on, it is determined that a payout operation for one game medal is being performed). In the case of Yes in step 1277, in step 1278, the CPUC 100 calls a medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1450.

<Processing in the second ROM / RAM area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1284, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1286.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 1277, in step 1279, based on the data in the first ROM / RAM area, the CPUC 100 has passed a predetermined time (for example, 5 seconds) after driving the hopper (after the processing timing of step 1276). It is determined whether or not. In the case of Yes in step 1279, in step 1280, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM / RAM area (for example, equivalent to turning on the medal empty error flag area in the first RAM area). Update with the value you want). Next, in step 1281, the CPUC 100 executes a medal empty error display with a 7-segment LED based on the data in the first ROM / RAM area. Next, in step 1282, the CPUC 100 determines whether or not the medal empty error has been canceled based on the data in the first ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1282, in step 1283, the CPUC 100 turns off the medal empty error flag based on the data in the first ROM / RAM area (for example, this corresponds to turning off the medal empty error flag area in the first RAM area). Update with the value) and go to Step 1286. On the other hand, if No in step 1282, the process proceeds to step 1281.

<Processing in the first ROM / RAM area>
Next, in step 1286, the CPUC 100 determines whether or not the first payout sensor H10s and the second payout sensor H20s are off based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the first payout sensor H10s and the second payout sensor H20s are turned off after the two payout sensors H20s are turned on, it is determined that the payout operation of one game medal on which the payout operation has been performed is completed. In the case of Yes in Step 1286, in Step 1288, the CPUC 100 turns off the hopper driving flag based on the data in the first ROM / RAM area, and proceeds to Step 1290. If No in step 1279 or step 1286, the process proceeds to step 1277. Next, in step 1290, the CPUC 100 determines whether or not the payout corresponding to the winning (the winning that becomes Yes in step 1275) is completed based on the data in the first ROM / RAM area. In the case of Yes in step 1290, in step 1292, the CPUC 100 executes game end processing (for example, clearing the number of bets, game state transition processing, etc.) based on the data in the first ROM / RAM area, and the next processing The process proceeds to (Step 1202). If No in step 1286, the process proceeds to step 1277. If No in step 1275, the process proceeds to step 1292.

<Processing in the first ROM / RAM area>
Next, FIG. 13 is a flowchart of non-recoverable error processing relating to the subroutine of step 1300 in FIG. 8 (and called in other flowcharts). First, in step 1302, the CPUC 100 prohibits an interrupt based on the data in the first ROM / RAM area (hereinafter, a flowchart relating to a timer interrupt process described later is not executed). Next, in step 1304, the CPUC 100 sets the output port address and the number of output ports based on the data in the first ROM / RAM area. Next, in step 1306, the CPUC 100 turns off the output port (0 to 6 in this example, display output to various LEDs and drive output to various motors) based on the data in the first ROM / RAM area. To. Next, in step 1308, the CPUC 100 sets the next port output address based on the data in the first ROM / RAM area (by repeating this, the display output to various LEDs and the drive output to various motors are sequentially stopped. ) Next, in step 1310, the CPUC 100 determines whether or not the output to each output port is completed based on the data in the first ROM / RAM area. In the case of Yes in step 1310, in step 1312, the CPUC 100 executes the set error display based on the data in the first ROM / RAM area (some error occurs when executing this process). If the power supply voltage is lowered, the reset signal is input and the process ends. (That is, since an infinite loop is entered, any operation that prompts a return is not accepted). In the case of No in step 1310, the process proceeds to step 1306. The processing from step 1306 to step 1310 is processing for clearing the output to the LED / motor (however, since the external output signal is not cleared, information about the error, game progress status at the time of the error, etc. are displayed on the hall computer side. It is possible to output to

<Processing in the second ROM / RAM area>
Next, FIG. 14 is a flowchart of medal insertion error detection processing according to the subroutine of step 1400 in FIG. First, in step 1402, the CPUC 100 sets the inserted medal backflow error flag (a flag turned on in step 1706, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1402, in step 1404, the CPUC 100 determines that the inserted medal backflow error (an error caused by the backflow of the inserted game medal is based on the data in the second ROM / RAM area. D20s off and the second throwing sensor D30s on → an error occurs when the first throwing sensor D20s is on and the second throwing sensor D30s is on). Next, the CPUC 100 determines whether or not the inserted medal error backflow error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1406, in step 1408, the CPUC 100 turns off the inserted medal backflow error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

  On the other hand, in the case of No in step 1402, in step 1410, based on the data in the second ROM / RAM area, the CPUC 100 is an inserted medal retention error flag (turned on in step 1710. In this embodiment, It is determined whether the flag in the 2RAM area is ON. In the case of Yes in step 1410, in step 1412, the CPUC 100 determines that the inserted medal retention error (the error caused by the inserted game medal remaining, based on the data in the second ROM / RAM area, for example, the first insertion sensor D20s on and the second input sensor D30s on is an error when the state continues for a predetermined time). Next, in step 1414, the CPUC 100 determines whether or not the inserted medal staying error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1414, in step 1416, the CPUC 100 turns off the inserted medal staying error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

  On the other hand, in the case of No in step 1410, in step 1418, the CPUC 100 is based on the data in the second ROM / RAM area, and is an insertion number error flag (a flag that is turned on in step 1716. In this embodiment, the second RAM It is determined whether or not the flag in the area is on. In the case of Yes in step 1418, in step 1420, the CPUC 100, based on the data in the second ROM / RAM area, causes an inserted number error (because the number of inserted game medals and the number of game medals successfully passed do not match). (For example, an error occurs when the number of game medals detected by the insertion acceptance sensor D10s and the number of game medals detected by the second insertion sensor D30s do not match or are outside a predetermined allowable range.) Execute the display. Next, in step 1422, the CPUC 100 determines whether or not the insertion number error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1422, in step 1424, the CPUC 100 turns off the insertion number error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

<Processing in the second ROM / RAM area>
Next, FIG. 15 is a flowchart of medal payout error detection processing according to the subroutine of step 1450 in FIGS. 11 and 12. First, in step 1452, the CPUC 100 sets a payout medal retention error flag (a flag turned on in step 1756, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1452, in step 1456, the CPUC 100 is based on the data in the second ROM / RAM area, and is a payout medal retention error (an error caused by the payout game medal remaining. Display is performed when the sensor H10s is on and the second payout sensor H20s is on for a predetermined time. Next, in step 1458, the CPUC 100 determines whether or not the payout medal retention error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1458, in step 1460, the CPUC 100 turns off the payout medal retention error flag based on the data in the second ROM / RAM area, and proceeds to the next process (the process of step 1240 or step 1284).

<Processing in the second ROM / RAM area>
Next, FIG. 16 is a flowchart of the input / withdrawal error detection process according to the subroutine of step 1500 in FIGS. 11 and 12. First, in step 1502, the CPUC 100 turns on an abnormal insertion error flag (a flag that is turned on in step 1806, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. It is determined whether or not. In the case of Yes in step 1502, in step 1504, the CPUC 100 detects an abnormal insertion error (error due to detection of insertion of a game medal at a timing when a game medal should not be inserted) based on the data in the second ROM / RAM area. Execute the display. Next, in step 1506, the CPUC 100 determines whether or not the abnormal insertion error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1506, in step 1508, the CPUC 100 turns off the abnormal insertion error flag based on the data in the second ROM / RAM area, and proceeds to step 1510. In the case of No in step 1502, the process proceeds to step 1510.

  Next, in step 1510, the CPUC 100 sets an abnormal payout error flag (a flag that is turned on in step 1816, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1510, in step 1514, the CPUC 100 detects an abnormal payout error (error due to detection of game medal payout at the timing when the game medal should not be paid out) based on the data in the second ROM / RAM area. ) Execute the display. Next, in step 1516, the CPUC 100 determines whether or not the abnormal payout error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1516, in step 1518, the CPUC 100 turns off the abnormal payout error flag based on the data in the second ROM / RAM area, and proceeds to the next process (the process of step 1250 or step 1270). Even in the case of No in step 1510, the process proceeds to the next process (the process in step 1250 or step 1270).

  Next, FIG. 17 is a flowchart of processing at the time of timer interruption according to the subroutine of step 1600 in the present embodiment. The processing of the subroutine is started when a timer interrupt is started in the processing of step 1054 or step 1118, and thereafter, a predetermined time (in this example, T is set, but a time of about 2 ms is set, for example) To be periodically executed.

<Processing in the first ROM / RAM area>
First, in step 1602, the CPUC 100 performs processing at the start of an interrupt (for example, saving of data held in a register in the CPUC100, input port check of a power-off detection signal, etc.) based on data in the first ROM / RAM area. ). Next, in step 1604, the CPUC 100 determines whether or not a power-off is currently detected (in the current interrupt process) based on the data in the first ROM / RAM area. In the case of No in step 1604, in step 1900, the CPUC 100 executes a power-off process, which will be described later, based on the data in the first ROM / RAM area. On the other hand, in the case of Yes in step 1604, in step 1606, the CPUC 100 starts timer measurement (update processing of various timers managed by software) based on the data in the first ROM / RAM area. Next, in step 1608, the CPUC 100 generates input port data based on the data in the first ROM / RAM area, and stores the data (updates the storage area of each input port data in the first RAM area). ). Here, the input port data includes the settlement button D60, the start lever D50, the stop button D40, the door switch D80, the setting door switch M10, the setting key switch M20, the setting / reset button M30, the power-off detection signal, and the input acceptance sensor D10s. , Information relating to the detection of the first input sensor D20s, the second input sensor D30s, the first payout sensor H10s, the second payout sensor H20s, etc. (that is, whether or not these operation members are operated and the sensor detection state is Sampled at interrupt interval T).

  Next, in step 1610, the CPUC 100 refers to the input port data in the first RAM area based on the data in the first ROM / RAM area, and determines the door switch flag and the setting door according to the sampling result of each input port data. Switch on / off of the switch flag and setting key switch flag (for example, when the switch state of the door switch D80 is continuously on over a plurality of sampling times, the door switch flag is turned on to reduce noise. It is also possible to detect that the front door DU is in an open state without being affected by the above). Next, in step 1612, the CPUC 100 performs rotation drive control processing (reel M50 drive control) for all reels (left reel M51, middle reel M52, right reel M53) based on data in the first ROM / RAM area. This processing is executed. Next, in step 1614, the CPUC 100 outputs the output data to the output port based on the data in the first ROM / RAM area. Here, the output data is data for driving the reel M50, the blocker D100, and the like. In step 1616, the CPUC 100 calls an error check process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1700.

<Processing in the second ROM / RAM area>
Next, in step 1700, the CPUC 100 executes a medal insertion check process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1750, the CPUC 100 executes a medal payout check, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1800, the CPUC 100 executes an input / withdrawal error check process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1618, the CPUC 100 turns off all error flags based on the data in the second ROM / RAM area (inserted medal backflow flag, inserted number error flag, medal retention error flag, inserted abnormal error flag, payout error). It is determined whether the error flag, the payout medal retention error flag, the door switch flag, and the like are all off (however, in the present embodiment, the door switch flag is within the first RAM area). Since it is stored, it is determined with reference to the first RAM area). In the case of Yes in step 1618, in step 1620, based on the data in the second ROM / RAM area, the CPUC 100 issues an error non-detection command (a command to the sub-side indicating that no error has been detected). Set (for example, set in the register area), and go to Step 1624. On the other hand, in the case of No in step 1618, in step 1622, the CPUC 100 determines an error detection command (a command to the sub side and an error is detected) based on the data in the second ROM / RAM area. Is set (for example, in the register area), and the process proceeds to Step 1624. In step 1622, information related to an error (currently occurring error) corresponding to the error flag that is turned on is transmitted to the sub-side. The error not detected command may be set only when the error is released from the state where the error has occurred (only when it is determined that the flag is turned off). The information setting process may not be executed (S1620 may not be provided). Further, the error detection command may execute the set process only when an error occurs from a state where no error has occurred, or from the state where a first error (for example, a inserted medal retention error) has occurred. The set process may be executed when the type of error has changed, such as a second error (for example, a payout medal retention error). Next, in step 1624, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1626.

<Processing in the first ROM / RAM area>
Next, in step 1626, the CPUC 100 transmits a control command (sub-side command) based on the data in the first ROM / RAM area (for example, when it is set in the register area in step 1620 or step 1622). Will take over the set control command). Next, in step 1628, the CPUC 100 outputs an external signal (a signal for transmitting information from the spinning machine P to an external hall computer or the like) based on the data in the first ROM / RAM area. The information related to the error output by the external signal includes a door opening error, a closing abnormality error, a dispensing abnormality error, a setting door opening error (not shown), a closing reception sensor retention error (not shown), etc. Is output. The door opening error is configured to be an error when the front door DU is opened and the door switch flag is turned on, and the setting door opening error is set and the setting door switch flag is turned on. If the insertion acceptance sensor detects that a game medal has accumulated, an error will be generated. Next, in step 1630, the CPUC 100 outputs LED (7-segment LED lamp, etc.) output data (for example, a predetermined 7-segment LED among a plurality of 7-segment LED units) based on the data in the first ROM / RAM area. The unit is turned on and a predetermined segment of 7 segments is turned on) (so-called dynamic lighting). Next, in Step 1632, the CPUC 100 executes the LED lighting mode (for example, changing the LED lighting color) based on the data in the first ROM / RAM area. Note that step 1632 need not be executed. Next, in step 1634, the CPUC 100 executes a soft random number management process (such as an update process for random values managed by software) based on the data in the first ROM / RAM area. Next, in step 1636, the CPUC 100 calls a random number check process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1638.

<Processing in the second ROM / RAM area>
Next, in step 1638, the CPUC 100 obtains internal information register data based on the data in the second ROM / RAM area (in the internal information register, an area where an abnormality flag bit is set when an abnormality occurs in the random number generation circuit. Exist). Next, in step 1640, the CPUC 100 determines whether the frequency of the random number update clock is normal based on the data in the second ROM / RAM area (whether the abnormal flag bit indicating the frequency abnormality is not set). )). More specifically, the abnormality flag bit is set when the frequency of the random number update clock falls below a predetermined value. In the case of Yes in step 1640, in step 1642, the CPUC 100 determines whether the update state of the internal random number is normal based on the data in the second ROM / RAM area (the abnormal flag bit indicating the update state abnormality is set). Whether or not). In the case of Yes in step 1642, in step 1644, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area. On the other hand, in the case of No in step 1640 or step 1642, in step 1646, the CPUC 100 sets a built-in random number error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). To do). Next, in step 1300, the CPUC 100 executes the above-described non-recoverable error processing based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1648, the CPUC 100 executes interrupt termination processing based on the data in the first ROM / RAM area, and proceeds to the next processing (processing in step 1602).

<Processing in the second ROM / RAM area>
Next, FIG. 18 is a flowchart of medal insertion check processing according to the subroutine of step 1700 in FIG. First, in step 1702, the CPUC 100 determines whether or not the first input sensor D20s is on (detected) based on the data in the second ROM / RAM area (however, the first input sensor). If the input port data itself of D20s is stored in the first RAM area, the determination is made with reference to the first RAM area). In the case of Yes in step 1702, in step 1704, the CPUC 100 detects the backflow of the inserted game medal by the first insertion sensor D20s and the second insertion sensor D30s based on the data in the second ROM / RAM area. (For example, the detection is made when the first input sensor D20s is turned off, the second input sensor D30s is turned on, the first input sensor D20s is turned on, and the second input sensor D30s is turned on. It is determined whether the series data itself is held in the second RAM area). In the case of Yes in step 1704, in step 1706, the CPUC 100 turns on the inserted medal backflow error flag based on the data in the second ROM / RAM area (for example, turns on the inserted medal backflow error flag area in the second RAM area). Update to the corresponding value), and the process proceeds to step 1708. On the other hand, also in the case of No in step 1704, the process proceeds to step 1708.

  Next, in step 1708, the CPUC 100 detects the stay of the inserted medal by the first insertion sensor D20s and the second insertion sensor D30s based on the data in the second ROM / RAM area (for example, the first insertion sensor D20s and the second insertion sensor D30s). It is detected when the input sensor D20s is on for a predetermined time or when the second input sensor D30s is on for a predetermined time, and the detection state data itself is held in the second RAM area. Is determined). If YES in step 1708, in step 1710, the CPUC 100 turns on the inserted medal staying error flag based on the data in the second ROM / RAM area (for example, turns on the inserted medal staying error flag area in the second RAM area). Update to the corresponding value), and the process proceeds to step 1712. On the other hand, also in the case of No in step 1708, the process proceeds to step 1712. Next, in step 1712, the CPUC 100 determines from the number of accepted medals (the number of accepted game medals received) to the number of normally passed games (the number of game medals considered to have been inserted normally) based on the data in the second ROM / RAM area. It is determined whether the value obtained by subtracting the number of sheets is not within a predetermined range (for example, 0 to 2 sheets). In the case of Yes in step 1712, in step 1716, the CPUC 100 turns on the insertion number error flag based on the data in the second ROM / RAM area (for example, corresponds to turning on the insertion number error flag area in the second RAM area). Update with the value) and proceed to the next process (the process of step 1750). Even in the case of No in step 1712, the processing shifts to the next processing (processing in step 1750). It is to be noted that an insertion number error monitoring period of a predetermined time (for example, 5 seconds) is provided, and the value obtained by subtracting the normal passing number from the received medal number during the monitoring period is within a predetermined range (for example, 0 to 2). It may be configured such that an error in the number of inserted sheets occurs when there is no more.

<Processing in the second ROM / RAM area>
Next, FIG. 19 is a flowchart of medal payout check processing according to the subroutine of step 1750 in FIG. First, in step 1752, the CPUC 100 determines whether or not the hopper drive flag is on (detected or not) based on the data in the second ROM / RAM area (however, the hopper drive flag itself is If it is stored in the first RAM area, it is determined by referring to the first RAM area). In the case of Yes in step 1752, in step 1754, the CPUC 100 detects the stay of the paid-out medals based on the data in the second ROM / RAM area (for example, the state where the first payout sensor H10s is on continues for a predetermined time). And when the second payout sensor H20s is on for a predetermined period of time, the detection state data itself is held in the second RAM area). judge. In the case of Yes in step 1754, in step 1756, the CPUC 100 turns on the payout medal retention error flag based on the data in the second ROM / RAM area (for example, turns on the payout medal retention error flag area in the second RAM area). Update with the corresponding value), and proceed to the next process (the process of step 1800). In addition, also when it is No in step 1752 or step 1754, it transfers to the next process (process of step 1800).

<Processing in the second ROM / RAM area>
Next, FIG. 20 is a flowchart of the input / withdrawal error check process according to the subroutine of step 1800 in FIG. First, in step 1802, the CPUC 100 determines whether or not the blocker D100 is off based on the data in the second ROM / RAM area (however, the output port data of the blocker D100 itself is stored in the first RAM area). If it is determined, the determination is made with reference to the first RAM area). In the case of Yes in step 1802, in step 1804, the CPUC 100 detects the abnormality of the insertion sensor based on the data in the second ROM / RAM area (the first insertion sensor D20s or the second insertion sensor D30s should not detect the game medal). It is determined whether there is detection at the timing of In the case of Yes in step 1804, in step 1806, the CPUC 100 turns on the abnormal injection error flag based on the data in the second ROM / RAM area (for example, it corresponds to turning on the abnormal injection error flag area in the second RAM area). Update with the value) and go to Step 1808. Note that if the answer is No in Step 1802 or Step 1804, the process proceeds to Step 1808.

  Next, in step 1808, the CPUC 100 determines whether or not the hopper drive flag is off based on the data in the second ROM / RAM area (however, the hopper drive flag itself is stored in the first RAM area). If so, the determination is made with reference to the first RAM area). In the case of Yes in step 1808, in step 1810, the CPUC 100 detects abnormality of the payout sensor based on the data in the second ROM / RAM area (the first payout sensor H10s or the second payout sensor H20s should not detect the game medal). It is determined whether or not there is detection at the timing. In the case of Yes in step 1810, in step 1812, the CPUC 100 turns on the abnormal payout error flag based on the data in the second ROM / RAM area (for example, it corresponds to turning on the abnormal payout error flag area in the second RAM area). Update with the value) and proceed to the next process (the process of step 1618). Note that if the answer is No in step 1808 or step 181, the process proceeds to the next process (process in step 1618).

<Processing in the first ROM / RAM area>
Next, FIG. 21 is a flowchart of the power-off processing according to the subroutine of step 1900 in FIG. First, in step 1902, the CPUC 100 saves the stack pointer based on the data in the first ROM / RAM area. Next, in step 1904, the CPUC 100 turns on the power-off process completed flag based on the data in the first ROM / RAM area (for example, a value corresponding to turning on the power-off process completed flag area in the first RAM area). Update with). Next, in step 1906, the CPUC 100 calls a checksum calculation process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1908.

<Processing in the second ROM / RAM area>
Next, in step 1908, the CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the checksum area based on the data in the second ROM / RAM area, and detects an error based on the calculated checksum. Information (for example, the lower 1 byte in the calculated checksum or its complement) is set in the checksum area (the address relating to the checksum area is the “memory map relating to RAM” in the lower part of the figure) See). Next, in step 1910, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1912.

<Processing in the first ROM / RAM area>
Next, in step 1912, the CPUC 100 prohibits writing to the first RAM / second RAM based on the data in the first ROM / RAM area, and proceeds to step 1914. Next, in step 1914, the CPUC 100 executes an infinite loop process for waiting for reset based on the data in the first ROM / RAM area.

  With the configuration as described above, according to the swivel type gaming machine according to the present embodiment, the first RAM area (or the register area) is processed by the CPUC 100 based on the program code arranged in the second ROM area. ) Is configured so that it can be updated and referenced, and fraudulent acts are performed on gaming machines such as error detection and error display (for example, unauthorized access to gaming media slot and payout port for illegal gaming media By configuring the program for preventing fraud to protect against this in the process of the second ROM / RAM area, the process and area relating to the progress of the game are clearly separated. This makes it easy to verify the validity of the program for preventing fraud.

(Second Embodiment)
In the present embodiment, error display processing or the like is also regarded as a program for preventing fraud, and an example is shown for implementation as program code arranged in the second ROM area. Is an indispensable process for controlling the progress of the game, so it may be easier to perform human verification if it is viewed as a program for implementing gameplay specifications rather than a program for preventing fraud There is. Therefore, in view of such circumstances, processing that may be more suitable as a program for implementing the gaming specifications is arranged in the first ROM area based on the example shown in the present embodiment. An example to be implemented as program code is a second embodiment, and changes from the present embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 22 shows a flow of processing executed for the first time by the CPUC 100 of the main control board M after turning on the power of the spinning-reel type gaming machine P according to the second embodiment (or at the time of system reset or user reset). It is the flowchart (1st sheet) which showed. The difference from the present embodiment is that step 1005-1 (second), step 1005-2 (second), step 1009-1 (second), step 1009-2 (second), step 1017 (second) ), Step 1019-1 (second) to step 1019-3 (second), step 1021-1 (second), step 1021-2 (second), step 1027 (second), step 1029 (second) ), Step 1035-1 (second) and step 1035-2 (second), that is, after executing the function setting of the chip in step 1004, in step 1005-1 (second), the CPUC 100 Based on the data in the first ROM / RAM area, a checksum from the head address of the first RAM area to the address immediately before the first checksum area is calculated. Here, as shown on the right side of the drawing (memory map related to the RAM), in the second embodiment, the checksum area (first checksum area) of the first RAM area and the checksum area (first area) of the second RAM area are shown. 2 checksum areas) and the checksum calculation of the first RAM area and the checksum calculation of the second RAM area are performed separately in the power-off process in the second embodiment to be described later. The error detection information based on the calculation result is stored in each area. Next, in step 1005-2, the CPUC 100 checks the first RAM based on the data in the first ROM / RAM area, and generates first RAM power-off recovery data (power-off recovery data related to the first RAM). 1006 is entered. Therefore, the “check first RAM” here is based on the checksum for the first RAM area and the error detection information held in the first checksum area, by power-off / power-off recovery. This is a process for checking whether or not the data stored in the built-in RAMC 120 is correctly held.

<Processing in the second ROM / RAM area>
On the other hand, after the power-off recovery process is called in step 1006, in step 1009-1 (second), the CPUC 100 determines the second checksum from the start address of the second RAM area based on the data in the second ROM / RAM area. Calculate the checksum up to the last address excluding the area. Next, in step 1009-2 (second), the CPUC 100 checks the second RAM based on the data in the second ROM / RAM area, and obtains the second RAM power-off recovery data (power-off recovery data related to the first RAM). Generate and move to step 1012. In other words, the “check the second RAM” here is based on the checksum for the second RAM area and the error detection information held in the second checksum area, by power-off / power-off recovery. This is a process for checking whether or not the data stored in the built-in RAMC 120 is correctly held.

<Processing in the first ROM / RAM area>
If all the switches are turned on in step 1016, in step 1017 (second), the CPUC 100 turns on the setting change operation flag based on the data in the first ROM / RAM area (for example, the first RAM The flag area with the region setting change operation is updated with a value corresponding to ON), and the process proceeds to Step 1018.

<Processing in the second ROM / RAM area>
After calling the initialization process at the time of non-setting change in step 1018, in step 1019-1 (second), the CPUC 100 sets a flag indicating that there is a setting operation in the first RAM area based on the data in the second ROM / RAM area. It is determined whether or not is off. If YES in step 1019-1 (second), in step 1019-2 (second), the CPUC 100 has normal power-off recovery data in the first RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the first RAM area is normal). In the case of Yes in step 1019-2 (second), in step 1019-3 (second), the CPUC 100 has normal power-off recovery data in the second RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the second RAM area is normal). If YES in step 1019-3 (second), the initialization range of the first RAM area and the second RAM area is determined and set as an unused RAM range in step 1028, and the second RAM is set in step 1027 (second). The power-off abnormality flag in the area is turned off, and the process proceeds to step 1036. On the other hand, if step 1019-2 (second) or step 1019-3 (second) is No, in step 1029 (second), the CPUC 100 determines whether the second RAM area is based on the data in the second ROM / RAM area. Is turned on, and the process proceeds to Step 1036.

  On the other hand, if NO in step 1019-1 (second), in step 1021-1 (second), CPUC 100 determines that the power-off recovery data in the first RAM area is normal based on the data in the second ROM / RAM area. (Particularly, whether or not the error detection result for the first RAM area is normal). In the case of Yes in step 1021-1 (second), in step 1021-2 (second), the CPUC 100 has normal power-off recovery data in the second RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the second RAM area is normal). If YES in step 1021-2 (second), in step 1032 the CPUC 100 sets the initialization range of the first RAM area and the second RAM area to the set value in the first RAM area based on the data in the second ROM / RAM area. In step 1035-1 (second), the CPUC 100 turns off the power failure abnormality flag in the second RAM area based on the data in the second ROM / RAM area in step 1035-1 (second). 1036. On the other hand, if step 1021-1 (second) or step 1021-2 (second) is No, in step 1034, the CPUC 100 determines whether the first RAM area and the second RAM area are based on the data in the second ROM / RAM area. In step 1035-2 (second), the CPUC 100 turns on the power failure abnormality flag in the second RAM area based on the data in the second ROM / RAM area. Then, the process proceeds to step 1036.

<Processing in the first ROM / RAM area>
Next, FIG. 23 shows a process executed for the first time by the CPUC 100 of the main control board M after turning on the power of the rotary gaming machine P according to the second embodiment (or at the time of system reset or user reset). It is the flowchart (2nd sheet) which showed the flow. The difference from this embodiment is that step 1039-1 (second), step 1039-1 (second), step 1026 (second), step 1300 (second), step 1045 (second), step 1046. (Second) and step 1047 (second), that is, in step 1039-1 (second), the CPUC 100 sets the flag indicating that there is a setting operation in the first RAM area based on the data in the first ROM / RAM area. It is determined whether or not it is off. In the case of Yes in step 1039-1 (second), in step 1039-1 (second), the CPUC 100 has the power failure abnormality flag in the second RAM area turned off based on the data in the first ROM / RAM area. It is determined whether or not. If step 1039-1 (second) is Yes or step 1039-1 (second) is No, the process proceeds to step 1040 (that is, the setting change device is operated or the setting change device is operated). If not, including the fact that the separate error detection results for the first RAM area and the second RAM area are normal, the subsequent processing is continued when the power failure is restored normally), and step 1039-2 In the case of No in (second), in step 1026 (second), the CPUC 100 sets a backup error display based on the data in the first ROM / RAM area (for example, sets an error number in the register area). . Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area (that is, the first RAM area when the setting change device is not operated). In addition, if the result of the separate error detection for the second RAM area is abnormal, the state shifts to a state where it cannot be restored if the power interruption is not normally restored). Here, in this example, when the setting change device is not operated, when the separate error detection results for the first RAM area and the second RAM area are both normal, the subsequent processing is continued. However, the present invention is not limited to this. For example, if the error detection result for the first RAM area is normal, even if the error detection result for the second RAM area is abnormal (all of the second RAM area). It may be configured to continue the subsequent processing (after initializing the area).

<Processing in the second ROM / RAM area>
If the setting value in the first RAM area is within the normal range in step 1044, the CPUC 100 sets the setting in the second RAM area based on the data in the second ROM / RAM area in step 1045 (second). The value abnormality flag is turned off, the process returns to the caller of the first ROM area, and the process proceeds to step 1047 (second). On the other hand, in the case of No in Step 1044, in Step 1046 (second), the CPUC 100 turns on the set value abnormality flag in the second RAM area based on the data in the second ROM / RAM area, and calls the first ROM area. The process returns to step 1047 (second).

<Processing in the first ROM / RAM area>
Next, in step 1047 (second), the CPUC 100 determines whether or not the set value abnormality flag in the second RAM area is OFF based on the data in the first ROM / RAM area. If YES in step 1047 (second), the process proceeds to step 1050. If NO, in step 1048 (second), the CPUC 100 determines that a set value error has occurred based on the data in the first ROM / RAM area. Set the display (for example, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error processing and the set processing of the generated non-recoverable error display (backup error display, setting value error display) are executed in the first ROM / RAM area. It is configured as follows.

<Processing in the first ROM / RAM area>
Next, FIG. 24 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in the second embodiment. The difference from this embodiment is that step 1228 (second), step 1700 (second), step 1400 (second), step 1237 (second), step 1750 (second), step 1450 (second) , Step 1249-1 (second), Step 1800 (second), Step 1500 (second), Step 1254-1 (second) to Step 1254-3 (second), Step 1256 (second) and step 1300 (second), that is, after accepting the insertion of a game medal in step 1227, or when the first insertion sensor D20s and the second insertion sensor D30s are not OFF in step 1230, step 1228 (second) In 2), the CPUC 100 calls the medal insertion check process in the second ROM area based on the data in the first ROM / RAM area. And, the process proceeds to step 1700 (second).

<Processing in the second ROM / RAM area>
Next, in step 1700 (second), the CPUC 100 executes medal insertion check processing based on the data in the second ROM / RAM area, and proceeds to step 1229. The purpose of the medal insertion check process in the second ROM area is the medal insertion check implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. It is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1229, in step 1400 (second), the CPUC 100 executes medal insertion error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1230. In the second embodiment, the medal insertion error detection process is executed in the first ROM / RAM area.

  Further, when the first payout sensor H10s or the second payout sensor H20s is turned on at step 1236, when the predetermined time has not elapsed after the hopper is driven at step 1241, or at step 1247, the first payout sensor H10s and the second payout sensor H10s. If the 2 payout sensor H20s is not OFF, in step 1237 (second), the CPUC 100 calls the medal payout check process in the second ROM area based on the data in the first ROM / RAM area, and step 1750 (second). ).

<Processing in the second ROM / RAM area>
Next, in step 1750 (second), the CPUC 100 executes medal payout check processing based on the data in the second ROM / RAM area, and proceeds to step 1240. The purpose of the medal payout check process in the second ROM area is the medal payout check implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. This is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area in step 1240, in step 1450 (second), the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1247. In the second embodiment, the medal payout error detection process is executed in the first ROM / RAM area.

  If there is no operation of the checkout button D60 in step 1232, or if there are no remaining credits and bet medals in step 1233, in step 1249-1 (second), the CPUC 100 is in the first ROM / RAM area. On the basis of the data, the input / output error check process for the second ROM area is called, and the process proceeds to Step 1800 (second).

<Processing in the second ROM / RAM area>
Next, in step 1800 (second), the CPUC 100 executes input / withdrawal error check processing based on the data in the second ROM / RAM area, and proceeds to step 1250. The purpose of the second ROM area input / withdrawal error check process is the input implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. -An example of a method for collectively implementing payout error check related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1250, in step 1500 (second), the CPUC 100 executes input / dispensing error detection processing, which will be described later, based on the data in the first ROM / RAM area. , The process proceeds to step 1251. In the second embodiment, the input / output error detection process is executed in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
If the set value in the first RAM area is within the normal range in step 1253, in step 1254-2 (second), the CPUC 100 determines whether the setting value in the second RAM area is based on the data in the second ROM / RAM area. The set value abnormality flag is turned off, the process returns to the caller of the first ROM area, and the flow proceeds to step 1254-3 (second). On the other hand, if the set value in the first RAM area is not within the normal range in step 1253, in step 1254-1 (second), the CPUC 100 determines whether the set value in the second RAM area The set value abnormality flag is turned on, the process returns to the caller of the first ROM area, and the flow proceeds to step 1254-3 (second).

<Processing in the first ROM / RAM area>
Next, in step 1254-3 (second), the CPUC 100 determines whether or not the set value abnormality flag in the second RAM area is OFF based on the data in the second ROM / RAM area. If YES in step 1254-3 (second), the process proceeds to the next process (process in step 1257). If NO, in step 1256 (second), the CPUC 100 determines that the first ROM / RAM area is in the first ROM / RAM area. A set value error display is set based on the data (for example, an error number is set in the register area). Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error processing and the set processing of the generated non-recoverable error display (setting value error display) are executed in the first ROM / RAM area. Yes.

<Processing in the first ROM / RAM area>
Next, FIG. 25 is a flowchart of medal insertion error detection processing according to the subroutine of step 1400 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing an error display process related to a medal insertion error, the process implemented in the second ROM area is called. In the second embodiment, the process is performed by the first ROM. If an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area and executed. It is doing. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. It should be noted that the inserted medal backflow error flag, the inserted medal retention error flag, and the inserted number error are flags in the second RAM area for transferring information indicating that an error has been detected to the error display process implemented in the first ROM area. When the error is canceled, the flag may be directly turned off from the error display process implemented in the first ROM area as in this example, or the process for turning off the flag in the second ROM area. You may comprise so that a process may be called and turned off.

<Processing in the first ROM / RAM area>
Next, FIG. 26 is a flowchart of medal payout error detection processing according to the subroutine of step 1450 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing an error display process related to a medal payout error, the process implemented in the second ROM area is called, but in the second embodiment, the process is called the first ROM. If an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area and executed. It is doing. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. The payout medal retention error flag, which is a flag in the second RAM area for transferring information indicating that an error has been detected to the error display process implemented in the first ROM area, is displayed when the error is released. The error display process implemented in the first ROM area may be turned off directly as in this example, or the process for turning off the flag, which is the process of the second ROM area, is configured to be turned off. Also good.

<Processing in the first ROM / RAM area>
Next, FIG. 27 is a flowchart of input / withdrawal error detection processing according to the subroutine of Step 1500 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing the error display process related to the input / withdrawal error, the process implemented in the second ROM area is called. In the second embodiment, the process is When an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area. It is running. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. It should be noted that the error input error flag and the abnormal payout error flag, which are flags in the second RAM for transferring information indicating that an error has been detected, to the error display processing implemented in the first ROM area, have been canceled. In this case, the error display process implemented in the first ROM area may be turned off directly as in this example, or the process for turning off the flag, which is a process in the second ROM area, is called off. It may be configured.

<Processing in the second ROM / RAM area>
Next, FIG. 28 is a flowchart of the game progress control process (third sheet) in the second embodiment. The difference from the present embodiment is that step 1269-1 (second) to step 1269-4 (second), step 1272 (second), step 1300 (second), step 1800 (second), step 1500. (Second), Step 1277-1 (Second), Step 1750 (Second), and Step 1450 (Second), that is, if the displayed symbol combination is normal in Step 1269, Step 1269 -1 (second), the CPUC 100 turns off the display determination abnormality flag in the second RAM area based on the data in the second ROM / RAM area, returns to the caller of the first ROM area, and returns to step 1269-3 ( Move to 2). On the other hand, if the combination of symbols displayed in step 1269 is not normal, in step 1269-2 (second), the CPUC 100 determines the display determination abnormality flag in the second RAM area based on the data in the second ROM / RAM area. Is turned on to return to the calling source of the first ROM area, and the flow proceeds to Step 1269-3 (second).

<Processing in the first ROM / RAM area>
Next, in Step 1269-3 (second), the CPUC 100 determines whether or not the display determination abnormality flag in the second RAM area is off based on the data in the first ROM / RAM area. In the case of Yes in step 1269-3 (second), in step 1269-4 (second), the CPUC 100 calls the input / output error check processing of the second ROM area based on the data in the first ROM / RAM area, The process proceeds to step 1500 (second). On the other hand, if NO in step 1269-3 (second), in step 1272 (second), CPUC 100 sets a display determination error display based on the data in the first ROM / RAM area (for example, register Set the error number in the area). Next, in step 1300 (second), the CPUC 100 sets the above-described unrecoverable error processing based on the data in the first ROM / RAM area. As described above, in the second embodiment, the setting process of the non-recoverable error process and the non-recoverable error display (display determination error display) that has occurred is executed in the first ROM / RAM area. Yes.

<Processing in the second ROM / RAM area>
Next, in step 1800 (second), the CPUC 100 executes input / withdrawal error check processing based on the data in the second ROM / RAM area, and proceeds to step 1270. The purpose of the second ROM area input / withdrawal error check process is the input implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. -An example of a method for collectively implementing payout error check related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1270, in step 1500 (second), the CPUC 100 executes the aforementioned input / out error detection process based on the data in the first ROM / RAM area. Then, the process proceeds to step 1274. In the second embodiment, the input / output error detection process is executed in the first ROM / RAM area.

  On the other hand, if the first payout sensor H10s or the second payout sensor H20s is on in step 1277, the CPUC 100 determines in step 1277-1 (second) the second ROM area based on the data in the first ROM / RAM area. The medal payout check process is called, and the process proceeds to step 1750 (second).

<Processing in the second ROM / RAM area>
Next, in step 1750 (second), the CPUC 100 executes medal payout check processing based on the data in the second ROM / RAM area, and proceeds to step 1284. The purpose of the medal payout check process in the second ROM area is the medal payout check implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. This is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area in step 1284, in step 1450 (second), the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1286. In the second embodiment, the medal payout error detection process is executed in the first ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 29 is a flowchart of non-recoverable error processing according to the subroutine of step 1300 (second) in FIGS. 23, 24, 28, and 30 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing the non-recoverable error process, the process implemented in the second ROM area is called. In the second embodiment, the process is implemented in the first ROM area. When an error is detected in various error detection processes in the second ROM / RAM area, information indicating that the error has been detected is transferred to the process implemented in the first ROM area and executed. It is. When configured in this way, a program for implementing a gameplay specification with a process having a forcible force to shift to a state in which it cannot be restored (that is, to make the spinning machine P inoperable) It can be implemented as a program for controlling the game progress.

<Processing in the second ROM / RAM area>
Next, FIG. 30 is a flowchart of timer interruption processing according to the subroutine of step 1600 in the second embodiment. The difference from this embodiment is step 1648 (second), step 1650 (second), and step 1654 (second), that is, if the update state of the built-in random number is normal in step 1642, In step 1648 (second), the CPUC 100 turns off the internal random number abnormality flag in the second RAM area based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area. ). On the other hand, if the frequency of the random number update clock is not normal in step 1640, or if the update state of the internal random number is not normal in step 1642, in step 1650 (second), the CPUC 100 determines that the second ROM Based on the data in the RAM area, the built-in random number abnormality flag in the second RAM area is turned on, the process returns to the caller of the first ROM area, and the process proceeds to step 1654 (second).

<Processing in the first ROM / RAM area>
Next, in step 1654 (second), the CPUC 100 determines whether or not the internal random number abnormality flag is off based on the data in the first ROM / RAM area. In the case of Yes in step 1654 (second), the process proceeds to step 1636. In the case of No, in step 1648 (second), the CPUC 100 determines whether the built-in random number error is based on the data in the first ROM / RAM area. Set the display (for example, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets the above-described unrecoverable error processing based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error process and the set process of the generated non-recoverable error display (built-in random number error display) are executed in the first ROM / RAM area. Yes.

<Processing in the first ROM / RAM area>
Next, FIG. 31 is a flowchart of the power-off process according to the subroutine of Step 1900 of FIG. 30 in the second embodiment. The difference from the present embodiment is step 1905 (second) and step 1909 (second), that is, after turning on the power-off processing flag in step 1904, in step 1905 (second), The CPUC 100 calculates a checksum from the first address of the first RAM area to the address immediately before the first checksum area based on the data in the first ROM / RAM area, and information for error detection based on the calculated checksum (for example, The lower 1 byte of the calculated checksum or its complement) is set in the first checksum area. Next, in step 1906, the checksum calculation process of the second ROM area is called, and the process proceeds to step 1909 (second).

<Processing in the second ROM / RAM area>
Next, in step 1909 (second), the CPUC 100 calculates a checksum from the start address of the second RAM area to the immediately preceding address of the second checksum area based on the data in the second ROM / RAM area, and the calculation is performed. Error detection information based on the checksum (for example, the lower 1 byte of the calculated checksum or its complement) is set in the second checksum area, and the process proceeds to step 1910. As described above, in the second embodiment, the checksum area is divided into the first checksum area and the second checksum area. As shown in the lower part of FIG. The second checksum area exists at the final address of the area, and the second checksum area exists at the final address of the second RAM area. The checksum calculation and set of the first RAM area are executed in the first ROM area, and the checksum calculation and set of the second RAM area are executed in the second ROM area.

  With the configuration as described above, according to the rotary type gaming machine according to the second embodiment, the second RAM area can be referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area. The first RAM area can be referred to by the processing of the CPUC 100 based on the program code that is configured and arranged in the second ROM area, and an illegal act is performed on the gaming machine such as error detection (for example, In the second ROM / RAM area, a program for preventing illegal acts is used to prevent unauthorized access to the game media slot and payout port to obtain game media by unauthorized means. By configuring so that it can be executed, the process and the area related to the progress of the game can be clearly separated, and the program for preventing illegal acts can be properly executed as in the present embodiment. It is easy to verify the sex.

(Third embodiment)
In this embodiment, the error display process is also regarded as a program for preventing fraud, and an example for implementing it as a program code arranged in the second ROM area has been shown. In addition to error display processing, the program to be arranged can be conceptualized. In particular, a program for testing the ball that is used only for the ball test (a test for certifying that the machine is not a socially non-conforming machine that remarkably rejoices the player's happiness) is essential in the market (during mass production). Since it is a program that is not executed, it may be preferable to arrange it in the second ROM area. Therefore, based on the example shown in the present embodiment, an example of a configuration for executing a further program in the second ROM area is referred to as a third embodiment, and differences from the present embodiment will be described in detail below. .

  First, FIG. 32 is a list of basic specifications of the swivel type gaming machine in the third embodiment. The swivel type gaming machine according to the third embodiment has a prescribed number (the maximum number of game medals that can be bet in one game) of three, and the number of frames of the left reel M51, the middle reel M52, and the right reel M53 are all 20. The valid line for which the frame and winning determination is made is one line of “left reel M51 middle stage, middle reel M52 middle stage, right reel M53 middle stage”, the maximum payout number is 9, and the minimum payout number is 1 (the winning combination and the payout number) The bonus symbol is “Sheep / Sheep / Sheep” (finished with over 450 cards) and “Seven Seven Seven” (finished with over 300 cards). It is 1 type BB (a so-called first-type special accessory continuous action device). In addition, the priority winning order (retraction priority order) is “re-game → small role (bell, watermelon) → bonus”. For example, when re-game and bonus are established at the same time, Wins and bonuses are not possible. Also, when the bell and watermelon are established, if a stop button is pressed at a position where both can be retracted (positions within 4 frames to the winning stop position), priority is given to a small part with a large number of payouts. It is configured to retract. The configuration shown in the figure is merely an example, and the number of frames of each reel is changed (for example, changed to 21 frames), or the configuration of the effective line is changed (for example, 5 lines of 3 horizontal lines and 2 diagonal lines). There is no problem even if you change the line)

  Next, FIG. 33 is a list of reel arrangements of the spinning cylinder type gaming machine in the third embodiment. As shown in the figure, the number of frames of the left reel M51, the middle reel M52 and the right reel M53 are all 20 frames (0 to 19), and the symbols are “Seven”, “Sheep”, “Blank B”. ”,“ Bell ”,“ Replay A ”,“ Replay B ”,“ Watermelon ”,“ Cherry ”, and“ Blank A ”. The configuration shown in the figure is merely an example, and there is no problem even if the type of design is increased / decreased / changed.

  Next, FIG. 34 is a list of small role appearance rates in the third embodiment. As shown in the figure, in the third embodiment, the appearance rate (lottery probability) of a small role (especially replay) can be different depending on the game state, and “replay 01, 02” is ART. In the preparation state and the ART state, the appearance rate is higher than the post-bonus state and the normal state. In addition, “re-games 03, 04” (so-called falling re-games, and when the re-game is won, the game will shift to the normal game state thereafter) does not appear in the post-bonus state, but appears most in the ART state It is easy. Further, “re-game 05” (so-called preparation state transition re-game, and when the re-game is won in the normal game state, it will shift to the ART preparation state thereafter) appears only in the normal game state. Has been. Further, “re-game 06” (so-called promoted re-game, and when the re-game is won in the ART ready state, it will be shifted to the ART state thereafter) is configured to appear only in the ART ready state. . Note that the game state transition associated with the winning of the re-gamer will be described later with a separate game state transition flow. Further, the appearance rate shown in the figure is merely an example, and the winning combination to be won in the actual combination lottery is, for example, a conditional device number (winning number, also referred to as a winning combination) shown in FIGS. , “Replay-A, replay-B1,...”. In other words, as shown in FIG. 37 to FIG. 39, the appearance rate of the symbol combination that is stopped and displayed can vary depending on the lottery probability of the winning combination and the stop operation mode (stop operation position, stop operation order). ing. It should be noted that there is no problem even if the lottery probability is appropriately changed.

  Next, FIG. 35 and FIG. 36 are symbol combination lists 1 and 2 in the third embodiment. In the third embodiment, there are a plurality of symbol combinations for each condition device. As will be described later, according to the stop order and stop position of the left reel M51, the middle reel M52, and the right reel M53, Any one of the symbol combinations is configured to be stopped and displayed on the effective line (the one line described above). Note that even if the same type of symbols is not on the active line, the same symbols are easily arranged in a line on the lines other than the active line when viewed from the player. It is configured such that three watermelon symbols are aligned in any one line on the reel, such as aligned in a horizontal line).

  Next, FIG. 37 to FIG. 39 are condition device lists 1 to 3 in the third embodiment. In the third embodiment, replays are provided from replay-A to replay I3 (conditional device numbers 1 to 18), and in the stop order and stop position of the left reel M51, the middle reel M52, and the right reel M53. Accordingly, the re-game player to win is configured to be different. The item “push order etc.” describes the type of replay that will be won in the stop order, for example, “left reel M51: 1, middle reel M52: 2, right reel M53: 3”. "123" means that the operation is stopped in the pressing order of "left reel M51-> middle reel M52-> right reel M53". For example, "replay C-1" (condition device number 7) In this case, if “123” = “left → middle → right” is stopped in this order, “replay 06” will be won. Furthermore, when the stop is made in the order of “left → right → middle”, “re-game 04” is won, and when the first stop is made, “re-game 04” is performed regardless of the types of reels of the second stop and the third stop. Will win the first stop on the right, and "replay 03" will win regardless of the type of reels of the second stop and the third stop. By configuring in this way, if the correct answer can be made in the push order, the gaming state is promoted (to shift to a gaming state that is highly profitable for the player), or if the correct answer is not made in the order of pushing, the gaming state falls (the gaming state having a low profit for the player) Can be created. Further, in the case of “winning-A1 (bell)” (condition device number 19), “123” = “left → middle → right” is stopped in this order, that is, when the correct answer is given in the pushing order, nine payouts are obtained. It is configured to stop in another pressing order, that is, if one cannot answer correctly in the pressing order, it is configured so that one sheet is paid out. With this configuration, the bell pressing order can be navigated in the ART state and the ART ready state ( The push order display device D270 displays the push order with the highest profit), and can create a plurality of game states with different profit margins of the player not navigating the push order between the normal game state and the post-bonus state. .

<Processing in the first ROM / RAM area>
Next, FIG. 40 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in FIG. 9 in the third embodiment. The difference from the present embodiment is that step 1257-1 (third), step 1255-2 (third), step 3100 (third), step 3150 (third), step 3200 (third), step 1291 -1 (third) to step 1291-3 (third), step 3250 (third), step 3300 (third) and step 3350 (third), the purpose of which is a conventional spinning machine In this case, the push order navigation function controlled on the sub-control board S side is shifted to the main control board M side. That is, after executing the internal lottery (condition device number determination process) in step 1257, in step 1257-1 (third), the CPUC 100 determines the executed internal lottery based on the data in the first ROM / RAM area. The result and the condition device identification value (a bonus identification value, a small role identification value, etc., see the example of the condition device information in FIG. 49) are temporarily stored in the first RAM area. In this example, regarding the result of the executed internal lottery, the determined condition device number is set to “D0 to D5 bits” in the example of the condition device information of FIG. And whether the result of the executed internal lottery is related to a small role or a bonus (in this example, the first type BB). (D6 to D7 bits for the small combination is set as “D6 to D7 bits” = “10” as the small combination state information, and “D6 to D7 bits” is set to “01” for the bonus. "Set as bonus status information). Next, in Step 1257-1 (third), the CPUC 100 proceeds with the game according to the ART counter M60 (the push order navigation display displayed on the push order display device D270) based on the data in the first ROM / RAM area. It is determined whether or not the counter value of the counter that measures the number of games that can stay in the ART state to be guaranteed is greater than zero. In the case of Yes in step 1255-2 (third), in other words, in the ART state, in step 3100 (third), the CPUC 100 determines the number of winning games, which will be described later, based on the data in the first ROM / RAM area. Addition execution processing is executed. Next, in step 3150 (third), the CPUC 100 executes a push order navigation control process, which will be described later, based on the data in the first ROM / RAM area, and proceeds to step 3200 (third). On the other hand, also in the case of No in step 1257-2 (third), the process proceeds to step 3200 (third). Next, in step 3200 (third), the CPUC 100 executes a reel rotation start preparation process, which will be described later, based on the data in the first ROM / RAM area, and proceeds to step 1258.

<Processing in the first ROM / RAM area>
In step 1290, after the payout corresponding to the winning of the condition device related to the game is completed, in step 1291-1 (third), the CPUC 100 determines the current game based on the data in the first ROM / RAM area. It is determined whether or not the state is in a normal gaming state. If YES in step 1291-1 (third), an ART lottery execution control process, which will be described later, is executed in step 3250 (third), and the process proceeds to step 3350 (third). On the other hand, if No in step 1291-1 (third), in step 1291-2 (third), CPUC 100 determines whether the counter value of ART counter M60 is greater than 0 based on the data in the first ROM / RAM area. No, in other words, it is determined whether or not the current gaming state is the ART state. In the case of Yes in step 1291-2 (third), in step 3300 (third), the CPUC 100 executes a winning game number addition execution process, which will be described later, based on the data in the first ROM / RAM area. Next, in step 1291-3 (third), the CPUC 100 subtracts 1 from the counter value of the ART counter M60 based on the data in the first ROM / RAM area, and proceeds to step 3350 (third). On the other hand, in the case of No in step 1291-2 (third), in other words, even if the current gaming state is other than the normal gaming state and the ART state (for example, the ART ready state, the post-bonus state), step 3350 (the first state) Move to 3). Next, in step 3350 (third), the CPUC 100 executes a gaming state transition control process, which will be described later, based on the data in the first ROM / RAM area, and proceeds to step 1292.

<Processing in the first ROM / RAM area>
Next, FIG. 41 is a flowchart of the winning game number addition execution process according to the subroutine of Step 3100 (third) in FIG. 40 in the third embodiment. First, in step 3102, based on the data (for example, the condition device number) in the first ROM / RAM area, the CPUC 100 wins the condition device related to the game, regardless of whether or not the winning combination is won. Thus, it is determined whether or not the condition device is capable of adding the number of ART games. In the third embodiment, watermelon = condition device number 25 is used as an additional combination at the time of winning, but the additional combination at the time of winning is not limited to this, and a re-game combination or a push order bell combination is also provided. Then, there is no problem even if other small roles not shown are added and the lottery is executed. In the case of Yes in step 3102, in step 3104, the CPUC 100 determines a predetermined probability (1/4) based on the data in the first ROM / RAM area (for example, a lottery table provided in the first data area in the first ROM area). ) To execute the lottery on the number of ART games to be won (lottery of whether to increase the counter value of the ART counter M60). In the third embodiment, only the watermelon is added as a winning combination. However, when a re-playing combination or a push-bell combination is also configured as an additional winning combination, the ART depends on the selected winning combination type. The winning rate of the game number addition lottery (and / or the distribution of the ART addition game number) may be made different. Next, in step 3106, the CPUC 100 determines whether or not the lottery with the number of executed ART games is won based on the data in the first ROM / RAM area (for example, the latched random number value is within the winning range). To determine if it ’s fit.) In the case of Yes in step 3106, in step 3108, based on the data in the first ROM / RAM area, the CPUC 100 adds a game number lottery table at the time of the watermelon (for example, a lottery table provided in the first data area in the first ROM area). Then, referring to the table that is referred to when the number of ART games is added due to the formation of a watermelon, the number of ART adding games is determined (for example, in the lottery table shown outside the box, the latched random number value is To determine whether it falls within the range). Next, in step 3110, based on the data in the first ROM / RAM area, the CPUC 100 adds the determined ART added game number to the counter value of the ART counter M60, and uses the ART counter value after the addition as the ART counter. Then, the process proceeds to the next process {step 3150 (third) process}. In addition, also when it is No in step 3102 or step 3106, it transfers to the next process {process of step 3150 (3rd)}.

  Here, the lottery table shown outside the figure is an example of a watermelon extra game number lottery table. As shown in the figure, when the ART extra lottery is won, the ART extra game number is “10”. ”To“ 300 ”are determined by lottery, and the determined value is added to the counter value of the ART counter M60. It should be noted that the average number of ART addition games when winning an ART addition lottery at the time of watermelon is “28.9”. In the third embodiment, when determining the number of ART additional games, “the number of games is determined by lottery based on the additional game number lottery table in the case of winning the ART game number additional lottery →” The lottery is divided into stages, but by providing a lost area (ART added game number = 0) in the added game number lottery table, the number of ART added games (and the number of ART games added) can be executed by one lottery. ) May be determined.

<Processing in the first ROM / RAM area>
Next, FIG. 42 is a flowchart of the push-sequence navigation control process according to the subroutine of Step 3150 (third) in FIG. 40 in the third embodiment. First, in step 3152, the CPUC 100 determines whether or not the counter value of the ART counter M60 is greater than 0, in other words, whether or not it is in the ART state, based on the data in the first ROM / RAM area. If Yes in step 3152, the process proceeds to step 3156. On the other hand, in the case of No in step 3152, in step 3154, the CPUC 100 determines whether or not it is currently in the ART ready state based on the data in the first ROM / RAM area. Also in the case of Yes in step 3154, the process proceeds to step 3156. Next, in step 3156, based on the data in the first ROM / RAM area, the CPUC 100 adds the condition device related to the game in the push order (the number of ART games is increased by correctly answering the push order in the ART state). In this example, it is determined whether or not cherry replay = condition device numbers 16 to 18). The pressing order in this example is an order in which the reels are stopped in one game. In the case of Yes in step 3156, in step 3158, the CPUC 100 determines a predetermined probability (for example, 1) based on data in the first ROM / RAM area (for example, a lottery table provided in the first data area in the first ROM area). / 5) A push order navigation execution lottery to win is executed. Next, in step 3160, the CPUC 100 determines whether or not the push order navigation execution lottery has been won based on the data in the first ROM / RAM area (for example, the latched random number value is within the winning range). Whether or not). If Yes in step 3160, the process proceeds to step 3163. On the other hand, in the case of No in step 3156, in step 3162, based on the data in the first ROM / RAM area, the CPUC 100 determines that the conditional device related to the game has a pushing order (the player's profit rate varies depending on the pushing order). It is determined whether or not it is a conditional device. In the case of Yes in step 3162, in other words, if the condition device of the game includes replay 03, 04, 06 or bell (for example, condition device numbers 7 to 14 or 19 to 24), the process proceeds to step 3163. To do.

<Processing in the first ROM / RAM area>
Next, in step 3163, the CPUC 100, based on the data in the first ROM / RAM area, based on the condition device information related to the game, has the highest machine discount order operation mode information (first to third stop operation mode information). ) And temporarily stored in the first RAM area. Here, the operation mode information with the highest machine split order is the reel with the highest profit rate for the player in a game in which a small role with a push order (a condition device in which the profit rate of the player differs depending on the push order) is established. This information is related to the stop order and the reel stop position. In the third embodiment, as will be described later, the information can be transmitted from the main control board M side to the outside of the revolving game machine (conventional technology). Then, the information is transmitted from the sub-control board S side to the second test board that mediates the information transmission between the outgoing ball tester and the spinning cylinder game machine). Note that the highest machine discount operation mode information (operation mode information with the highest machine split order, operation mode information without the highest machine split order) is referred to as optimum operation mode information, advantageous operation mode information, high profit operation mode information, etc. You can also. Next, in step 3164, the CPUC 100 presses the push order display device D270 during the game based on the operation mode information with the highest machine split order in the first RAM area based on the data in the first ROM / RAM area. Execute sequential navigation display (For example, when “2” is displayed, the order of “left → middle → right” is displayed; Become). Next, in step 3165, based on the data in the first ROM / RAM area, the CPUC 100 sets a command (command to the sub side) related to the operation mode information with the highest machine splitting order, and the next processing {step 3200 The process proceeds to (third) processing}.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 3154, in step 3166, based on the data in the first ROM / RAM area, the CPUC 100 is an internal ART winning flag (a flag that is turned on when the transition to the ART state becomes definite). It is determined whether or not (Yes) is ON. In the case of Yes in step 3166, in step 3168, based on the data in the first ROM / RAM area, the CPUC 100 determines that the condition device related to the game is in the ready state transition replay (replay that can transition from the normal game state to the ART ready state). It is a game, and in this example, it is a condition device including the re-game 05, for example, it is determined whether it is a condition device number 2-6). In the case of Yes in step 3168, in step 3170, the CPUC 100 turns off the internal ART winning flag based on the data in the first ROM / RAM area. Next, in step 3171, the CPUC 100 operates based on the data in the first ROM / RAM area, based on the condition device information related to the game, and has the highest machine discount order operation mode information (first to third stop operation mode information). ) And temporarily stored in the first RAM area. Next, in step 3172, the CPU C 100 presses the push order display device D270 during the game based on the operation mode information with the highest machine split order in the first RAM area based on the data in the first ROM / RAM area. Execute sequential navigation display {For example, when the condition device number is “2”, display “2” (in order of “left → middle → right”), and when the condition device number is “3”, “3” Is displayed (in order of “left → right → middle”), and the reels are stopped according to the display, thereby shifting to the ART ready state}. Next, in step 3174, the CPUC 100 sets a command (command to the sub side) related to the operation mode information with the highest machine splitting order based on the data in the first ROM / RAM area, and the next processing {step 3200 The process proceeds to (third) processing}. In addition, also in the case of No in step 3160, step 3162, step 3166, or step 3168, the process proceeds to the next process {step 3200 (third) process}.

<Processing in the first ROM / RAM area>
Next, FIG. 43 is a flowchart of reel rotation start preparation processing according to the subroutine of step 3200 (third) in FIG. 40 in the third embodiment. First, in step 3204, the CPUC 100 determines whether or not the timer value of the game interval minimum time timer M70 (subtraction timer) is 0 based on the data in the first ROM / RAM area. Here, the game interval minimum time timer M70 is a time (4.1 seconds in this example) that should be secured from a certain game start timing (reel rotation start timing) to the next game start timing (reel rotation start timing). It is a timer that measures. In the case of Yes in step 3204, in step 3206, based on the data in the first ROM / RAM area, the CPUC 100 newly adds a minimum time (4.1 seconds in this example) to the timer value of the game interval minimum time timer M70. Set and start. Next, in step 3208, the CPUC 100 newly sets a conditional device information output time (24 interrupts in this example) to the output time timer M80 (subtraction timer) based on the data in the first ROM / RAM area, Control goes to step 3210. Here, in this example, the details will be described later, but after setting the condition device information output time in step 3208, the rotation from the main control board M side according to the timer value of the output time timer M80. It is configured so that output control of information transmitted outside the game machine is performed. If the answer is No in step 3204, the process in step 3204 is repeated again. Therefore, in the third embodiment, the condition device output time is set after the minimum game interval (4.1 seconds in this example) has elapsed.

<Processing in the first ROM / RAM area>
Next, in step 3210, based on the data in the first ROM / RAM area, the CPUC 100 clears the information related to the reel stop order and the information related to the push order related to the finished game. Next, in step 3212, the CPUC 100 clears the information related to the reel stop related to the finished game and the drawing point creation request based on the data in the first ROM / RAM area. Next, in step 3214, the CPUC 100 initializes the symbol stop position data relating to the finished game based on the data in the first ROM / RAM area. Next, in Step 3218, the CPUC 100 sets an output request at the start of reel rotation related to the game based on the data in the first ROM / RAM area. Next, in step 3220, the CPUC 100 sets a reel control command related to the game based on the data in the first ROM / RAM area. In other words, a command for indicating that the reel starts to rotate can be transmitted to the sub-control board S by the processing of Step 3218 and Step 3220. Next, in step 3222, the CPUC 100 updates the reel drive state stored in the first RAM area from the reel stop state to the reel rotation start standby state based on the data in the first ROM / RAM area, and performs the next processing. The process proceeds to (Step 1258).

<Processing in the first ROM / RAM area>
Next, FIG. 44 is a flowchart of the ART lottery execution control process according to the subroutine of Step 3250 (third) in FIG. 40 in the third embodiment. First, in step 3252, the CPUC 100 determines whether or not the internal ART winning flag is off based on the data in the first ROM / RAM area. In the case of Yes in step 3252, in step 3254, the CPUC 100 confirms the current gaming state (whether the gaming state is the low probability state or the high probability state) based on the data in the first ROM / RAM area. . Next, in step 3256, based on the data in the first ROM / RAM area, the CPUC 100 determines that the condition device related to the game is ART lottery {the transition to the ART state in the normal gaming state has not been confirmed (during internal ART) In the present example, it is determined whether or not watermelon = condition device number 25}. As with the processing of step 3100 (third), the ART lottery combination is not limited to the conditional device number 25 (watermelon), but is shown in the replay game combination and the push order bell combination, and in the third embodiment. There is no problem even if there is no other small part as an ART lottery. In such a configuration, the winning rate of the ART transfer lottery may be varied depending on the type of the ART lottery that has been won. In the case of Yes in step 3256, in step 3258, the CPUC 100 determines whether or not the current gaming state is a high probability state based on the data in the first ROM / RAM area. In the case of Yes in step 3258, in step 3260, the CPUC 100 determines a predetermined probability based on the data in the first ROM / RAM area (for example, the lottery table for high probability state provided in the first data area in the first ROM area). The ART transfer lottery to be won at A (1/3) is executed, and the flow shifts to Step 3264. On the other hand, in the case of No in step 3258, in other words, if the current gaming state is a low probability state, in step 3262, the CPUC 100 determines the data in the first ROM / RAM area (for example, the first data area in the first ROM area). Based on the low-probability state lottery table provided in FIG. 4, the ART transfer lottery to win with the predetermined probability B (1/50) is executed, and the process proceeds to Step 3264. Thus, in the third embodiment, the high probability state is more difficult to win the ART transition lottery than the low probability state, and there is a problem even if the predetermined probability A and / or the predetermined probability B is changed. However, it is desirable to configure so that “predetermined probability A> predetermined probability B”.

<Processing in the first ROM / RAM area>
Next, in step 3264, the CPUC 100 determines whether or not the executed ART lottery is won based on the data in the first ROM / RAM area (for example, the latched random number value falls within the winning range). Whether or not). In the case of Yes in step 3264, in step 3266, the CPUC 100 turns on the internal ART winning flag based on the data in the first ROM / RAM area, and proceeds to the next processing {step 3350 (third) processing}. . In addition, also in the case of No in step 3252, step 3256, or step 3264, the process proceeds to the next process {step 3350 (third) process}. When the internal ART winning flag is turned on, the state shifts to the ART state thereafter.

<Processing in the first ROM / RAM area>
Next, FIG. 45 is a flowchart of the winning game number addition execution process according to the subroutine of step 3300 (third) in FIG. 40 in the third embodiment. First, in step 3302, the CPUC 100 is based on the data in the first ROM / RAM area, and the condition device related to the game is a push-up order (in this example, cherry replay = condition device numbers 16 to 18). It is determined whether or not. If YES in step 3302, in step 3306, the CPUC 100 corrects the cherry re-game push order based on the data in the first ROM / RAM area (whether one of the re-games 09, 10, or 11 wins). Determine whether. In the case of Yes in step 3306, in step 3308, the CPUC 100 adds the game during the cherry replay based on the data in the first ROM / RAM area (for example, the lottery table provided in the first data area in the first ROM area). Refer to the number lottery table (the table that is referred to when the number of ART games is added by winning the cherry replay) and determine the number of ART added games (for example, the random number value latched in the lottery table shown outside the column) Is within which range). Next, in step 3310, the CPUC 100 adds the determined number of added ART games to the counter value of the ART counter M60 based on the data in the first ROM / RAM area, and adds the ART counter value after the addition to the ART counter M60. To the next process {step 1291-3 (third) process}. Even in the case of No in step 3302 or step 3306, the processing proceeds to the next processing {step 1291-3 (third) processing}.

  Here, the lottery table shown outside the figure is an example of the extra game number lottery table at the time of cherry replay. As shown in the figure, if the ART extra lottery is won, the ART extra game number is “30” to “300” are determined by lottery, and the determined value is added to the counter value of the ART counter M60. In addition, the average number of ART addition games when winning an ART addition lottery at the time of cherry replay is “57.8”, which is larger than the average number of ART addition games at the time of watermelon. Yes.

<Processing in the first ROM / RAM area>
Next, FIG. 46 is a flowchart of the gaming state transition control process according to the subroutine of step 3350 (third) in FIG. 40 in the third embodiment. First, in step 3352, the CPUC 100 satisfies the conditions for allowing the transition to the RT state in the game based on the data in the first ROM / RAM area. In other words, it can be satisfied by winning a replay}. In the case of Yes in step 3352, in step 3353, based on the data in the first ROM / RAM area, the CPUC 100 determines whether or not the game state can be changed based on the satisfied RT state changeable condition and the current game state (the game of FIG. 47). The game state after the next game is determined. Next, in Step 3354, the CPUC 100 determines whether or not the state has shifted to the ART state based on the data in the first ROM / RAM area. In the case of Yes in step 3354, in step 3355, the CPUC 100 sets the ART initial game (50 in this example) in the ART counter M60 based on the data in the first ROM / RAM area, and proceeds to step 3376. On the other hand, also in the case of No in step 3354, the process proceeds to step 3376.

<Processing in the first ROM / RAM area>
In the case of No in step 3352, in step 3356, the CPUC 100 determines whether or not the current gaming state is a low probability state based on the data in the first ROM / RAM area. In the case of Yes in step 3356, in step 3358, based on the data in the first ROM / RAM area, the CPUC 100 shifts the condition device related to the game from the low-probability state to the high-probability state by winning. Whether or not it is a watermelon in this example. In the case of Yes in step 3358, in step 3360, the CPUC 100 determines a predetermined probability (in this example, based on the data in the first ROM / RAM area (for example, the lottery table provided in the first data area in the first ROM area)). , 1/4), the high probability state transition lottery to be won is executed. In the case of Yes in step 3360, in step 3362, the CPUC 100 determines whether or not the high-probability transition lottery is won based on the data in the first ROM / RAM area (for example, the latched random value is within the winning range). To determine whether or not In the case of Yes in step 3362, in step 3364, the CPUC 100 determines the gaming state after the next game to be a high probability state based on the data in the first ROM / RAM area, and proceeds to step 3376. In the case of No in step 3358 or step 3362, the gaming state remains in the low probability state, and the process proceeds to step 3376.

<Processing in the first ROM / RAM area>
In the case of No in step 3356, in step 3366, the CPUC 100 determines whether the current gaming state is a high probability state based on the data in the first ROM / RAM area. In the case of Yes in step 3366, in step 3368, based on the data in the first ROM / RAM area, the CPUC 100 shifts the condition device related to the game from the high probability state to the low probability state by winning a prize. In this example, it is determined whether or not it is a replay excluding cherry replay and promoted replay). In the case of Yes in step 3368, in step 3370, the CPUC 100 determines a predetermined probability (in this example, based on the data in the first ROM / RAM area (for example, the lottery table provided in the first data area in the first ROM area)). , 1/7), the low probability state transition lottery to be won is executed. In the case of Yes in step 3370, in step 3372, the CPUC 100 determines whether or not the low-probability transition lottery has been won based on the data in the first ROM / RAM area (for example, the latched random number value is within the winning range). To determine whether or not In the case of Yes in step 3372, in step 3374, the CPUC 100 determines the gaming state after the next game as a low probability state based on the data in the first ROM / RAM area, and proceeds to step 3376. If No in step 3366, step 3368, or step 3372, the game state of the next game is other than the low probability state, and the process proceeds to step 3376.

<Processing in the first ROM / RAM area>
Next, in Step 3376, the CPUC 100 is based on the data in the first ROM / RAM area, with the current operating state information (information such as whether the re-gamer has won, is in bonus, or is in the ART state). Yes, refer to “Example of Operating State Information” in FIG. 49) and temporarily store it in the first RAM area, and proceed to the next process (the process of step 1292). That is, when the re-gamer wins at the end of the current game, “1” is set to “D0 bit” in the example of the operation state information of FIG. 49, but the re-gamer does not win. In this case, “0” is set to “D0 bit” in the example of the operation state information of FIG. When the first type BB combination wins at the end of the current game, “1” is set to “D1 bit” in the example of the operation state information in FIG. 49, while the first type BB is ended. When the condition is satisfied (when the payout exceeding the predetermined number is completed after the first type BB combination is won), “0” is set to “D1 bit” in the example of the operation state information of FIG. Also, at the end of the current game, if the counter value of the ART counter M60 is greater than 0 (when the current gaming state is the ART state), the “D2 bit” in the example of the operating state information in FIG. On the other hand, when the counter value of the ART counter M60 is 0 while “1” is set, “0” is set to “D2 bit” in the example of the operation state information of FIG. It should be noted that the transition state of the gaming state shown in the third embodiment is merely an example, and there is no problem even if it is changed. For example, the RT state transition enabling condition can be satisfied by winning a specific small role. It is also possible to change / add a state promotion combination or a state fall combination, or to change / add a type of gaming state that can be transferred (super easy to shift to ART state than high probability state) Providing a high probability state, etc.).

  Next, FIG. 47 is a game state transition diagram (game state transition flow) in the third embodiment. As shown in FIG. 47, the normal game state has a low probability state and a high probability state. The high probability state is configured to be more easily shifted to the ART state than the low probability state (as described above, the high probability state and the low probability state are managed on the main control board M side). . In addition, as described above, it is configured to be able to shift from a low probability state to a high probability state by winning a watermelon, and from a high probability state to a low probability state being configured to be transferred by winning a re-game. Has been. In addition, after the bonus is over, the game is shifted to the post-bonus state, and the game is shifted to the normal game state when the correct answer cannot be made in the bell formation game (the push order is incorrect). Even if a bonus is established in the ART state or the ART ready state, after the bonus, the state transitions to the post-bonus state, and after the transition to the normal gaming state by misunderstanding the bell pressing order, It is configured to shift again to the ART ready state when the “game 05” is established (if the bonus is established in the ART state, then the “regame 06” is established and then the state is again shifted to the ART state. ). It should be noted that the transition from the normal game state to the ART ready state is made by winning a “re-game 05”, and the transition from the ART ready state to the ART state is made by winning a “re-game 06”. The state is shifted from the state to the normal gaming state by winning “re-game 03 or re-game 04” or by an incorrect answer of the bell pushing order (when 9 tickets are not paid out). That is, all the gaming states shown above are managed on the main control board M side (especially based on the data in the first ROM / RAM area), and in the conventional revolving game machine, on the sub control board S side. All of the so-called AT functions (including the push order navigation function) that were controlled in step 1 have been transferred to the main control board M side (all information relating to the game is managed on the main control board M side). become.

<Processing in the first ROM / RAM area>
Next, FIG. 48 is a flowchart of timer interrupt processing according to the subroutine of step 1600 in the third embodiment. The difference from the present embodiment is Step 1656 (third) to Step 1660 (third), Step 3450 (third), Step 3500 (third) and Step 1662 (third). It is to be possible to transmit information relating to the ball-out from the main control board M side to the outside of the rotary type gaming machine. That is, after executing the reel drive control process for all reels in step 1612, in step 1656 (third), the CPUC 100 determines that the counter value of the ART counter M60 is greater than 0 based on the data in the first ROM / RAM area. It is determined whether or not. In the case of Yes in step 1656 (third), in step 1658 (third), the CPUC 100 determines the number of remaining ART games (the ART counter M60) in the ART counter value display device D280 based on the data in the first ROM / RAM area. Counter value) is displayed, and the process proceeds to step 1614. On the other hand, also in the case of No in step 1656 (third), the process proceeds to step 1614. In the third embodiment, the ART remaining game number is displayed on the ART counter value display device D280 when the counter value of the ART counter M60 is larger than 0. However, the remaining ART number is only in the ART state. May be configured to be displayed.

<Processing in the first ROM / RAM area>
Further, after outputting an external signal in step 1628 (which is a signal output to a so-called external output terminal board and is separate from the program for the ball test described in detail later), in step 1660 (third), the CPUC 100 Calls the test signal output processing of the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 3450 (third).

<Processing in the second ROM / RAM area>
Next, in step 3450 (third), the CPUC 100 executes a first test signal output process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 3500 (third), the CPUC 100 executes a second test signal output process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1662 (third), the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1630. In the third embodiment, when the timer measurement in step 1606 is executed, 1 is subtracted from the conditional device output time of the output time timer M80 set in step 3208 (that is, the timer interrupt interval). = In about 2 ms, 1 is subtracted from the count value of the output time timer M80).

<Processing in the second ROM / RAM area>
Next, FIG. 49 is a flowchart of first test signal output processing according to the subroutine of step 3450 (third) in FIG. 48 in the third embodiment. First of all, the roll-out test in the spinning-type game machine is performed by connecting the actual machine of the rotary-type game machine for which a roll-out test has been applied and the roll-out test machine to each other via a relay board (hereinafter referred to as a test board) The ball-out test is carried out by extracting the actual operation contents of the trunk type game machine with the ball-out tester. Conventionally, the information on the result of the internal lottery and the game state is information on the push order navigation (especially the stop button D40) while taking the transmission path from the main control board M → the first test board → the output test machine. (Information relating to the operation order and operation timing) takes a transmission path from the sub-control board S → the second test board → the output testing machine. When configured as in the third embodiment, as described above, all the information relating to the appearance of balls is managed on the main control board M side. It is also possible to further refine the information transmitted to the machine. Therefore, an example of the information output control method to the ball tester (test board) when configured as in the third embodiment is shown as the first test signal output process and the second test signal output process below. To do. In the embodiment shown below, both the first test board and the second test board are configured so that these boards are not controlled by the microcomputer, that is, the information output contents and information output timing that can be recognized by the ball tester side. In this example, the main control board M is output from the main control board M (however, when these boards are controlled by a microcomputer, the main control board M is compared with the test board side and the ball tester side. The raw data of the information to be output to the output may be output in a lump, and adjusted and output on the test board side so that the information output content and the information output timing that can be recognized by the ball tester side may be output).

  First, in step 3452, the CPUC 100 temporarily stores the operation state information in the first RAM area in the register area (for example, A register) based on the data in the second ROM / RAM area. Next, in step 3454, the CPUC 100 outputs the operating state information temporarily stored in the register area (for example, A register) to the first test board based on the data in the second ROM / RAM area (for example, main memory). The value of the A register is set to the first output port which is the output port to the first test board in the control board M). Here, the upper right part of the figure is an example of the operating state information, and as shown in the figure, “D0” to “D7” are “1” (actuated) or “0” (not actuated). It is possible to manage the gaming state (operating state). Note that the operating state information is not limited to this, and for example, “Type 2 BB” (a so-called second-type special accessory continuous action device), “CB” (a so-called Type 2 special accessory), for example. , “SB” (so-called ordinary actor), “ART internal winning state” (flag state of the internal ART winning flag in the third embodiment), “ART operating state” (in the third embodiment Various operation states to be transmitted to the first test board such as “count value of ART counter M60 being larger than 0)”, “pseudo game (reel driving as an effect, etc.)” may be provided. In the third embodiment, the operation state information is configured to transmit the information related to “RB” (so-called first type special object) to the first test board. However, the third embodiment relates to the third embodiment. The rotating type gaming machine is configured such that when “1 type BB” is activated, “RB” is automatically activated (so-called 1 type BB continuous operation of RB). In the example, when “sheep”, “seven”) is displayed, “RB” is also activated (operation state information relating to “RB” is set to “1”), and a test signal indicating that “RB” is activated Is transmitted to the first test board. In addition, “RB” has an end condition {for example, 8 wins or 12 games (games) end}, and after “RB” is ended, the operation state information related to “RB” is displayed. It is set to “0” for a predetermined time (for example, 6 interrupts). Thereafter, when the termination condition of “1 type BB” is not satisfied (“1 type BB” continues to operate), the operation state information related to “RB” is set to “1” again. With this configuration, it is possible to determine whether or not the testing machine satisfies the rule relating to the termination condition of “RB” through the test signal transmitted to the first test board.

<Processing in the second ROM / RAM area>
Next, in step 3456, the CPUC 100 is configured so that the timer value of the output time timer M80 in the first RAM area is set to 0 when the output timing of the conditional device information ends based on the data in the second ROM / RAM area. Is temporarily stored in a register area (for example, A register). Next, in step 3458, the CPUC 100 determines whether it is the output timing of the conditional device information based on the data in the second ROM / RAM area (the determination is based on the timer value of the output time timer M80, No. In this case, all the A registers contain “0”). In the case of Yes in step 3458, in step 3460, based on the data in the second ROM / RAM area, the CPUC 100 uses the bonus state information address (2834 in this example) as the condition device information in the register area (for example, the HL register). Temporarily store. Next, in Step 3462, the CPUC 100 determines whether or not it is the output timing of the bonus state information based on the data in the second ROM / RAM area [for example, from the value related to the output time timer value information of the A register. It is determined whether the value obtained by subtracting {(23/2) +1}) is greater than 0]. If Yes in step 3462, the process proceeds to step 3466. On the other hand, in the case of No in step 3462, in step 3464, based on the data in the second ROM / RAM area, the CPUC 100 sets the small role state information address (2833 in this example) as the condition device information in the register area (for example, Temporarily stored in the HL register), and the process proceeds to step 3466 (the value obtained by subtracting the lower 8 bits of the bonus state information from “−1” is the small combination state information address). Next, in step 3466, the CPUC 100 sets the conditional device information corresponding to the address temporarily stored in the register area (for example, HL register) based on the data in the second ROM / RAM area to another register area (for example, The data is temporarily stored in the A register), and the process proceeds to step 3468. In the case of No in step 3458, the process proceeds to step 3468. Next, in step 3468, the CPUC 100 outputs the condition device information temporarily stored in the register area (for example, A register) to the first test board based on the data in the second ROM / RAM area (for example, main memory). The value of the A register is set in the second output port which is the output port to the first test board in the control board M), and the process proceeds to the next process {step 3500 (third) process}. Here, the lower right part of the figure is an example of the condition device information. As shown in the figure, with respect to “D0” to “D5”, the condition device number that becomes the lottery result in the game by the above-described processing. Is set. Further, in the case of small role status information, “D6” is set to “1” and “D7” is set to “0”, and in the case of bonus status information, “D7” is set to “0” and “D6”. “1” is set, and the information output in step 3468 is configured to be able to determine which condition device information is a small combination or bonus (on the tester side). Although not shown, in the third embodiment, in a game, when a bonus is won before the game (inside), the bonus that has been won is displayed in the bonus state. The information is output to the first test board. In the third embodiment, the address (2834) storing the bonus status information and the address (2833) storing the small combination status information are adjacent to each other. For this reason, in the third embodiment, after the bonus state information address is stored in the HL register, when the small role state information is output, the value of the HL register is simply set to “−1”. Can be output. In the third embodiment, the bonus status information is stored in the HL register. However, the small bonus status information may be stored in the HL register. It may be an address of information. With this configuration, it is possible to specify an address where information to be output is stored with a small number of logical operations.

  Note that the output time timer M80 and the information related to the timer value are always output in step 3468, which is processing at the time of interruption. In the game progress control processing, from the start of rotation of the reel M50 related to the previous game. The minimum time (the time that must be guaranteed at least from the rotation start timing of the reel M50 related to a certain game to the rotation start timing of the reel M50 related to the next game is 4.1 seconds in this example) By setting the condition device information output time (24 interrupts in this example) to the output time timer M80 in step 3208, which is the elapsed timing (optimum output start timing of the condition device information), the interrupt immediately after the set timing By the process of step 3468 which is a time process, the first test base is performed at an appropriate timing. And it is configured to output condition device information. Also, the conditional device information output time (24 interrupts in this example) set in the output time timer M80 in step 3208 is decremented by 1 for each interrupt, and {( 23/2) +1}) is greater than 0 (when it is the first half of the period until the timer value becomes “0”), bonus state information is output and the output time timer M80 When the value obtained by subtracting {(23/2) +1}) from the timer value is smaller than 0 (in the latter half of the period until the timer value becomes “0”), the small role status information is output. It is configured so that the timer value of the output time timer M80 becomes 0 when the output time of the small combination state information ends (the output time of the condition device ends). With this configuration, when the output timing timer value information is set in the A register when the OFF signal related to the conditional device information is output after the output timing of the conditional device information ends, all “0” is stored in the A register. The OFF signal related to the condition device information can be output without having a fixed value for setting "", and the OFF signal related to the condition device information can be output by the simplified processing. The condition device information output time (24 interrupts in this example) is set in the output time timer M80 immediately after the game interval minimum time timer value becomes 0 in step 3204, that is, the minimum time (there is This is the time that must be guaranteed at least from the rotation start timing of the reel M50 related to the game to the rotation start timing of the reel M50 related to the next game. In this example, immediately after 4.1 seconds) Since the timing is configured, the minimum game time can be obtained by simplified processing using the output time timer M80 without newly providing a means for outputting a signal guaranteeing the minimum time to the first test board. It is possible to execute a test that guarantees the above.

<Processing in the second ROM / RAM area>
Next, FIG. 50 is a flowchart of second test signal output processing according to the subroutine of Step 3500 (third) in FIG. 48 in the third embodiment. First, in step 3508, the CPUC 100 determines whether it is the output timing of the operation mode information (for example, 2 seconds from the start of rotation of the reel M50) based on the data in the second ROM / RAM area. In the case of Yes in step 3508, in step 3510, the CPU C 100 determines whether or not the push order information is displayed on the push order display device D270 based on the data in the second ROM / RAM area (displays on the push order display device D270). Whether or not the information related to the pressing order is stored in the first RAM area) (or if the pressing order information is temporarily stored in the first RAM area, refer to the pressing order information). . In the case of Yes in step 3510, in step 3550 (third), the CPUC 100 executes signal control processing with push order navigation described later based on the data in the second ROM / RAM area, and proceeds to step 3512. On the other hand, in the case of No in step 3510, in step 3600 (third), the CPUC 100 executes signal control processing without push order navigation, which will be described later, based on the data in the second ROM / RAM area, and proceeds to step 3512. To do. In the case of No in step 3508, the process proceeds to step 3512. Next, in step 3512, the CPUC 100, based on the data in the second ROM / RAM area, stores operation mode information temporarily stored in a register area (for example, A register) (The signal set in the signal control process when there is no push order navigation) is output to the second test board (for example, the value of the A register is set to the third output port which is the output port to the second test board in the main control board M). Set), and the process proceeds to the next process {step 1662 (third) process}. The information transmission / reception method (command communication method) between the main control board M and the second test board may be parallel communication or serial communication.

<Processing in the second ROM / RAM area>
Next, FIG. 51 is a flowchart of the signal control processing when there is a push order navigation according to the subroutine of step 3550 (third) in FIG. 50 in the third embodiment. First, in step 3552, the CPUC 100 determines whether it is currently the first stop operation mode information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3552, in step 3554, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area {most in the game in which the push order navigation is executed. The first stop operation mode information (operation mode information related to the first stop) of the operation mode (push order, stop position, etc.) with a high profit rate for the player is temporarily stored in the register area (for example, the HL register). To do. Next, in step 3556, the CPUC 100 performs the first stop operation of the operation mode information with the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3552, in step 3558, the CPUC 100 determines whether or not it is currently the second stop operation mode information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3558, in step 3560, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area { The second stop operation mode information (operation mode information related to the second stop) of the operation mode (push order, stop position, etc.) with a high profit rate for the player is temporarily stored in the register area (for example, HL register). To do. Next, in Step 3562, the CPUC 100 performs the second stop operation of the operation mode information with the highest machine splitting order stored temporarily in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3558, in step 3564, the CPUC 100 determines whether or not it is currently the third stop operation mode information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3564, in step 3566, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area {most in the game in which the push order navigation is executed. The third stop operation mode information (operation mode information related to the third stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in the register area (for example, the HL register). To do. Next, in step 3568, the CPUC 100 performs the third stop operation of the operation mode information with the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512). Even in the case of No in step 3564, the processing shifts to the next processing (processing in step 3512). Here, in the third embodiment, the order of operation mode information output timing when there is push order navigation is “first stop operation mode information output timing → second stop operation mode information output timing → third stop operation mode information”. The order is “output timing”.

<Processing in the second ROM / RAM area>
Next, FIG. 52 is a flowchart of the signal control process when no push order navigation is performed according to the subroutine of step 3600 (third) in FIG. 50 in the third embodiment. First, in step 3602, the CPUC 100 determines whether it is currently the first stop operation mode information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3602, in step 3604, based on the data in the second ROM / RAM area, the CPUC 100 determines the highest machine splitting order no operation mode information in the second ROM area {the most game in the game in which the pushing order navigation is not executed. The operation mode (push order, stop position, etc.) has a high profit rate for the player, but if the player does not display the push order navigation, the established condition device and the push order cannot be determined. The first stop operation mode information (operation mode information related to the first stop) address of {which will execute the optimal operation mode} is temporarily stored in a register area (for example, HL register). Next, in Step 3606, the CPUC 100 performs the first stop operation of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3602, in step 3608, the CPUC 100 determines based on the data in the second ROM / RAM area whether the current timing is the second stop operation mode information output timing. In the case of Yes in step 3608, in step 3610, based on the data in the second ROM / RAM area, the CPUC 100 determines the highest machine split order operation mode information in the second ROM area {most game in the game in which the push order navigation is not executed. The operation mode (push order, stop position, etc.) has a high profit rate for the player, but if the player does not display the push order navigation, the established condition device and the push order cannot be determined. The second stop operation mode information (operation mode information related to the second stop) address of {which will execute the optimal operation mode} is temporarily stored in the register area (for example, the HL register). Next, in step 3612, the CPUC 100 performs the second stop operation of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3608, in step 3614, based on the data in the second ROM / RAM area, the CPUC 100 determines whether it is currently the third stop operation mode information output timing. In the case of Yes in step 3614, in step 3616, based on the data in the second ROM / RAM area, the CPUC 100 determines the highest machine splitting order no operation mode information in the second ROM area {most game in the game in which the pushing order navigation is not executed The operation mode (push order, stop position, etc.) has a high profit rate for the player, but if the player does not display the push order navigation, the established condition device and the push order cannot be determined. The third stop operation mode information (operation mode information related to the third stop) address of {which will execute the optimal operation mode} is temporarily stored in the register area (for example, the HL register). Next, in Step 3616, the CPUC 100 performs the third stop operation of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512). Even in the case of No in step 3614, the processing shifts to the next processing (processing in step 3512). Here, in the third embodiment, the order of the operation mode information output timing when there is no push order navigation is “first stop operation mode information output timing → second stop operation mode information output timing → third stop operation mode information”. The order is “output timing”. In the third embodiment, the operation mode information is output to the second test board at the timing after the condition device information is output to the first test board. However, the operation mode information is output to the second test board. You may comprise so that condition apparatus information may be output to a 1st test board | substrate at the timing after outputting.

<Processing in the second ROM / RAM area>
Next, FIG. 53 is an operation mode information list in the third embodiment. In the third embodiment, the operation mode information with the highest machine split order is determined in the same order as the push order displayed on the push order display device D270 (in which position the stop button D40 is operated). If it can be stopped, it is configured to execute a method of operating the stop button D40). Further, the operation mode information without the highest machine split order is all in the order of “left → middle → right”, and when the bonus is not established, the first stop is “left 19” (the left reel M51 No. 19 is the left stop button D41 is operated at the lower timing), and when the watermelon is established, the second stop is “middle 5” (the fifth of the middle reel M52 is at the lower timing). The middle stop button D42 is operated), and the third stop is “Right No. 3” (No. 3 of the right reel M53 operates the right stop button D43 at the lower timing), and the watermelon is established. When there is no, the second stop is free hitting the middle reel M52, and the third stop is free hitting the right reel M53. On the other hand, when the bonus is established, the established bonus symbol is configured to operate the stop button D40 at the upper timing, and when the bonus is established by operating in this way, Then, it is configured to immediately arrange (start) the established bonuses. Further, the contents of the operation mode information to be specifically transmitted are information relating to the reel (pressing order) to be stopped by the upper 3 bits, and information relating to the position to be stopped by the lower 5 bits. For example, in the left reel, the upper 3 bits are “001”, and “18” is “10010” when the stop button D40 is operated at the lower timing, and “11111” when the free play is made. In addition, the output example of the operation mode information relating to one game is, for example, when the left-to-right-to-middle push-order bells are aligned (in the case of a bell, winning can be won regardless of all reel stop positions) Includes a first stop signal (first stop operation mode information): “00111111”, a second stop signal (second stop operation mode information): “01111111”, and a third stop signal (third stop operation mode information). Information): “0101111”. Also, when the cherry replays for the first stop of the left reel are arranged (in the case of cherry replays, a winning can be won regardless of all reel stop positions), a first stop signal (first stop operation mode information) : “00111111”, second stop signal (second stop operation mode information): “01011111”, third stop signal (third stop operation mode information): “01111111”. In the third embodiment, the type of the stop reel is indicated by the upper 3 bits. For example, “01” indicates “left reel M51”, “10” indicates “middle reel M52”, and “11” indicates “ It is possible to express the upper 2 bits as in the case of the right reel M53, and in this case, the information related to the position to be stopped may be expressed in the lower 6 bits.

  With the configuration as described above, according to the rotary type gaming machine according to the third embodiment, the process for controlling the signal output to the first test board and the second test board is changed to the process in the second ROM / RAM area. By executing the above, processing that is not necessary when the player plays the gaming machine actually installed in the game hall, that is, processing that does not interfere with the progress of the game, can be implemented in the second program area. Thus, the used capacity of the first program area can be reduced.

  Further, according to the swivel type gaming machine according to the third embodiment, the condition device information output time is set after the minimum game interval time (4.1 seconds in this example) has elapsed, and the first At the time of output to one test board, the output timing of the small role state information and bonus state information is determined with reference to the condition device information output time. When the output time timer value is 0, the A register is set to “0”. When the type test is executed by the first test board, the test that guarantees the minimum game time can be executed by the simplified processing.

  In the third embodiment, the condition device information can be transmitted to the sub side (sub control board S side) in the interrupt processing after the timing when the condition device information is set in the first RAM area. , “Elapsed minimum game interval time → Set minimum game interval time in game interval minimum time timer M70 → Set conditional device information output time in output time timer M80”. The condition apparatus information can be transmitted, and the condition control information transmission timing can be different between the sub-control board S and the first test board.

(Modification 1 from the third embodiment)
In the third embodiment, as the condition device information to be output to the first test board, the identification value (small role identification value, bonus identification value) relating to which timing device information is output is the first. By the processing in the program area, the output signal to the second test board is controlled in a form that is temporarily stored in the first RAM area and corresponding to the push order navigation by the push order display device D270 executed in the first program area. However, the configuration for controlling the signals output to the first test board and the second test board in the second program area is not limited to this. Therefore, an example of such processing is referred to as a first modification from the third embodiment, and changes from the third embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 54 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in FIG. 9 in Modification 1 from the third embodiment. The change from the third embodiment is step 1294 (third variation 1), that is, after executing the game state transition control process in step 3400 (third), in step 1294 (third variation 1), Based on the data in the first ROM / RAM area, the CPUC 100 turns off the winning order navigation {the flag that is turned on in step 3176 (third modification 1)}, and proceeds to step 1292.

<Processing in the first ROM / RAM area>
Next, FIG. 55 is a flowchart of the push order navigation control process according to the subroutine of Step 3150 (third) in FIG. 54 in Modification 1 from the third embodiment. The change from the third embodiment is step 3176 (third variation 1), that is, if the push-order navigation lottery is won in step 3160, the CPUC 100 determines that the first ROM is the first ROM in step 3176 (third variation 1). Based on the data in the RAM area, the push order navigation winning flag is turned on, and the flow proceeds to step 3163. With this configuration, in the first modification from the third embodiment, when the push order navigation lottery is won and the push order navigation is executed, the second test is performed without referring to the push order display device D270. It is possible to transmit information related to the order of pressing to the substrate (details will be described later).

<Processing in the second ROM / RAM area>
Next, FIG. 56 is a flowchart of first test signal output processing according to the subroutine of step 3450 (third) in FIG. 48 in Modification 1 from the third embodiment. Changes from the third embodiment are step 3464 (third variation 1), step 3470 (third variation 1) to step 3476 (third variation 1), that is, output of bonus state information at step 3462. If it is the timing, in step 3464 (third modification 1), the CPUC 100 temporarily stores the condition device information address of the bonus state information in the register area (for example, the HL register) based on the data in the second ROM / RAM area. To do. Next, in step 3466, the CPUC 100 sets the condition device information address of the bonus state information temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area to another register area ( For example, it is temporarily stored in the A register). Next, in step 3470 (third variation 1), the CPUC 100 rewrites the register area (for example, “D6” and “D7” in the A register) with bonus identification values based on the data in the second ROM / RAM area. (Rewrite “D6” to “0” and “D7” to “1”).

<Processing in the second ROM / RAM area>
If it is not the output timing of the bonus status information in step 3462, in step 3472 (third variation 1), the CPUC 100 determines the condition device information address of the small role status information based on the data in the second ROM / RAM area. Is temporarily stored in a register area (for example, HL register). Next, in step 3474 (third change 1), the CPUC 100, based on the data in the second ROM / RAM area, the condition device information address of the small combination status information temporarily stored in the register area (for example, the HL register). Are temporarily stored in another register area (for example, the A register). Next, in step 3476 (third change 1), the CPUC 100 rewrites the register area (for example, “D6” and “D7” of the A register) to the small role identification value based on the data in the second ROM / RAM area. (Rewrite “D6” to “1” and “D7” to “0”), and proceed to Step 3468. The storage area for condition device information (internal lottery result, etc.) related to the progress of the game and the storage area for condition device information for output to the test board may be provided separately, or the storage area for the condition device information. May also be used. With this configuration, the storage area of the first RAM area can be reduced.

<Processing in the second ROM / RAM area>
Next, FIG. 57 is a flowchart of second test signal output processing according to the subroutine of Step 3500 (third) in FIG. 48 in Modification 1 from the third embodiment. The change from the third embodiment is step 3650 (third variation 1), that is, if it is the output timing of the operation mode information in step 3508, step 3650 (third variation 1) will be described later. Operation mode information control processing is executed, and the process proceeds to step 3512.

<Processing in the second ROM / RAM area>
Next, FIG. 58 is a flowchart of the operation mode information control process according to the subroutine of Step 3650 (third) in FIG. 57 in Modification 1 from the third embodiment. First, in step 3652, the CPUC 100 determines whether or not the counter value of the ART counter M60 is greater than 0, in other words, whether or not it is in the ART state, based on the data in the second ROM / RAM area. If Yes in step 3652, the process moves to step 3656. On the other hand, in the case of No in step 3652, in step 3654, the CPUC 100 determines based on the data in the second ROM / RAM area whether or not it is currently in the ART ready state. In the case of Yes in step 3654, in step 3656, based on the data in the second ROM / RAM area, the CPUC 100 adds the condition device related to the game in the order of pushing (in the ART game by correctly answering the pushing order in the ART state). It is a conditional device to which the number is added, and in this example, it is determined whether or not it is cherry replay). In the case of Yes in step 3656, in step 3658, the CPUC 100 determines whether or not the push order navigation winning flag is on based on the data in the second ROM / RAM area. In the case of Yes in step 3658, in step 3550 (third variation 1), the CPUC 100 executes signal control processing with push-order navigation described later based on data in the second ROM / RAM area, and performs the following processing ( The process proceeds to step 3512. On the other hand, in the case of No in step 3656, in step 3660, based on the data in the second ROM / RAM area, the CPUC 100 determines that the conditional device related to the game has a pushing order (the player's profit rate varies depending on the pushing order). It is determined whether or not it is a conditional device). In the case of Yes in step 3660, in other words, if the game condition device is not replay 03, 04, 06 or bell, in step 3600 (third variation 1), the CPUC 100 is in the second ROM / RAM area. Based on the data, a signal control process without push order navigation, which will be described later, is executed, and the process proceeds to the next process (the process of step 3512). In addition, also in the case of No in step 3658, the process proceeds to step 3600 (third variation 1).

<Processing in the second ROM / RAM area>
In the case of No in step 3654, in step 3662, the CPUC 100 determines based on the data in the second ROM / RAM area, the internal ART winning flag (the flag turned on in step 3166, and the transition to the ART state is performed). It is determined whether or not (a flag that is turned on when deterministic) is on. In the case of Yes in step 3662, in step 3664, based on the data in the second ROM / RAM area, the CPUC 100 determines that the condition device related to the game is in the ready state transition replay (replay that can transition from the normal game state to the ART ready state). It is a game, and in this example, it is determined whether or not it is a replay 05). In the case of Yes in Step 3664, in Step 3550 (Third Modification 1), the CPUC 100 executes signal control processing with push order navigation described later based on the data in the second ROM / RAM area, and performs the following processing ( The process proceeds to step 3512. If No in step 3660, the process proceeds to step 3550 (third change 1). Further, in the case of No in step 3662 or step 3664, the processing shifts to the next processing (processing in step 3512).

<Processing in the second ROM / RAM area>
Next, FIG. 59 is a flowchart of the signal control processing when there is push order navigation according to the subroutine of Step 3550 (third variation 1) in FIG. 50 in Modification 1 from the third embodiment. First, in step 3570, the CPUC 100 determines whether it is currently the first stop reel information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3570, in step 3572, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area {most in the game in which the push order navigation is executed. The first stop reel information (reel information related to the first stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in a register area (for example, HL register). Next, in step 3574, the CPUC 100, based on the data in the second ROM / RAM area, temporarily stores in the register area (for example, the HL register), the first stop reel of the operation mode information with the highest machine splitting order. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3570, in step 3576, the CPUC 100 determines whether it is currently the first stop step information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3576, in step 3578, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine split order operation mode information in the first RAM area { The first stop step information (step information related to the first stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in a register area (for example, HL register). Next, at step 3580, the CPUC 100 first stops the operation mode information with the highest machine split order stored temporarily in the register area (for example, HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3576, in step 3582, the CPUC 100 determines whether it is currently the second stop reel information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3582, in step 3583, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area {most in the game in which the push order navigation is executed. The second stop reel information (reel information related to the second stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in a register area (for example, HL register). Next, in step 3584, the CPUC 100, based on the data in the second ROM / RAM area, temporarily stores in the register area (for example, the HL register), the second stop reel of the operation mode information with the highest machine splitting order. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3582, in step 3585, based on the data in the second ROM / RAM area, the CPUC 100 determines whether it is currently the second stop step information output timing. In the case of Yes in step 3585, in step 3586, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine split order operation mode information in the first RAM area { The second stop step information (step information related to the second stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in a register area (for example, HL register). Next, in step 3588, the CPUC 100 performs the second stop step of the operation mode information with the highest machine splitting order stored temporarily in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3585, in step 3589, the CPUC 100 determines whether it is currently the third stop reel information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3589, in step 3590, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine split push order operation mode information in the first RAM area {most in the game in which the push order navigation is executed. The third stop reel information (reel information related to the third stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in the register area (for example, the HL register). Next, in step 3592, the CPUC 100 determines the third stop reel of the operation mode information with the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3589, in step 3594, the CPUC 100 determines whether or not it is currently the third stop step information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3594, in step 3596, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order operation mode information in the first RAM area { The third stop step information (step information related to the third stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the player is temporarily stored in a register area (for example, HL register). Next, in step 3598, the CPUC 100 performs the third stop step of the operation mode information with the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512). Even in the case of No in step 3594, the processing shifts to the next processing (processing in step 3512). As described above, in the first modification from the third embodiment, the information about the stop reel and the information about the stop step (stop position) are transmitted separately, and the output timing is “first stop reel information → first The order is “stop step information → second stop reel information → second stop step information → third stop reel information → third stop step information”.

<Processing in the second ROM / RAM area>
Next, FIG. 60 is a flowchart of the signal control processing at the time of no push order navigation according to the subroutine of Step 3600 (third variation 1) in FIG. 50 in Modification 1 from the third embodiment. First, in step 3620, the CPUC 100 determines whether it is currently the first stop reel information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3570, in step 3622, based on the data in the second ROM / RAM area, the CPUC 100 is the highest machine splitting order no operation mode information in the second ROM area {most game in the game in which the pushing order navigation is not executed. The first stop reel information (reel information related to the first stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the user is temporarily stored in the register area (for example, the HL register). Next, in step 3624, the CPUC 100 first stores the highest machine splitting order no operation mode information first stop reel temporarily stored in the register area (for example, HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3620, in step 3626, the CPUC 100 determines whether or not it is currently the first stop step information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3626, in step 3628, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order no operation mode information in the second ROM area {most game in the game in which the pushing order navigation is not executed. The first stop step information (step information related to the first stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the user is temporarily stored in a register area (for example, HL register). Next, in Step 3630, the CPUC 100 performs first stop step of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3626, in step 3632, the CPUC 100 determines based on the data in the second ROM / RAM area whether or not it is currently the second stop reel information output timing. In the case of Yes in step 3632, in step 3634, the CPUC 100 determines the highest machine split push order no operation mode information in the second ROM area based on the data in the second ROM / RAM area {most game in the game in which push order navigation is not executed. The second stop reel information (reel information related to the second stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the user is temporarily stored in the register area (for example, the HL register). Next, in step 3636, the CPUC 100 determines the second stop reel of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3632, in step 3638, the CPUC 100 determines whether it is currently the second stop step information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3638, in step 3640, based on the data in the second ROM / RAM area, the CPUC 100 is the highest machine splitting order no operation mode information in the second ROM area. The second stop step information (step information related to the second stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the user is temporarily stored in the register area (for example, the HL register). Next, in step 3641, the CPUC 100 performs the second stop step of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3538, in step 3642, the CPUC 100 determines whether or not it is currently the third stop reel information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3642, in step 3643, based on the data in the second ROM / RAM area, the CPUC 100 determines the highest machine splitting order no operation mode information in the second ROM area {most game in the game in which the pushing order navigation is not executed. The third stop reel information (reel information related to the third stop) address of the operation mode (push order, stop position, etc.) having a high profit rate for the user is temporarily stored in the register area (for example, the HL register). Next, in step 3644, the CPUC 100 determines the third stop reel of the operation mode information with the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
On the other hand, in the case of No in step 3642, in step 3645, the CPUC 100 determines whether or not it is currently the third stop step information output timing based on the data in the second ROM / RAM area. In the case of Yes in step 3645, in step 3646, based on the data in the second ROM / RAM area, the CPUC 100 has the highest machine splitting order no operation mode information in the second ROM area {most game in the game in which the pushing order navigation is not executed. The third stop step information (step information related to the third stop) address of the operation mode (push order, stop position, etc.) with a high profit rate for the user is temporarily stored in a register area (for example, HL register). Next, in step 3648, the CPUC 100 performs the third stop step of the operation mode information without the highest machine splitting order temporarily stored in the register area (for example, the HL register) based on the data in the second ROM / RAM area. Information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512). Even in the case of No in step 3645, the processing shifts to the next processing (processing in step 3512). As described above, in the first modification from the third embodiment, the information about the stop reel and the information about the stop step (stop position) are transmitted separately, and the output timing is “first stop reel information → first The order is “stop step information → second stop reel information → second stop step information → third stop reel information → third stop step information”.

<Processing in the second ROM / RAM area>
Next, FIG. 61 is an operation mode information list in the first modification from the third embodiment. Regarding the contents of the operation mode information to be specifically transmitted in the first modification from the third embodiment, the stop reel information is information consisting of 3 bits, and for example, the left reel is “001”. The stop step information is 9-bit information. For example, the stop step information is stopped at the timing of driving 65 steps from the state where the reference position of the reel M50 (for example, the position at the boundary between No. 0 and No. 19) is at the bottom of the lower stage. When the button is operated, “001000001” is set, and when free-handed, “111111111” is set. Note that the stop step information in this example is merely an example, and if the stop position of the reel M50 can be determined by the stop step information, there is no problem and the reference position of the reel M50 (for example, the position at the boundary between No. 0 and No. 19). Is not limited to the step information related to the amount of driving from the lowermost state of the lower stage, and is driven from the state where the reference position of the reel M50 (for example, the position of the boundary between No. 0 and No. 19) is the lowermost part of the middle stage. There is no problem with the step information relating to the amount that has been driven, or the step information relating to the portion that has been driven from a state where the reference position of the reel M50 (for example, the position of the boundary between No. 0 and No. 19) is at the bottom of the upper stage. There is no problem with the step information relating to the amount of driving from the state where the reference position (for example, the position between the 0th and 19th boundaries) is at the top of the upper stage. In addition, the output example of the operation mode information relating to one game is, for example, when pressing the right-to-left-to-middle push order bells (in the case of a bell, it is possible to win a free game regardless of all reel stop positions). When there is push order navigation, the most significant bit of stop step information is added to the first stop reel information: “01100001”, first stop step information: “11111111”, stop at the second stop reel information The most significant bit of the step information is added: “00100001”, the second stop step information: “11111111”, and the most significant bit of the stop step information is added to the third stop reel information: “01000001”, the third stop step information : “11111111”, and when there is no push order navigation, the most significant bit of stop step information is added to the first stop reel information: “0010 001 ”, first stop step information:“ 11111111 ”, most significant bit of stop step information added to second stop reel information:“ 01000001 ”, second stop step information:“ 11111111 ”, third stop reel information The most significant bit of the stop step information is added: “01100001”, and the third stop step information: “11111111”. Thus, in the first modification from the third embodiment, “first signal: upper 3 bits are the type of stop reel, lower 1 bit is the upper step number”, “second signal: 8 bits are lower By transmitting the information related to the stop of one reel as the “step number”, the information related to the stop reel and the stop step can be transmitted.

  By configuring as described above, according to the rotating game machine according to Modification 1 from the third embodiment, any condition device information is output as the condition device information to be output to the first test board. Are temporarily stored in the register area by processing in the second program area, and the second program area regardless of the push order navigation in the first program area. By controlling the output signal to the second test board at, the processing related to the signal output to more test boards than in the third embodiment can be executed in the second program area, and more The used capacity of the first program area can be reduced.

(Modification 2 from the third embodiment)
In the first modification from the third embodiment, as operation mode information to be output to the second test board, information on the reel to be stopped and information on the stop position of the reel are all stopped (first stop to first stop). However, the output mode of the operation mode information to the second test board is not limited to this. Further, the information output to the sub control board S may be different from the information output to the first test board. Therefore, the configuration is the output mode of the operation mode information to the second test board and the output mode of the condition device information to the sub-control board S different from the third embodiment and / or the modified example 1 from the third embodiment. The second modification from the third embodiment will be described below, and the modification from the third embodiment or the first modification from the third embodiment will be described in detail below.

<Processing in the second ROM / RAM area>
First, FIG. 62 is a flowchart of the game progress control process (second sheet) according to the subroutine of Step 1200 in FIG. 9 in Modification 2 from the third embodiment. Changes from the third embodiment are step 1296 (third variation 2) and step 1257-1 (third variation 2). That is, after the internal lottery is executed in step 1257, step 1296 (third variation 2). In 2), the CPUC 100, based on the data in the first ROM / RAM area, commands related to the lottery result of the internal lottery and the condition device identification value (bonus identification value, small role identification value, etc.) Is temporarily stored in the first RAM area. Next, in step 1257-1 (third variation 2), the CPUC 100, based on the data in the first ROM / RAM area, the lottery result of the internal lottery for output to the first test board and the condition device identification value (bonus Identification value, small role identification value, etc.) are temporarily stored in the first RAM area. Here, the upper right part of the figure is an example of condition device information for output to the sub-side. As shown in the figure, in the second modification from the third embodiment, the condition device information for output to the first test board and the condition device information for output to the sub-side are stored at different addresses. ing. Further, the condition device information for output to the first test board and the condition device identification value (bonus identification value, small role identification value, etc.) to the first test board are stored at the same address (“D0”). To “D5” is condition device information, and “D6” to “D7” are condition device identification values), the condition device information for output to the sub side and the condition device for output to the sub side It is stored at an address different from the identification value (bonus identification value, small role identification value, etc.).

<Processing in the second ROM / RAM area>
Next, FIG. 63 is a flowchart of processing at the time of timer interruption according to the subroutine of Step 1600 in Modification 2 from the third embodiment. The change from the third embodiment is step 1664 (third variation 2), that is, after transmitting the control command (command to the sub side) in step 1626, in step 1664 (third variation 2), Based on the data in the first ROM / RAM area, the CPUC 100 uses the internal lottery result and the condition device identification value (bonus identification value, small role identification value, etc.) set in step 1296 (third variation 2). The command (command to the sub side) is transmitted, and the process proceeds to Step 1628. It should be noted that the transmission timing of the command related to the lottery result of the internal lottery to the sub side and the condition device identification value (bonus identification value, small role identification value, etc.) While the timer interrupt process, the command transmission timing related to the lottery result of the internal lottery to the first test board and the condition device identification value (bonus identification value, small role identification value, etc.) is immediately after the execution of the process of step 3208. Timer interruption processing, and the transmission timing of the command related to the lottery result of the internal lottery relating to a certain game and the condition device identification value (bonus identification value, small role identification value, etc.) is the transmission timing to the sub side The timing is earlier than the transmission timing to the first test board.

<Processing in the second ROM / RAM area>
Next, FIG. 64 is a flowchart of the signal control processing when there is push order navigation according to the subroutine of step 3550 (third variation 1) in FIG. 50 in Modification 2 from the third embodiment. Changes from the first modification from the third embodiment are step 3599-1 (third modification 2) to step 3599-3 (third modification 2), and the purpose thereof is the stop reel on the second test board. Without outputting the information, the reel stop order information is output, and the reel stop order is output all three times by outputting the information once, that is, in step 3599-1 (third variation 2). The CPUC 100 determines based on the data in the second ROM / RAM area whether or not it is the current reel stop order information output timing. In the case of Yes in step 3599-1 (third modification 2), in step 3599-2 (third modification 2), the CPUC 100 determines the highest machine discount in the first RAM area based on the data in the second ROM / RAM area. Ordered operation mode information {reel stop order information address of the operation mode (push order, stop position, etc.) having the highest profit rate for the player in the game in which the push order navigation is executed} ) Temporarily. Next, in step 3599-3 (third modification 2), the CPUC 100 has the highest machine discount order temporarily stored in the register area (for example, HL register) based on the data in the second ROM / RAM area. The reel stop order information of the operation mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
Next, FIG. 65 is a flowchart of the signal control processing at the time of no push order navigation according to the subroutine of Step 3600 (third variation 1) in FIG. 50 in Modification 2 from the third embodiment. Changes from the first modification from the third embodiment are step 3649-1 (third modification 2) to step 3649-3 (third modification 2), and the purpose is to stop reel on the second test board. It is to output reel stop order information without outputting information, and to output all three reel stop orders by outputting information once, that is, in step 3649-1 (third variation 2). The CPUC 100 determines based on the data in the second ROM / RAM area whether or not it is the current reel stop order information output timing. In the case of Yes in step 3649-1 (third modification 2), in step 3649-2 (third modification 2), the CPUC 100 determines the highest machine discount in the second ROM area based on the data in the second ROM / RAM area. Unreserved operation mode information {Reel stop order information address of operation mode (push order, stop position, etc.) having the highest profit rate for the player in a game where push order navigation is not executed}, register area (for example, HL register) Temporarily store. Next, in step 3649-3 (third modification 2), the CPUC 100, based on the data in the second ROM / RAM area, is temporarily stored in the register area (for example, the HL register), and there is no highest machine discount order. The reel stop order information of the operation mode information is temporarily stored in another register area (for example, A register), and the process proceeds to the next process (the process of step 3512).

<Processing in the second ROM / RAM area>
Next, FIG. 66 is an operation mode information list in the second modification from the third embodiment. Regarding the contents of the operation mode information to be specifically transmitted in the second modification from the third embodiment, the reel stop order information is information consisting of 8 bits. For example, in the push order of “middle → left → right” In this case, “00000010” and “00000000” in the order of “left → middle → right”. The stop step information is 8-bit information, and is configured so that 504 steps are divided every two steps, and information relating to 252 steps can be transmitted. Specifically, when the stop button is operated at the timing of two-step driving from the state where the reference position of the reel M50 (for example, the position of the boundary between the number 0 and the number 19) is the lowermost part of the lower stage, “00000001” ( When the stop button is operated at a timing of driving 64 steps from a state in which the reference position of the reel M50 (for example, the position of the boundary between No. 0 and No. 19) is at the bottom of the lower stage, the decimal point is “1”. When the stop button is operated at a timing of driving 504 steps from the state where the reference position of the reel M50 (for example, the position at the boundary between the number 0 and the number 19) is the lowermost part of the lower stage, "00100000" (decimal number "32") Is “11111100” (decimal number “252”), and “11111111” in the case of free hit. An example of output of operation mode information relating to one game is, for example, when “middle → left → right” push order bells are aligned (in the case of a bell, winning is possible regardless of all reel stop positions) In the case of push order navigation, reel stop order information: “00000010”, first stop step information: “11111111”, second stop step information: “11111111”, third stop step information: “11111111” Similarly, when there is no push order navigation, reel stop order information: “00000010”, first stop step information: “11111111”, second stop step information: “11111111”, third stop step information: “11111111” It has become.

  With the configuration as described above, according to the rotating game machine according to the modified example 2 from the third embodiment, the operation mode information output to the second test board is information relating to the reel to be stopped, that is, the reel. By configuring the information related to the stop order to be transmitted to the second test board with a single output, the number of times of output to the second test board can be reduced, and an unexpected situation such as garbled transmission information due to noise or the like can occur. The fear of occurring can be reduced. In addition, regarding the transmission timing of the command relating to the lottery result of the internal lottery relating to a certain game and the condition device identification value (bonus identification value, small role identification value, etc.), the transmission timing to the sub side is directed to the first test board. By configuring so that the timing is earlier than the transmission timing, it is possible to configure so as not to delay the execution of the effect based on the winning combination (operation of the start lever) related to the certain game.

  In this example, as the output mode of the operation mode information regarding each game, the operation mode information (including information regarding the stop position) related to the pressing order of “left → middle → right” is output, and thereafter the optimal mode in the game It may be configured to output the operation mode information (which is the highest machine discount). In addition, as an output mode of signals to the test boards (first test board, second test board), all information may be output by one interrupt process, or a predetermined byte (for example, 1 byte) ) May be configured to be divided and output every time.

  Further, in this example, as the output mode of the operation mode information, for example, the information regarding the step number is transmitted in two steps. For example, “the upper 2 bits are used for the lower-level identification information (both the upper and lower steps). Identification information as to whether it is number information) and the remaining bits as lower step numbers "," higher two bits as higher identification information (identification information as to whether the upper or lower step number) The remaining bits may be transmitted as the upper step number. Specifically, in the case of a bell in the push order of “middle → left → right”, when there is push order navigation, “middle → left → Information related to the pressing order of “Right”: “00000011” → First stop upper step number: “00000001” → First stop lower step number: “11111111” (free hit) → Second stop upper Step number: “00000001” → second stop lower step number: “11111111” (free hit) → third stop upper step number: “00000001” → third stop lower step number: “11111111” (free hit) When there is no push order navigation, information related to the push order of “left → middle → right”: “00000001” → first stop upper step number: “00000000” → first stop lower Step number: “01000001” (65 steps) → second stop upper step number: “00000001” → second stop lower step number: “11111111” (free hit) → third stop upper step number: “00000001” "→ Step number of the lower third stop:" 11111111 "(free hit) It may be sent to.

  In this example, the output mode (signal control processing) of the signal to the second test board can be different between when there is push order navigation and when there is no push order navigation. The classification method of the signal control processing is not limited to this, and for example, the output mode (signal control processing) may be different depending on whether or not it is during ART (ART state).

  In addition, the configuration in this example is not limited to a spinning-type gaming machine that uses a game medal to play, but for example, a spinning-type gaming machine that uses a game ball used in a pachinko gaming machine. (So-called parrot) and enclosed game machines that do not use game media are also applicable.

  Further, in this example, an ART state is provided in which the push order display device D270 can notify (navigate) the push order of the small roles such as bells and replays (the push order that gives the highest profit to the player). However, the present invention is not limited to this, and the replay probability variation game state (the replay win rate is higher (or lower) than the normal game state in which the replay win rate is a predetermined value) ( RT state) or an AT (assist time) state that can notify the stop order of the reels for winning the winning combination, or in the AT state or ART state, You may comprise so that the state (what is called a push-type AT state, a push-type ART state) which can alert | report the kind (or stop position for winning a small combination) which is winning is provided.

(Fourth embodiment)
In the present embodiment to the third embodiment, the first RAM area (or register area) can be updated and referred to by the processing of the CPUC 100 based on the program code arranged in the second ROM area. Prevents illegal acts on gaming machines such as error detection and error display (for example, illegal access to game media slot and payout port to obtain game media by unauthorized means, etc.) In order to execute the program for preventing fraud to be executed by the processing in the second ROM / RAM area, the above-described configuration is used when such a configuration is applied to an actual revolving game machine. It is also possible to apply a configuration different from the above. Therefore, such a configuration is referred to as a fourth embodiment, and differences from the third embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 67 is a flowchart of main control unit main processing according to the subroutine of Step 1000 (fourth) in the fourth embodiment. First, in step 1000 (fourth), after turning on the power of the revolving game machine P, in step 1057, the CPUC 100 sets a timer interrupt based on the data in the first ROM / RAM area (here, Only the type of timer interrupt is set, and in the subsequent processing, when the timer interrupt is started, a flowchart related to timer interrupt processing described later is periodically executed). Next, in step 1058, the CPUC 100 executes the function setting of the main control chip C based on the data in the first ROM / RAM area. Next, in step 1060, the CPUC 100 adds the start address in the first RAM to the last address in the stack area (calculates a checksum) to generate power-off recovery data. Next, in step 1061, the CPUC 100 checks the switch states of the door switch D80, the setting door switch M10, and the setting key switch M20 based on the data in the first ROM / RAM area. Next, in step 1076, the CPUC 100 refers to the data in the first ROM / RAM area, and determines whether any of the door switch D80, the setting door switch M10, and the setting key switch M20 is OFF. In the case of Yes in step 1076, in step 3700 (fourth), the CPUC 100 executes RAM initialization processing without setting change, which will be described later, based on the data in the first ROM / RAM area. Next, in step 1077, the CPUC 100 calls a setting value check process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1078. On the other hand, in the case of No in step 1076, in step 1100, the CPUC 100 executes a setting change device control process to be described later based on the data in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
Next, in step 1078, the CPUC 100 determines whether or not the set value in the first RAM is within a normal range (1 to 6 in this example) based on the data in the second ROM / RAM area. In the case of Yes in Step 1078, in Step 1079, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to Step 1081. On the other hand, in the case of No in step 1078, in step 1080, the CPUC 100 sets a setting value error display (for example, displayed on the payout number display device D190) based on the data in the second ROM / RAM area. (For example, set in the register area). Next, in step 1300, the CPUC 100 executes the above-described non-recoverable error based on the data in the second ROM / RAM area. In the fourth embodiment, the checksum area exists in the first RAM area, and there is no problem even if the address of the checksum area is changed except for the head address. In other words, the checksum area is arranged at address F102H in FIG. 67, but it may be stored at a predetermined address in the first work area of FIG. 67, and 1-byte data is stored as the checksum area. Not only that, but also 2-byte data may be stored.

<Processing in the first ROM / RAM area>
Next, in step 1081, the CPUC 100 reads the input port based on the data in the first ROM / RAM area. Next, in step 1082, the CPUC 100 starts the timer interrupt set in step 1057 based on the data in the first ROM / RAM area. Next, in step 1083, the CPUC 100 turns off the power-off processing completion flag in the flag area in the first ROM / RAM area, and returns to the processing at the time of power-off according to the returned stack pointer.

<Processing in the first ROM / RAM area>
Next, FIG. 68 is a flowchart of setting change device control processing according to the subroutine of step 1100 of FIG. 67 in the fourth embodiment. The difference from the third embodiment is step 3750 (fourth). That is, in step 3750 (fourth), the CPUC 100 determines whether or not the RAM initial setting is changed based on the data in the first ROM / RAM area. Processing is executed, and the routine goes to Step 1118. Note that the stack pointer set executed in step 1102 is executed in the process in the subroutine of step 3750 (fourth).

<Processing in the first ROM / RAM area>
FIG. 69 is a flowchart of the RAM initialization process without setting change according to the subroutine of step 3700 (fourth) in FIG. 67 in the fourth embodiment. First, in step 3704, the CPUC 100 determines whether or not the power interruption recovery data in the first RAM is normal based on the data in the first ROM / RAM area. In the fourth embodiment, when the result of adding from the first address of the first RAM area to the last address of the stack area (from the first address of all RAM areas to the last address) is 0, the power interruption recovery data is It is configured to determine that it is normal. In the case of Yes in step 3704, in step 3706, the CPUC 100 sets a backup error display based on the data in the first ROM / RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes the above-described non-recoverable error processing based on the data in the first ROM / RAM area. Note that the unrecoverable error processing in this processing is all processing in the first ROM / RAM area as in the processing of FIG. As described above, when it is determined that an error (in this case, the power-off recovery data is abnormal) based on the data in the first ROM / RAM area, the process in the second ROM / RAM area is called (CALL, CALL instruction, calling instruction). The error processing is also performed. That is, by configuring so that complicated processing is not executed in the case of an error, the program configuration is simplified (preventing complications and preventing program runaway).

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 3704, in step 3707, the CPUC 100 restores the stack pointer based on the data in the first ROM / RAM area. More specifically, the stack pointer is a kind of so-called register, and is a storage area provided in the CPU that is cleared when the power is turned off. Therefore, at step 1902 in FIG. 76, when the power is turned off, the stack pointer is stored at a predetermined address in the first RAM area, so that the return address and various register values stored in the stack area before the power is turned off are restored. be able to. Next, in step 3708, based on the data in the first ROM / RAM area, the CPUC 100 determines and sets the initialization range of the first RAM as an unused RAM range in the first RAM. Next, in step 3710, the CPUC 100 executes initialization of the first RAM within the determined initialization range based on the data in the first ROM / RAM area. Next, in step 3712, the CPUC 100 calls the second RAM initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 3713.

<Processing in the second ROM / RAM area>
Next, in step 3713, the CPUC 100 saves the data on the plurality of registers to the stack area by the PUSH instruction based on the data in the second ROM / RAM area (the order of saving is, for example, A, F, B , C, D, E, H, L). Next, in step 3714, the CPUC 100 determines and sets the initialization range of the second RAM as an unused RAM range in the second RAM based on the data in the second ROM / RAM area, and proceeds to step 3736. Here, the PUSH instruction refers to an instruction for saving (storing) a conventional register in the stack area. Specifically, the eight registers shown in FIG. 69 are stored by an instruction “PUSH GPR”. At this time, since each register is saved in the stack area, 1 (a total of 8) is subtracted from the stack pointer before execution, and then the effective address and the register are stored at the address specified by the stack pointer. . The POP instruction indicates an instruction for extracting (returning) data from the uppermost stage (address indicated by the stack pointer) of the stack area saved in the stack area. Specifically, the eight registers shown in FIG. 69 are restored by an instruction “POP GPR”, and 1 (8 in total) is added to the value of the stack pointer.

<Processing in the second ROM / RAM area>
Next, in step 3736, the CPUC 100 executes the initialization of the second RAM within the determined initialization range based on the data in the second ROM / RAM area. Next, in step 3738, the CPUC 100 restores the data on the plurality of registers from the stack area by the POP instruction based on the data in the second ROM / RAM area (the order of restoration is, for example, L, H, E , D, C, B, F, A in this order and return in the reverse order of the retracted order). Next, in Step 3740, the CPUC 100 returns to the caller of the first RAM based on the data in the second ROM / RAM area, and proceeds to the next process (the process of Step 1077). As described above, in the fourth embodiment, the determination of the initialization range of the first RAM area and the execution of the initialization are performed by the processing in the first ROM / RAM area, and the initialization range of the second RAM area is determined and initialized. Execution is configured to be executed by processing in the second ROM / RAM area. In the fourth embodiment, the non-recoverable error process immediately after power-on is executed as a process in the first ROM / RAM area, while the non-recoverable error process at other timings is performed in the first ROM / RAM area. This is because the non-recoverable error processing executed immediately after the power is turned on is not ready to be executed as processing in the second ROM / RAM area, so the initial value of the stack pointer This is because it is not possible to determine whether or not to set. A temporary stack area may be provided in an unused area, and the temporary stack area may be used as a stack area only when calculating a checksum when power is turned on.

<Processing in the first ROM / RAM area>
Next, FIG. 70 is a flowchart of the RAM initialization process with setting change according to the subroutine of step 3750 (fourth) of FIG. 68 in the fourth embodiment. First, in step 3752, the CPUC 100 determines whether or not the power-off recovery data in the first RAM is normal based on the data in the first ROM / RAM area (the power-off processing flag state and all RAMs are checked). Judgment is made by referring to the thumb status). In the case of Yes in step 3752, in step 3754, the CPUC 100 clears the stack area and sets the initial value of the stack pointer based on the data in the first ROM / RAM area. Next, in step 3756, the CPUC 100 determines and sets the initialization range of the first RAM to all ranges excluding the set values in the first RAM based on the data in the first ROM / RAM area. In addition to the set value, other ranges (for example, carry-over information related to bonus carry-over) may be excluded from the initialization range. Next, in step 3758, the CPUC 100 executes initialization of the first RAM within the determined initialization range based on the data in the first ROM / RAM area. Next, in step 3760, the CPUC 100 calls the second RAM initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 3762. Note that the initialization order may determine the initialization range of the first RAM and execute the initialization before clearing the stack area, and the initialization order is not limited to the order shown in FIG. .

<Processing in the second ROM / RAM area>
Next, in Step 3762, the CPUC 100 saves the data on the plurality of registers to the stack area by the PUSH instruction based on the data in the second ROM / RAM area (the order of saving is, for example, A, F, B , C, D, E, H, L). Next, in step 3764, the CPUC 100 determines and sets the initialization range of the second RAM to all the ranges in the second RAM based on the data in the second ROM / RAM area, and proceeds to step 3778. In this example, the information related to the set value is not stored in the second RAM area, but is stored only in the first RAM area.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 3752, in step 3766, based on the data in the first ROM / RAM area, the CPUC 100 clears the stack area and sets the initial value of the stack pointer. Next, in step 3768, the CPUC 100 determines and sets the initialization range of the first RAM as the entire range of the first RAM based on the data in the first ROM / RAM area. Next, in step 3770, the CPUC 100 executes the initialization of the first RAM within the determined initialization range based on the data in the first ROM / RAM area. Next, in step 3772, the CPUC 100 calls the second RAM initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 3774. Note that the initialization order may determine the initialization range of the first RAM and execute the initialization before clearing the stack area, and the initialization order is not limited to the order shown in FIG. .

<Processing in the second ROM / RAM area>
Next, in step 3774, the CPUC 100 saves the data on the plurality of registers to the stack area by the PUSH instruction based on the data in the second ROM / RAM area (the order of saving is, for example, A, F, B , C, D, E, H, L). Next, in step 3776, the CPUC 100 determines and sets the initialization range of the second RAM to all the ranges in the second RAM based on the data in the second ROM / RAM area, and proceeds to step 3778.

<Processing in the second ROM / RAM area>
Next, in step 3778, the CPUC 100 executes the initialization of the second RAM within the determined initialization range based on the data in the second ROM / RAM area. Next, in step 3780, the CPUC 100 restores the data on the plurality of registers from the stack area by the POP instruction based on the data in the second ROM / RAM area (the order of restoration is, for example, L, H, E , D, C, B, F, A in this order and return in the reverse order of the retracted order). Next, in step 3882, the CPUC 100 returns to the caller of the first RAM based on the data in the second ROM / RAM area (also referred to as RETURN, RETURN instruction, return instruction), and the next process (process of step 1118). Migrate to

<Processing in the first ROM / RAM area>
FIG. 71 is a flowchart of the game progress control process (first sheet) in the fourth embodiment. The difference from the third embodiment is step 1206 (fourth). That is, after the RAM data necessary for the game is set in step 1204, in step 1206 (fourth), the CPUC 100 Based on the data in the 1ROM / RAM area, the game state in the game is temporarily stored in the first RAM area, and the process proceeds to step 1208. Note that this processing is used when information relating to the gaming state is output to the sub-side and when output to the test board side.

<Processing in the first ROM / RAM area>
Next, FIG. 72 is a flowchart of the game progress control process (third sheet) in the fourth embodiment. Differences from the third embodiment are step 1293 (fourth), step 3500 (fourth), step 1294 (fourth) to step 1296 (fourth), and step 1300, that is, step 3150 (third ) Or when the ART counter value is 0 in step 1257-2 (third), the CPUC 100 in the first ROM / RAM area in step 1293 (fourth) Based on the data, the second test signal output process in the second ROM area is called, and the process proceeds to step 3500 (fourth).

<Processing in the second ROM / RAM area>
Next, in step 3500 (fourth), the CPUC 100 executes a second test signal output process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1294 (fourth), the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area. Thus, in the fourth embodiment, the second test signal output process is configured to be executed not as an interrupt process but as a main loop process (game progress control process).

<Processing in the second ROM / RAM area>
In addition, after executing the insertion / withdrawal error detection process in step 1500, in step 1295 (fourth), the CPUC 100 determines that the set value in the first RAM is within the normal range based on the data in the second ROM / RAM area. In the example, it is determined whether or not 1-6). If YES in step 1295 (fourth), the process proceeds to step 1270; if NO, in step 1296 (fourth), the CPUC 100 displays a setting value error display based on the data in the second ROM / RAM area. (For example, it will be displayed on the payout number display device D190) is set (for example, set in the register area). Next, in step 1300, the CPUC 100 executes the above-described non-recoverable error processing based on the data in the second ROM / RAM area. As described above, the fourth embodiment is configured to check the set value abnormality even when all the reels are stopped. The reason for executing the set value abnormality check at the timing when all reels are stopped is, for example, the combination of symbols stopped and displayed at a predetermined timing (for example, after the third stop operation) when all reels are stopped. Depending on the result, based on the data in the first ROM / RAM area, a lottery related to ART (a lottery table (low probability state, high probability state) used for ART lottery / non-winning, ART lottery)) This is because there is a case of executing based on In other words, when an abnormal setting value such as “7” is selected at this time, there is a possibility that the lottery table of unintended will be used to execute the ART lottery. Running to prevent.

<Processing in the second ROM / RAM area>
Next, FIG. 73 is a flowchart of the second test substrate signal output process according to the subroutine of Step 3500 (fourth) of FIG. 70 in the fourth embodiment. First, in step 3518, the CPUC 100 outputs a step number designation command (command related to the number of steps of each reel) based on the information in the second ROM area based on the data in the second ROM / RAM area. Next, in step 3520, the CPUC 100 outputs a frame number designation command (command relating to the number of frames each reel has) in the second ROM area based on the data in the second ROM / RAM area. By configuring in this way, it is possible to notify the testing machine side of the number of steps and the number of frames used in the gaming machine to be tested, depending on the winning combination etc. based on other test signals It is possible to grasp at which position to stop. As described above, in the fourth embodiment, the step number designation command and the frame number designation command are output to the second test board side. However, the present invention is not limited to this. For example, a gaming machine to be produced If there is no difference in the number of steps and the number of frames depending on the type, there is no problem even if the step number information and the reel frame number information are not output to the second test board side.

<Processing in the second ROM / RAM area>
Next, in step 3522, the CPUC 100 outputs a push order designation command based on the data in the second ROM / RAM area. Next, in Step 3524, the CPUC 100 outputs a left cylinder reception position designation command in the first RAM area based on the data in the second ROM / RAM area. Next, in Step 3526, the CPUC 100 outputs a middle-cylinder receiving position designation command based on the data in the second ROM / RAM area. Next, in step 3528, the CPUC 100 outputs a right-handed cylinder reception position designation command based on the data in the second ROM / RAM area, and proceeds to the next process {process of step 1294 (fourth)}. As described above, in the fourth embodiment, “step number designation command → frame number designation command → push order designation command → left cylinder reception position designation command → middle cylinder reception position designation command → right cylinder reception position designation command” Are output to the second test board in the order of "." In addition, in the case of the push order navigation, the push order designation command, the left circling reception position designation command, the middle circling reception position designation command, and the right circling reception position designation command are determined in step 3150 (third). The command content is determined based on the generated information, and if there is no push order navigation, the command content is determined based on the information generated in step 3600 (third). Note that the contents of the push order designation command and the frame number designation command include the information with the highest machine discount order, the information without the highest machine discount order, and the lowest order that is the most disadvantageous for the player. It may be configured to output information such as the same push order, such as information on machine cut order, information on the highest machine push order, and stop frames. Although not shown in the fourth embodiment, the rotating cylinder reception position designation command output to the second test board is converted into stop step number information by the second test board (when the reel stop position is instructed). The unit is converted from the number of frames to the number of steps) and output to the ball tester. When the second test board is not converted to the stop step number designation command, the second test A stop step number designation command may be output as a signal to the second test board.

  Next, FIG. 74 is an example of second test signal output information in the fourth embodiment. In the figure, a specific example of a signal (information) output to the second test board is shown. First, the command name of the step number information is “step number designation” and is configured to output a value obtained by dividing the step number of the stepping motor by the actual step number by 8. Next, the command name of the reel frame number information is “frame number designation” and is configured to output the number of symbols per reel. Next, the command name of the reel stop order information is “push order designation”, and for example, “0” is output in the case of “left → middle → right” push order. Next, the command name of the stop frame information is “Cylinder reception position specification” (“Left Cylinder reception position specification”, “Medium Cylinder reception position specification”, “Right Cylinder reception position specification”), As the stop reception position, “0 to 20” is output to specify the pressing position, or “127” is output to specify the pressing order (designating to stop at random). In the fourth embodiment, one command is transmitted in the order of “first command → second command → sum command”. The sum command is obtained by performing an OR operation on the first command and the second command, and performing an OR operation on the operation result and “10000000”. Further, as shown in the lower part of the figure, the first command and the second command are composed of an 8-bit string of “0 ******” having a leading bit of 0, and the sum command has a leading bit of 1. It is composed of an 8-bit string of “1 *******”, and a numerical value obtained by converting a decimal number of “0 to 127” related to the output command content into a binary number is the lower 7 bits. It is configured as follows. With this configuration, the second test board can distinguish the first command, the second command, and the sum command by the difference in the most significant bit. Then, by transmitting the sum command, it is possible to grasp on the second test board side that one piece of information (for example, a step number designation command composed of the first command and the second command) has been transmitted. Become. Also, if there is a difference between the sum value calculated on the testing machine side and the value of the received sum command, it may be transmitted to the second test board so as to operate in a predetermined specific operation order. good.

<Processing in the first ROM / RAM area>
Next, FIG. 75 is a flowchart of processing at the time of timer interruption according to the subroutine of step 1600 in the fourth embodiment. The difference from the third embodiment is step 1666 (fourth) to step 1680 (fourth). That is, after outputting the output data to the output port in step 1614, the CPUC 100 in step 1666 (fourth) , A control command (sub-side command) is transmitted based on the data in the first ROM / RAM area {for example, step 1672 (fourth), step 1684 (fourth), step 1678 (fourth), step 1680 ( If it is set in the register area in step 4), the set control command is taken over}. Next, in step 1667 (fourth), the CPUC 100 determines, based on the data in the first ROM / RAM area, the result of the set internal lottery, the command related to the condition device identification value and the gaming state (command to the sub side) ). Next, in step 1668 (fourth), the CPUC 100 performs timer measurement related to game progress based on the data in the first ROM / RAM area (timer measurement necessary when the game is progressing normally, for example, A timer measurement such as a minimum game interval timer M70, etc. (also referred to as a first timer measurement) is executed, and the process proceeds to step 1616.

<Processing in the second ROM / RAM area>
In addition, after executing the insertion / withdrawal error check process in step 1800, in step 1670 (fourth), the CPUC 100 determines an error flag (normally a game not related to game progress) based on the data in the second ROM / RAM area. It is a flag relating to an error that cannot occur when the progress proceeds, for example, whether or not a inserted medal backflow error flag or the like is off. In the case of Yes in step 1670 (fourth), in step 1672 (fourth), the CPUC 100 determines that the second error non-detection command (sub-side command is a normal game based on the data in the second ROM / RAM area. The command related to the case where the error related to the case where the error is not detected is not detected) is set, and the process proceeds to step 1638. On the other hand, in the case of No in step 1670 (fourth), in step 1684 (fourth), the CPUC 100 determines the second error detection command (sub-side command based on the data in the second ROM / RAM area, A command related to an error detected when the game is not progressing normally is set), and the process proceeds to step 1638. Note that the command based on step 1672 (fourth) may not be set. Further, the command based on step 1684 (fourth) may be configured to set the command only once when an error is detected.

<Processing in the second ROM / RAM area>
If the update state of the internal random number is normal in step 1642, in step 1675 (fourth), the CPUC 100 determines a timer measurement not related to the game progress based on the data in the second ROM / RAM area {described above. Timer measurement related to errors not related to game progress (for example, medal retention error in the selector). Also called second timer measurement. }, And the process proceeds to Step 3450 (third).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1644, in step 1676 (fourth), the CPUC 100 determines that an error flag related to the game progress {the game progresses normally based on the data in the first ROM / RAM area. In this case, it is a flag relating to an error that may occur. For example, it is determined whether or not a door switch flag, a hopper empty error (an error indicating that the hopper H40 medal has become empty), and the like are off. To do. In the case of Yes in step 1676 (fourth), in step 1678 (fourth), the CPUC 100, based on the data in the first ROM / RAM area, is the first error non-detection command (sub-side command and is normally played) The command relating to the case where the error relating to the case where the process is in progress has not been detected is set, and the process proceeds to step 1628. On the other hand, in the case of No in step 1676 (fourth), in step 1680 (fourth), the CPUC 100 determines the first error detection command (sub-command) based on the data in the first ROM / RAM area. A command related to the case where an error related to the case where the game is progressing normally is detected is set, and the process proceeds to step 1628. As described above, in the fourth embodiment, when a command related to the occurrence of an error is set, a command related to an error that may occur during normal progress of the game is executed by processing related to the first ROM / RAM area. On the other hand, a command related to an error that does not occur during normal progress of the game is configured to be executed by processing related to the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 76 is a flowchart of the power-off process according to the subroutine of Step 1900 of FIG. 75 in the fourth embodiment. The difference from the third embodiment is step 1918 (fourth), that is, after the power-off processing completed flag is turned on in step 1904, the CPUC 100 executes the first ROM / RAM area in step 1918 (fourth). The complement of the value obtained by adding the first address of the first RAM area to the last address of the second RAM address is calculated based on the data in the first RAM area, and the complement is stored in the checksum area of the first RAM area (the complement is calculated in step 1060). Used in processing). In other words, the checksum area is arranged at address F102H in FIG. 76, but it may be stored at a predetermined address in the first work area of FIG. 76, and 1-byte data is stored as the checksum area. Not only that, but also 2-byte data may be stored.

<Processing in the second ROM / RAM area>
Next, FIG. 77 is a flowchart of first test signal output processing according to the subroutine of step 3450 (third) in the fourth embodiment. The difference from the third embodiment is step 3469 (fourth) to step 3476 (fourth). That is, in step 3456, the timer value information of the output time timer M80 in the first RAM area is temporarily stored in the register area. Thereafter, in step 3469 (fourth), the CPUC 100 determines whether or not it is the output timing of the first condition device information based on the data in the second ROM / RAM area. Here, in the fourth embodiment, the first test signal is output in the order of “first bonus state information → first small combination state information → second bonus state information → second small combination state information”. ing. Further, as a method for judging the output timing, when the quotient obtained by dividing the timer value of the output time timer M80 of the A register (the initial value is 48) by 12 is (1) 3, the first bonus state Information output timing, (2) In the case of 2, the output timing of the first small role state information, (3) In the case of 1, the output timing of the second bonus state information, (4) When 0 and there is a remainder Is determined to be the output timing of the first small combination state information, and (5) when 0 and there is no remainder, it is determined that it is not the output timing of the bonus state information and the small combination state information. In addition, the number enclosed by (circle) on drawing corresponds to the said description (1)-(5). In the case of Yes in step 3469 (fourth), in step 3470 (fourth), the CPUC 100 uses the first bonus state information address as the condition device information based on the data in the second ROM / RAM area, for example, in the register area (for example, Temporarily stored in the HL register). Next, in step 3471-1 (fourth), the CPUC 100 determines whether it is the output timing of the first bonus state information based on the data in the second ROM / RAM area. In the case of Yes in step 3471-1 (fourth), the process proceeds to step 3466, and in the case of No, that is, when it is the output timing of the first small combination state information that is the first small combination state information, step 3471. -2 (fourth), the CPUC 100 temporarily stores the first small role state information address as the conditional device information in the register area (for example, the HL register) based on the data in the second ROM / RAM area, and the step 3466.

<Processing in the second ROM / RAM area>
Further, after the condition device information is temporarily stored in another register area (for example, the A register) in step 3466, or in the case of No in step 3469, in step 3472 (fourth), the CPUC 100 executes the second ROM / RAM area. It is determined whether or not it is the output timing of the second condition device information based on the data inside. In the case of Yes in step 3472 (fourth), in step 3473 (fourth), the CPUC 100 uses the second bonus state information address as the condition device information based on the data in the second ROM / RAM area, for example, in the register area (for example, Temporarily stored in the HL register). Next, in Step 3474 (fourth), the CPUC 100 determines whether it is the output timing of the second bonus state information based on the data in the second ROM / RAM area. In the case of Yes in step 3474 (fourth), the process proceeds to step 3476 (fourth). In the case of No, that is, when it is the output timing of the second small combination state information which is the second small combination state information, In step 3475 (fourth), the CPUC 100 temporarily stores the second small role state information address as the conditional device information in the register area (for example, the HL register) based on the data in the second ROM / RAM area. The process shifts to 3476 (fourth). Next, in step 3476 (fourth), the CPUC 100 stores the conditional device information temporarily stored in the register area (for example, HL register) based on the data in the second ROM / RAM area in another register area (for example, The data is temporarily stored in the A register), and the process proceeds to step 3468. Note that if the result is No in step 3472 (fourth), the process proceeds to step 3468. The output image of the four condition device information is configured such that the bonus state information and the small combination state information are alternately turned on and off as shown in the lower right part of the figure. Also, as shown in the middle right of the figure, the lower 6 bits of the first small role status information and the upper 6 bits of the second small role information are combined to form one 12% small role status information, the first bonus The lower 6 bits of the status information and the upper 6 bits of the second bonus information are combined into a single 12-bit bonus status information. By configuring in this way, there are 6 or more types, in other words 0 to 0. It is possible to output bonus state information and small part state information composed of more than 63 types. In this embodiment, the condition device number related to the bonus is composed of 0 to 2, and the information device number related to the small role is composed of 0 to 25. However, the number of condition devices was changed depending on the development stage of the gaming machine ( (Increased) can be dealt with. This is program control that is possible because it is a program stored in the second ROM area that is not limited by the program capacity. Further, when developing another gaming machine having a different number of conditional devices, it is not necessary to use a different program according to the number of conditional devices, and any gaming machine can be used universally.

  With the above-described configuration, according to the rotating type gaming machine according to the fourth embodiment, the bonus state information and the small combination state information are output twice as the condition device information to be output to the first test board. Then, by combining the two commands (combining the first bonus state information and the second bonus state information, or combining the first small combination state information and the second small combination state information), 1 It is configured to be able to output the number of types of condition device information that could not be output by each time. The RAM initialization process executed immediately after the power is turned on (setting change device control process) when the setting change key is turned on (turned to the right) is the first ROM area. -The process in the RAM area is executed, and the process related to the initialization of the second RAM area is executed in the process in the second ROM / RAM area. It can be made clear that there is only no processing.

  In addition, in the swivel type gaming machine according to the fourth embodiment, when outputting a test signal, the test signal is acquired not only from the operation state information but also from another address and a lit lamp (for example, a re-game lamp). You may comprise.

  In addition, in the spinning type gaming machine according to the fourth embodiment, when the processing of the first ROM / RAM area is executed by interrupt processing, a plurality of registers are stored in the stack area by the PUSH instruction, and the second ROM area When a process is called, a plurality of registers are further stored in the stack area by a PUSH instruction.

(Fifth embodiment)
In the present embodiment to the fourth embodiment, processing that affects the progress of the game is executed in the first ROM / RAM area, and processing that does not affect the progress of the game is executed in the second ROM / RAM area. However, it is possible to make the configuration more clear. Therefore, such a configuration is referred to as a fifth embodiment, and differences from the third embodiment will be described in detail below. In the fifth embodiment to the eleventh embodiment, detailed description will be mainly given of the stack pointer. Therefore, a detailed description of the process executed in the first main process, the process executed in the second main process, and the process actually executed in the first interrupt process and the second interrupt process is omitted.

<Processing in the first ROM / RAM area>
First, FIG. 78 is an example of processing when calling the processing of the second ROM area in the fifth embodiment. First, in step 4002, the CPUC 100 executes processing of the first ROM / RAM area based on the data in the first ROM / RAM area. Next, in step 4004, the CPUC 100 calls the processing in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 4006.

<Processing in the second ROM / RAM area>
Next, in step 4006, the CPUC 100 temporarily stores the address of the stack pointer at a predetermined address in the second RAM area based on the data in the second ROM / RAM area. Next, in step 4008, the CPUC 100 executes processing in the second ROM / RAM area based on the data in the second ROM / RAM area. Next, in step 4010, the CPUC 100 confirms whether the address of the stack pointer matches the address temporarily stored in the predetermined address in step 4006 based on the data in the second ROM / RAM area. Next, in step 4012, the CPUC 100 determines whether or not the stack pointer addresses confirmed in step 4010 match based on the data in the second ROM / RAM area. If YES in step 4012, in step 4014, the CPUC 100 determines that the processing of the second ROM / RAM area has been normally executed based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area. The process proceeds to step 4016. On the other hand, in the case of No in step 4012, in step 4018, the CPUC 100 executes error processing based on the data in the second ROM / RAM area (for example, error notification and interruption of game by sound / lamp).

<Processing in the first ROM / RAM area>
Next, in step 4016, the CPUC 100 executes processing in the first ROM / RAM area based on the data in the first ROM / RAM area. Note that the address of the stack pointer is temporarily stored at a predetermined address in the first RAM area immediately before calling the processing in the second ROM area in step 4004 (processing in the first ROM / RAM area), and in step 4014, the caller of the first ROM area Immediately after returning (processing in the first ROM / RAM area), it may be configured to check whether the addresses of the stack pointers coincide with each other, or immediately before calling processing in the second ROM area in step 4004 (first ROM / RAM area). In step 4014, the stack pointer address is temporarily stored at a predetermined address in the first RAM area, and immediately before returning to the caller of the first ROM area in step 4014 (processing in the second ROM / RAM area), Configure to make sure they match Good. In step 4012, the address of the stack pointer is set at the start of execution of the process in the second ROM / RAM area (when called from the first ROM area) and at the end of execution (when returning to the caller of the first ROM area). If they match, the data related to the processing from the start of execution of the processing in the second ROM / RAM area to the end of execution, which is stacked above the address of the stack pointer in the stack area, is cleared. The data in the stack area including data related to all processing related to the second ROM / RAM area stacked above the address of the stack pointer in the stack area {data from the stack pointer to the stack area Data up to the address when the number is stacked at the maximum (the smallest address) Alternatively, the data from the stack pointer to the minimum address in the stack area (address F2CAH in FIG. 76) may be cleared (for example, “the game progress control process relating to the first ROM / RAM area starts → Game progress control process related to the second ROM / RAM area starts → Interrupt process related to the first ROM / RAM area starts → Interrupt process related to the second ROM / RAM area starts → Interrupt process related to the second ROM / RAM area ends → At the end of the game progress control process related to the second ROM / RAM area, the interrupt process related to the first ROM / RAM area is finished → the game progress control process related to the second ROM / RAM area is finished. And when the address match between the start of the game progress control process related to the second ROM / RAM area is confirmed, Clear the data relating to the interrupt processing according to a game progress control processing and the 2ROM · RAM area according to ROM · RAM area, etc.). In other words, at least the data in the range using the stack area is cleared by the process based on the second ROM / RAM area, but the data in the range using the stack area is not cleared by the process based on the first ROM / RAM area. By doing so, it is possible to prevent a situation in which an illegal act or the like by the process based on the first ROM / RAM area is executed using the data stored in the stack area by the process based on the second ROM / RAM area. The process based on the first ROM / RAM area can be executed again without any trouble.

  Next, FIG. 79 is a stack area image diagram in the fifth embodiment. This figure shows the situation of the stack area when executing the processing of the second ROM / RAM area in the fifth embodiment. First, the process is executed in the first ROM / RAM area, and the data in the first ROM / RAM area is loaded in the stack area, and the process in the second ROM / RAM area is called (CALL). Data related to the return address is stacked in the stack area. Next, the address (B) of the stack pointer at the timing when the data related to the return address is stacked is temporarily stored in the second RAM area. Thereafter, processing is executed in the second ROM / RAM area, and data related to the second ROM / RAM area is stacked in the stack area. Next, the processing in the second ROM / RAM area is completed, and it is confirmed whether or not the address (B) of the stack pointer matches the address temporarily stored in the second RAM area (processing in the second ROM / RAM area). When the address of the stack pointer at the time when the process ends is the same as the address of the stack pointer at the time when the process in the second ROM / RAM area is started, normal processing related to the second ROM / RAM area is executed. Determined). As a result of the confirmation, if the addresses match, it returns to the caller of the first ROM area, and if it does not match, error processing is executed.

  With the configuration described above, according to the swivel type gaming machine according to the fifth embodiment, the address of the stack pointer when calling the process of the second ROM area while executing the process of the first ROM area, It is determined whether or not the address of the stack pointer matches when returning to the caller of the first ROM area after finishing the processing of the 2ROM area. By determining that is executed normally, the processing of the first ROM area and the processing of the second ROM area can be separated more clearly than in the embodiment described above, and a more fair gaming machine can be obtained. It will be possible.

(Sixth embodiment)
In the fifth embodiment, the address of the stack pointer when the process of the second ROM area is called while the process of the first ROM area is being executed, and the caller of the first ROM area after completing the process of the second ROM area The processing of the first ROM area and the processing of the second ROM area are separated by matching the address of the stack pointer when returning to the above, but the present invention is not limited to this, and two stack areas are used. Thus, the processing of the first ROM / RAM area and the processing of the second ROM / RAM area can be separated. Such a configuration is referred to as a sixth embodiment, and differences from the fifth embodiment will be described in detail below. In addition, for the sixth to eleventh embodiments, for example, “the main processing of the first ROM / RAM area is executed, and data in and out of the first stack area is performed by PUSH / CALL / POP / RETURN”. Is a plurality of steps (processes) described in the main process on the main controller side (processes in the first ROM / RAM area) described in the present embodiment to the fourth embodiment, etc., or any step (Processing). Similarly, “the main processing of the second ROM / RAM area is executed and data in / out of the second stack area is performed by PUSH / CALL / POP / RETURN” is the main described in the present embodiment to the fourth embodiment. It indicates a plurality of steps (processes) described in the control device side main process (process in the second ROM / RAM area) or any one of the steps (processes). For example, “execute processing at the time of interrupt in the first ROM / RAM area and put data in and out of the first stack area by PUSH / CALL / POP / RETURN” means processing in the first ROM / RAM area at the time of timer interrupt Or a plurality of steps (processes) described in the above. Similarly, for example, “execute processing at the time of interrupt in the second ROM / RAM area and put data in / out of the first stack area by PUSH / CALL / POP / RETURN” means that in the second ROM / RAM area of the timer interrupt processing It refers to a plurality of steps (processes) described in the process, or any step (process).

  First, in the sixth and subsequent embodiments, the processing in the first stack area and the second ROM / RAM area, which are mainly used when executing the processing in the first ROM / RAM area, is executed as the stack area. And a second stack area that will be mainly used in the process.

<Processing in the first ROM / RAM area>
First, FIG. 80 is a flowchart of the first main process and the second main process according to the subroutine of steps 5000 (sixth) and 5050 (sixth) in the sixth embodiment. Note that the description of the stack area on the right side in the flowcharts after this figure indicates the stack area in which the stack pointer is set when processing is being executed. First, the first main process in step 5000 (sixth) will be described in detail. First, in step 5002, the CPUC 100 sets a stack pointer (address is X) in the first stack area based on the data in the first ROM / RAM area. This address X indicates the initial address (for example, F200H) of the first stack area. Next, in step 5004, the CPUC 100 executes the main process of the first ROM / RAM area (game progress control process, which is different from the interrupt process) based on the data in the first ROM / RAM area. Data in / out of the first stack area is executed by predetermined processing using CALL / POP / RETURN or the like, and then processing in the second ROM area is called.

<Processing in the second ROM / RAM area>
Next, in step 5050 (sixth), the CPUC 100 is a second main process (a game progress control process related to the second ROM / RAM area based on the data in the second ROM / RAM area, which is different from the interrupt process). ) To return to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5008, the CPUC 100 executes the main process (a game progress control process, a process different from the interrupt process) of the first ROM / RAM area based on the data in the first ROM / RAM area. Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN.

<Processing in the second ROM / RAM area>
Next, the second main process of step 5050 (sixth) will be described in detail. First, in step 5052, the CPUC 100 saves all the registers to the first stack area based on the data in the second ROM / RAM area. Next, in step 5054, based on the data in the second ROM / RAM area, the CPUC 100 saves the stack pointer (address B) to a predetermined address (also referred to as β address) in the second RAM area. Next, in step 5056, the CPUC 100 sets a stack pointer (address is set to Y) based on the data in the second ROM / RAM area. Next, in step 5058, the CPUC 100 executes the main process (a game progress control process, a process different from the interrupt process) of the second ROM / RAM area based on the data in the second ROM / RAM area. Data in / out of the second stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5060, the CPUC 100 restores the stack pointer (address B) from a predetermined address (β address) in the second RAM area based on the data in the second ROM / RAM area. Next, in step 5062, the CPUC 100 restores all the registers saved in the first stack area based on the data in the second ROM / RAM area. As shown in the lower part of the figure, in the sixth embodiment (the same applies to the following embodiments), the first stack area (may be recognized as an area adjacent to the first RAM area) is the first stack area. The second stack area exists (may be recognized as an area adjacent to the second RAM area) in the second RAM area. In the sixth embodiment, the first stack area is from F1CAH to F200H, and the second stack area is from F3CAH to F400H. However, the present invention is not limited to this, and the first stack area is the first RAM area. The predetermined address of the second RAM area may be used as the second stack area. The stack pointer is a predetermined area of the CPUC 100 and is configured to store only one address. In the sixth and subsequent embodiments, by switching the address of the one stack pointer to the address of the first stack area and the address of the second stack area (by repeatedly saving to and returning from the RAM area) ), A process using two stack areas, the first stack area and the second stack area, is configured to be executable.

<Processing in the first ROM / RAM area>
Next, FIG. 81 is a flowchart of first interrupt processing according to the subroutine of Step 5100 (sixth) in the sixth embodiment. First, in step 5102, the CPUC 100 saves all the registers to the currently set stack area based on the data in the first ROM / RAM area. Next, in step 5104, based on the data in the first ROM / RAM area, the CPUC 100 saves the stack pointer (address is A) to a predetermined address (also referred to as α address) in the first RAM area. Next, in step 5106, the CPUC 100 determines whether or not the stack area being set at the time of interrupt processing is the second stack area based on the data in the first ROM / RAM area. Specifically, when the final address of the first stack area is F1 ** and the final address of the second stack area is F3 **, a predetermined address (also referred to as α address) in the first RAM area is referred to. When the data stored at the address is F1ΔΔ, it is determined that the interrupt is generated in the first stack area, and when the data stored at the address is F3ΔΔ. It is determined that the interrupt is generated when the second stack area is set. More specifically, data stored at a predetermined address (α address) in the first RAM area is written into the HL register. If F1FD is stored, “F1” is stored in the H register and “FD” is stored in the L register. At this time, “11110001” is stored in the H register. On the other hand, when F3FD is stored, “F3” is stored in the H register and “FD” is stored in the L register. At this time, “11110011” is stored in the H register. Here, it is possible to determine which stack area is set by determining the D1 bit (second bit from the lower order) of the H register (when “0”, the first stack area, “1”) "Is the second stack area). If YES in step 5106, in step 5108, the CPUC 100 returns the stack pointer (address B) from the predetermined address (β address) in the second RAM area based on the data in the first ROM / RAM area. Move to 5110. On the other hand, also in the case of No in step 5106, the process proceeds to step 5110. With these processes, the stack area used in step 5110 is set as the first stack area. Next, in step 5110, the CPUC 100 executes predetermined processing of interrupt processing in the first ROM / RAM area based on the data in the first ROM / RAM area, and by processing using PUSH / CALL / POP / RETURN or the like. After the data in / out of the first stack area is executed, the processing in the second ROM area is called.

<Processing in the second ROM / RAM area>
Next, in step 5150 (sixth), the CPUC 100 executes the second interrupt process during stack setting based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5114, the CPUC 100 executes predetermined processing of interrupt processing of the first ROM / RAM area based on the data in the first ROM / RAM area, and by processing using PUSH / CALL / POP / RETURN or the like. Data in / out of the first stack area is executed. Next, in step 5116, the CPUC 100 restores the stack pointer A from a predetermined address (also referred to as α address) in the first RAM area based on the data in the first ROM / RAM area. Next, in step 5118, the CPUC 100 restores all the registers saved in step 5102 based on the data in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
Next, FIG. 82 is a flowchart of second interrupt processing according to the subroutine of step 5150 (sixth) in the sixth embodiment. First, in step 5152, the CPUC 100 saves all the registers in the currently set stack area based on the data in the second ROM / RAM area. Next, in step 5154, based on the data in the second ROM / RAM area, the CPUC 100 saves the stack pointer (address is C) to a predetermined address (also referred to as γ address) in the second RAM area. Next, in step 5156, the CPUC 100 sets a stack pointer (address is set to Y) based on the data in the second ROM / RAM area. This address Y indicates the initial address (for example, F400H) of the second stack area. Next, in step 5158, it is determined whether or not the stack area at the time of occurrence of the interrupt is the second stack area. Specifically, referring to a predetermined address {address storing the value of the stack pointer (address A)} in the first RAM area, if the data stored at the address is F1ΔΔ, the first is generated when an interrupt occurs. If it is determined that the data is stored in the stack area and the data stored in the address is F3ΔΔ, it is determined that the interrupt is generated when the data is set in the second stack area. If YES in step 5158, the stack pointer (address is A) is restored from the predetermined address (α address) in the first RAM area in step 5160, and the flow advances to step 5162. As a result, the register and return address are saved using the subsequent stack pointer without destroying the stack pointer used in the second stack area, not the initial value of the second stack area set in step 5156. be able to. On the other hand, also in the case of No in step 5158, the process proceeds to step 5162. With these processes, the stack area used in step 5162 is set as the second stack area. In the case of No in step 5158, the initial value of the second stack area set in step 5156 is used. In other words, since the second stack area is not used, there is no problem even if the first address of the second stack area is indicated. Next, in step 5162, the CPUC 100 executes predetermined processing of interrupt processing in the second ROM / RAM area based on the data in the second ROM / RAM area, and by processing using PUSH / CALL / POP / RETURN or the like. Data in / out of the first stack area is executed. Next, in step 5164, the CPU C 100 restores the stack pointer (address is C) from a predetermined address (also referred to as γ address) in the second RAM area based on the data in the second ROM / RAM area. Next, in step 5166, all the registers saved in step 5152 are restored.

  Next, FIG. 83 is a main processing image diagram A in the sixth embodiment. In the image diagrams after this figure, a state in which data is stacked in the stack area is shown, and a stack pointer in which an address surrounded by a circle is set is shown. The display of << Step *** >> indicates steps corresponding to the above-described flowchart. The white circle inside is the address indicated by the stack pointer. First, processing is executed in the first ROM / RAM area, and after setting the stack pointer (address is X) (set to the address of the first stack area), processing is executed in the first ROM / RAM area, Thereafter, the second ROM area is called. The first stack area is loaded with data related to the return address. Next, all registers A (the registers to be saved in this process are all registers A because a plurality of processes to save all registers appear are all registers A, and all registers with the same name have the same contents) in the first stack. After saving to the area, the stack pointer B is saved to a predetermined address (also referred to as β address) in the second RAM area (the address B of the stack pointer is temporarily stored in the second RAM area). Next, the stack pointer (address is Y) is set. The second stack area is used from this timing. Thereafter, processing by the second ROM / RAM area is executed, the stack pointer becomes A, and then the stack pointer B (address is the first stack area) is restored from a predetermined address (also referred to as β address) in the second RAM area. The register A is restored from the first stack area and returned to the caller of the first ROM area.

  Next, FIG. 84 is a first stack setting interrupt image diagram A in the sixth embodiment. First, an interrupt process occurs during the setting of the first stack area, and after all registers A are saved to the first stack area, the stack pointer A is saved to the first RAM area. Since the first stack area is being set, the data related to the first ROM / RAM area and the data related to the return address before the interrupt are stacked in the first stack area. Thereafter, the processing of the first ROM / RAM area is executed, the stack pointer becomes D, and the processing of the second ROM area is called. Next, after all registers B are saved to the first stack area, the stack pointer C is saved to a predetermined address (also referred to as γ address) in the second RAM area, and the stack pointer (address is Y) is set in the second stack area. Then, the processing of the second ROM / RAM area is executed. Next, after the stack pointer C is restored from a predetermined address (also referred to as γ address) in the second RAM area, all the registers B are restored from the first stack area and returned to the caller of the first ROM / RAM area. After executing the processing of the first ROM / RAM area, the stack pointer A is restored from a predetermined address (also referred to as α address) in the first RAM area, all the registers A are restored from the first stack area, and the interrupt process is completed. To do. As shown in the figure, when the process of the second ROM area is called, the data related to the return address is loaded in the stack area.

  Next, FIG. 85 is a second stack setting interrupt image diagram A in the sixth embodiment. First, an interrupt process occurs during the setting of the second stack area, and after all registers A are saved to the second stack area, the stack pointer A is saved to the first RAM area. Since the second stack area is being set, the first stack area is loaded with data related to the first ROM / RAM area, data related to the return address before the interrupt, and all registers C. The area is loaded with data relating to the second ROM / RAM area. After that, the stack pointer B (indicating the address of the first stack area) is restored from the predetermined address (also referred to as β address) of the second RAM area, the process of the first ROM / RAM area is executed, and the process of the second ROM area is called. (The stack pointer is D at the timing of calling the second ROM area). Next, after all registers B are saved to the first stack area, the stack pointer C is saved to a predetermined address (also referred to as γ address) in the second RAM area. Next, the stack pointer (address is Y) of the second stack area is set, the stack pointer A (indicating the address of the second stack area) is restored from the first RAM area, and the processing of the second ROM / RAM area is executed. I will do it. Next, after the stack pointer C (indicating the address of the first stack area) is restored from a predetermined address (also referred to as γ address) in the second RAM area, all registers B are restored from the first stack area, and the first ROM / RAM Returning to the area caller, the processing of the first ROM / RAM area is executed. Thereafter, the stack pointer A (indicating the address of the second stack area) is restored from a predetermined address (also referred to as α address) in the first RAM area, and then all the registers A are restored from the second stack area and the interrupt process is terminated. .

  With the configuration as described above, according to the spinning-reel game machine according to the sixth embodiment, by providing two stack areas of the first stack area and the second stack area as the stack area, the first ROM / Data related to processing in the RAM area and data related to processing in the second ROM RAM area can be prevented from being mixed in one stack area, and data related to processing in the first ROM / RAM area and the second ROM RAM area more clearly. It can be separated from the process.

  In the sixth embodiment, when interrupt processing is executed when the stack pointer is the address of the first stack area, the return address is stored in the first stack area, and the stack pointer is stored in the second stack area. When the interrupt process is executed when the address is the address, the return address is stored in the second stack area.

(Seventh embodiment)
In the sixth embodiment, when the process of the second ROM area is called while the process of the first ROM / RAM area is being executed, all the registers are saved and the first ROM / RAM area is saved by the process of the second ROM / RAM area. The data related to the process in the second ROM / RAM area is separated from the process in the second ROM / RAM area, but the data related to the process in the first ROM / RAM area and the process in the second ROM / RAM area are similarly separated from each other. be able to. Therefore, such a configuration is referred to as a seventh embodiment and will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 86 is a flowchart of the first main process and the second main process related to the subroutines of steps 5200 (seventh) and 5250 (seventh) in the seventh embodiment. Note that the description of the stack area on the right side in the flowcharts after this figure indicates the stack area in which the stack pointer is set when processing is being executed. First, the first main process in step 5200 (seventh) will be described in detail. First, in step 5202, the CPUC 100 sets a stack pointer (address is X) in the first stack area based on the data in the first ROM / RAM area. Next, in step 5204, based on the data in the first ROM / RAM area, the CPUC 100 executes the main process of the first ROM / RAM area (a game progress control process, a process different from the interrupt process), Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5206, based on the data in the first ROM / RAM area, the CPUC 100 saves all registers in the first stack area and calls the process in the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 5250 (seventh), the CPUC 100 is a second main process (a game progress control process related to the second ROM / RAM area based on the data in the second ROM / RAM area, which is different from the interrupt process). ) To return to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5210, the CPUC 100 restores all the registers saved in the first stack area in step 5206 based on the data in the first ROM / RAM area. Next, in step 5212, the CPUC 100 executes a main process (a game progress control process, a process different from the interrupt process) of the first ROM / RAM area based on the data in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
Next, the second main process in step 5250 (seventh) will be described in detail. First, in step 5252, the CPUC 100 saves the stack pointer (address is B) to a predetermined address (also referred to as β address) in the second RAM area based on the data in the second ROM / RAM area. This stack pointer is the stack pointer of the first stack area. Next, in Step 5254, the CPUC 100 sets a stack pointer (address is Y) based on the data in the second ROM / RAM area. Next, in step 5256, the CPUC 100 executes the main process of the second ROM / RAM area (a game progress control process, a process different from the interrupt process) based on the data in the second ROM / RAM area. Data in / out of the second stack area is executed by a predetermined process such as CALL / POP / RETURN. Next, in step 5258, based on the data in the second ROM / RAM area, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area, and the first ROM area. Return to the caller of.

<Processing in the first ROM / RAM area>
Next, FIG. 87 is a flowchart of first interrupt processing according to the subroutine of Step 5300 (seventh) in the seventh embodiment. First, in step 5302, the CPUC 100 saves all the registers to the currently set stack area based on the data in the first ROM / RAM area. Next, in step 5304, the CPUC 100 saves the stack pointer (address is A) to the first RAM area based on the data in the first ROM / RAM area. Next, in step 5306, based on the data in the first ROM / RAM area, the CPUC 100 determines whether or not the stack area at the time of occurrence of the interrupt is the second stack area. In the case of Yes in step 5306, in step 5308, based on the data in the first ROM / RAM area, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area. , Step 5310 is entered. On the other hand, also in the case of No in step 5306, the process proceeds to step 5310. With these processes, the stack area used in step 5310 is set as the first stack area. Next, in step 5310, the CPUC 100 executes processing at the time of interruption of the first ROM / RAM area based on the data in the first ROM / RAM area, and performs predetermined processing using PUSH / CALL / POP / RETURN or the like. Realizes data in and out of the first stack area. Next, in step 5312, the CPUC 100 saves all the registers to the currently set stack area (first stack area) based on the data in the first ROM / RAM area, and calls the process in the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 5350 (seventh), the CPUC 100 executes the second interrupt processing based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5316, the CPUC 100 restores all the registers saved in step 5312 based on the data in the first ROM / RAM area. Next, in step 5318, the CPUC 100 executes predetermined processing for interrupt processing in the first ROM / RAM area based on the data in the first ROM / RAM area, and performs predetermined processing using PUSH / CALL / POP / RETURN or the like. Data in / out of the first stack area is executed by the processing. Next, in step 5320, the CPUC 100 restores the stack pointer A from a predetermined address (also referred to as α address) in the first RAM area based on the data in the first ROM / RAM area. Next, in step 5322, the CPUC 100 restores all the registers saved in step 5302 based on the data in the first ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 88 is a flowchart of second interrupt processing according to the subroutine of Step 5350 (seventh) in the seventh embodiment. First, in step 5352, based on the data in the second ROM / RAM area, the CPUC 100 saves the stack pointer (address is C) to a predetermined address (also referred to as γ address) in the second RAM area. Next, in step 5354, the CPUC 100 sets a stack pointer (address is assumed to be Y) based on the data in the second ROM / RAM area. Next, in step 5356, it is determined whether or not the stack area at the time of occurrence of the interrupt is the second stack area. In the case of Yes in step 5356, in step 5358, the stack pointer (address is assumed to be A) is restored from a predetermined address (also referred to as α address) in the first RAM area, and the process proceeds to step 5360. On the other hand, also in the case of No in step 5356, the process proceeds to step 5360. With these processes, the stack area used in step 5360 is set as the second stack area. Next, in step 5360, the CPUC 100 executes predetermined processing of interrupt processing in the second ROM / RAM area based on the data in the second ROM / RAM area, and performs predetermined processing using PUSH / CALL / POP / RETURN or the like. The data in / out of the second stack area is executed by processing. Next, in step 5362, the CPU C 100 restores the stack pointer C (address is C) from a predetermined address (also referred to as γ address) in the second RAM area based on the data in the second ROM / RAM area.

  FIG. 89 is a main process image diagram B in the seventh embodiment. First, the stack pointer X (indicating the address of the first stack area) is set in the first stack area. Then, after executing the processing by the first ROM / RAM area, all registers A (the registers to be saved in this processing are all registers A because a plurality of processes to save all registers appear, and all registers having the same name are the same) Is saved in the first stack area, and the process of the second ROM area is called. Thereafter, the stack pointer B is saved to a predetermined address (also referred to as β address) in the second RAM area (the address B of the stack pointer is temporarily stored in the second RAM area), and the stack pointer Y (the address of the second stack area is changed). Is set in the second stack area, and the processing of the second ROM / RAM area is executed. Next, the stack pointer B is set in the first stack area to return to the caller of the first ROM area. Thereafter, all the registers A are restored from the first stack area, and the processing of the first ROM / RAM area is executed.

  Next, FIG. 90 is a first stack setting interrupt image diagram B in the seventh embodiment. First, interrupt processing occurs during the setting of the first stack area, and after all registers A are saved to the first stack area, the stack pointer A (indicating the address of the first stack area) is set to a predetermined address (first RAM area address). (also referred to as α address). Since the first stack area is being set, the data related to the first ROM / RAM area and the data related to the return address before the interrupt are stacked in the first stack area. Thereafter, the processing of the first ROM / RAM area is executed, the stack pointer becomes C, all registers B are saved in the first stack area, and the processing of the second ROM area is called. Next, the stack pointer C is saved at a predetermined address (also referred to as γ address) in the second RAM area, and the stack pointer Y (indicating the address of the second stack area) of the second stack area is set, and the second ROM / RAM The area processing is executed. Next, after returning the stack pointer C (indicating the address of the first stack area) from a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer C is returned to the caller of the first ROM / RAM area and all registers B are stored. Returning from the first stack area, the processing of the first ROM / RAM area is executed. Thereafter, after the stack pointer A (indicating the address of the first stack area) is restored from a predetermined address (also referred to as α address) in the first RAM area, all the registers A are restored from the first stack area, and the interrupt process is terminated. .

  Next, FIG. 91 is a second stack setting interrupt image diagram B in the seventh embodiment. First, interrupt processing occurs during the setting of the second stack area, and after all registers A are saved in the second stack area, the stack pointer A (indicating the address of the second stack area) is set to a predetermined address ( (also referred to as α address). Since the second stack area is being set, the first stack area is loaded with data related to the first ROM / RAM area, all registers C, and data related to the return address before the interrupt. Is loaded with data relating to the second ROM / RAM area. Thereafter, the stack pointer B (indicating the address of the first stack area) is restored from a predetermined address (also referred to as β address) in the second RAM area, the processing of the first ROM / RAM area is executed, and all registers B are stored in the second stack. After saving to the area, the processing of the second ROM area is called (the stack pointer is C at the timing of calling the second ROM area). Next, the stack pointer C is saved to a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer (Y) of the second stack area is set, and the stack pointer A (indicating the address of the second stack area) ) From a predetermined address (also referred to as α address) in the first RAM area, and the processing in the second ROM / RAM area is executed. Next, after returning the stack pointer C from a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer C is returned to the caller of the first ROM area, and all the registers B are restored from the second stack area. The area processing is executed. Thereafter, the stack pointer A (indicating the address of the second stack area) is restored from a predetermined address (also referred to as α address) in the first RAM area, and then all the registers A are restored from the second stack area and the interrupt process is terminated. .

  With the configuration described above, according to the swivel type gaming machine according to the seventh embodiment, when calling the process in the second ROM area while executing the process in the first ROM / RAM area, all the registers are saved. Then, the second ROM area processing is called, and by providing two stack areas as the stack area, the first stack area and the second stack area, the data related to the processing of the first ROM / RAM area and the second ROMRAM It is possible to prevent a situation in which data relating to area processing is mixed in one stack area, and to clearly separate data relating to processing in the first ROM / RAM area and processing in the second ROM / RAM area.

(Eighth embodiment)
In the fifth embodiment, when calling the process in the second ROM area while executing the process in the first ROM / RAM area, all the registers are saved by the process in the second ROM / RAM area and the first ROM / RAM area is saved. The data related to the processing of the area and the processing of the second ROM / RAM area are separated from each other, but the data related to the processing of the first ROM / RAM area and the processing of the second ROM / RAM area are similarly configured in other configurations. Can be carved. Therefore, such a configuration is referred to as an eighth embodiment, which will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 92 is a flowchart of the first main process and the second main process according to the subroutine of steps 5400 (eighth) and 5450 (eighth) in the eighth embodiment. First, the first main process in step 5400 (eighth) will be described in detail. First, in step 5402, the CPUC 100 sets a stack pointer X (indicating the address of the first stack area) in the first stack area based on the data in the first ROM / RAM area. Next, in step 5404, based on the data in the first ROM / RAM area, the CPUC 100 executes the main process of the first ROM / RAM area (a game progress control process, a process different from the interrupt process), Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5406, the CPUC 100 prohibits the interrupt processing based on the data in the first ROM / RAM area (if the interrupt is disabled, the timer interrupt processing cannot be executed until the interrupt is permitted. After that, the process of the second ROM area is called.

<Processing in the second ROM / RAM area>
Next, in step 5450 (eighth), the CPUC 100 executes a second main process (a predetermined process related to the second ROM / RAM area, a game progress control process) based on the data in the second ROM / RAM area. Then, the process returns to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5410, the CPUC 100 permits the interrupt processing that has been prohibited based on the data in the first ROM / RAM area. Next, in step 5412, the CPUC 100 executes main processing (game progress control processing, processing different from interrupt processing) of the first ROM / RAM area based on the data in the first ROM / RAM area, Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN.

<Processing in the second ROM / RAM area>
Next, the second main process in step 5450 (eighth) will be described in detail. First, in step 5452, the CPUC 100 saves the stack pointer (address B) to a predetermined address (also referred to as β address) in the second RAM area based on the data in the second ROM / RAM area. Next, in step 5454, the CPUC 100 sets a stack pointer (address is Y) based on the data in the second ROM / RAM area. Next, in step 5456, the CPUC 100 saves all the registers to the second stack area based on the data in the second ROM / RAM area. Next, in step 5458, the CPUC 100 permits an interrupt based on the data in the second ROM / RAM area. Next, in step 5460, the CPUC 100 executes the main process of the second ROM / RAM area (game progress control process, which is different from the interrupt process) based on the data in the second ROM / RAM area. Data in / out of the second stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5462, the CPUC 100 prohibits the interrupt based on the data in the second ROM / RAM area (if the interrupt is disabled, the timer interrupt process cannot be executed until the interrupt is permitted. ) Next, in step 5464, the CPUC 100 restores all registers from the second stack area based on the data in the second ROM / RAM area. Next, in step 5466, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area based on the data in the second ROM / RAM area. In the eighth embodiment, the process of switching the stack pointer (for example, switching from the address of the first stack area to the address of the second stack area) can be executed across a plurality of steps (processes). If an interrupt process occurs during the execution of the switching process, it can occur both when the various data based on the interrupt process is stored in the first stack area and when stored in the second stack area. In order to prevent such a situation from occurring, interrupt processing is not generated during execution of processing required for stack pointer switching.

<Processing in the first ROM / RAM area>
Next, FIG. 93 is a flowchart of the first interrupt process according to the subroutine of Step 5500 (eighth) in the eighth embodiment. First, in step 5502, the CPUC 100 saves the AF register (A register) in the back register based on the data in the first ROM / RAM area. The back register is another register that holds a copy of the register used mainly, and is configured to be able to switch the register to be accessed from the main register to the back register in an instant. The F register indicates that when an operation instruction or the like is executed, each flag of S, Z, H, P / V, N, and C changes to “1” or “0” according to the operation result. This is a register that does not change, and is configured so that the contents of the F register cannot be changed by a program. The AF register is saved if there is no problem if only the F register can be saved, but since only the F register cannot be saved, the AF register is saved. With this configuration, it is possible to avoid that the F register that is overwritten by the immediately previous calculation result is overwritten (broken) by the interrupt process (for example, the process of step 5508). Next, in step 5504, the CPUC 100 saves the stack pointer (address A) to the first RAM area based on the data in the first ROM / RAM area. Next, in step 5506, the CPUC 100 determines whether or not the second main process (the main process of the second ROM / RAM area) is being executed based on the data in the first ROM / RAM area {for example, ( 1) Judgment is made based on whether the address of the saved stack pointer (the address at the start of interrupt processing, which is A) is the address of the first stack area or the address of the second stack area (2 ) Determine whether the address of the return address stored in the stack area at the start of interrupt processing is the address of the first ROM / RAM area or the address of the second ROM / RAM area, etc.}. In the case of Yes in step 5506, in step 5508, based on the data in the first ROM / RAM area, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area. The process proceeds to step 5510. On the other hand, also in the case of No in step 5506, the process proceeds to step 5510. Next, in step 5510, the CPUC 100 saves all the registers to the currently set stack area based on the data in the first ROM / RAM area. Next, in step 5512, the CPUC 100 executes a predetermined process (game progress control process) of the interrupt process of the first ROM / RAM area based on the data in the first ROM / RAM area, and pushes, push, call, pop, and return. After the data in and out of the first stack area is executed by a predetermined process using, etc., the process in the second ROM area is called.

<Processing in the second ROM / RAM area>
Next, in step 5550 (eighth), the CPUC 100 executes the second interrupt processing based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5516, the CPUC 100 executes a predetermined process (game progress control process) of the interrupt process of the first ROM / RAM area based on the data in the first ROM / RAM area, and PUSH / CALL / POP / RETURN. The data in and out of the first stack area is executed by a predetermined process using the above. Next, in step 5518, the CPUC 100 restores all the registers saved in step 5510 based on the data in the first ROM / RAM area. Next, in step 5520, the CPUC 100 restores the stack pointer (address is A) from a predetermined address (also referred to as α address) in the first RAM area based on the data in the first ROM / RAM area. In step 5524, the CPU C 100 restores the AF register saved in the back register based on the data in the first ROM / RAM area, and ends the interrupt process.

<Processing in the first ROM / RAM area>
Next, FIG. 94 is a flowchart of the second interrupt process relating to the subroutine of step 5550 (eighth) in the eighth embodiment. First, in step 5552, based on the data in the second ROM / RAM area, the CPUC 100 saves the stack pointer (address is C) to a predetermined address (also referred to as γ address) in the second RAM area. Next, in Step 5554, the CPUC 100 sets a stack pointer (address is Y) based on the data in the second ROM / RAM area. Next, in step 5556, it is determined whether or not the second main process (the main process of the second ROM / RAM area) is being executed when the interrupt occurs {eg, (1) the address of the saved stack pointer (interrupt process) It is determined whether it is the address of the first stack area or the address of the second stack area. (2) Stored in the stack area at the start of interrupt processing Determination based on whether the address of the return address is the address of the first ROM / RAM area or the address of the second ROM / RAM area, etc.}. In the case of Yes in step 5556, in step 5558, the stack pointer (address is assumed to be A) is restored from a predetermined address (also referred to as α address) in the first RAM area, and the process proceeds to step 5560. On the other hand, also in the case of No in step 5556, the process proceeds to step 5560. Next, in Step 5560, the CPUC 100 saves all registers to the currently set stack area based on the data in the second ROM / RAM area. Next, in step 5562, the CPUC 100 executes predetermined processing of interrupt processing in the second ROM / RAM area based on the data in the second ROM / RAM area, and performs predetermined processing using PUSH / CALL / POP / RETURN or the like. The data in / out of the second stack area is executed by processing. Next, in step 5564, the CPUC 100 restores all the registers saved in step 5560 based on the data in the second ROM / RAM area. Next, in Step 5566, the CPU C 100 returns the stack pointer (address is C) from a predetermined address (also referred to as γ address) in the second RAM area based on the data in the second ROM / RAM area.

  Next, FIG. 95 is a main process image diagram C in the eighth embodiment. First, after setting the stack pointer (address is X) in the first stack area, the processing by the first ROM / RAM area is executed, and the interrupt is prohibited under the situation where the address of the stack pointer is B (the interrupt is prohibited) If it is, the timer interrupt process cannot be executed until the interrupt is permitted) and the process in the second ROM area is called. Next, the stack pointer B is saved to a predetermined address (also referred to as β address) in the second RAM area (the address B of the stack pointer is temporarily stored in the second RAM area), and the stack pointer Y (indicating the address of the second stack area) ) Is set, all registers A (there are multiple registers A that are saved, so all registers A have the same contents). After saving to the second stack area, the interrupt is permitted. After that, after calling the process of the second ROM area and executing the process of the second ROM / RAM area, the interrupt is disabled (if the interrupt is disabled, the timer interrupt process cannot be executed until the interrupt is permitted. After all registers A are restored from the second stack area, the stack pointer B is restored from a predetermined address (also referred to as β address) in the second RAM area, and is returned to the caller of the first ROM / RAM area. Thereafter, the interrupt is permitted and the processing of the first ROM / RAM area is executed.

  Next, FIG. 96 shows an interrupt image C during the first main processing in the eighth embodiment. First, an interrupt process occurs during execution of the main process in the first ROM / RAM area. After the AF register is saved in the back register, the stack pointer A (indicating the address of the first stack area) is set to a predetermined address (in the first RAM area). (also referred to as α address). Since interrupt processing occurs during the first main processing, data related to the first ROM / RAM area and data related to the return address before interrupt are stacked in the first stack area. Next, all registers A are saved in the first stack area. Thereafter, the processing of the first ROM / RAM area is executed, the stack pointer becomes C (indicating the address of the first stack area), and the processing of the second ROM area is called. Next, the stack pointer C (indicating the address of the first stack area) is saved to a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer (Y) of the second stack area is set, and all registers After saving B to the second stack area, the processing of the second ROM / RAM area is executed. Next, all registers B are restored from the second stack area, and the stack pointer C (indicating the address of the first stack area) is restored from a predetermined address (also referred to as β address) in the second RAM area, Returning to the caller, the processing of the first ROM / RAM area is executed. Thereafter, after all the registers A are restored from the first stack area, the stack pointer A is restored from a predetermined address (also referred to as α address) in the first RAM area, the AF register is restored from the back register, and the interrupt process is terminated.

  Next, FIG. 97 is a second main-processing interrupt image diagram C in the eighth embodiment. First, an interrupt process occurs during execution of the main process of the second ROM / RAM area, the AF register is saved in the back register, and the stack pointer A (indicating the address of the second stack area) is set to a predetermined address (α (Also referred to as an address). Since this is an interrupt process during the second main process, the data related to the first ROM / RAM area and the data related to the return address before the interrupt are loaded in the first stack area, and all the data related to the return address before the interrupt are loaded. Data relating to the register B, the second ROM / RAM area, and data relating to the return address before the interruption are stacked. Thereafter, the stack pointer B (indicating the address of the first stack area) is restored from a predetermined address (also referred to as β address) in the second RAM area, and all the registers A are saved in the first stack area, Execute the process. Thereafter, the processing of the second ROM area is called (the stack pointer is C at the timing of calling the second ROM area), and the stack pointer C (indicating the address of the first stack area) is set to a predetermined address (γ address) of the second RAM area. The stack pointer (address is Y) is set, and the stack pointer A (indicating the address of the second stack area) is set to a predetermined address (also referred to as α address) in the first RAM area. Return from. Thereafter, after all the registers B are saved in the second stack area, the processing of the second ROM / RAM area is executed. Thereafter, the processing of the second ROM / RAM area is terminated and all the registers B are restored from the second stack area. Return). Thereafter, the process returns to the caller of the first ROM / RAM area, and the processing of the first ROM / RAM area is executed. Thereafter, after all the registers A are restored from the first stack area, the stack pointer A (indicating the address of the second stack area) is restored from a predetermined address (also referred to as α address) in the first RAM area, and the AF register is set to the back register. Return from, and end the interrupt processing.

  With the configuration described above, according to the swivel type gaming machine according to the eighth embodiment, interrupt processing is prohibited when calling the processing of the second ROM area while executing the processing of the first ROM / RAM area. By doing so, switching of the ROM / RAM area to be used and the stack area to be used can be executed without any problem, and the data related to the processing of the first ROM / RAM area and the processing of the second ROM / RAM area can be clearly separated. Will be able to.

(Ninth embodiment)
In the eighth embodiment, when the process in the second ROM area is called while the process in the first ROM / RAM area is being executed, the interrupt process is prohibited by the process in the second ROM / RAM area, thereby The data related to the processing in the RAM area and the processing in the second ROM / RAM area are separated, but the other data having the interrupt-inhibiting configuration is also the same as the data related to the processing in the first ROM / RAM area. 2 ROM / RAM area processing can be separated. Therefore, such a configuration is referred to as a ninth embodiment, which will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 98 is a flowchart of the first main process and the second main process according to the subroutines of steps 5600 (9th) and 5650 (9th) in the ninth embodiment. Note that the description of the stack area on the right side in the flowcharts after this figure indicates the stack area in which the stack pointer is set when processing is being executed. First, the first main process in step 5600 (9th) will be described in detail. First, in step 5602, the CPUC 100 sets a stack pointer (address is X) in the first stack area based on the data in the first ROM / RAM area. Next, in step 5604, the CPUC 100 executes the main processing (game progress control processing, which is different from the interrupt processing) of the first ROM / RAM area based on the data in the first ROM / RAM area. Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5606, the CPUC 100 prohibits interrupt processing based on the data in the first ROM / RAM area (if interrupt is disabled, the timer interrupt processing cannot be executed until the interrupt is permitted. Be) Next, in step 5608, the CPUC 100 saves all the registers in the first stack area based on the data in the first ROM / RAM area, and calls the process in the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 5650 (9th), the CPUC 100 is based on the data in the second ROM / RAM area, and is different from the second main process (interrupt process related to the second ROM / RAM area). ) To return to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5612, the CPUC 100 restores all registers from the first stack area based on the data in the first ROM / RAM area. Next, in step 5614, the CPUC 100 permits the interrupt processing that has been prohibited based on the data in the first ROM / RAM area. Next, in step 5616, based on the data in the first ROM / RAM area, the CPUC 100 executes the main process of the first ROM / RAM area (a game progress control process, a process different from the interrupt process), Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN.

<Processing in the second ROM / RAM area>
Next, the second main process of Step 5650 (9th) will be described in detail. First, in step 5562, based on the data in the second ROM / RAM area, the CPUC 100 saves the stack pointer (address B) to a predetermined address (also referred to as β address) in the second RAM area. Next, in step 5654, the CPUC 100 sets a stack pointer (address is set to Y) based on the data in the second ROM / RAM area. Next, in step 5656, the CPUC 100 permits interrupt processing based on the data in the second ROM / RAM area. Next, in step 5658, the CPUC 100 executes a main process (a game progress control process, a process different from the interrupt process) in the second ROM / RAM area based on the data in the second ROM / RAM area. Data in / out of the second stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in Step 5660, the CPUC 100 prohibits interruption based on the data in the second ROM / RAM area. Next, in step 5562, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area based on the data in the second ROM / RAM area. In the ninth embodiment, the process of switching the stack pointer (for example, switching from the address of the first stack area to the address of the second stack area) is executed over a plurality of steps (processes). If an interrupt process occurs during the execution of the switching process, it can occur both when the various data based on the interrupt process is stored in the first stack area and when stored in the second stack area. In order to prevent such a situation from occurring, interrupt processing is not generated during execution of processing required for stack pointer switching.

<Processing in the first ROM / RAM area>
Next, FIG. 99 is a flowchart of first interrupt processing according to the subroutine of Step 5700 (ninth) in the ninth embodiment. First, in step 5702, the CPUC 100 saves the AF register (A register) to the back register based on the data in the first ROM / RAM area. Next, in step 5704, based on the data in the first ROM / RAM area, the CPUC 100 saves the stack pointer (address A) to a predetermined address (also referred to as α address) in the first RAM area. Next, in step 5706, the CPUC 100 determines whether or not the second main process (the main process of the second ROM / RAM area) is being executed based on the data in the first ROM / RAM area {for example, ( 1) Judgment is made based on whether the address of the saved stack pointer (the address at the start of interrupt processing, which is A) is the address of the first stack area or the address of the second stack area (2 ) Determine whether the address of the return address stored in the stack area at the start of interrupt processing is the address of the first ROM / RAM area or the address of the second ROM / RAM area, etc.}. In the case of Yes in step 5706, in step 5708, based on the data in the first ROM / RAM area, the CPUC 100 restores the stack pointer (address B) from a predetermined address (also referred to as β address) in the second RAM area. , Step 5710 is entered. On the other hand, also in the case of No in step 5706, the process proceeds to step 5710. Next, in step 5710, the CPUC 100 saves all the registers to the currently set stack area (first stack area) based on the data in the first ROM / RAM area. Next, in step 5712, the CPUC 100 executes a predetermined process (game progress control process) of the interrupt process of the first ROM / RAM area based on the data in the first ROM / RAM area, and PUSH / CALL / POP / RETURN. The data in and out of the first stack area is executed by a predetermined process using the above. Next, in step 5714, based on the data in the first ROM / RAM area, the CPUC 100 saves all the registers in the currently set stack area (first stack area), and then calls the process in the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 5750 (9th), the CPUC 100 executes the second interrupt processing based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area.

<Processing in the first ROM / RAM area>
Next, in step 5718, the CPUC 100 restores all the registers saved in step 5714 based on the data in the first ROM / RAM area. Next, in step 5720, a predetermined process (game progress control process) of the interrupt process of the first ROM / RAM area is executed, and data in the first stack area is processed by a predetermined process using PUSH / CALL / POP / RETURN. Execute loading and unloading. Next, in step 5722, the CPUC 100 restores all the registers saved in step 5710 based on the data in the first ROM / RAM area. Next, in step 5724, the stack pointer (address A) is restored from a predetermined address (also referred to as α address) in the first RAM area. Next, in step 5726, the CPUC 100 restores the AF register saved in the back register based on the data in the first ROM / RAM area, and ends the interrupt process.

<Processing in the second ROM / RAM area>
Next, FIG. 100 is a flowchart of second interrupt processing according to the subroutine of Step 5750 (ninth) in the ninth embodiment. First, in step 5752, the CPU C 100 saves the stack pointer (address is C) to a predetermined address (also referred to as γ address) in the second RAM area based on the data in the second ROM / RAM area. Next, in step 5754, the CPUC 100 sets a stack pointer (address is Y) based on the data in the second ROM / RAM area. Next, in Step 5756, it is determined whether or not the second main process (the second ROM / RAM area main process) is being executed {for example, (1) the address of the saved stack pointer (when the interrupt process starts) (2) The return address stored in the stack area at the start of interrupt processing is determined based on whether it is the address of the first stack area or the address of the second stack area. Is determined based on whether the address is the address of the first ROM / RAM area or the address of the second ROM / RAM area, etc.}. In the case of Yes in step 5756, in step 5758, the stack pointer (address is A) is restored from a predetermined address (also referred to as α address) in the first RAM area, and the process proceeds to step 5760. On the other hand, also in the case of No in step 5756, the process proceeds to step 5760. Next, in step 5760, the CPUC 100 executes a predetermined process (game progress control process) of the interrupt process of the second ROM / RAM area based on the data in the second ROM / RAM area, and PUSH / CALL / POP / RETURN. The data in and out of the first stack area is executed by a predetermined process using the above. Next, in step 5762, the CPU C 100 restores the stack pointer (address is C) from a predetermined address (also referred to as γ address) in the second RAM area based on the data in the second ROM / RAM area.

  Next, FIG. 101 is a main process image diagram D in the ninth embodiment. First, after setting the stack pointer (address is X) in the first stack area, the processing by the first ROM / RAM area is executed, and in the situation where the address of the stack pointer is B, all interrupts are prohibited. After A is saved to the first stack area, A (the registers saved in this process are all registers A and all registers with the same name have the same contents). Then, the process of the second ROM area is called. Next, the stack pointer B is saved to a predetermined address (also referred to as β address) in the second RAM area (the address B of the stack pointer is temporarily stored in the second RAM area), and the stack pointer Y (indicating the address of the second stack area) ) Is set, then interrupts are enabled. Then, after calling the process of the second ROM area and executing the process of the second ROM / RAM area, the interrupt is disabled and the stack pointer B is restored from a predetermined address (also referred to as a β address) of the second RAM area. Return to the caller of the RAM area. Thereafter, the interrupt is permitted and the processing of the first ROM / RAM area is executed.

  Next, FIG. 102 is an interrupt image D during the first main processing in the ninth embodiment. First, an interrupt process occurs during execution of the main process in the first ROM / RAM area. After the AF register is saved in the back register, the stack pointer A (indicating the address of the first stack area) is saved in the first RAM area. Since interrupt processing occurs during the first main processing, data related to the first ROM / RAM area and data related to the return address before interrupt are stacked in the first stack area. Next, all registers A are saved in the first stack area. Thereafter, after processing of the first ROM / RAM area, all registers B are saved in the first stack area, the stack pointer becomes C (indicating the address of the first stack area), and the process of the second ROM area is called. Next, the stack pointer C (indicating the address of the first stack area) is saved to a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer (Y) of the second stack area is set, and the second ROM -The RAM area processing is executed. Next, after returning the stack pointer C (indicating the address of the first stack area) from a predetermined address (also referred to as γ address) in the second RAM area, the stack pointer C is returned to the caller of the first ROM area. Next, after all the registers B are restored from the first stack area, the processing of the first ROM / RAM area is executed. Thereafter, after all the registers A are restored from the first stack area, the stack pointer A is restored from a predetermined address (also referred to as α address) in the first RAM area, the AF register is restored from the back register, and the interrupt process is terminated.

  Next, FIG. 103 is a second main processing interrupt image diagram D in the ninth embodiment. First, an interrupt process occurs during execution of the main process in the second ROM / RAM area, the AF register is saved in the back register, and the stack pointer A is saved in the first RAM area. Since an interrupt has occurred during the second main process, the data related to the first ROM / RAM area and the data related to the return address before the interrupt are loaded in the first stack area. Are loaded with all registers C, data relating to the second ROM / RAM area, and data relating to the return address before interruption. Thereafter, the stack pointer B (indicating the address of the first stack area) is restored from a predetermined address (also referred to as β address) in the second RAM area, and after all the registers A are saved in the first stack area, the first ROM / RAM area is restored. This process is executed to save all the registers B in the first stack area. Thereafter, the processing of the second ROM area is called (the stack pointer is C at the timing of calling the second ROM area), the stack pointer C is saved to a predetermined address (also referred to as γ address) in the second RAM area, and the second stack After setting the stack pointer of the area (address is Y), the stack pointer A (indicating the address of the second stack area) is restored from the predetermined address (also referred to as α address) in the first RAM area. Thereafter, the processing of the second ROM / RAM area is executed, the stack pointer C is restored from a predetermined address (also referred to as γ address) in the second RAM area, and then all the registers B are restored from the first stack area. Returning to the area caller, the processing of the first ROM / RAM area is executed. Thereafter, after all the registers A are restored from the first stack area, the stack pointer A (indicating the address of the second stack area) is restored from a predetermined address (also referred to as α address) in the first RAM area, and the AF register is set to the back register. Return from, and end the interrupt processing.

  By configuring as described above, according to the swivel type gaming machine according to the ninth embodiment, even if the ROM / RAM area for executing the processing and the timing for saving the register is different from the eighth embodiment, When calling the process of the second ROM area while executing the process of the first ROM / RAM area, it is possible to execute the switching of the ROM / RAM area to be used and the stack area to be used without any problem by prohibiting the interrupt process. It is possible to clearly separate the data related to the processing in the first ROM / RAM area and the processing in the second ROM / RAM area.

(10th Embodiment)
In the sixth embodiment, when the process of the second ROM area is called while the process of the first ROM / RAM area is being executed, all the registers are saved by the process of the second ROM / RAM area and the first ROM / RAM area is saved. The data related to the processing of the area and the processing of the second ROM / RAM area are separated from each other, but the data related to the processing of the first ROM / RAM area and the processing of the second ROM / RAM area are similarly configured in other configurations. Can be carved. Therefore, such a configuration is referred to as a tenth embodiment, and differences from the sixth embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 104 is a flowchart of the first main process and the second main process according to the subroutine of steps 5000 (sixth) and 5050 (sixth) in the tenth embodiment. The difference from the sixth embodiment is step 5057 (tenth) and step 5059 (tenth), that is, after setting the stack pointer Y (indicating the address of the second stack area) in step 5056, In step 5057 (tenth), the CPUC 100 saves all registers to the second stack area based on the data in the second ROM / RAM area. Next, in step 5058, the CPUC 100 executes a main process (a game progress control process, a process different from the interrupt process) of the second ROM / RAM area based on the data in the first ROM / RAM area. Data in / out of the first stack area is executed by a predetermined process using CALL / POP / RETURN. Next, in step 5059 (tenth), the CPUC 100 restores all registers from the second stack area based on the data in the second ROM / RAM area, and proceeds to step 5060.

<Processing in the first ROM / RAM area>
Next, FIG. 105 is a flowchart of first interrupt processing according to the subroutine of Step 5100 (tenth) in the tenth embodiment. The difference from the sixth embodiment is step 5109 (tenth) and step 5115 (tenth), that is, in step 5108, the stack pointer (address is B) is set to a predetermined address (β of the second RAM area). In step 5109 (tenth), the CPUC 100 stores the contents of the first ROM / RAM area in the first ROM / RAM area. Based on the data, all registers are saved in the currently set stack area, and the process proceeds to step 5150 (sixth).

<Processing in the first ROM / RAM area>
In step 5114, data in / out of the first stack area is executed by a predetermined process using PUSH / CALL / POP / RETURN. Based on this data, all the registers saved in step 5109 (tenth) are restored, and the process proceeds to step 5116.

<Processing in the second ROM / RAM area>
Next, FIG. 106 is a flowchart of second interrupt processing according to the subroutine of Step 5150 (tenth) in the tenth embodiment. The difference from the sixth embodiment is step 5161 (tenth) and step 5163 (tenth), that is, in step 5160, the stack pointer (address is A) is set to a predetermined address (α In step 5161 (tenth), the CPUC 100 in the second ROM / RAM area is restored from the address), or when the stack area at the time of interrupt generation in step 5158 is the first stack area. Based on the data, all registers are saved in the currently set stack area (second stack area). Next, in step 5162, the CPUC 100 executes predetermined processing at the time of interrupt processing of the second ROM / RAM area based on the data in the second ROM / RAM area, and performs predetermined processing using PUSH / CALL / POP / RETURN or the like. The data in / out of the second stack area is executed by processing. Next, in step 5163 (tenth), the CPUC 100 restores all the registers saved in step 5161 (tenth) based on the data in the second ROM / RAM area, and proceeds to step 5164.

  By configuring as described above, according to the spinning-reel game machine according to the tenth embodiment, even if the ROM / RAM area for executing the processing and the timing for saving the register is different from the sixth embodiment, As in the sixth embodiment, the data related to the processing in the first ROM / RAM area and the processing in the second ROM / RAM area can be clearly separated.

(Eleventh embodiment)
In the sixth embodiment, when the process of the second ROM area is called while the process of the first ROM / RAM area is being executed, all the registers are saved by the process of the second ROM / RAM area and the first ROM / RAM area is saved. The data related to the processing of the area and the processing of the second ROM / RAM area are separated from each other, but the data related to the processing of the first ROM / RAM area and the processing of the second ROM / RAM area are similarly configured in other configurations. Can be carved. Thus, such a configuration is referred to as an eleventh embodiment, and differences from the sixth embodiment will be described in detail below.

<Processing in the second ROM / RAM area>
First, FIG. 107 is a flowchart of the first main process and the second main process according to the subroutine of steps 5000 (sixth) and 5050 (sixth) in the eleventh embodiment. The difference from the sixth embodiment is Step 5051 (11th), Step 5064 (11th), Step 5066 (11th), and Step 5068 (11th), that is, the second main process is called. Thereafter, in Step 5051 (11th), the CPUC 100 prohibits interruption based on the data in the second ROM / RAM area, and proceeds to Step 5052.

<Processing in the second ROM / RAM area>
After setting the stack pointer (address is set to Y) in step 5056, in step 5064 (11th), the CPUC 100 permits an interrupt based on the data in the second ROM / RAM area, and proceeds to step 5058. To do.

<Processing in the second ROM / RAM area>
In step 5058, after the data in and out of the first stack area is executed by a predetermined process using PUSH, CALL, POP, RETURN, etc., in step 5066 (11th), the CPUC 100 stores the data in the second ROM / RAM area. Based on the data, the interrupt is prohibited and the process proceeds to step 5062.

<Processing in the second ROM / RAM area>
After all the registers are restored from the first stack area in step 5062, in step 5068 (11th), the CPUC 100 permits an interrupt based on the data in the second ROM / RAM area. In the eleventh embodiment, the process of switching the stack pointer (for example, switching from the address of the first stack area to the address of the second stack area) is executed over a plurality of steps (processes). If an interrupt process occurs during the execution of the switching process, it can occur both when the various data based on the interrupt process is stored in the first stack area and when stored in the second stack area. In order to prevent such a situation from occurring, interrupt processing is not generated during execution of processing required for stack pointer switching.

  By configuring as described above, according to the spinning-reel game machine according to the eleventh embodiment, even if the ROM / RAM area for executing the processing and the timing for saving the register is different from the sixth embodiment, When calling the process of the second ROM area while executing the process of the first ROM / RAM area, it is possible to execute the switching of the ROM / RAM area to be used and the stack area to be used without any problem by prohibiting the interrupt process. It is possible to clearly separate the data related to the processing in the first ROM / RAM area and the processing in the second ROM / RAM area.

  Note that the spinning cylinder game machine in this example is configured so that the value of each register can be restored from the stack area by predetermining where the registers are stored in the stack area.

(Summary)
Note that the following concepts can be extracted (listed) based on the configuration shown in the above embodiments. However, the concepts listed below are merely examples, and the concepts based on the further configurations shown in the above embodiments are added to these concepts as well as the combination and separation (higher level conceptualization) of these listed concepts. May be.

  First, the problems to be solved by the above embodiments will be briefly described. The program capacity for controlling the operation of gaming machines, etc., is strictly restricted from the viewpoint of preventing unauthorized program mixing (guaranteeing the legitimacy of programs provided by gaming machine manufacturers), and implements gaming specifications. In addition to a program for the purpose, an illegal act is performed on a gaming machine (for example, illegally accessing a game medium slot or payout port to obtain a game medium by an illegal means). A number of programs for preventing fraud are also implemented for protection. However, at present, a program for implementing the game playability specification and a program for preventing fraud are often mixed on the ROM, and as a result, it is difficult to verify the legitimacy of these programs. There is a problem of becoming.

The rotary type gaming machine according to this aspect (1-1)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The gaming machine is configured to be divided into at least a second data area).

  According to the rotary type gaming machine according to the aspect (1-1), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU. Since they are arranged apart from each other on the memory map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or the dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

The rotary type gaming machine according to this aspect (1-2)
There is one or more address values that are larger than the second end point address value and smaller than the third start point address value, and for the one or more address values, the program and the data This is a gaming machine according to the aspect (1-1) in which special information that cannot be used is arranged.

  According to the rotary type gaming machine according to the aspect (1-2), in addition to the above-described effects, the program that exists in the first control area and is accessed by the CPU and the first control area are read out. The first block is the first block, and the program accessed in the second control area and accessed from the CPU and the data read and read in the second control area are the second block. Since special information that is not accessed by the CPU is arranged between the block and the second block, the special information is separated in the program source code or dump list, and the arrangement position of both blocks Can be clearly separated visually. As a result, for example, by arranging the first block as a control block for implementing the gaming specification and the second block as a control block for preventing fraud, both control blocks having different functional properties can be obtained. Since it is possible to clearly distinguish visually on the program source code or the dump list, it is easy to artificially verify the correctness of both control blocks.

The rotary type gaming machine according to this aspect (1-3)
The special information is the gaming machine according to the aspect (1-2) in which all bits are zero.

  According to the swivel type gaming machine according to the aspect (1-3), in addition to the above-described effects, the special information that is not accessed by the CPU is arranged between the first block and the second block. Since all bits of the special information are zero, the special information preferably serves as a delimiter in the program source code or dump list, and the arrangement positions of both blocks can be clearly separated visually. it can.

The rotary type gaming machine according to this aspect (1-4)
The special information is the gaming machine according to the aspect (1-2), in which information relating to the gaming machine is coded by a predetermined coding method.

  According to the swivel type gaming machine according to the present aspect (1-4), in addition to the above-described effects, when placing special information that is not accessed by the CPU between the first block and the second block, Since the special information becomes “information about the gaming machine”, the special information serves as a delimiter on the program source code or dump list, and the source of the program source code can be indicated at the same time. It becomes easier to artificially verify the validity of the control block.

The spinning machine according to this aspect (1-5)
The total number of bytes related to all the programs arranged in the second control area is smaller than the total number of bytes related to all the programs arranged in the first control area, and the first The total number of bytes related to all the data arranged in the two data areas is smaller than the total number of bytes related to all the data arranged in the first data area. ) Gaming machine.

  According to the swivel type gaming machine according to this aspect (1-5), in addition to the above-described effects, the first block = a control block for implementing the game play specification, and the second block = for preventing fraud In the case of being arranged as a control block, the data capacity for preventing fraud is smaller than the data capacity for implementing the game specification. Here, since the data for preventing fraud is likely to have different specifications for each gaming machine manufacturer, it is highly necessary to verify the validity artificially, but the data capacity is relatively small. If it is restricted, it is possible to reduce the labor for artificially verifying the validity of the data for preventing fraud.

The rotary type gaming machine according to this aspect (2)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When the CPU executes processing according to the program arranged in the first control area, the data arranged in the first data area can be read out, and the first The data arranged in two data areas is configured not to be read,
When the CPU executes processing according to the program arranged in the second control area, the data arranged in the second data area can be read out, and the first The gaming machine is configured such that the data arranged in one data area is not read out.

  According to the rotary type gaming machine according to the aspect (2), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the rotary type gaming machine according to the aspect (2), the program that exists in the first control area and that is accessed from the CPU can be applied to the data that exists in the first control area and is read out. A program that can only be accessed and exists in the second control area and that is accessed by the CPU exists in the first control area because it can only access data that is present in the second control area and read. The program that is accessed from the CPU and the data that is present and read in the first control area is the first block, the program that is present in the second control area and is accessed from the CPU and is present in the second control area. If the data to be read is the second block, it is easy to ensure that the first block and the second block are control blocks having different functional properties. It is easy to artificially verify the validity.

The rotary type gaming machine according to this aspect (3)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The program arranged in the second control area is configured to be able to execute processing by the CPU when there is a call instruction in the program arranged in the first control area. ,
It is a gaming machine characterized by this.

  According to the rotary type gaming machine according to the aspect (3), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (3), the program that exists in the second control area and is accessed by the CPU is called in the program that is present in the first control area and accessed by the CPU. Only when there is an instruction, processing by the CPU can be executed. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the execution timing of the program for preventing fraud can be limited only when this call instruction is issued, so the execution timing of the program for preventing fraud can be determined on the program source code or dump list. It becomes clear visually, and in particular, it becomes easy to artificially verify the legitimacy of the program for preventing fraud. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (4) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, The gaming machine is configured to be able to refer to information (for example, information held in a register in the CPUC 100) stored at the time when a call instruction is issued.

  According to the spinning machine according to the aspect (4), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (4), the program that exists in the second control area and is accessed from the CPU is called in the program that is present in the first control area and accessed from the CPU. When there is an instruction, processing by the CPU can be executed. In this case, as information stored at the time when the call instruction is issued, for example, information held in a register in the CPU (that is, the information stored in the first control area immediately before the call instruction exists). The processing result processed by the program accessed from the CPU can be transferred to the program that exists in the second control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the program for implementing the main gameability specification is taken over, It becomes possible to execute a program for preventing fraud. Here, since the processing result of the program for implementing the main gaming specification can be highly confidential information, the information for misconduct notification can be output externally to the subordinate fraud prevention program If it is handed over darkly, it may lead to a decrease in security, but the execution timing of the program for preventing fraud can be limited to this call instruction. In the list, the execution timing of the program for preventing fraud is clarified visually, and the delivery timing of the processing result is also clarified in the program source code or the dump list. Artificially verify the legitimacy of anti-fraud programs (including the timing of delivery) Theft is facilitated. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (5) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, Processing of the CPU according to the program arranged in the second control area based on the information stored in the call control instruction (for example, information held in a register in the CPUC 100) when the call instruction is issued The gaming machine is configured to be updatable.

  According to the rotating type gaming machine according to the aspect (5), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (5), the program that exists in the second control area and is accessed by the CPU is called in the program that exists in the first control area and is accessed by the CPU. When there is an instruction, processing by the CPU can be executed. In this case, as information stored at the time when the call instruction is issued, for example, information held in a register in the CPU (that is, the information stored in the first control area immediately before the call instruction exists). The processing result processed by the program accessed from the CPU) can be updated with the processing result processed by the program that exists in the second control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the subordinate fraud prevention program is taken over to become the main game It becomes possible to execute a program for implementing the sex specification. Here, since the processing result of the program for implementing the main gaming specification can be highly confidential information, it is possible to output information for misconduct notification from a subsidiary program for preventing misconduct that can be output externally. If it is updated implicitly, there is a risk that security may be reduced, but the execution timing of the program for preventing fraud can be limited to the case where there is this call instruction. As a result of visually clarifying the execution timing of the program for preventing illegal acts on the dump list, the update timing of the processing result is also clarified on the program source code or the dump list. It is possible to artificially verify the legitimacy of anti-fraud programs (including the timing of updating results) To become. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The rotary type gaming machine according to the aspect (6)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, After the CPU returns the processing result according to the program arranged in the second control area based on the call instruction, the CPU executes the program arranged in the first control area after returning from the call instruction. The gaming machine is configured to be able to refer to when executing the process.

  According to the rotary type gaming machine according to the aspect (6), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (6), the program that exists in the second control area and that is accessed by the CPU is called in the program that exists in the first control area and is accessed by the CPU. When there is an instruction, processing by the CPU can be executed. In that case, as information stored at the time of returning from the call instruction, for example, information held in a register in the CPU (that is, in the second control area immediately before returning from the call instruction) The processing result processed by the program accessed from the CPU) can be transferred to the program that exists in the first control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the subordinate fraud prevention program is taken over to become the main game It becomes possible to execute a program for implementing the sex specification. Here, since the program for implementing the main gaming specifications can process highly confidential information, the processing of the secondary fraud prevention program that can take in the information for fraud prevention from the outside If the result is handed over implicitly, security may be reduced. However, the execution timing of the program for preventing fraud can be limited to this call instruction. Alternatively, on the dump list, the execution timing of the program for preventing fraud is clarified visually, and the delivery timing of the processing result is also clarified on the program source code or on the dump list. Artificially verify the legitimacy of anti-fraud programs (including the timing of delivery of processing results) It becomes easy to testify. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (7) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When a first error (for example, an event in which the medal payout device H is full of game medals shown in step 1208) is detected by the processing of the CPU according to the program arranged in the first control area. And an error process associated with the first error (for example, a medal full error state control process shown in step 1210) can be executed,
The second error (for example, an event in which the data related to the set value is not within the normal range shown in step 1044) is detected by the processing of the CPU according to the program arranged in the second control area. The gaming machine is configured to be capable of executing error processing associated with two errors (for example, non-recoverable error processing shown in steps 1048 and 1300).

  According to the rotary type gaming machine according to the present aspect (7), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (7), the error processing accompanying the first error processed by the program that exists in the first control area and is accessed from the CPU, and the second control area Can be clearly separated on the program source code or the dump list from the error processing associated with the second error processed by the program accessed by the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the error handling associated with the first error is an error that can occur in the game progress (ie, even if no fraud is performed), and the error handling associated with the second error is It can be clarified that the roles of error processing are different from each other. Here, since the specification for the anti-fraud program is likely to be different for each gaming machine maker, it is highly necessary to verify the validity by hand, but the necessity of error processing associated with the second error Can be easily verified in comparison with the error processing associated with the first error, so that it is possible to reduce the labor for verifying the program for preventing fraud.

The spinning machine according to the aspect (8) is
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When performing error detection on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing result data stored in the first information storage area Error detection based on error detection information (for example, a method for performing checksum check) and error detection based on error detection information regarding processing result data stored in the second information storage area (for example, a method for performing checksum check) ) And the game machine are characterized by being performed separately.

  According to the rotary type gaming machine according to the present aspect (8), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the rotary type gaming machine according to the aspect (8), the processing result processed by the program that is present in the first control area and accessed from the CPU, and the processing result that is present in the second control area from the CPU. The processing results processed by the accessed program can be stored in separate information storage areas. In that case, when performing error detection of the stored processing results, each information storage area On the other hand, error detection can be performed separately. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game playability specification and the processing result processed by the program for preventing fraud are not mixedly stored, and the storage If the processed result is destroyed, it is possible to clearly know which of the two processed results has been destroyed. Therefore, for example, when the importance of the processing result processed by the program for preventing fraud is low, even if the processing result processed by the program for preventing fraud is destroyed, If the processing result processed by the program for implementing the game playability specification is held without being destroyed, the processing can be continued.

The spinning machine according to this aspect (9)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When error detection is performed on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing result data stored in the first information storage area A gaming machine configured to perform error detection (for example, a method of performing a checksum check) based on error detection information added to the processing result data stored in the second information storage area is there.

  According to the swivel type gaming machine according to the present aspect (9), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the spinning machine according to the aspect (9), the processing result processed by the program that exists in the first control area and is accessed from the CPU, and the processing result that exists in the second control area and from the CPU. The processing results processed by the accessed program can be stored in separate information storage areas. In this case, when performing error detection of the stored processing results, the respective information storage areas are stored. Error detection can be performed on the integrated one. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game playability specification and the processing result processed by the program for preventing fraud are not mixedly stored, and the storage If the processed result is destroyed, it can be easily known that one of the two processed results is destroyed. Therefore, for example, when the importance of the processing result processed by the program for preventing fraud is high, the processing result processed by the program for implementing the gaming specifications and the program for preventing fraud are processed. It can be configured to continue the processing only when it can be easily derived that none of the processing results is destroyed.

The spinning machine according to this aspect (10)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
Based on an input signal from a predetermined sensor unit (for example, the first input sensor D20s or the second input sensor D30s) by the processing of the CPU according to the program arranged in the first control region, a predetermined event ( For example, it is configured to be able to determine whether or not the occurrence of an event that received one game medal (shown in step 1227)
Based on the input signal from the predetermined sensor unit by the processing of the CPU according to the program arranged in the second control area, an abnormal event related to game progress (for example, shown in a subroutine of step 1400, The gaming machine is configured to be able to determine whether or not an inserted medal backflow error or an inserted medal staying error has occurred.

  According to the spinning cylinder gaming machine according to the aspect (10), the program that exists in the first control area and is accessed from the CPU, and the program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (10), the presence / absence of a normal event related to the game progress based on the sensor signal is further determined by a program that exists in the first control area and is accessed from the CPU. The presence or absence of an abnormal event related to the game progress based on the sensor signal can be determined by a program that exists in the second control area and is accessed by the CPU. In any case, the determination is based on the same sensor signal. It can be. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the same sensor signal is handled as an input signal necessary for the progress of the game in the program for implementing the gameability specification, and the same sensor signal is illegal in the program for preventing illegal acts. Since it can be handled as an input signal necessary for preventing action, it can be clarified that the same sensor signal is handled differently on the program source code or on the dump list. Here, since the specification for the fraud prevention program is likely to be different for each gaming machine manufacturer, it is highly necessary to verify the validity artificially, but the difference in how to handle the same sensor signal. Since it becomes easy to verify by comparing points, it is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to this aspect (11)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
A control signal (for example, a hopper motor drive signal) for instructing payout of the game medium and a predetermined sensor unit (for example, the first payout sensor H10s or the like) by processing of the CPU according to the program arranged in the first control area Based on the non-detection time of the second payout sensor H20s), a payout operation for one game medal after the hopper driving is performed as shown in step 1279, which is an abnormal event related to game progress. It is possible to determine whether or not an event has occurred,
Based on the detection time of the predetermined sensor unit by the processing of the CPU according to the program arranged in the second control area, a second abnormal event (for example, step 1450) A gaming machine configured to be able to determine whether or not a payout medal retention error (shown in a subroutine) has occurred.

  According to the spinning cylinder gaming machine according to the aspect (11), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (11), there is further an event of an “exceptional” abnormal event related to a game progress based on a sensor signal by a program that exists in the first control area and is accessed from the CPU. The presence / absence of occurrence can be determined, and the presence / absence of a “serious” abnormal event related to the game progress based on the sensor signal can be determined by a program that exists in the second control area and is accessed by the CPU. The determination based on the same sensor signal can also be made. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, in the program for implementing the gameability specification, the same sensor signal is handled as an input signal necessary for error detection that can occur during normal game progress, and in the program for preventing fraud Can handle the same sensor signal as an input signal necessary for preventing fraud (that is, necessary for error detection that is difficult to occur during normal game progression), and therefore can be used on program source code or dump list. , It can be clarified that the handling of the same sensor signal is different. . Here, since the specification for the fraud prevention program is likely to be different for each gaming machine manufacturer, it is highly necessary to verify the validity artificially, but the difference in how to handle the same sensor signal. Since it becomes easy to verify by comparing points, it is possible to reduce labor for verifying a program for preventing fraud.

The rotary type gaming machine according to this aspect (12)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A gaming machine including a main game control unit (for example, a main control board M) that controls the progress of the game,
The main game control unit (for example, the main control board M)
A role lottery means (for example, step 1257 executed by the CPUC 100) for performing a role lottery based on the operation of the start switch (for example, the start lever D50);
Until a predetermined minimum game time elapses, even if the start switch (for example, start lever D50) is operated, the game progress restricting means (for example, CPUC100) that waits for the rotation of the plurality of reels (for example, reel M50) to start. Step 3204 executed by
It is configured to store condition device information, which is information related to the winning combination determined by the winning lottery, in a predetermined RAM area,
The condition device information includes first condition device information related to a predetermined type of winning combination, and second condition device information related to a specific type of winning combination different from the predetermined type of winning combination, and the predetermined RAM area The first condition device information is stored in the first storage area, and the second condition device information is stored in the second storage area in the predetermined RAM area,
When storing the first condition device information in the first storage area, 1 is set and stored in the first bit position in the first storage area,
When storing the second condition device information in the second storage area, it is configured to store by setting 1 to the second bit position in the second storage area,
When the start switch (for example, start lever D50) is operated and the winning lottery is performed after completion of a predetermined game, a condition device information output timer (for example, output time timer M80) after the predetermined minimum game time has elapsed. ) Set a predetermined value,
If the value of the condition device information output timer (for example, output time timer M80) is not 0 and the value of the condition device information output timer (for example, output time timer M80) is within a predetermined range, the condition device information Output the first condition device information stored in the first storage area as outside the gaming machine,
When the value of the conditional device information output timer (for example, output time timer M80) is not 0 and the value of the conditional device information output timer (for example, output time timer M80) is within a specific range different from the predetermined range The second condition device information stored in the second storage area as the condition device information is output outside the gaming machine,
When the value of the condition device information output timer (for example, output time timer M80) is 0, the gaming machine is configured to output information based on the value to the outside of the gaming machine. .

The spinning machine according to the aspect (13)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A gaming machine including a main game control unit (for example, a main control board M) that controls the progress of the game,
The main game control unit (for example, the main control board M)
A role lottery means (for example, step 1257 executed by the CPUC 100) for performing a role lottery based on the operation of the start switch (for example, the start lever D50);
Until a predetermined minimum game time elapses, even if the start switch (for example, start lever D50) is operated, the game progress restricting means (for example, CPUC100) that waits for the rotation of the plurality of reels (for example, reel M50) to start. Step 3204 executed by
It is configured to store condition device information, which is information related to the winning combination determined by the winning lottery, in a predetermined RAM area,
The condition device information includes first condition device information related to a predetermined type of winning combination, and second condition device information related to a specific type of winning combination different from the predetermined type of winning combination, and the predetermined RAM area The first condition device information is stored in the first storage area, and the second condition device information is stored in the second storage area in the predetermined RAM area,
When the start switch (for example, start lever D50) is operated and the winning lottery is performed after completion of a predetermined game, a condition device information output timer (for example, output time timer M80) after the predetermined minimum game time has elapsed. ) Set a predetermined value,
If the value of the condition device information output timer (for example, output time timer M80) is not 0 and the value of the condition device information output timer (for example, output time timer M80) is within a predetermined range, the condition device information Read out the first condition device information stored in the first storage area, set 1 at the first bit position in the read first condition device information and output it outside the gaming machine,
When the value of the conditional device information output timer (for example, output time timer M80) is not 0 and the value of the conditional device information output timer (for example, output time timer M80) is within a specific range different from the predetermined range The second condition device information stored in the second storage area is read as the condition device information, and 1 is set at the second bit position in the read second condition device information. Output outside the machine,
When the value of the condition device information output timer (for example, output time timer M80) is 0, the gaming machine is configured to output information based on the value to the outside of the gaming machine. .

The spinning machine according to this aspect (14)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A main game control unit (for example, main control board M) for controlling the progress of the game;
A gaming machine comprising a secondary game control unit (for example, a secondary control board S) that controls information output according to the progress of the game,
The main game control unit (for example, the main control board M)
A role lottery means (for example, step 1257 executed by the CPUC 100) for performing a role lottery based on the operation of the start switch (for example, the start lever D50);
Until a predetermined minimum game time elapses, even if the start switch (for example, start lever D50) is operated, the game progress restricting means (for example, CPUC100) that waits for the rotation of the plurality of reels (for example, reel M50) to start. Step 3204 executed by
Game information transmission means (for example, the processing of step 3165 executed by the CPUC 100) for transmitting game information necessary for information output on the side of the sub game control unit (for example, the sub control board S),
It is configured to store condition device information, which is information related to the winning combination determined by the winning lottery, in a predetermined RAM area,
The condition device information includes first condition device information related to a predetermined type of winning combination, and second condition device information related to a specific type of winning combination different from the predetermined type of winning combination, and the predetermined RAM area The first condition device information is stored in the first storage area, and the second condition device information is stored in the second storage area in the predetermined RAM area,
When storing the first condition device information in the first storage area, 1 is set and stored in the first bit position in the first storage area,
When storing the second condition device information in the second storage area, it is configured to store by setting 1 to the second bit position in the second storage area,
When the start switch (for example, start lever D50) is operated and the winning lottery is performed after completion of a predetermined game, a condition device information output timer (for example, output time timer M80) after the predetermined minimum game time has elapsed. ) Set a predetermined value,
If the value of the condition device information output timer (for example, output time timer M80) is not 0 and the value of the condition device information output timer (for example, output time timer M80) is within a predetermined range, the condition device information Output the first condition device information stored in the first storage area as outside the gaming machine,
When the value of the conditional device information output timer (for example, output time timer M80) is not 0 and the value of the conditional device information output timer (for example, output time timer M80) is within a specific range different from the predetermined range The second condition device information stored in the second storage area as the condition device information is output outside the gaming machine,
When the value of the condition device information output timer (for example, the output time timer M80) is 0, it is configured to output information based on the value to the outside of the gaming machine,
A condition device temporarily stored in a specific RAM area different from the predetermined RAM area at a timing before the condition apparatus information temporarily stored in the predetermined RAM area is output to the outside of the gaming machine. The gaming machine is configured to transmit the game information based on the information to a sub game control unit (for example, the sub control board S).
In addition, the gaming machine according to this aspect may be configured as follows,
The gaming machine according to this aspect (14)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A main game control unit (for example, main control board M) for controlling the progress of the game;
A gaming machine comprising a secondary game control unit (for example, a secondary control board S) that controls information output according to the progress of the game,
The main game control unit (for example, the main control board M)
A role lottery means (for example, step 1257 executed by the CPUC 100) for performing a role lottery based on the operation of the start switch (for example, the start lever D50);
Until a predetermined minimum game time elapses, even if the start switch (for example, start lever D50) is operated, the game progress restricting means (for example, CPUC100) that waits for the rotation of the plurality of reels (for example, reel M50) to start. Step 3204 executed by
Game information transmission means (for example, the processing of step 3165 executed by the CPUC 100) for transmitting game information necessary for information output on the side of the sub game control unit (for example, the sub control board S),
It is configured to store condition device information, which is information related to the winning combination determined by the winning lottery, in a predetermined RAM area,
The condition device information includes first condition device information related to a predetermined type of winning combination, and second condition device information related to a specific type of winning combination different from the predetermined type of winning combination, and the predetermined RAM area The first condition device information is stored in the first storage area, and the second condition device information is stored in the second storage area in the predetermined RAM area,
When the start switch (for example, start lever D50) is operated and the winning lottery is performed after completion of a predetermined game, a condition device information output timer (for example, output time timer M80) after the predetermined minimum game time has elapsed. ) Set a predetermined value,
If the value of the condition device information output timer (for example, output time timer M80) is not 0 and the value of the condition device information output timer (for example, output time timer M80) is within a predetermined range, the condition device information As a result, the first condition device information stored in the first storage area is read out, and information in which 1 is set in the first bit position in the first condition device information is output to the outside of the gaming machine,
When the value of the conditional device information output timer (for example, output time timer M80) is not 0 and the value of the conditional device information output timer (for example, output time timer M80) is within a specific range different from the predetermined range The second condition device information stored in the second storage area as the condition device information is read out, and information in which 1 is set in the second bit position in the second condition device information is taken out of the gaming machine. Output,
When the value of the condition device information output timer (for example, the output time timer M80) is 0, it is configured to output information based on the value to the outside of the gaming machine,
The game information based on the first condition device information is sub-gamed at a predetermined timing before the information in which the first bit position in the first condition device information is set to 1 is output to the outside of the gaming machine. It is configured to transmit to the control unit (for example, sub-control board S) side,
The game information based on the second condition device information is sub-gamed at a predetermined timing before the information in which the second bit position in the second condition device information is set to 1 is output to the outside of the gaming machine. A gaming machine that is configured to transmit to a control unit (for example, sub-control board S) may be used.

The spinning machine according to this aspect (15)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A gaming machine including a main game control unit (for example, a main control board M) that controls the progress of the game,
The main game control unit (for example, the main control board M)
Role lottery means for performing a role lottery based on the operation of the start switch (for example, start lever D50) (for example, processing of step 1257 executed by CPUC100)
With
It is configured to store information on the winning combination determined by the combination lottery in a predetermined RAM area,
When the winning combination determined by the combination lottery is a predetermined winning combination, when the stop switch (for example, the stop button D40) is operated in the first operation mode, the first symbol combination can be stopped and displayed. When the stop switch (for example, stop button D40) is operated in the second operation mode, a second symbol combination different from the first symbol combination can be stopped and displayed.
The profit given to the player is different between when the first symbol combination is stopped and when the second symbol combination is stopped,
When the winning combination determined by the combination lottery is the predetermined winning combination, operation mode data that is information related to the operation mode of the stop switch (for example, the stop button D40) can be output outside the gaming machine,
When the operation mode data is output outside the gaming machine, the first operation mode data is output when the predetermined condition is satisfied, and the first operation mode is output when the predetermined condition is not satisfied. It is configured to output second operation mode data different from the data,
The operation mode data includes data related to the type of the stop switch (for example, the stop button D40) and data related to the stop timing when the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) are stopped. It is a gaming machine characterized by being.

The rotary type gaming machine according to this aspect (16)
A plurality of reels (for example, a reel M50) having a plurality of reels (for example, a left reel M51, a middle reel M52, and a right reel M53) displaying a plurality of types of symbols;
A start switch (for example, start lever D50) operated by a player when rotating the plurality of reels (for example, reel M50);
A player operates to stop the reels (for example, the left reel M51, the middle reel M52, and the right reel M53) provided corresponding to the reels (for example, the left reel M51, the middle reel M52, and the right reel M53). A plurality of stop switches (eg, stop button D40);
A gaming machine including a main game control unit (for example, a main control board M) that controls the progress of the game,
The main game control unit (for example, the main control board M)
Role lottery means for performing a role lottery based on the operation of the start switch (for example, start lever D50) (for example, processing of step 1257 executed by CPUC100)
With
It is configured to store information on the winning combination determined by the combination lottery in a predetermined RAM area,
When the winning combination determined by the combination lottery is a predetermined winning combination, when the stop switch (for example, the stop button D40) is operated in the first operation order, the first symbol combination can be stopped and displayed. When the stop switch (for example, the stop button D40) is operated in the second operation order, the second symbol combination can be stopped and displayed.
The profit given to the player is configured differently when the first symbol combination is stopped and when the second symbol combination is stopped,
When the winning combination determined by the combination lottery is the predetermined winning combination, operation mode data that is information related to the operation mode of the stop switch (for example, the stop button D40) can be output outside the gaming machine,
When the operation mode data is output outside the gaming machine, the first operation mode data is output when the predetermined condition is satisfied, and the first operation mode is output when the predetermined condition is not satisfied. It is configured to output second operation mode data different from the data,
The operation mode data is formed as an aggregate of a plurality of unit data having a predetermined number of bits as unit data, and each unit data in the plurality of unit data includes first data including data related to the operation order of the stop switch, Or it is comprised so that it may become either of the 2nd data including the data regarding the stop timing at the time of stopping the said reel.

The spinning machine according to the aspect (17)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
The processing result data stored in the first information storage area and the processing result stored in the second information storage area by the predetermined program processing arranged in the first control area after returning from the power interruption The gaming machine is configured to perform error detection of data and data saved in the stack area.

The spinning machine according to the aspect (18)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Specific data (for example, set value) among the processing result data that can be stored in the first information storage area but not stored in the second information storage area is arranged in the second control area. A gaming machine configured to determine whether or not it is normal by a predetermined program.

The spinning machine according to this aspect (19)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
The processing result data stored in the first information storage area can be updated by processing by a program arranged in the first control area,
The processing result data stored in the second information storage area is configured not to be updated by a program arranged in the first control area,
The processing result data stored in the second information storage area can be updated by processing by a program arranged in the second control area,
The processing result data stored in the first information storage area is configured not to be updated by a program arranged in the second control area.
Or
The gaming machine according to this aspect is
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
After returning from the power interruption, the processing result data stored in the first information storage area can be initialized by processing by a program arranged in the first control area,
The processing result data stored in the second information storage area is configured not to be initialized by the program arranged in the first control area after returning from the power interruption.
After returning from power-off, the processing result data stored in the second information storage area can be initialized by processing by a program arranged in the second control area,
The processing result data stored in the first information storage area is configured not to be initialized by a program arranged in the second control area after returning from a power failure.
Interrupt control periodically generated after the processing result data stored in the first information storage area and the processing result data stored in the second information storage area are initialized after returning from a power failure Is a game machine that is configured to be executable.

The rotary type gaming machine according to this aspect (20)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
The ROM stores a program for controlling instructions to the CPU and data read according to the program,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which a program is stored (for example, a first control area in the first ROM area);
A first data area in which data is stored (for example, a first data area in the first ROM area);
A second control area in which the program is stored (for example, a second control area in the second ROM area);
A second data area in which data is stored (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program stored in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program stored in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Call a predetermined program stored in the second control area when there is a predetermined call instruction in the program stored in the first control area,
When the CPU executes processing according to the predetermined program, the gaming machine is configured to save data stored in a register before the call instruction to the stack area. is there.
Or
The gaming machine according to this aspect is
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
The ROM stores a program for controlling instructions to the CPU and data read according to the program,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which a program is stored (for example, a first control area in the first ROM area);
A first data area in which data is stored (for example, a first data area in the first ROM area);
A second control area in which the program is stored (for example, a second control area in the second ROM area);
A second data area in which data is stored (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program stored in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the program stored in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Call a predetermined program stored in the second control area when there is a predetermined call instruction in the program stored in the first control area,
When the CPU executes processing in accordance with the predetermined program, the gaming machine is configured to save data stored in a register after the call instruction to the stack area .

The spinning machine according to this aspect (21)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Predetermined data (for example, game state information, information related to the lottery) is stored in the first information storage area, not stored in the second information storage area,
A gaming machine configured to output specific information outside the gaming machine based on the predetermined data by processing by the CPU according to a predetermined program arranged in the second control area. is there.

The spinning machine according to the aspect (22)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Predetermined data (for example, game status information, information relating to the lottery) is stored in the first information storage area, and arranged in the first control area when interrupt control is performed periodically. When there is a call instruction from the first interrupt program being executed, the second interrupt program processing arranged in the second control area is executed, and the second interrupt processing is specified based on the predetermined data A gaming machine characterized in that information can be output outside the gaming machine.

The rotary gaming machine according to the aspect (23)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Call a predetermined program arranged in the second control area when there is a call instruction in the program arranged in the first control area,
When processing is performed in accordance with the predetermined program, check data of the stack area before the call instruction (for example, the stack pointer address value before the call instruction or the stack area before the call instruction) Stored in the predetermined address of the first information storage area,
After the processing by the predetermined program is executed, it is determined whether or not it is normal based on the check data, and if it is determined that it is not normal, error processing is executed.
Or
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
Call a predetermined program arranged in the second control area when there is a call instruction in the program arranged in the first control area,
When executing the process according to the predetermined program, the address value of the stack pointer before the call instruction is stored in the predetermined address of the first information storage area,
After executing the processing by the predetermined program, when determining whether or not it is normal based on the address value of the stack pointer after the execution and the address value stored in the predetermined address, Is a gaming machine characterized by executing error processing.

The rotary type gaming machine according to this aspect (24)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
The stack area is divided into a first stack area and a second stack area,
While the data stored in the register is saved to the first stack area at a specific timing for executing the first processing according to the program arranged in the first control area, the second control area Is configured to save the data stored in the register to the second stack area at a predetermined timing to execute the second processing according to the program arranged in
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, the stack area The gaming machine is configured to change an address value of a stack pointer for managing the address from an address value indicating the first stack area to an address value indicating the second stack area.
The spinning machine according to the aspect (25)
A gaming machine including a ROM (for example, a built-in ROMC110), a RAM (for example, a built-in RAMC120), and a CPU (for example, a CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored,
The ROM (for example, in the example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area in which the program is arranged (for example, a first control area in the first ROM area);
A first data area in which data is arranged (for example, a first data area in the first ROM area);
A second control area in which the program is arranged (for example, a second control area in the second ROM area);
A second data area in which data is arranged (for example, a second data area in the second ROM area);
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by a program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by a program arranged in the second control area;
A stack area (for example, a stack area) in which data stored in a register can be saved;
The stack area is divided into a first stack area and a second stack area,
While the data stored in the register is saved to the first stack area at a specific timing for executing the first processing according to the program arranged in the first control area, the second control area Is configured to save the data stored in the register to the second stack area at a predetermined timing to execute the second processing according to the program arranged in
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, the stack area Is configured to change the address value of the stack pointer for managing the address value indicating the first stack area from the address value indicating the second stack area,
The period until the processing for changing the address value of the stack pointer from the address value indicating the first stack area to the address value indicating the second stack area is completed at the execution timing of interrupt control that occurs periodically. Even if it arrives, the gaming machine is configured such that execution of the interrupt control is prohibited.

P Cylinder type game machine, DU front door (door)
D Door board, D10s Input acceptance sensor D20s First input sensor, D30s Second input sensor D40 Stop button, D41 Left stop button D42 Middle stop button, D43 Right stop button D50 Start lever, D60 Checkout button D70 Display panel, D80 Door switch D90 coin shooter, D100 blocker D130 upper panel, D140 lower panel D150 decoration lamp unit, D160 reel window D170 medal slot, D180 operation status indicator D190 payout number display device, D200 credit number display device D210 insertion number indicator light, D220 bet Button D230 Medal tray, D240 Release port D250 Special game state display device, D260 Key hole D270 Push order display device, D280 ART counter value display device M Main control board, M10 Setting door switch M20 setting key switch, M30 setting / reset button C main control chip, M50 reel M51 left reel, M52 middle reel M53 right reel, M60 ART counter M70 game interval minimum timer, M80 output time timer S sub control board, S10 LED lamp S20 Speaker, S30 Revolving backlight S40 Production display device, SC Sub control chip E Power supply board, E10 Power switch H Medal paying device, H10s First payout sensor H20s Second payout sensor, H40 Hopper H50 Disc, H50a Disc rotation shaft H60 Medal exit, H70 discharge biasing means H80 Hopper motor K rotor board, K10 rotor motor K20 rotor sensor IN Relay board

Claims (1)

In the ROM area ,
A first control area in which the program is stored;
A first data area in which data is stored;
A second control area in which the program is stored;
A second data area in which data is stored,
In the RAM area ,
A first information storage area for storing processing result data by a program stored in the first control area;
A second information storage area for storing processing result data by a program stored in the second control area;
A first stack area where data stored in a register can be saved ;
A second stack area in which data stored in the register can be saved;
Have
After returning from the power-off, at least, the first information storage area in the storage process result data, said second information storage area in the storage process result data, prior Symbol data saved in the first stack region, And error detection based on data saved in the second stack area is performed ,
When executing the program stored in the second control area, the address information stored in the stack pointer is stored in the second information storage area, and the stack pointer corresponds to the second stack area. When storing specific address information and finishing the program stored in the second control area, the address information stored in the second information storage area can be stored in the stack pointer. A gaming machine characterized by the above.

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