JP6503704B2 - Gaming machine - Google Patents

Description

  It relates to a gaming machine.

  A rotating drum type gaming machine (slot machine) is a plurality of rows of a plurality of symbols arranged on the outer periphery, triggered by the game start instruction device (start lever) being operated after inserting a predetermined number of game medals. The cylinder (reel) rotates, and as a result of stopping the rotating cylinder using the rotating cylinder stop device (stop button) for stopping the rotating operation, a combination of predetermined symbols (for example, “777”) on the effective line If there is a line), it is common that the special gaming state in which the player has a higher profit state than the normal gaming state {the gaming state in which the winning probability of the winning combination is higher than that in the normal state} is there. Here, in the slot machine, an image or the like for presentation for enhancing the amusement of the game may be displayed on a display such as liquid crystal in a form synchronized with the rotation operation and the stop operation of the reel. Many are configured to predict and enjoy the game result while comparing a symbol displayed on the reel with an image for effect displayed on the display when the stop button or the like is operated.

  In the pachinko game machine, a symbol called "special symbol" is displayed on the display unit such as 7 segments in a variable display, triggered by the game ball entering the starting opening (start chucker), and the special symbol Is a special mode (for example, "7"), a special gaming state in which the player has a high profit state than the normal gaming state {a special winning state (normally closed at a special winning opening in the closed state) The so-called "digi patch" type (conventional "first type game machine") of the type that transitions to the game of {is generally used. Here, in order to reduce the burden of display control of the special symbol directly linked to the player's profit, it is called "decorative symbol" for effect to enhance the interest of the game separately from the "special symbol" described above. The symbol to be displayed may be variably displayed on a display such as a liquid crystal having a size larger than that of the display unit in a form synchronized with the variation of the special symbol. Then, when the variation of the special symbol is started, the decorative symbol also begins to change accordingly, and when the special symbol is stopped in a specific mode (for example, "7"), the decorative symbol is also according to this, a predetermined mode (for example, It will stop at "777". In many cases, the player can clearly recognize that the transition to the special game has been decided by the decorative symbol being stopped in a predetermined manner.

  Such a scheme is common to many types of gaming machines of this type, but the program capacity for controlling the operation of gaming machines, etc. is for preventing the mixture of unauthorized programs (guaranteeing the legitimacy of programs provided by gaming machine manufacturers). From the point of view, the upper limit of the capacity is strictly regulated, and in addition to the program for implementing the game characteristic specification, the gaming machine is tampered with (for example, for the slot and slot for game media) There are also a number of anti-tamper programs implemented to prevent unauthorized access to game media and the like by illegal means.

JP 2011-147675

  However, under the present circumstances, there are many cases where a program for implementing gameplay specifications and a program for preventing fraudulent actions are mixedly arranged on the ROM, and as a result, it is difficult to verify the legitimacy of these programs There is a problem that

The gaming machine according to this aspect is
As ROM area,
A first control area in which the program is stored,
A first data area in which data is stored;
A second control area in which the program is stored,
A second data area in which data is stored and
Have at least
As a RAM area,
A first information storage area capable of storing processing result information of a program stored in the first control area;
A second information storage area capable of storing processing result information of a program stored in the second control area;
Have at least
Based on the program stored in the first control area, it is determined whether or not the power failure has occurred, and when it is determined that the power failure has occurred, the program stored in the second control area is: The error detection information can be calculated based on the information in the RAM area, and the calculated error detection information is stored in a predetermined storage area of the second information storage area by the program stored in the second control area. After that, the loop process waiting for reset can be executed by the program stored in the first control area, and in the loop process waiting for reset, it is not judged whether or not the voltage state is recovered.
It is a game machine characterized by.
<Supplementary Note>
In addition, although listed about another aspect different from this aspect below, it is possible to implement without being limited to these at all.
The gaming machine according to this aspect is
A gaming machine comprising a ROM (for example, a built-in ROM C110), a RAM (for example, a built-in RAM C120), and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program disposed in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When error detection is performed on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing related data stored in the first information storage area Error detection based on error detection information (for example, a method of performing a checksum check) and error detection based on error detection information on processing result data stored in the second information storage area (for example, a method of performing a checksum check) And the like are separately configured.

  According to the gaming machine of the present aspect, it is possible to easily verify the legitimacy of the program for implementing the game characteristic specification and the program for preventing fraudulent acts.

FIG. 1 is a perspective view of a drum-type gaming machine according to the present embodiment. FIG. 2 is a perspective view of the turning-type gaming machine according to the present embodiment with the door open. FIG. 3 is a perspective view of the inside of the medal slot in the reel-type gaming machine according to the present embodiment. FIG. 4 is a front view and a top view of the medal payout device in the roll-type game machine according to the present embodiment. FIG. 5 is an overall electrical configuration diagram of the reel-type gaming machine according to the present embodiment. FIG. 6 is an electrical configuration diagram according to the main control chip of the roll-type game machine according to the present embodiment. FIG. 7 is a memory map configuration diagram of a main control chip in the reel-type gaming machine according to the present embodiment. FIG. 8 is a main flowchart on the main control board side in the reel-to-play type gaming machine according to the present embodiment. FIG. 9 is a flowchart of setting change device control processing on the main control board side in the reel-type game machine according to the present embodiment. FIG. 10 is a flowchart of the game progression control process (first sheet) on the main control board side in the reel-type game machine according to the present embodiment. FIG. 11 is a flow chart of the game progression control process (second sheet) on the main control board side in the reel-type game machine according to the present embodiment. FIG. 12 is a flow chart of the game progression control process (third sheet) on the main control board side in the reel-type game machine according to the present embodiment. FIG. 13 is a flow chart of return impossible error processing on the main control board side in the reel-type game machine according to the present embodiment. FIG. 14 is a flowchart of medal insertion error detection processing on the main control board side in the reel-type game machine according to the present embodiment. FIG. 15 is a flowchart of a medal payout error detection process on the main control board side in the reel-type game machine according to the present embodiment. FIG. 16 is a flowchart of insertion / withdrawal error detection processing on the main control board side in the reel-type gaming machine according to the present embodiment. FIG. 17 is a flowchart of timer interrupt processing on the main control board side in the reel-type game machine according to the present embodiment. FIG. 18 is a flowchart of the medal insertion check process on the main control board side in the reel-type game machine according to the present embodiment. FIG. 19 is a flowchart of the medal payout check process on the main control board side in the reel-type game machine according to the present embodiment. FIG. 20 is a flowchart of insertion / withdrawal error check processing on the main control board side in the reel-type game machine according to the present embodiment. FIG. 21 is a flowchart of the power-off process on the main control board side in the reel-type game machine according to the present embodiment. FIG. 22 is a main flowchart (first sheet) on the main control board side in the reel-to-play type gaming machine according to the second embodiment. FIG. 23 is a main flowchart (second sheet) on the main control board side in the reel-type gaming machine according to the second embodiment. FIG. 24 is a flow chart of the game progression control process (second sheet) on the main control board side in the reel-type game machine according to the second embodiment. FIG. 25 is a flowchart of medal insertion error detection processing on the main control board side in the reel-type game machine according to the second embodiment. FIG. 26 is a flowchart of medal payout error detection processing on the main control board side in the reel-type game machine according to the second embodiment. FIG. 27 is a flowchart of insertion / withdrawal error detection processing on the main control board side in the reel-type gaming machine according to the second embodiment. FIG. 28 is a flow chart of the game progression control process (third sheet) on the main control board side in the reel-type game machine according to the second embodiment. FIG. 29 is a flow chart of return impossible error processing on the main control board side in the reel-to-play type gaming machine according to the second embodiment. FIG. 30 is a flow chart of timer interrupt processing on the main control board side in the reel-type game machine according to the second embodiment. FIG. 31 is a flowchart of the power-off process on the main control board side in the reel-type game machine according to the second embodiment.

  First, the meaning of each term in the present specification will be described. "Random number" is a random number used in a lottery (lottery by an electronic computer) for determining some game contents in a revolving type gaming machine, and includes pseudo random numbers in addition to random numbers in a narrow sense (for example, as random numbers Are hard random numbers, soft random numbers as pseudo random numbers). For example, so-called "basic random numbers" that affect the outcome of the game, specifically, "winning random numbers" associated with the transition of special games or winning combinations can be mentioned. The "CPU" is synonymous with what is known in the art, and is not limited at all to the used architecture (CISC, RISC, number of bits, etc.) or processing performance. "Power off (power off)" indicates that the power supply voltage supplied to the gaming machine has become equal to or lower than a predetermined level regardless of whether or not the power switch provided in the gaming machine is operated. It also includes the interruption of power supply due to unforeseen situations such as unit damage or blackout. "ROM" is synonymous with what is known in the industry, and physically holds information (for example, "1" for an element configuration that conducts when a current for reading data is given, conduction In the case of an element configuration that does not perform, it becomes "0"). RAM is synonymous with what is well known in the industry, and holds information electrically (for example, when a current for reading data is given, “1” if stored, if not stored. It becomes “0.” It is a general rule that the backup power is supplied to the part or all of the data stored in the RAM at the time of power interruption). The “playing state” is, for example, a special gaming state in which game medals are easily obtained and which is advantageous to the player (so-called a big hit game, which corresponds to what is called a bonus game, first type BB, second type BB, etc.) ) Replay probability change gaming state (RT state), which is a state in which the replay probability is higher (or lower) than the normal gaming state where the replay rate is a predetermined value For example, an AT (assist time) state in which the stopping order of the reels can be notified, an ART (assist replay time) state in which the RT state and the AT state are combined, and the like can be mentioned. Further, even in the normal gaming state, there are high probability normal gaming state, low probability normal gaming state, etc., in which the transition lottery probability to the RT state, the AT state, and the ART state is different. In addition, there is no problem even if the gaming state is combined {Furthermore, these gaming states and functions (for example, a transition lottery to an AT state, an output of a notification instruction according to a stop order of reels, etc.) control the game progress There is no problem even if everything is mounted on the main control board side}.

  Although the following embodiments are based on a reeled type gaming machine (so-called slot machine), the present invention is not limited thereto, and other gaming machines (for example, a pachinko gaming machine, ball ball, arrangement) When applied to a ball, etc.), it is within the range, that is, one having a microcomputer chip (chip mounted with CPU, ROM, RAM) for controlling the progression of the game and operating the program by the microcomputer chip It is a technology that can be applied. Note that the present embodiment is merely an example, and relates to the order of each step regarding various processes such as the location and function of each means, the on / off timing of the flag, and the means name etc. It is not limited to the following aspects. In addition, the embodiments and modifications described above should not be construed as limiting as applied to specific ones, and may be any combination. For example, it should be understood that a modification of one embodiment is a modification of another embodiment, and even if one modification and another modification are independently described, It should be understood that a combination of the modification and the other modification is also described.

  Prior to the detailed description of the present invention, a brief configuration according to the present invention will now be described.

  The present invention is not limited to a configuration in which the first RAM area (or the register area) can be updated and referred to in the processing of the CPUC 100 based on the program code arranged in the second ROM area among the reeled type gaming machines according to the present invention. Embodiment) will be described in detail.

  In the process of the CPUC 100 based on the program code arranged in the first ROM area among the reeling type gaming machines according to the present invention, the second RAM area can be referred to and arranged in the second ROM area. A configuration in which the first RAM area can be referred to in the processing of the CPUC 100 based on the program code being described will be described in detail in the second embodiment.

(This embodiment)
Here, before describing each component, the feature (outline) of the reel-type gaming machine P according to the present embodiment will be described. Hereinafter, each element will be described in detail with reference to the drawings.

  First, the basic structure of the front side of the roll-to-play gaming machine according to the present embodiment will be described with reference to FIG. 1 (FIG. 2 for a part of the configuration). First, the reel-type game machine P mainly includes a front door (also referred to as a front door), a back box (also referred to as a cabinet or a base), and a reel unit installed in the back box, a hopper unit, a power supply unit, and main control It comprises a substrate M (substrate on which the main control chip C is mounted). Hereinafter, these will be described in order.

  Next, the front door DU of the reel-type game machine P includes a decoration lamp unit D150 and a medal receiver D230. First, the decoration lamp unit D150 has a light emission source that emits light in accordance with the progress of the game of the reel-type game machine P. Further, a door switch D80 capable of detecting the open / close state of the front door DU is provided. In addition, the front door DU is provided with a keyhole D260, and a key (door key) matching the shape of the keyhole D260 is inserted into the keyhole D260 {by adding it and twisting it in a predetermined direction (for example, clockwise)} The front door DU is configured to be openable. Furthermore, in the present embodiment, an error state (a door opening error or the like described later) can be canceled by inserting the door key into the keyhole D 260 (in addition and twisting in a predetermined direction (for example, counterclockwise)). It is configured. Next, the medal receiver D230 is a receiver for gaming medals (or may be simply referred to as medals) discharged from the outlet D240.

  Next, the front door DU includes a mechanism for making the gaming state visible, a mechanism for enabling the input of game media, a mechanism for operating the reel unit, and the like. Specifically, as a mechanism for making the gaming state visible, the reel window D160, the number-of-inputs indicator light D210, the operation state indicator light D180, the special gaming state display device D250, the number-of-payouts display device D190, the number-of-credits display device D200 etc. are attached. In addition, as a mechanism for enabling the insertion of game media and the input of the bet number (bet number), the medal insertion slot D170, the bet button D220, and the mechanism for enabling the payout of the inserted game media, the settlement The button D60 is attached. A start lever D50 and a stop button D40 are attached as a mechanism for operating the reel unit. Each element will be described in detail below.

<Mechanism for making the gaming state visible>
Next, the reel window D160 is a transparent member formed of a synthetic resin or the like that constitutes a part of the front door DU, and is configured to allow visual recognition of the reel unit installed in the gaming machine frame through the reel window D160. ing. Further, the number-of-inputs indicator light D210 is configured by LEDs, and is configured to light the same number of LEDs as the number of medals currently bet (to insert game medals necessary to start one game) It is done. In addition, the operation state indicator light D 180 is configured by an LED, and is configured to be turned on / off according to the current operation state (the medal acceptance / non-replay state, the re-game winning state, the game start wait state, etc.). Further, the special game state display device D250 is configured of a 7-segment display, and is configured to display the total number of payouts paid out during the special game. Incidentally, the special game state display device D250 may not be provided, and in such a case, the player is in the special game by displaying the total number of payouts on the effect display device S40. The total number of payouts paid out can be recognized and can be a user-friendly game machine. Further, the number-of-payouts display device D190 is configured of a 7-segment display, and is configured to display the number of game medals currently paid out. Further, the credit number display device D200 is configured of a 7-segment display, and is configured to display the total number of credits (credit number) stored in the gaming machine as medals owned by the player.

<A mechanism for enabling input of gaming media>
Next, the medal insertion slot D170 is an insertion slot for game medals, and the game medals inserted into the insertion slot under the situation where the medals can be received are guided into the gaming machine frame. Further, an insertion acceptance sensor D10s, a first insertion sensor D20s, and a second insertion sensor D30s are provided in the gaming machine frame as sensors for detecting the insertion of medals, and the gaming machine frame When it is determined that the guided game medal has been inserted normally, the inserted medal can be detected as a betted medal. In addition, the bet button D220 is configured to be operable by the player, and is configured to be able to bet medals (credit medals) stored therein by the operation. Further, the settlement button D60 is configured to be operable by the player, and it becomes possible to pay back the stored medals (credit medals) and / or the bet medals to the player by the operation. ing. The gaming medals paid back by the operation of the settlement button D60 are paid out to the outlet D240.

<Mechanism for Operating Reel Unit>
Next, the start lever D50 is configured to be operable by the player, and is configured to be able to start the operation of the reel unit by the operation. The stop button D40 also has a left stop button D41, a middle stop button D42 and a right stop button D43 which can be operated by the player, and the operation of the reel unit can be sequentially stopped by operating the respective stop buttons. It is configured.

  Next, the reel unit of the reel-type game machine P includes a reel M50 and a drive source (a stepping motor or the like) of the reel M50. Further, the reel M50 includes a left reel M51, a middle reel M52, and a right reel M53. Here, each reel portion is formed of a synthetic resin or the like, and a plurality of symbols are drawn on the outer periphery (on the reel band) of the reel portion. And based on operation of each stop button in start lever D50 and stop button D40, it is constituted so that rotation operation and stop operation of each reel part are enabled. Although not shown, LEDs (hereinafter sometimes referred to as reel backlights) are provided inside the left reel M51, the middle reel M52 and the right reel M53, and when the LEDs are lit, the reel portion The light transmitted through the outer periphery can be visually recognized as if the outer periphery of the reel portion was lit.

<Other mechanism>
In addition, inside and outside of the gaming machine frame of the revolving type gaming machine P, as a mechanism for enhancing the interest of the game, effect display device S40 for displaying effects such as advance notice effect and background effect, various lighting modes The upper panel D130 and the lower panel D140 which are members formed with LED lamp S10 which can be lighted, speaker S20 which can output a sound, and a synthetic resin etc. are provided.

  Next, FIG. 2 is a perspective view showing the internal structure of the reel-type gaming machine P by opening the front door DU. The effect display device S40 is attached to the upper part on the back side of the front door DU. A reel window D160 is provided substantially at the center of the front door DU, and a door substrate D described later is provided below the reel window D160. Further, to the door substrate D, input signals such as the above-described stop button D40, start lever D50, and settlement button D60 are input. Further, below the door substrate D, a speaker S20 is provided.

  Further, although details will be described later, an insertion reception sensor D10s, which is a passage for game medals inserted from the medal insertion slot D170, is provided near the door substrate D, and below the insertion reception sensor D10s. A coin shooter D90 or the like is provided for guiding the gaming medals to the outlet D240. The insertion acceptance sensor D10s mainly has the function of sorting the game medals inserted from the medal insertion slot D170 based on the dimensions, and accepting only the game medals conforming to the standard dimensions, and it is determined that the functions do not conform. The medal (or other foreign matter) that has been made is configured to be returned to the outlet D240 by the blocker D100. If the game medal is inserted before the player operates the start lever D50 (in a state where the insertion of the game medal is effective), the game medal is selected by the insertion reception sensor D10s, and only those which satisfy the standard The medals which are inserted into the hopper H40 and which do not meet the standard are to be returned to the outlet D240 through the coin shooter D90. On the other hand, when the game medal is inserted after the start lever D50 is operated (in a state where the insertion of the game medal is not effective), the inserted game medal passes through the coin shooter D90 and the discharge port D240. Will be returned to Further, a sensor relating to medal insertion described later in detail is provided in the inside (the back of the flow path) of the insertion acceptance sensor D10s, and when the accepted game medal that satisfies the dimensional standard passes, the first insertion sensor D20s The signal is detected by the second loading sensor D30s and supplied to the main control board M described later.

  Above the reel M50 is stored a main control board M described later which controls the entire game, and behind each reel M50 is driven each reel (left reel M51, middle reel M52, right reel M53) A later-described turning base substrate K is stored. Further, on the left side of the reel M50, there is stored a sub control board S described later which controls various effects performed using the effect display device S40 shown in FIG. 1, the LED lamp S10, the speaker S20 etc. . In addition, on the main control board M, a setting key switch M20 used to execute setting change device control processing to be described later (for setting change), setting / reset capable of executing setting value change, error cancellation, etc. A setting door switch M10 is connected which determines the opening and closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30 and the like. Although the setting key switch M20, the setting / reset button M30, and the setting door switch M10 are not illustrated, they may be provided at appropriate positions on the main control substrate M (ie, the front door) It should be provided at a position where artificial access is difficult if the DU is not opened).

  Below the reel M50, a hopper H40 from which inserted game medals are collected, and a medal payout device H for paying out game medals are provided, and a power supply substrate for supplying power to the entire rotating game machine P E is stored. The game medals paid out from the medal payout device H are paid out from the outlet D240 through the coin shooter D90. Further, on the front surface of the power supply substrate E, a power switch E10 for turning on the power of the reel-type game machine P is also provided.

  Next, FIG. 3 is a perspective view showing a path (selector) of the game medal inserted into the medal insertion slot D170 inside the reeling type gaming machine. The gaming medal inserted into the medal insertion slot D170 first passes through the insertion acceptance sensor D10s. The insertion acceptance sensor D10s is a mechanical double sensor, and when the game medal passes, two projecting mechanisms are pressed to turn on and the game medal can normally pass through the passage. Become. In addition, with such a configuration, when a foreign object (for example, one having a diameter smaller than the game medal) which is not a game medal is inserted, the two protruding mechanisms are not pressed. Since the medal can not maintain the standing state, the medal can not pass through the passage (the medal falls) and is paid back to the discharge port D240. Besides, the insertion reception sensor D10s is configured to be able to determine that it is an error even when the on time continues for a predetermined time or more (as a result, the blocker D100 may be turned off). .

  When the gaming medal normally passes through the blocker D100, it passes through the first insertion sensor D20s and the second insertion sensor D30s immediately after the passage. The input sensors (the first input sensor D20s and the second input sensor D30s) are composed of two sensors (arranged adjacent to each other at a distance smaller than the standard diameter of the game medals).・ Various errors (to be described later) by monitoring the off state (the transition sequence of the combination of the on / off of the first closing sensor D20s and the second closing sensor D30s, etc.) and the on / off time , An insertion medal retention error, an insertion medal backflow error, etc.).

  Next, FIG. 4 is a front view and a perspective view of the medal payout device H in the reeling type gaming machine. The medal payout device H operates the settlement button in a state where there is a credit (a game medal stored electronically in the gaming machine) or a bet (a medal inserted to start a game). It will be activated when the game medal is paid out by winning or winning. In operation, first, the hopper motor H80 is driven to rotate the disk H50 about the disk rotation axis H50a. By the rotation, the game medal in the medal payout device H displaces the discharge urging means H70 and flows downward from the game medal outlet H60 toward the discharge port D240. The payout sensors (the first payout sensor H10s and the second payout sensor H20s) are composed of two sensors, and the on / off states of the respective sensors (the first payout sensor H10s and the second payout sensor H20s are on). It is configured to be able to detect various errors (disbursed medal retention errors, etc. described later) by monitoring the transition sequence of combinations of off, etc., and the on / off time. More specifically, for example, when the game medal outlet H60 is normally passed, the first payout sensor H10s = off, the second payout sensor H20s = off, and so on by the displacement of the discharge energizing means H70. 1 Dispensing sensor H10s = off Second dispensing sensor H20s = off → first dispensing sensor H10s = on second dispensing sensor H20s = off first dispensing sensor H10s = on second dispensing sensor H20s = on → first dispensing Since sensor state transition such as sensor H10s = on, second dispensing sensor H20s = off → first dispensing sensor H10s = off, second dispensing sensor H20s = off, the movement opposite to this sensor state transition is detected It can be exemplified to configure to make an error.

  Next, referring to the block diagram of FIG. 5, an electrical schematic configuration of the reel-to-play type gaming machine P according to the present embodiment will be described. First, the drum-type gaming machine according to the present embodiment mainly includes the sub control board S, the door board D, the rotating body board K, the power supply board E, the relay board IN, centering on the main control board M for controlling the progress of the game A setting door switch M10, a setting key switch M20, a setting / reset button M30 and the like are connected to be able to exchange data. The solid line in the figure shows the movement related to the exchange of data, and the broken line in the figure shows the power supply route. The power supply route is not limited to this. For example, power may be supplied from the power supply substrate E to the relay substrate IN or the door substrate D without intervention of the main control substrate.

  The main control board M is a board that controls the progress of the entire game performed in the reel-type game machine P. The main control chip C is mounted on the main control board M, and the CPUC 100, the built-in ROM C 110, the built-in RAM C 120, etc. are mounted on the main control chip C so that they can mutually exchange data by bus ( The illustration and details will be described later). The main control board M receives a signal indicating that the start lever D50 or the like has been operated from the door board D mounted on the front door DU, and the sub control board S, the door board D, and the rotating body board The operation of these various substrates is controlled by outputting a control command (or control signal) to K and the like.

  Further, the sub control chip S is also mounted on the sub control substrate S as in the case of the main control substrate M described above, and the sub control chip SC is provided with a CPU, a ROM, a RAM, etc. Are mutually connected so as to be able to exchange data with each other. In addition, to the sub control substrate S, various LED lamps S10, speakers S20, effect display devices S40, a torso backlight S30, and the like are connected. Here, the rotating drum back light S30 is a light which is provided inside the left reel M51, the middle reel M52, and the right reel M53, and illuminates the design drawn on the surface of the reel from the back side. The sub control board S analyzes various control commands received from the main control board M, and outputs various driving signals to the various LED lamps S10, the speaker S20, the effect display device S40, the rotating drum back light S30, etc. We are directing.

  On the door substrate D, the above-described closing acceptance sensor D10s, first closing sensor D20s, second closing sensor D30s, stop button D40 for stopping the rotating reel M50, and start for starting the rotation of the reel M50 A lever D50, a payment button D60 for paying out stored game medals (credits) and inserted game medals and ending the game, various display panels D70 for displaying the state of the game D210, operation status indicator light D180, special gaming status display device D250, number-of-payouts display device D190 is a group of display devices such as a credit number display device D200, etc.) Door switch D80 for executing changes, game medals determined to be incompatible after being inserted (or other Blocker D100 or the like for refund things) the outlet D240 is connected. Further, the door substrate D is connected so as to be able to exchange data with the main control substrate M described above. Therefore, when the start lever D50, the stop button D40, the settlement button D60, etc. provided on the front door DU are operated, a signal relating to the operation is supplied to the main control board M via the door board D. It has become. Further, a signal that the insertion acceptance sensor D10s detects the passage of the game medal is also supplied to the main control board M via the door board D.

  Further, to the spinning drum substrate K, a spinning drum motor K10 for rotating the reel M50, a spinning drum sensor K20 for detecting the rotational position of the reel M50, and the like are connected. The spinning drum substrate K can stop the reel M50 at the determined stop position by driving the spinning drum motor K10 while detecting the rotational position of the reel M50 by the spinning drum sensor K20. There is. Further, in the reel-type gaming machine of the present embodiment, a so-called step motor (stepping motor) is used for the reel-in motor K10. In the step motor, 504 steps are set as the number of steps for one rotation of the reel M50. In addition, a predetermined number (for example, 21 pieces) of symbols of substantially uniform size are set on each reel (left reel M51, middle reel M52, right reel M53), and the number of steps corresponds to one symbol. , 24 steps (= 21/504) are set. There is no problem in changing the number of steps and the number of symbols per revolution of the reel.

  The medal payout device H is connected to the main control board M via the relay board IN, and pays a predetermined number (for example, 10) of game medals based on a control signal from the main control board M. Do the action to put out. The first payout sensor H10s and the second payout sensor H20s, which execute determination of whether or not the medals have been normally paid out, and measurement of the number of gaming medals, are provided to the medal payout device H, and the disc H50. A hopper motor H80 for rotating is connected.

  The power consumed by these various control boards and boards is supplied from a power supply board E (a board for controlling the presence or absence of power supply by a power switch E10). In FIG. 5, the manner in which power is supplied from the power supply substrate E is indicated by a broken arrow. As illustrated, power is directly supplied from the power supply substrate E to the main control substrate M and the sub control substrate S, and various substrates (the door substrate D, the rotating drum substrate K, the relay substrate IN) Power is supplied via the main control board M. An AC voltage of a predetermined amount (for example, 100 V) is supplied to the power supply substrate E, and the power is converted to a DC voltage of a specified voltage and then supplied to each control substrate and substrate.

  In addition, on the main control board M, a setting key switch M20 used to execute setting change device control processing to be described later (for setting change), setting / reset capable of executing setting value change, error cancellation, etc. A setting door switch M10 is connected which determines the opening and closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30 and the like.

<Configuration Example of Basic Circuit of Main Control Unit>
Next, a configuration example of the main control chip C of the main control substrate M will be described with reference to FIG.

  First, in the main control chip C shown in FIG. 6, the CPU C 100, built-in ROM C 110 (first ROM area C 111, second ROM area C 112), built-in RAM C 120 (first RAM area C 121, second RAM area C 122), external bus control circuit C 190, parallel In addition to input port C130, address decode circuit C150, timer circuit C170, counter circuit C180, and reset control circuit C220, interrupt control circuit C160, clock circuit C210, random number generation circuit C140, verification block C230, unique information C240, arithmetic circuit C250 Are all connected to one another via an internal bus C200.

  The details of the above-described units will be described below.

  First, the CPUC 100 executes various numerical calculations, information processing, control processing and the like according to programs and data of the built-in ROM C 110 and the built-in RAM C 120. The built-in ROM 110 stores control programs and various data. The built-in RAM 120 temporarily stores data. Also, the built-in ROM C 110 and the built-in RAM C 120 hold an address and data as a set, and the application is divided by the address range. The main applications are the program area and the data area, but the details of this point will be given to the description of the memory map described later.

  The external bus control circuit C190 has an IO request terminal (XIORQ terminal), a memory request terminal (XMREQ terminal), a read signal terminal (XRD terminal), a write signal terminal (XWR terminal), and a 16-bit address output terminal (A0 terminal to A15 terminal) and data input / output terminals (D0 terminal to D7 terminal) which are input / output terminals of 8-bit width. In the present embodiment, among the data input / output terminals (terminals D0 to D7), data output to each drive circuit (for example, the trunk board K via the relay board IN) and each peripheral control circuit (for example, the peripheral control circuit) , And is used for data input from various sensors and various operation members via the door substrate D. The data input / output destination by this data input / output terminal (terminal D0 to terminal D7) is the address signal output from the address output terminal (terminal A0 to terminal A15) and the chip select signal output from the address decoding circuit C150. It is switched by using.

  The parallel input port C130 has four input terminals (terminal P0 to terminal P3). For example, one of the input terminals of these input terminals (terminal P0 to terminal P3) is connected to the start lever D50, and a latch signal for causing the CPUC 100 to acquire a random number generated by the random number generation circuit C140 It outputs to the random number generation circuit C140.

  The address decode circuit C150 has a predetermined number (for example, 14) of output terminals (XCS0 terminal to XCS13 terminal). The output terminals (terminals XCS0 to XCS13) are connected to a peripheral control circuit outside the main control chip C, and are output from data input / output terminals (terminal D0 to D7) of the external bus control circuit C190. It is used to output a chip select signal or the like for switching the data transmission destination.

  The timer circuit C170 is used to measure time. The timer circuit C170 outputs a time-out signal to the counter circuit C180 when the set measurement time has passed. On the other hand, the counter circuit C180 is used to measure the number of times of rising (or falling) of various signals. As signals measured by the counter circuit, besides the system clock of the main control chip C, a timeout signal from the timer circuit, a memory read / write signal, a memory request signal, an external input / output signal, a response signal to an interrupt, etc. It can be measured.

  The reset control circuit C220 has two terminals of a system reset input terminal (XSRST terminal) and a reset output terminal (XRSTO terminal). The system reset input terminal (XSRST terminal) is connected to a voltage monitoring circuit (a circuit for monitoring a voltage, not shown). When a system reset signal (for example, a signal of L level for a predetermined time) is input from the system reset input terminal (XSRST terminal), the reset control circuit C220 transmits the system reset signal to the circuit inside the main control chip C. While outputting, a reset signal (for example, a rising signal from L level to H level) is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the main control chip C. In this case, in the main control chip C, a process called system reset is performed to initialize each circuit. One example of the system reset is performed at the time of power on.

  Further, the reset control circuit C220 includes a watchdog timer C222 and a designated area outside traveling inhibition circuit C221. When the watchdog timer C 222 times out, or when the CPU C 100 refers to an address outside the predetermined range (traveling outside the designated area), the reset control circuit C 220 compares the internal circuit of the main control chip C with that of the main control chip C. Output either a system reset signal or a user reset signal. Note that which of the system reset signal and the user reset signal is to be output depends on the setting of the program area (details will be described later) in the built-in ROM C110. Further, to the peripheral control circuit outside the main control chip C, a reset signal is output from the reset output terminal (XRSTO terminal).

  The main control chip C can execute either the above-described system reset or a process called user reset depending on the setting.

  Traveling outside the designated area means that the program is operating unexpectedly. In this case, the CPUC 100 operates with code that should not be treated as a program. Such a situation may be caused by some sort of fraud as well as a so-called runaway situation due to a program error. In this case, normal operation can be restored by any of the above-described system reset and user reset processing. Further, when the watchdog timer C 222 times out, there may be a runaway state due to a program error, or a case where the CPUC 100 can not perform the originally designed operation due to a voltage drop. In this case as well, it is configured to be able to restore normal operation by any of the above-described system and user reset processing.

  The interrupt control circuit C160 generates an interrupt to appropriately execute processing according to the change of the external input or the internal state. The interrupt process includes, for example, a process that is executed when an external input (a signal from a sensor) is received. In the present embodiment, timer interrupt processing executed in response to an interrupt request from the timer circuit is executed. The interrupt control circuit C160 includes an internal information register C161, and the internal information register C161 includes an abnormality in the cycle of the external clock (count clock) that determines the random number update cycle in the random number generation circuit C140, and an update of the random number. , And information on the reset factor of the user reset that occurred immediately before are stored.

  The clock circuit C210 has a predetermined division ratio (for example, 1/2) of an external clock (in this example, a 24 MHz clock) input from a crystal oscillator (not shown) through an external clock input terminal (EX terminal). Then, the system clock after division (in this example, a clock of 12 MHz) is supplied to each circuit in the main control chip C. Also, the system clock is output to the peripheral control circuit outside the main control chip C via the system clock output terminal (CLKO terminal).

  The random number generation circuit C 140 holds the updated random number in the random number register when the latch signal of the random number is received using a clock signal (count clock) for updating the random number. In this embodiment, the external clock signal input from the crystal oscillator through the external clock input terminal (RCK terminal) is divided by a predetermined division ratio (for example, 1/2) and used as this count clock. However, it is also possible to use a clock signal inside the main control chip C, in which case the crystal oscillator is not necessary. The value held in the random number register can be read out and used as a random number. Incidentally, when the random number is read out from the random number register, the random number register can be made into an allowable state which allows the next random number to be latched.

  The verification block C230 is for executing a security check which is an authenticity inspection of whether or not the main control chip C is a legitimate one that has passed the type approval, and the signal related to the security check is transmitted via the SC terminal and the BRC terminal. The external terminal board is configured to be able to transmit or receive from the external terminal board.

  The unique information C 240 stores a unique identification number written at the time of manufacture of the main control chip C, and the identification number can not be rewritten. The arithmetic circuit C250 is a circuit that executes arithmetic operations and logical operations.

<Memory map>
Next, an example of a memory map of the main control chip C shown in FIG. 6 will be described with reference to FIG. In the memory map, address spaces from "0000H" to "FFFFH" are shown. Among these, the built-in ROM C 110 is allocated to the space from "0000H" to "27FFH", and the register area built in each circuit in the main control chip C is allocated to the space from "2800H" to "28FFH" In the space from "F000H" to "F2FFH", the built-in RAMC 120 is allocated, and in the space from "FDD0H" to "FDFBH", XCS decode area (interpreting a given machine language as internal representation An area for executing decoding is allocated. The CPU C 100 can execute an access to the corresponding hardware by executing an instruction to access these addresses.

  The built-in ROM C 110 has a first ROM area that mainly controls the progress of the game and a second ROM area that mainly controls processing different from normal progress of the game such as error-related operations. The first ROM area is allocated to the space from "0000H" to "1FFFH", and the second ROM area is allocated to the space from "2000H" to "27FFH". The first ROM area is configured to have a larger capacity than the second ROM area (in other words, the data capacity existing in the first ROM area and accessed by the CPUC 100 exists in the second ROM area). Is configured to be larger than the data capacity accessed from

  The first ROM area stores a first control area in which a program code (instruction code set for the CPUC 100) is stored, and program data used by the program (read by CPUC 100 processing based on the program code). The first data area being stored, the area where various identification information (company name, manufacturing date, model name, etc.) is stored, and the various settings used when operating the main control chip C (operation of the random number generation circuit C140 And a program management area in which the operation setting of the watchdog timer C 222 and the like are stored. Although the memory map image in the first ROM area is illustrated in the same drawing, the number of bytes in each area and the presence or absence of the unused area are merely examples.

  The second ROM area stores a second control area in which a program code (instruction code set for the CPUC 100) is stored, and program data used by the program (read by CPUC 100 processing based on the program code). And the second control area is configured to have a smaller capacity than the first control area (in other words, the CPUC 100 exists in the second control area). The program code capacity accessed from the first control area is smaller than the program code capacity accessed from the CPUC 100), and the second data area is configured to have a smaller capacity than the first data area. (In other words, it exists in the second data area and is accessed by the CPUC 100. Program data capacity is smaller than the program data capacity to be accessed from there to the first data area CPUC100).

  On the other hand, the built-in RAMC 120 is a first RAM area which is an area for mainly storing information based on the progress of the game and a second RAM area which is an area for storing information based on processing different from the normal progress of the game such as error mainly And the stack area used when the program needs to store data internally, the first RAM area is allocated to the space from "F000H" to "F1FFH", and The second RAM area is allocated to the space from F200H to F2C9H, and the stack area is allocated to the space from F2CAH to F2FFH (However, the number of bytes in each area is only an example. ).

  In addition, the first RAM area has a first work area which is a work area for temporarily storing information relating mainly to the progress of the game, and the second RAM area temporarily stores information relating mainly to an error relation and the like. And a checksum area, which is a work area for detecting an error of information temporarily stored in the first RAM area and the second RAM area. The first RAM area is configured to have a larger capacity than the second RAM area. Further, in the present embodiment, the checksum area includes only the second RAM area (does not include the first RAM area), and the checksum area includes both the first RAM area and the second RAM area. It is configured to manage a checksum (summed information temporarily stored in both sides). Further, in the present embodiment, as described later, when calculating the checksum, the calculation is also performed including the unused area, but it is not limited to this, and the area excluding the unused area (the first The checksum may be calculated for the work area and the second work area). Further, the method of error detection is not limited to the method of performing checksum check, but may use another method (e.g., parity check etc.), in which case the checksum area This is an area for storing information for error detection (for example, parity bits etc.) required when using the method.

  The address of the area where various identification information (company name, manufacturing date, model name, etc.) is stored may be used as the address of the built-in RAM or later. Further, there is no problem even if the address which is an unused area is changed, but it is preferable to provide an unused area between (between) the first data area and the second control area. That is, in the case of the memory map configuration as shown in FIG. 7, the program code existing in the first control area and accessed by the CPUC 100 and the program code existing in the second control area and accessed by the CPUC 100 are Since they are arranged separately (in a non-consecutive arrangement of addresses) on the memory map and sandwich the unused area, both program codes can be visually arranged on the program source code or dump list. The above can be clearly divided (otherwise, the same can be said in the case where an unused area is interposed).

  Here, with respect to the ROM mounted on the main control board M, in order to prevent the program etc. modified by the fraudulent action being written, it is configured not to provide an unused area (area not filled with). It is preferable (for example, filling unused areas with all 0's, filling used areas at a young address, etc.). Also, in the first control area and the first data area, unused data (for example, reference in a gaming machine with a difference in specifications) is prevented to prevent reference to data that is not normally referred to due to noise or cheating. It is preferable not to provide data to be used or data used only for testing in the development stage. In addition, the first control area, the first data area, the second control area, the second data area, the first work area, and the second work area are packed in young addresses and used in the area (in the area No unused area (for example, "0010H" to "0050H" in the first control area in the range of "0000H" to "0FA7H" are not considered as unused areas). Is preferred. In this example, in the unused area, all bits are “0”, and in the area other than the unused area, any bit is “1” (not “0”. ing).

  Next, FIGS. 8 to 34 are flowcharts showing a flow of general processing performed by the main control board M in the present embodiment. First, in the flowchart showing the flow of these processes, when the CPUC 100 executes a process based on the program code and program data arranged in the first ROM area, or the process result is registered in the CPUC 100 (register “Processing in the first ROM / RAM area” is the case where the processing result is referred to in the processing of the CPUC 100 based on the program code arranged in the first ROM area or in the first RAM area). As shown in the figure, it is shown surrounded by a dotted line, and describes that the CPUC 100 executes processing "based on data in the first ROM / RAM area". Further, in the flowchart showing the flow of these processing, when the CPUC 100 executes processing based on the program code and program data arranged in the second ROM area, or the processing result is registered in the CPUC 100 (register “Processing in the second ROM and RAM area” when storing (updating) in the area (the second RAM area) or referring to the processing result in the processing of the CPUC 100 based on the program code arranged in the second ROM area As shown in the figure, it is shown surrounded by a dotted line, and describes that the CPUC 100 executes processing "based on the data in the second ROM / RAM area".

  The flowchart is mainly composed of processing steps (shown as rectangles), judgments (shown as diamonds), flow lines (arrows), and terminals (shown as rounded rectangles) indicating start / end / return etc. ing. Also, in the case where the details of the processing steps are illustrated in another flowchart, those referring to the other flowchart are illustrated as a subroutine (shown as a rectangle in which the left and right lines are double lines). . Here, at the development stage of the gaming machine, it is also carried out to simultaneously develop gaming machines with different specifications, but in this example, the subroutine executed by the gaming machines with different specifications in the processing on the main side ( It is configured so as not to leave a subroutine not normally used, and prevents processing relating to an unused subroutine that is not normally executed due to noise or cheating.

  Then, in the case of not following these movements, for example, when the second RAM area is updated or referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area, or conversely, the second ROM area When updating or referring to the first RAM area in the processing of the CPUC 100 based on the program code arranged in step (d), it is noted that the update / reference destination is (or Even in line with the movement, it may be noted as necessary for clarity). In addition, if the movement of the process in the embodiment shown below is summarized conceptually, it is divided into the following cases.

  <Operation 1> The program data arranged in the first ROM area (particularly, the first data area) is processed by the processing of the CPUC 100 based on the program code arranged in the first ROM area (especially, the first control area). It is arranged in the second ROM area (especially the second data area) by the processing of the CPUC 100 based on the program code read or arranged in the second ROM area (especially the second control area) Program data is read out. However, depending on the processing of the CPUC 100 based on the program code arranged in the first ROM area (especially, the first control area), the program data arranged in the second ROM area (especially, the second data area) is read. Depending on the processing of the CPUC 100 based on the program code arranged in the second ROM area (especially the second control area), the program arranged in the first ROM area (especially the first data area) Data can not be read.

  <Operation 2> The first RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and the program data arranged in the first ROM area. Further, the second RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and program data arranged in the second ROM area.

  <Operation 3> The processing of the CPUC 100 based on the program code arranged in the second ROM area may be executed by a call instruction (for example, a CALL instruction in mnemonic) in the program code arranged in the first ROM area. The processing of the CPUC 100 based on the program code disposed in the first ROM area can not be executed by a call instruction (for example, a CALL instruction in mnemonic) in the program code disposed in the second ROM area. That is, the program code disposed in the first ROM area and the program code disposed in the second ROM area are in a master-slave relationship, and a call instruction in the program code disposed in the main first ROM area Only then can the CPUC 100 process be executed based on the program code arranged in the secondary second ROM area.

  <Operation 4> When there is a call instruction in the program code arranged in the main first ROM area and the processing of the CPUC 100 based on the program code arranged in the subordinate second ROM area is executed At the time of execution of processing of the CPUC 100 based on a program code arranged in the second ROM area, the information (for example, information in the register area) stored at the time of the call instruction is referred to. Alternatively, after processing of the CPUC 100 is executed based on the program code disposed in the second ROM area, the processing returns to CPUC 100 processing based on the program code disposed in the first ROM area. In this case, when executing the processing of the CPUC 100 based on the program code arranged in the main first ROM area, the information (for example, the information in the register area) stored at the time of the return is referred to.

  <Operation 5> In the above <Operation 4>, when the information in the register area is not referred to, <Operation 5-1> the processing result of the CPUC 100 based on the program code arranged in the main first ROM area. Is stored in the first RAM area, and the processing result stored in the first RAM area can be referenced and updated when executing the processing of the CPUC 100 based on the program code arranged in the secondary second ROM area. (When returning the processing of the CPUC 100 based on the program code arranged in the main first ROM area, refer to the updated first RAM area), <Operation 5-2> Main ROM area 1 The processing result of the CPUC 100 based on the program code placed in the above is stored in the first RAM area. When executing processing of CPUC 100 based on the program code arranged in the second ROM area, the processing result stored in the first RAM area can be referred to, and arranged in the subordinate second ROM area The processing result of the CPUC 100 based on the program code is stored in the second RAM area, and is stored in the second RAM area when processing of the CPUC 100 based on the program code arranged in the main first ROM area is restored. Operate in one of the following ways:

  Although the flow of the general process performed by the main control board M will be described based on the above premise (the premise in the description), the above-described <Operation 1> to <Operation 3 will be described. While it is a premise that> is essential, <Operation 4> and <Operation 5> are discarded by the implementation method of how to carry over the processing results in the CPUC 100 between program codes in a master-slave relationship. Since it is a premise that can be selected, even if it is exemplified in only one of <Operation 4> and <Operation 5> in the following processing flow, it is possible to substitute by the other. It supplements beforehand.

  First, FIG. 8 is a flow chart showing a flow of processing executed for the first time by the CPUC 100 of the main control board M after the power supply of the reeling type game machine P is turned on (or at the time of system reset or user reset) . In this case, in general, the program codes are sequentially executed from the program code arranged in the address (that is, the first control area) to be 0000H of the built-in ROM C110. Depending on the configuration of the main control chip C in the main control board M, after turning on the power supply of the reel-type game machine P (or at the time of system reset or user reset), the above-described security check is performed In some cases, it may be assumed that the program code for executing the security check is configured to be executed first, but even in such a configuration, it is disposed in the first control area shown in the present embodiment. (In addition, even if the initial address of the built-in ROM 110 is not 0000H, it does not change to the entire configuration of the memory map described above = each address Is only shifted properly). Further, in the present embodiment, the backup power is supplied to the built-in RAM C 120 so that the data stored in the built-in RAM C 120 is maintained even when the power is shut off.

<Processing in the first ROM / RAM area>
First, after turning on the power supply of the reel-type gaming machine P at step 1000, the CPUC 100 sets a timer interrupt based on the data in the first ROM and RAM area at step 1002 (here, the type of timer interrupt). Is set, and in the subsequent processing, when the timer interrupt is started, the flowchart related to the timer interrupt processing which will be described later is periodically executed). Next, in step 1004, the CPUC 100 executes function setting of the main control chip C based on the data in the first ROM / RAM area. Next, in step 1006, the CPUC 100 calls power on / off recovery processing of the second ROM area.

<Processing in Second ROM and RAM Area>
Next, in step 1008, the CPU 100 calculates a checksum from the top address of the first RAM area to the address immediately before the checksum area based on the data in the first ROM and RAM area. Next, in step 1010, the CPUC 100 checks the first RAM and the second RAM based on the data in the first ROM and RAM area (for example, the calculated checksum and the checksum data held in the checksum area). Check whether the data stored in the built-in RAM C120 is correctly held by power off / power off recovery based on the above, and generate the power off recovery data (the result of the check or the process on power off in step 1800) Based on the processing executed in step b) and held in the second RAM area). Next, in step 1012, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1014.

<Processing in the first ROM / RAM area>
Next, in step 1014, the CPUC 100 confirms the switch states of the front door switch D80, the setting door switch M10 and the setting key switch M20 based on the data in the first ROM and RAM area. Next, in step 1016, the CPUC 100 refers to the data in the first ROM / RAM area and determines whether any of the door switch D80, the setting door switch M10 and the setting key switch M20 is off. If Yes in step 1016, in step 1018, the CPUC 100 calls non-setting change time initialization processing in the second ROM area based on the data in the first ROM and RAM area, and shifts to step 1022. On the other hand, if No in step 1016, the CPUC 100 calls the setting change initialization processing in the second ROM area based on the data in the first ROM and RAM area in step 1020, and shifts to step 1030.

<Processing in Second ROM and RAM Area>
Next, in step 1022, the CPUC 100 turns on / off the power-off processing flag in the first RAM (turns on in step 1904) based on the data in the second ROM and RAM area and checks sum status of all the RAMs ( Referring to the check result in step 1010, it is determined whether the power failure recovery data in the second RAM is not normal. If Yes in step 1022, in step 1026, the CPUC 100 sets a backup error display based on data in the second ROM and RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes an impossible-to-return error process, which will be described later, based on the data in the second ROM / RAM area. On the other hand, in the case of No at step 1022, the CPUC 100 at step 1028 displays an initialization range of the first RAM and the second RAM based on the data in the second ROM and RAM area. It determines and sets (for example, sets in the register area) the unused area in the 1 RAM area and the unused area in the second RAM area, and proceeds to step 1036.

  On the other hand, after the process of step 1020, in step 1030, CPUC 100 turns on / off the power-off processed flag in the first RAM based on the data in the second ROM and RAM area (turned on in step 1904) and all Referring to the checksum state (the check result in step 1010) of the RAM, it is determined whether or not the power failure recovery data in the second RAM is normal. If Yes in step 1030, in step 1032, the CPUC 100 determines and sets the initialization ranges of the first RAM and the second RAM to all ranges except the setting value in the RAM based on the data in the second ROM and RAM area. (For example, set in the register area), and the process goes to step 1036. The setting value is stored at the top address of the first RAM area. On the other hand, if No in step 1030, the CPUC 100 determines and sets the initialization ranges of the first RAM and the second RAM to all the ranges of the RAM based on the data in the second ROM and RAM area in the step 1034 (for example, , Set in the register area), and the process goes to step 1036.

  Next, in step 1036, the CPUC 100 executes initialization of only the second RAM area within the determined initialization range based on the data in the second ROM and RAM area. Next, in step 1038, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1040.

<Processing in the first ROM / RAM area>
Next, in step 1040, the CPUC 100 executes initialization of only the first RAM area within the initialization range determined in step 1028, step 1032, or step 1034, based on the data in the first ROM / RAM area. Next, in step 1041, the CPUC 100 determines whether any one of the front door switch D80, the setting door switch M10 and the setting key switch M20 is off based on the data in the first ROM / RAM area. If Yes in step 1041, the CPUC 100 calls setting value check processing in the second ROM area based on the data in the first ROM / RAM area in step 1042, and shifts to step 1044. On the other hand, if No in step 1041, the CPUC 100 executes setting change device control processing (also referred to as setting change processing) to be described later based on the data in the first ROM and RAM area in step 1100.

<Processing in Second ROM and RAM Area>
Next, in step 1044, the CPUC 100 refers to the inside of the first RAM area based on the data in the second ROM and RAM area, and the data relating to the setting value in the first RAM area is within the normal range (1 to 6 in this example). 6) It is determined whether or not it is. If Yes in step 1044, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area in step 1046, and proceeds to step 1050. On the other hand, if No in step 1044, the CPUC 100 sets a set value error display (for example, it will be displayed on the number-of-payouts display device D190) based on the data in the second ROM and RAM area in step 1048. (For example, set in the register area). Next, in step 1300, the CPUC 100 executes an impossible-to-return error process, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1050, the CPUC 100 restores the stack pointer based on the data in the first ROM / RAM area, based on the data related to the stack pointer saved in the process upon power-off (step 1902). Next, in step 1052, the CPUC 100 reads the input port based on the data in the first ROM and RAM area. Next, in step 1054, the CPUC 100 starts the timer interrupt set in step 1002 based on the data in the first ROM and RAM area. Next, in step 1056, the CPUC 100 turns off the power-off processing flag in the flag area in the first ROM and RAM area, and returns to the processing at the power-off according to the restored stack pointer.

  Although not shown, it is preferable that the initial value (value at the start of processing) of the temporary storage area (RAM area etc.) mounted on the main control board M is configured not to be a value at which the special game is executed. (In order to prevent the special game from being erroneously executed when the process for judging the execution of the special game has been executed immediately after the start of the processing of the program, due to noise or cheating. Further, although not shown, when storing random numbers such as winning random numbers in the RAM area of the main control board M, a dedicated storage area is secured, and in the byte storing information related to the random numbers. It is preferable to be configured to store only the information related to the random number (do not store other information such as various timer values) (by noise or the like when operating another data stored in the same 1 byte) To prevent information related to random numbers from being rewritten).

<Processing in the first ROM / RAM area>
Next, FIG. 9 is a flowchart of setting change device control processing according to the subroutine of step 1100 in FIG. First, in step 1102, the CPUC 100 sets a stack pointer based on data in the first ROM / RAM area (initializes with the start address of the process). Next, in step 1118, the CPUC 100 starts timer interrupt based on the data in the first ROM and RAM area. Next, in step 1120, the CPUC 100 refers to the data in the first ROM and RAM area and determines whether or not the set value in the first RAM area is within the normal range (1 to 6 in this example). . If Yes in step 1120, in step 1122, the CPUC 100 sets a predetermined value (for example, 1 = the value most disadvantageous to the player) to the set value based on the data in the first ROM and RAM area, and step 1124 Migrate to On the other hand, also in the case of No at step 1120, the process proceeds to step 1124. Next, in step 1124, the CPUC 100 displays that the setting change device is in operation on the error display LED (not shown) based on the data in the first ROM and RAM area, and sets the setting display LED (not shown). Display the value and move to step 1126.

  Next, in step 1126, the CPUC 100 determines whether the setting / reset button M30 has been switched from off to on based on the data in the first ROM and RAM area. If Yes in step 1126, the CPUC 100 adds 1 to the current set value in step 1128 based on the data in the first ROM and RAM area (if the set value exceeds 6 as a result of the addition, the setting is made The value is 1), and the process proceeds to step 1130. Also in the case of No at step 1126, the process proceeds to step 1130. Next, in step 1130, the CPUC 100 determines whether the start lever D50 has been switched from off to on based on the data in the first ROM / RAM area. If Yes in step 1130, in step 1132, the CPUC 100 determines whether the setting key switch M20 has been switched from on to off based on the data in the first ROM and RAM area. In the case of No at step 1132, the process of step 1132 is looped. On the other hand, if Yes in step 1132, the CPUC 100 displays that the operation of the setting change device has ended on the error display LED (not shown) based on the data in the first ROM and RAM area in step 1134 and displays the setting The display of the setting value of the LED (not shown) is erased, and the process proceeds to the game progress control process of step 1200. In the case of No at step 1130, the process proceeds to step 1126.

<Processing in the first ROM / RAM area>
Next, FIG. 10 is a flowchart of the game progression control process (first sheet) according to the subroutine of step 1200 in FIG. First, in step 1202, the CPUC 100 sets a stack pointer based on the data in the first ROM / RAM area (initializes with the start address of the process). Next, in step 1204, the CPUC 100 sets data (e.g., bet upper limit number, winning pay line, etc.) necessary for the game based on the data in the first ROM / RAM area. Next, in step 1206, CPUC 100 sets the gaming state (for example, during normal game, during big hit, during reprobability fluctuation game, during AT game, etc.) based on the data in the first ROM and RAM area. Do. Next, in step 1208, the CPUC 100 determines whether or not the medal payout device H is full of game medals, based on the data in the first ROM / RAM area. Specifically, a sub tank (not shown) for storing medals overflowing from the medal payout device H is provided, and it is judged by conduction / non-conduction of current by a plurality of full detection sensors provided in the sub tank (through the medal If the current is turned on, it is judged full. If Yes in step 1208, then the process moves to step 1218.

  On the other hand, if No in step 1208, the CPUC 100 turns on the medal full error flag based on the data in the first ROM and RAM area in step 1210 (for example, it turns on the medal full error flag area in the first RAM area). Update with a value equivalent to Next, in step 1212, based on the data in the first ROM and RAM area, the CPUC 100 displays an error number corresponding to a medal full error with a 7-segment LED (for example, storage display LED or number of acquired LEDs). Next, in step 1214, the CPUC 100 refers to the data in the first ROM and RAM area, and whether or not the medal full error has been released (for example, the current by the sub tank is non-conductive, and the setting / reset button M30 is It is determined whether or not it has been pressed. If Yes in step 1214, the CPUC 100 turns off the medal full error flag based on the data in the first ROM and RAM area in step 1216 (for example, corresponds to turning off the inside of the medal full error flag area of the first RAM area). Update with the value), and move on to step 1218. On the other hand, in the case of No at step 1214, the process proceeds to step 1212. Next, in step 1218, the CPUC 100 permits medal insertion acceptance based on the data in the first ROM and RAM area (in the next game of replay, the insertion operation is automatically executed), and Processing (processing of step 1220). Here, in step 1218, the on process (the process of forming the medal channel) of the blocker D100 is performed. Specifically, when the replay role is established in the previous game, the on processing of the blocker D100 is performed on the condition that the current storage number (credits) is less than a predetermined value (50 sheets in this example). Run. In other words, when the current storage number (credit) is a predetermined value, the on process of the blocker D100 is not executed. On the other hand, when the player is not established in the previous game, the on process of the blocker D100 is uniformly executed. By configuring in this manner, even when the replay is established, when the number of stored (credits) does not reach the predetermined value, the gaming medals can be inserted, and it is possible to re-enter more than the normal gaming state. When staying in the RT state with a high probability of gaming, or reminiscent of the re-playing in a hard-to-understand manner re-playing (replay spoofed as a small part: bell-bell-bell on invalid line, cherry on left reel) Even when the symbol combination) is stopped, the player can play the game with good rhythm (without feeling of incongruity).

<Processing in the first ROM / RAM area>
Next, FIG. 11 is a flowchart of the game progression control process (second sheet) according to the subroutine of step 1200 in FIG. First, in step 1220, the CPUC 100 determines, based on the data in the first ROM and RAM area, whether a gaming medal has not been bet and there is no credit. If YES in step 1220, the CPUC 100 satisfies the setting display conditions in step 1221 based on the data in the first ROM and RAM area (for example, door switch D80, setting door switch M10, and setting key switch M20). When all are turned on, it is determined whether or not the condition is satisfied. If YES in step 1221, the CPUC 100 displays a setting display LED (not shown, but the number-of-payouts display device D190, the number-of-credits display device D200, the number-of-inputs indicator light D210). Setting values are displayed, and the process moves to step 1221. In the case of No at step 1220 or step 1221, at step 1224, the CPUC 100 executes management relating to the insertion and settlement of game medals based on the data in the first ROM and RAM area. Next, in step 1225, the CPUC 100 confirms the number of receivable game medals based on the data in the first ROM / RAM area. Next, in step 1226, the CPUC 100 determines whether the blocker D100 is on based on the data in the first ROM and RAM area. In the case of Yes in step 1226, the CPUC 100 determines in step 1227 whether the first insertion sensor D20s or the second insertion sensor D30s is on based on the data in the first ROM and RAM area (first input) When the sensor D20s or the second insertion sensor D30s is turned on, it is determined that one game medal has been received). If Yes in step 1227, the CPUC 100 calls the medal insertion error detection process in the second ROM area based on the data in the first ROM and RAM area in step 1228, and proceeds to step 1400.

<Processing in Second ROM and RAM Area>
Next, in step 1400, the CPUC 100 executes a medal insertion error detection process described later based on the data in the second ROM and RAM area. Next, in step 1229, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1230.

<Processing in the first ROM / RAM area>
Next, in step 1230, the CPUC 100 determines whether the first loading sensor D20s and the second loading sensor D30s are off based on the data in the first ROM and RAM area (first loading sensor D20s or [2] When the first insertion sensor D20s and the second insertion sensor D30s are turned off after the insertion sensor D30s is turned on, it is assumed that one game medal received passes the first insertion sensor D20s and the second insertion sensor D30s judge). In the case of Yes in step 1230, the CPUC 100 determines in step 1231 that the insertion of one normal game medal has been accepted based on the data in the first ROM and RAM area. Although not shown, after step 1231, the CPUC 100 sets the upper limit number of credits (50 in this example) and the maximum number of bets (3 in this example) based on the data in the first ROM and RAM area. It is determined whether or not the blocker D100 is turned off (in a state in which the medal passage is not formed). If NO in step 1230, the process goes to step 1228. If NO in step 1226 or 1227, the process goes to step 1232.

  Next, in step 1232, the CPU 100 determines whether or not the settlement button D 60 has been operated, based on the data in the first ROM and RAM area. In the case of Yes in step 1232, in step 1233, the CPUC 100 determines whether or not there is a remaining number of credits or gaming medals bet based on the data in the first ROM / RAM area. In the case of Yes in step 1233, the CPUC 100 sets the hopper drive flag (a flag in the first RAM area) in step 1234 based on the data in the first ROM and RAM area, and turns on when driving the hopper motor H80. Turn on the flag) and execute payout of one game medal. Next, in step 1236, the CPUC 100 refers to the data in the first ROM / RAM area to determine whether the first payout sensor H10s or the second payout sensor H20s is on (the first payout sensor H10s or When the second payout sensor H20s is turned on, it is determined that the payout operation of one gaming medal is being performed). If Yes in step 1236, the CPUC 100 calls the medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area in step 1238, and proceeds to step 1450. Here, although not specified on the flowchart, only the remaining number of credits is subject to settlement if the previous game was a replay role.

<Processing in Second ROM and RAM Area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing described later based on the data in the second ROM and RAM area. Next, in step 1240, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1247.

<Processing in the first ROM / RAM area>
On the other hand, if No in step 1236, the CPUC 100 in step 1241 has passed a predetermined time (for example, 5 seconds) after hopper driving (after the processing timing in step 1234) based on the data in the first ROM and RAM area. It is determined whether or not. Specifically, whether or not the situation in which it is determined that the medal is not paid out continued for a predetermined time despite the fact that the hopper drive signal is transmitted to the hopper motor H80 (the hopper motor H80 is rotating) It is determined whether or not. If Yes in step 1241, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM and RAM area in step 1242 (for example, it corresponds to turning on the inside of the medal empty error flag area of the first RAM area) Update with the value to Next, in step 1244, the CPUC 100 executes a medal empty error display based on the data in the first ROM and RAM area. Next, in step 1245, the CPUC 100 determines whether the medal empty error has been canceled (for example, whether the setting / reset button M30 has been pressed) based on the data in the first ROM and RAM area. If Yes in step 1245, the CPUC 100 turns off the medal empty error flag in the flag area in the first ROM and RAM area in step 1246 (for example, turns off the medal empty error flag area in the first RAM area). Update with the corresponding value), and the process proceeds to step 1247. On the other hand, in the case of No at step 1245, the process proceeds to step 1244.

<Processing in the first ROM / RAM area>
Next, in step 1247, the CPUC 100 determines whether the first dispensing sensor H10s and the second dispensing sensor H20s are off based on the data in the first ROM and RAM area (the first dispensing sensor H10s or the first 2) When the first payout sensor H10s and the second payout sensor H20s are turned off after the payout sensor H20s is turned on, it is determined that the payout operation of one game medal for which the payout operation has been performed is completed). If YES in step 1247, the CPUC 100 turns off the hopper drive flag based on the data in the first ROM and RAM area in step 1248, and proceeds to step 1233. If the result of the step 1241 or the step 1247 is NO, the process proceeds to the step 1236.

  On the other hand, if No in step 1232 or step 1233, the CPUC 100 calls the second ROM area insertion / withdrawal error detection processing based on the data in the first ROM / RAM area in step 1249 and shifts to step 1500.

<Processing in Second ROM and RAM Area>
Next, in step 1500, the CPUC 100 executes an insertion / withdrawal error detection process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1250, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1251.

<Processing in the first ROM / RAM area>
Next, in step 1251, the CPUC 100 determines that the start lever D50 is effective (for example, the specified number of game medals for starting the game has been inserted, etc.) based on the data in the first ROM and RAM area, and It is determined whether or not the start lever D50 has been operated. If Yes in step 1251, the CPUC 100 executes processing for obtaining random numbers and turning off the blocker D 100 based on data in the first ROM and RAM areas in step 1252, and then performs setting value check processing for the second ROM area. The call is transferred to step 1253.

<Processing in Second ROM and RAM Area>
Next, in step 1253, the CPUC 100 determines whether the set value in the first RAM area is within the normal range (1 to 6 in this example) based on the data in the second ROM / RAM area. In the case of Yes at step 1253, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area at step 1254, and shifts to the next process (the process of step 1257). On the other hand, if No in step 1253, in step 1256, the CPUC 100 sets a setting value error display based on the data in the second ROM and RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes an impossible-to-return error process, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 12 is a flowchart of the game progression control process (third sheet) according to the subroutine of step 1200 in FIG. First, in step 1257, the CPUC 100 starts an internal lottery (a lottery for determining the winning combination in the game) based on the data in the first ROM and RAM area. Next, in step 1258, the CPUC 100 starts rotating all the reels (reel M50) based on the data in the first ROM and RAM area, and shifts to step 1260. Next, in step 1260, the CPUC 100 makes a draw-in point creation request (a request for determining the stop position of the rotating left reel M51, middle reel M52, right reel M53, based on the data in the first ROM and RAM area). It is determined whether or not there has been a request for stopping according to the stopping order and the stopping positions of the other reels. If Yes in step 1260, the CPUC 100 creates a lead-in point based on the data in the first ROM and RAM area in step 1261, and shifts to step 1262. On the other hand, also in the case of No at step 1260, the process proceeds to step 1262. Next, in step 1262, the CPUC 100 executes a reel stop acceptance check based on the data in the first ROM and RAM area. Next, in step 1263, the CPUC 100 determines whether or not any stop button (left stop button D 41, middle stop button D 42, right stop button D 43) has been operated based on the data in the first ROM and RAM area. Do. In the case of Yes in step 1263, the CPUC 100 selects the reel corresponding to the stop button operated based on the data in the first ROM / RAM area in step 1264 (for example, the left reel M51 corresponds to the left stop button D41) The stop position of is determined, and the process moves to step 1265. On the other hand, also in the case of No at step 1263, the process proceeds to step 1265. Next, in step 1265, the CPUC 100 executes an all reel stop check process based on the data in the first ROM and RAM area. Next, in step 1266, the CPUC 100 determines whether or not all reels (left reel M51, middle reel M52, right reel M53) have stopped based on the data in the first ROM / RAM area. If Yes in step 1266, the CPUC 100 calls the display determination check process of the second ROM area based on the data in the first ROM and RAM area in step 1267, and proceeds to step 1268. In the case of No at step 1266, the process proceeds to step 1260.

<Processing in Second ROM and RAM Area>
Next, in step 1268, the CPUC 100 compares the symbol stop position data in the first RAM with the internally established combination stoppable position data based on the data in the second ROM and RAM area. Next, in step 1269, the CPUC 100 refers to the data in the second ROM and RAM area to determine whether or not the combination of the displayed symbols is normal. If it does not match, it is judged to be abnormal). In the case of Yes in step 1269, in step 1500, the CPUC 100 executes an insertion / withdrawal error detection process described later based on the data in the second ROM / RAM area. Next, in step 1270, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1274. On the other hand, if No in step 1269, the CPUC 100 sets a display determination error display based on the data in the second ROM and RAM area (for example, sets it in the register area) in step 1272. Next, in step 1300, the CPUC 100 executes an impossible-to-return error process, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1274, the CPUC 100 executes payout processing of game medals by winning based on data in the first ROM / RAM area. Next, in step 1275, the CPUC 100 determines whether or not there is a winning combination for paying out gaming medals based on the data in the first ROM and RAM area {the maximum number of credits of gaming medals acquired by winning combinations (this example Then, if 50) is exceeded, payout of game medals is executed}. In the case of Yes in step 1275, the CPUC 100 turns on the hopper drive flag (a flag in the first RAM area based on the data in the first ROM and RAM area in step 1276) when driving the hopper motor H80. Turn on the flag) and execute payout of one game medal. Next, in step 1277, the CPUC 100 determines whether or not the first payout sensor H10s or the second payout sensor H20s is on based on the data in the first ROM / RAM region (the first payout sensor H10s or the first (2) When the payout sensor H20s is turned on, it is determined that the payout operation of one gaming medal is being performed). If Yes in step 1277, the CPUC 100 calls the medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area in step 1278, and proceeds to step 1450.

<Processing in Second ROM and RAM Area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing described later based on the data in the second ROM and RAM area. Next, in step 1284, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1286.

<Processing in the first ROM / RAM area>
On the other hand, if No in step 1277, the CPUC 100 in step 1279 based on the data in the first ROM / RAM area has passed a predetermined time (for example, 5 seconds) after hopper driving (after the processing of step 1276). It is determined whether or not. If Yes in step 1279, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM and RAM area in step 1280 (for example, it corresponds to turning on the inside of the medal empty error flag area of the first RAM area). Update with the value to Next, in step 1281, the CPUC 100 executes the medal empty error display with the 7-segment LED based on the data in the first ROM and RAM area. Next, in step 1282, the CPUC 100 determines whether the medal empty error has been canceled (for example, whether the setting / reset button M30 has been pressed or not) based on the data in the first ROM / RAM area. If Yes in step 1282, the CPUC 100 turns off the medal empty error flag based on the data in the first ROM and RAM area in step 1283 (for example, it corresponds to turning off the inside of the medal empty error flag area of the first RAM area). Update with the value) and go to step 1286. On the other hand, in the case of No at step 1282, the process proceeds to step 1281.

<Processing in the first ROM / RAM area>
Next, in step 1286, the CPUC 100 determines whether the first dispensing sensor H10s and the second dispensing sensor H20s are off based on the data in the first ROM and RAM area (the first dispensing sensor H10s or the first 2) When the first payout sensor H10s and the second payout sensor H20s are turned off after the payout sensor H20s is turned on, it is determined that the payout operation of one game medal for which the payout operation has been performed is completed). If Yes in step 1286, the CPUC 100 turns off the hopper drive flag based on the data in the first ROM and RAM area in step 1288, and proceeds to step 1290. In the case of No at step 1279 or step 1286, the process proceeds to step 1277. Next, in step 1290, the CPUC 100 determines, based on the data in the first ROM and RAM area, whether or not the payout corresponding to the winning (the winning determined in step 1275) is completed. In the case of Yes in step 1290, the CPUC 100 executes game end processing (for example, clearing of the bet number, transition processing of the game state, etc.) in step 1292 based on the data in the first ROM and RAM area, and the next processing It transfers to (the process of step 1202). In the case of No at step 1286, the process proceeds to step 1277, and in the case of No at step 1275, the process proceeds to step 1292.

<Processing in the first ROM / RAM area>
Next, FIG. 13 is a flowchart of non-returnable error processing according to the subroutine of step 1300 (and called in the other flowcharts) in FIG. First, in step 1302, the CPUC 100 prohibits an interrupt based on the data in the first ROM and RAM area (hereinafter, the flowchart related to the timer interrupt process described later is not executed). Next, in step 1304, the CPUC 100 sets the output port address and the number of output ports based on the data in the first ROM / RAM area. Next, in step 1306, the CPUC 100 turns off the output port (0 to 6 in this example, and the display output to the various LEDs and the drive output to the various motors) based on the data in the first ROM and RAM area. Make it Next, in step 1308, the CPUC 100 sets the next port output address based on the data in the first ROM and RAM area (this repetition causes display output to various LEDs and drive output to various motors to be sequentially stopped) Will be Next, in step 1310, the CPUC 100 determines, based on the data in the first ROM and RAM area, whether or not the output to each output port has ended. In the case of Yes in step 1310, the CPUC 100 executes the set error display based on the data in the first ROM and RAM area in step 1312 (when an error occurs, some error occurs). And the execution of the process is repeated, and when the power supply voltage is lowered, the reset signal is input and the process ends. (In other words, since it enters an infinite loop, it does not accept any operation prompting return). In the case of No at step 1310, the process proceeds to step 1306. The processing in step 1306 to step 1310 is processing to clear the output to the LED and motor (However, since the external output signal is not cleared, the information on the error, the game progress status at the time of error occurrence, etc. It is possible to output to

<Processing in Second ROM and RAM Area>
Next, FIG. 14 is a flowchart of a medal insertion error detection process according to the subroutine of step 1400 in FIG. First, in step 1402, the CPUC 100 sets an inserted medal backflow error flag (a flag which is turned on in step 1706, and in this embodiment, a flag in the second RAM area) based on data in the second ROM / RAM area. It is determined whether or not it is on. In the case of Yes in step 1402, in step 1404, the CPUC 100 based on the data in the second ROM and RAM area, is an inserted medal backflow error (an error due to the inserted game medal being backflowed, for example, the first inserted sensor D20s OFF and second loading sensor D30s ON → 1st loading sensor D20s ON and second loading sensor D30s ON becomes an error). Next, based on the data in the second ROM and RAM area, the CPUC 100 determines whether or not the inserted medal error backflow error has been released (for example, whether the setting / reset button M30 has been pressed). If Yes in step 1406, in step 1408, the CPUC 100 turns off the inserted medal backflow error flag based on the data in the second ROM and RAM area, and shifts to the next process (the process of step 1229).

  On the other hand, in the case of No at step 1402, the CPUC 100 at step 1410 is an inserted medal retention error flag (a flag turned on at step 1710) based on data in the second ROM and RAM area 2) It is determined whether the flag in the RAM area is on. In the case of Yes in step 1410, the CPUC 100 in step 1412, based on the data in the second ROM and RAM area, is an insertion medal retention error (this is an error due to the inserted game medals being retained, for example, the first insertion sensor If a state in which D20s is on and the second on sensor D30s is on continues for a predetermined time, an error occurs. Next, in step 1414, the CPUC 100 determines whether or not the inserted medal retention error has been canceled (for example, whether or not the setting / reset button M30 has been pressed) based on the data in the second ROM and RAM area. If Yes in step 1414, the CPUC 100 turns off the inserted medal retention error flag based on the data in the second ROM and RAM area in step 1416, and shifts to the next processing (processing in step 1229).

  On the other hand, if No in step 1410, the CPUC 100 in step 1418 is an insertion number error flag (a flag turned on in step 1716 based on the data in the second ROM and RAM area, and in the present embodiment, the second RAM). It is determined whether the flag in the area is on. In the case of Yes in step 1418, the CPUC 100 causes an error in the number of inserted cards based on the data in the second ROM and RAM area in step 1420 (due to the fact that the number of inserted game medals does not match the number of game medals passed normally. It is an error, for example, an error occurs when the number of gaming medals detected by the insertion acceptance sensor D10s does not match the number of gaming medals detected by the second insertion sensor D30s or when the number falls outside a predetermined allowable range) Execute the display. Next, in step 1422, the CPUC 100 determines whether the insertion number error has been canceled (for example, whether the setting / reset button M30 has been pressed) based on the data in the second ROM and RAM area. If Yes in step 1422, the CPUC 100 turns off the insertion number error flag based on the data in the second ROM and RAM area in step 1424, and shifts to the next processing (processing in step 1229).

<Processing in Second ROM and RAM Area>
Next, FIG. 15 is a flowchart of the medal payout error detection process according to the subroutine of step 1450 in FIGS. 11 and 12. First, in step 1452, the CPUC 100 determines that the payout medal staying error flag (a flag that is turned on in step 1756, and in the present embodiment, the flag in the second RAM area) based on the data in the second ROM and RAM area. It is determined whether or not it is on. In the case of Yes in step 1452, the CPUC 100 in step 1456 based on the data in the second ROM and RAM area, is an error due to the payout medal staying error (an error due to the game medals paid out being stagnated, for example, the first payout An error occurs when the state in which the sensor H10s is on and the second dispensing sensor H20s is on continues for a predetermined time). Next, in step 1458, the CPUC 100 determines whether or not the payout medal retention error has been canceled (for example, whether the setting / reset button M30 has been pressed or not) based on the data in the second ROM and RAM area. If Yes in step 1458, in step 1460, the CPUC 100 turns off the payout medal retention error flag based on the data in the second ROM and RAM area, and shifts to the next processing (processing in step 1240 or step 1284).

<Processing in Second ROM and RAM Area>
Next, FIG. 16 is a flowchart of insertion / withdrawal error detection processing according to the subroutine of step 1500 in FIG. 11 and FIG. First, in step 1502, the CPUC 100 turns on an abnormal input error flag (a flag that is turned on in step 1806, and in the present embodiment, a flag in the second RAM area) based on data in the second ROM and RAM area. It is determined whether the In the case of Yes in step 1502, in step 1504, the CPUC 100 abnormally enters an error based on the data in the second ROM and RAM area (error due to detection of insertion of game medal at timing when game medal should not be inserted). Execute the display. Next, in step 1506, the CPUC 100 determines, based on the data in the second ROM and RAM area, whether or not the abnormal insertion error has been released (for example, whether or not the setting / reset button M30 has been pressed). If Yes in step 1506, the CPUC 100 turns off the abnormal input error flag based on the data in the second ROM and RAM area in step 1508, and proceeds to step 1510. Also in the case of No in step 1502, the process proceeds to step 1510.

  Next, in step 1510, the CPUC 100 sets an abnormal payout error flag (a flag turned on in step 1816, and in this embodiment, a flag in the second RAM area) based on the data in the second ROM and RAM area. It is determined whether or not it is on. In the case of Yes in step 1510, the CPUC 100 generates an abnormal payout error based on the data in the second ROM and RAM area in step 1514 (error due to detection of payout of gaming medal at timing when gaming medals should not be paid out) ) Execute the display. Next, in step 1516, the CPUC 100 determines whether or not the abnormal payout error has been canceled (for example, whether or not the setting / reset button M30 has been pressed) based on the data in the second ROM and RAM area. If YES in step 1516, the CPUC 100 turns off the abnormal payout error flag based on the data in the second ROM and RAM area in step 1518, and shifts to the next processing (processing in step 1250 or step 1270). Also in the case of No at step 1510, the process proceeds to the next process (the process of step 1250 or step 1270).

  Next, FIG. 17 is a flowchart of timer interrupt processing according to the subroutine of step 1600 in the present embodiment. The process of the subroutine is started when a timer interrupt is started in the process of step 1054 or step 1118, and thereafter, a predetermined time (in this example, T is set, for example, a time of about 2 ms) Is set to be performed periodically on a periodic basis.

<Processing in the first ROM / RAM area>
First, in step 1602, the CPUC 100 performs processing at the start of an interrupt (for example, save of data held in a register in the CPUC 100, input port check of the power-off detection signal, etc.) based on the data in the first ROM and RAM area. To do). Next, in step 1604, the CPUC 100 determines whether or not the power failure has been detected (in the current interrupt processing) based on the data in the first ROM and RAM area. If No in step 1604, in step 1900, the CPUC 100 executes power-off processing described later based on data in the first ROM and RAM area. On the other hand, if Yes in step 1604, the CPUC 100 starts timer measurement (update processing of various timers managed by software) based on the data in the first ROM and RAM area in step 1606. Next, in step 1608, the CPUC 100 generates input port data based on the data in the first ROM and RAM area and stores the data (updates the storage area of each input port data in the first RAM area) ). Here, the input port data includes the settlement button D60, start lever D50, stop button D40, front door switch D80, setting door switch M10, setting key switch M20, setting / reset button M30, power-off detection signal, closing acceptance sensor Information related to the detection of D10s, first insertion sensor D20s, second insertion sensor D30s, first dispensing sensor H10s, second dispensing sensor H20s, etc. , Sampled at interrupt interval T).

  Next, in step 1610, the CPUC 100 refers to the input port data in the first RAM area based on the data in the first ROM and RAM area, and sets the front door switch flag, according to the sampling result of each input port data. Turn on / off the door switch flag and the setting key switch flag (for example, when the switch state of the front door switch D80 is continuously on over a plurality of samplings, turn on the front door switch flag Therefore, it is possible to detect that the front door DU is open without being affected by noise). Next, at step 1612, the CPUC 100 controls the drive control for the drive of reels M50 (left reel M51, middle reel M52, right reel M53) based on the data in the first ROM and RAM area. Execute the relevant processing). Next, in step 1614, the CPUC 100 outputs output data to the output port based on the data in the first ROM / RAM area. Here, the output data is data for driving the reel M50, the blocker D100, and the like. At step 1616, the CPUC 100 calls an error check process of the second ROM area based on the data in the first ROM and RAM area, and shifts to step 1700.

<Processing in Second ROM and RAM Area>
Next, in step 1700, the CPUC 100 executes medal insertion check processing described later based on the data in the second ROM and RAM area. Next, in step 1750, the CPUC 100 executes a medal payout check, which will be described later, based on the data in the second ROM and RAM area. Next, in step 1800, the CPUC 100 executes an insertion / withdrawal error check process described later based on the data in the second ROM / RAM area. Next, in step 1618, the CPUC 100 turns off all error flags based on the data in the second ROM and RAM area (inserted medal backflow flag, inserted number error flag, medal staying error flag, inserted abnormality error flag, payout abnormality) It is determined whether or not all flags related to errors such as an error flag, a payout medal retention error flag, a door switch flag, etc. are off) (however, in the present embodiment, the door switch flag in the first RAM area) Because it is stored, it is determined with reference to the first RAM area). In the case of Yes in step 1618, the CPUC 100, in step 1620, based on the data in the second ROM and RAM area, generates an error not detected command (a command to the sub side and a command related to the fact that an error is not detected). Set (for example, set in the register area), and proceed to step 1624. On the other hand, if No in step 1618, the CPUC 100 detects an error based on the data in the second ROM and RAM area in step 1622 (this is a command to the sub side and a command related to the fact that an error is detected) Are set (for example, set in the register area), and the process proceeds to step 1624. In step 1622, information related to an error (currently occurring error) corresponding to the error flag that is turned on is transmitted to the sub side. In addition, the error non-detection command may be set only when the error is canceled after the error has occurred (only when it is determined that the flag is turned off), and when the error is not detected, the command may be set. It is not necessary to execute the information set process (S1620 may be omitted). Furthermore, the error detection command may execute the set process only when an error occurs from a state in which no error occurs, or from a state in which a first error (for example, an insertion medal retention error) has occurred. The set process may be executed when the type of error changes, such as a second error (e.g., a payout medal retention error). Next, in step 1624, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1626.

<Processing in the first ROM / RAM area>
Next, in step 1626, CPUC 100 transmits a control command (sub-side command) based on the data in the first ROM and RAM area (for example, when set in the register area in step 1620 and step 1622) Will take over the set control command). Next, in step 1628, the CPUC 100 outputs an external signal (a signal for transmitting information from the reel-type game machine P to an external hall computer or the like) based on the data in the first ROM / RAM area. In addition, as information related to an error output as the external signal, a door opening error, a closing error, a dispensing error, a setting door opening error (not shown), a closing acceptance sensor retention error (not shown), etc. It is output. The door open error is configured to be an error when the front door DU is opened and the door switch flag is turned on. The setting door open error is caused when the setting door is opened and the setting door switch flag is turned on. The insertion acceptance sensor retention error is configured to be an error when the insertion acceptance sensor detects retention of a game medal. Next, in step 1630, the CPUC 100, based on the data in the first ROM and RAM area, outputs predetermined data of LED (7-segment LED lamp etc.) output data (for example, a plurality of 7-segment LED units). The unit is turned on, and a predetermined segment of 7 segments is turned on (so-called dynamic lighting). Next, in step 1632, the CPUC 100 executes the lighting mode of the LED (for example, changing the lighting color of the LED) based on the data in the first ROM and RAM area. Note that step 1632 may not be performed. Next, in step 1634, the CPUC 100 executes soft random number management processing (such as update processing of random number values managed by software) based on the data in the first ROM and RAM area. Next, in step 1636, the CPUC 100 calls the random number check process of the second ROM area based on the data in the first ROM and RAM area, and shifts to step 1638.

<Processing in Second ROM and RAM Area>
Next, in step 1638, the CPUC 100 acquires internal information register data based on the data in the second ROM and RAM area (in the internal information register, an abnormality flag bit is set when abnormality occurs in the random number generation circuit). Exists). Next, in step 1640, the CPUC 100 determines whether the frequency of the random number update clock is normal or not based on the data in the second ROM and RAM area (a bit for abnormality flag indicating the frequency abnormality is not set or not). To determine Specifically, the abnormality flag bit is set when the frequency of the random number update clock falls below a predetermined value. If Yes in step 1640, in step 1642 the CPUC 100 determines whether the update status of the internal random number is normal or not based on the data in the second ROM / RAM area (an error flag bit indicating the update status is set) To determine if the If Yes in step 1642, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area in step 1644. On the other hand, if No in step 1640 or step 1642, CPUC 100 sets an internal random number error display based on the data in the second ROM and RAM area in step 1646 (for example, sets an error number in the register area) To do). Next, in step 1300, the CPUC 100 executes the above-described non-returnable error processing based on the data in the second ROM and RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1648, the CPUC 100 executes interrupt termination processing based on the data in the first ROM and RAM area, and shifts to the next processing (processing in step 1602).

<Processing in Second ROM and RAM Area>
Next, FIG. 18 is a flowchart of the medal insertion check process according to the subroutine of step 1700 in FIG. First, in step 1702, the CPUC 100 determines whether the first insertion sensor D 20 s is on (detected or not) based on the data in the second ROM and RAM area (however, the first insertion sensor When the input port data D20s itself is stored in the first RAM area, the determination is made with reference to the first RAM area). In the case of Yes in step 1702, in step 1704, the first insertion sensor D20s and the second insertion sensor D30s detect the backflow of the inserted game medal based on the data in the second ROM and RAM area. (For example, it is detected when the first loading sensor D20s is turned off and the second loading sensor D30s is turned on and then the first loading sensor D20s is turned on and the second loading sensor D30s is turned on. It is determined whether the series data itself is held in the second RAM area). If Yes in step 1704, the CPUC 100 turns on the inserted medal backflow error flag based on the data in the second ROM and RAM area in step 1706 (for example, turns on the inside of the inserted medal backflow error flag area of the second RAM area). Update with the corresponding value), and the process proceeds to step 1708. On the other hand, also in the case of No at step 1704, the process moves to step 1708.

  Next, in step 1708, the CPUC 100 detects that the first insertion sensor D20s and the second insertion sensor D30s have stagnated medals inserted based on the data in the second ROM and RAM area (for example, the first This is to detect when the state where the input sensor D20s is on continues for a predetermined time or when the state where the second input sensor D30s is on continues for a predetermined time, the data itself of the detection state is held in the second RAM area To determine whether or not the If Yes in step 1708, the CPUC 100 turns on the insertion medal retention error flag based on the data in the second ROM and RAM area in step 1710 (for example, turns on the inside of the insertion medal retention error flag area of the second RAM area). Update with the corresponding value), and the process proceeds to step 1712. On the other hand, also in the case of No at step 1708, the process proceeds to step 1712. Next, in step 1712, the CPUC 100 determines, based on the data in the second ROM and RAM area, the number of game medals that are considered to be normally passed (number of normal passing cards) from the number of received medals (the number of game medals received). It is determined whether the value obtained by subtracting the number of sheets is not within a predetermined range (for example, 0 to 2). If Yes in step 1712, the CPUC 100 turns on the insertion number error flag based on the data in the second ROM and RAM area in step 1716 (for example, the inside of the insertion number error flag area of the second RAM area corresponds to on). Update with the value) and move on to the next processing (processing of step 1750). Also in the case of No in step 1712, the process proceeds to the next process (the process of step 1750). It should be noted that an insertion number error monitoring period is provided for a predetermined time (for example, 5 seconds), and during the monitoring period, a value obtained by subtracting the normal passing number from the reception medal number is within a predetermined range (for example, 0 to 2). It may be configured that an insertion number error occurs when there is no more.

<Processing in Second ROM and RAM Area>
Next, FIG. 19 is a flowchart of the medal payout check process according to the subroutine of step 1750 in FIG. First, in step 1752, the CPUC 100 determines whether the hopper drive flag is ON (detected or not) based on the data in the second ROM and RAM area (however, the hopper drive flag itself is When stored in the first RAM area, determination is made with reference to the first RAM area). In the case of Yes in step 1752, CPUC 100 detects retention of paid-out medals based on data in the second ROM and RAM area in step 1754 (for example, the state where the first payout sensor H 10 s is on continues for a predetermined time) In this case, the second payout sensor H 20 s is detected when the state where it is on continues for a predetermined time, and it is determined whether the data of the detection state is held in the second RAM area). judge. If Yes in step 1754, the CPUC 100 turns on the payout medal retention error flag based on the data in the second ROM and RAM area in step 1756 (for example, turns on the inside of the payout medal retention error flag area of the second RAM area Update with the corresponding value), and shift to the next processing (processing of step 1800). Also in the case of No in step 1752 or step 1754, the process proceeds to the next process (the process of step 1800).

<Processing in Second ROM and RAM Area>
Next, FIG. 20 is a flowchart of the insertion / withdrawal error check process according to the subroutine of step 1800 in FIG. First, in step 1802, the CPUC 100 determines whether or not the blocker D100 is off based on the data in the second ROM and RAM area (however, the output port data of the blocker D100 itself is stored in the first RAM area). If it is determined, the determination is made with reference to the first RAM area). In the case of Yes in step 1802, in step 1804, the CPUC 100 detects abnormality of the insertion sensor based on the data in the second ROM and RAM area (the first insertion sensor D20s or the second insertion sensor D30s should not detect the gaming medals) It is determined whether or not there is detection at the timing of If Yes in step 1804, the CPUC 100 turns on the abnormal entry error flag based on the data in the second ROM and RAM area in step 1806 (for example, it corresponds to turning on the abnormal entry error flag area of the second RAM area). Update with the value) and go to step 1808. Also in the case of No in step 1802 or step 1804, the processing shifts to step 1808.

  Next, in step 1808, the CPUC 100 determines whether or not the hopper drive flag is off based on the data in the second ROM and RAM area (however, the hopper drive flag itself is stored in the first RAM area). If it is determined, the determination is made with reference to the first RAM area). If Yes in step 1808, in step 1810, the CPUC 100 detects that the payout sensor is abnormal based on the data in the second ROM and RAM area (the first payout sensor H10s or the second payout sensor H20s should not detect the gaming medals) It is determined whether or not there is detection at the timing of If Yes in step 1810, the CPUC 100 turns on the abnormal payout error flag based on the data in the second ROM and RAM area in step 1812 (for example, it corresponds to turning on the abnormal payout error flag area of the second RAM area). Update with the value) and move on to the next process (the process of step 1618). Also in the case of No in step 1808 or step 181, the processing shifts to the next processing (processing in step 1618).

<Processing in the first ROM / RAM area>
Next, FIG. 21 is a flowchart of the power-off process according to the subroutine of step 1900 in FIG. First, at step 1902, the CPUC 100 saves the stack pointer based on the data in the first ROM / RAM area. Next, in step 1904, the CPUC 100 turns on the power-off processed flag based on the data in the first ROM and RAM area (for example, a value corresponding to turning on the power-off processed flag area of the first RAM area). To update Next, in step 1906, the CPUC 100 calls checksum calculation processing for the second ROM area based on the data in the first ROM / RAM area, and shifts to step 1908.

<Processing in Second ROM and RAM Area>
Next, in step 1908, the CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the checksum area based on the data in the second ROM and RAM area, and detects an error based on the calculated checksum. Information (for example, the lower 1 byte in the calculated checksum or the complement thereof) is set in the checksum area (the address related to the checksum area is the See). Next, in step 1910, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM and RAM area, and shifts to step 1912.

<Processing in the first ROM / RAM area>
Next, in step 1912, the CPUC 100 prohibits writing of the first RAM and the second RAM based on the data in the first ROM and RAM area, and shifts to step 1914. Next, in step 1914, the CPUC 100 executes infinite loop processing for waiting for reset based on the data in the first ROM and RAM area.

  By configuring as described above, according to the reel type gaming machine according to the present embodiment, the first RAM area (or the register area) is processed by the processing of the CPUC 100 based on the program code arranged in the second ROM area. ) Can be updated and referred to, and an error is detected, an error is indicated, etc. is made to the gaming machine (for example, an unauthorized By using a program in the second ROM / RAM area so as to execute the program for preventing cheating or the like), thereby clearly separating the process and the area related to the progress of the game This makes it easy to verify the legitimacy of the program for preventing fraud.

Second Embodiment
In the present embodiment, an error display process or the like is also regarded as a program for preventing fraudulent activity, and an example for implementing it as a program code arranged in the second ROM area is shown. Is an essential process to control the game progression, so it may be easier to artificially verify if it is regarded as a program for implementing gameplay specifications rather than a program for preventing cheating. There is. Therefore, in view of such circumstances, processing based on the example shown in the present embodiment, which can be suitably regarded as a program for implementing a game characteristic specification, is disposed in the first ROM area An example for implementation as a program code will be described as a second embodiment, and changes from this embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 22 shows the flow of processing executed by the CPUC 100 of the main control board M for the first time after turning on the power of the drum-type gaming machine P according to the second embodiment (or at system reset and user reset) Is a flowchart (first sheet) showing The difference from the present embodiment is the step 1005-1 (second), the step 1005-2 (second), the step 1009-1 (second), the step 1009-2 (second), the step 1017 (second). Step 1019-1 (second) to step 1019-3 (second), step 1021-1 (second), step 1021-2 (second), step 1027 (second), step 1029 (second). , Step 1035-1 (second) and step 1035-2 (second), that is, after performing the function setting of the chip in step 1004, CPUC 100 performs step 1005-1 (second), Based on the data in the first ROM and RAM area, the checksum from the start address of the first RAM area to the address just before the first checksum area is calculated. Here, as shown in the right side of the figure (memory map for RAM), in the second embodiment, the checksum area (first checksum area) of the first RAM area and the checksum area (second RAM area) of the second RAM area (2) Checksum area calculation is performed separately in the power off process in the second embodiment described later, the checksum calculation of the first RAM area and the checksum calculation of the second RAM area are separately performed, respectively. The error detection information based on the calculation result of is stored in each area. Next, in step 1005-2, the CPUC 100 checks the first RAM based on the data in the first ROM and RAM area, generates first RAM power failure recovery data (power failure recovery data related to the first RAM), and step Transition to 1006. Therefore, “check the first RAM” here is based on the check sum for the first RAM area and the error detection information held in the first check sum area, by power failure / power failure recovery. It is a process of checking whether the data stored in the built-in RAM C 120 is correctly held.

<Processing in Second ROM and RAM Area>
On the other hand, after calling the power failure recovery process in step 1006, the CPUC 100 performs the second checksum from the start address of the second RAM area based on the data in the second ROM / RAM area in step 1009-1 (second). Calculate the checksum up to the final address excluding the area. Next, in step 1009-2 (second), the CPUC 100 checks the second RAM based on the data in the second ROM and RAM area, and restores the second RAM power failure recovery data (power failure recovery data related to the first RAM). Generate and move to step 1012. That is, “check the second RAM” here is based on the check sum for the second RAM area and the error detection information held in the second check sum area, by power failure / power failure recovery. It is a process of checking whether the data stored in the built-in RAM C 120 is correctly held.

<Processing in the first ROM / RAM area>
If all the switches are on in step 1016, the CPUC 100 turns on the setting change operation flag based on the data in the first ROM and RAM area in step 1017 (second) (for example, the first RAM) Region setting change operation present flag region is updated with a value corresponding to ON), and the process moves to step 1018.

<Processing in Second ROM and RAM Area>
Further, after calling up initialization processing at non-setting change at step 1018, at step 1019-1 (second), the CPUC 100 sets a setting operation flag in the first RAM area based on data in the second ROM and RAM area. Is determined whether or not it is off. If Yes in step 1019-1 (second), the CPUC 100 determines that the power failure recovery data in the first RAM area is normal based on the data in the second ROM / RAM area in step 1019-2 (second). (In particular, it is determined whether the error detection result for the first RAM area is normal or not). If Yes in step 1019-2 (second), the CPUC 100 determines that the power failure recovery data in the second RAM area is normal based on the data in the second ROM / RAM area in step 1019-3 (second). (In particular, it is determined whether the error detection result for the second RAM area is normal or not). If Yes in step 1019-3 (second), in step 1028, the initialization ranges of the first RAM area and the second RAM area are determined and set as the unused RAM range, and in step 1027 (second), the second RAM The power failure abnormality flag in the area is turned off, and the process proceeds to step 1036. On the other hand, in the case of No at step 1019-2 (second) or step 1019-3 (second), at step 1029 (second), the CPUC 100 generates a second RAM area based on the data in the second ROM and RAM area. The power failure abnormality flag is turned on, and the process proceeds to step 1036.

  On the other hand, if No in step 1019-1 (second), the CPUC 100 determines that the power failure recovery data in the first RAM area is normal based on the data in the second ROM / RAM area in step 1021-1 (second). (In particular, whether or not the error detection result for the first RAM area is normal). If Yes in step 1021-1 (second), the CPUC 100 determines that the power failure recovery data in the second RAM area is normal based on the data in the second ROM / RAM area in step 1021-2 (second). (In particular, it is determined whether the error detection result for the second RAM area is normal or not). If Yes in step 1021-2 (second), in step 1032, the CPUC 100 sets the initialization ranges of the first RAM area and the second RAM area to the set values in the first RAM area based on the data in the second ROM and RAM area. In step 1035-1 (second), the CPUC 100 turns off the power failure abnormality flag in the second RAM area based on the data in the second ROM and RAM area, and step Migrate to 1036. On the other hand, if No in step 1021-1 (second) or step 1021-2 (second), in step 1034, CPUC 100 determines the first and second RAM areas based on the data in the second ROM and RAM area. The initialization range is determined and set to all ranges, and in step 1035-2 (second), the CPUC 100 turns on the power failure abnormality flag in the second RAM area based on the data in the second ROM and RAM area. , And move to step 1036.

<Processing in the first ROM / RAM area>
Next, FIG. 23 shows a process that is executed by the CPUC 100 of the main control board M for the first time after turning on the power of the reel type gaming machine P according to the second embodiment (or at system reset and user reset). It is a flowchart (the 2nd sheet) which showed a flow. The difference from the present embodiment is the step 1039-1 (second), the step 1039-2 (second), the step 1026 (second), the step 1300 (second), the step 1045 (second), the step 1046 In the second and step 1047 (second), that is, in step 1039-1 (second), the CPUC 100 sets the flag with the setting operation in the first RAM area based on the data in the first ROM and RAM area. It is determined whether or not it is off. If Yes in step 1039-1 (second), the CPUC 100 determines that the power-off abnormality flag in the second RAM area is off based on the data in the first ROM / RAM area in step 1039-2 (second). It is determined whether or not. If Yes in step 1039-2 (second) or No in step 1039-1 (second), the process proceeds to step 1040 (that is, the setting change device is operated or the setting change device is operated). In the case where the power failure recovery is performed normally including the fact that the separate error detection result targeting the first RAM area and the second RAM area is normal when not being performed, the subsequent processing is continued), step 1039-2 In the case of (second) No, in step 1026 (second), the CPUC 100 sets a backup error display based on the data in the first ROM and RAM area (for example, sets an error number in the register area) . Next, in step 1300 (second), the CPUC 100 sets a return impossible error process, which will be described later, based on the data in the first ROM and RAM area (that is, the first RAM area when the setting change device is not operated). And when the power failure recovery is not normally performed, including the fact that the separate error detection result for the second RAM area is abnormal, the state is shifted to the impossible recovery state). Here, in the present embodiment, when the setting change apparatus is not operated, the subsequent processing is continued when the separate error detection results for the first RAM area and the second RAM area are normal. However, the present invention is not limited to this. For example, if the error detection result for the first RAM area is normal, even if the error detection result for the second RAM area is abnormal (the entire second RAM area It may be configured to continue the process after initializing the area).

<Processing in Second ROM and RAM Area>
If it is determined in step 1044 that the setting value in the first RAM area is within the normal range, the CPUC 100 performs setting in the second RAM area based on the data in the second ROM and RAM area in step 1045 (second). The value abnormality flag is turned off, and the process returns to the caller of the first ROM area, and the process proceeds to step 1047 (second). On the other hand, if No in step 1044, the CPUC 100 turns on the setting value abnormality flag in the second RAM area based on the data in the second ROM and RAM area in step 1046 (second), and the call source of the first ROM area. And return to step 1047 (second).

<Processing in the first ROM / RAM area>
Next, in step 1047 (second), the CPUC 100 determines whether the set value abnormality flag in the second RAM area is off based on the data in the first ROM and RAM area. If Yes in step 1047 (the second), the process proceeds to step 1050; if No, the CPUC 100 performs the setting value error based on the data in the first ROM and RAM area in step 1048 (the second). Set the display (eg, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets a return impossible error process, which will be described later, based on the data in the first ROM and RAM area. As described above, in the second embodiment, the return impossible error processing and the set processing of the return impossible error display (backup error display, setting value error display) that has occurred are executed in the first ROM and RAM area. It is configured as follows.

<Processing in the first ROM / RAM area>
Next, FIG. 24 is a flowchart of the game progression control process (second sheet) according to the subroutine of step 1200 in the second embodiment. The difference from this embodiment is the step 1228 (second), the step 1700 (second), the step 1400 (second), the step 1237 (second), the step 1750 (second), the step 1450 (second). , Step 1249-1 (second), step 1800 (second), step 1500 (second), step 1254-1 (second) to step 1254-3 (second), step 1256 (second) and step If the first insertion sensor D20s and the second insertion sensor D30s are not turned off in step 1230, or if the first insertion sensor D20s and the second insertion sensor D30s are not turned off, step 1228 (second In 2), the CPUC 100 calls the medal insertion check process of the second ROM area based on the data in the first ROM and RAM area. And, the process proceeds to step 1700 (second).

<Processing in Second ROM and RAM Area>
Next, in step 1700 (second), the CPUC 100 executes the medal insertion check processing based on the data in the second ROM and RAM area, and shifts to step 1229. In the present embodiment, the medal insertion check implemented separately for the game progress control process (loop process) and the timer interrupt process (non-loop process) is implemented as the purpose of the medal input check process of the second ROM area. It is to show an example of a method of collectively implementing related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area at step 1229, the CPUC 100 executes medal insertion error detection processing described later based on the data in the first ROM and RAM area at step 1400 (second). Transfer to step 1230. In the second embodiment, the medal insertion error detection process is configured to be executed in the first ROM and RAM area.

  Also, if the first dispensing sensor H10s or the second dispensing sensor H20s is on in step 1236, or if the predetermined time after hopper driving has not elapsed in step 1241, or if the first dispensing sensor H10s and the first in step 1247 2) If the payout sensor H 20 s is not turned off, the CPUC 100 calls the medal payout check process of the second ROM area based on the data in the first ROM and RAM area in step 1237 (second), step 1750 (second Move to).

<Processing in Second ROM and RAM Area>
Next, in step 1750 (second), the CPUC 100 executes the medal payout check process based on the data in the second ROM and RAM area, and shifts to step 1240. In this embodiment, the medal payout check process implemented in the present embodiment is divided into a game progress control process (loop process) and a timer interrupt process (non-loop process) in the second ROM area. It is to show an example of a method of collectively implementing related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
Also, after returning to the caller of the first ROM area at step 1240, at step 1450 (second), the CPUC 100 executes medal payout error detection processing described later based on the data in the first ROM and RAM area, Transfer to step 1247. In the second embodiment, the medal payout error detection process is configured to be executed in the first ROM and RAM area.

  If there is no operation of the settlement button D60 at step 1232 or if there are no remaining credits and bet medals at step 1233, then at step 1249-1 (second), the CPUC 100 is in the first ROM RAM area In the second ROM area, the processing for checking the insertion / withdrawal error of the second ROM area is called based on the data of (4), and the process proceeds to step 1800 (second).

<Processing in Second ROM and RAM Area>
Next, in step 1800 (second), the CPUC 100 executes an insertion / withdrawal error check process based on the data in the second ROM / RAM area, and shifts to step 1250. Note that, in the present embodiment, in the present embodiment, the second ROM area insertion / withdrawal error check processing is implemented separately for the game progress control processing (loop processing) and the timer interrupt processing (non-loop processing). The present invention is to show an example of a method of collectively implementing a payout error check-related process in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
Also, after returning to the caller of the first ROM area at step 1250, at step 1500 (second), the CPUC 100 executes an insertion / withdrawal error detection process described later based on the data in the first ROM / RAM area. , And move on to step 1251. In the second embodiment, the insertion / withdrawal error detection process is configured to be executed in the first ROM / RAM area.

<Processing in Second ROM and RAM Area>
If it is determined in step 1253 that the setting value in the first RAM area is within the normal range, the CPUC 100 determines in the second RAM area based on the data in the second ROM and RAM area in step 1254-2 (second). The set value abnormality flag is turned off, and the process returns to the caller of the first ROM area, and the process proceeds to step 1254-3 (second). On the other hand, if the set value in the first RAM area is not within the normal range in step 1253, the CPUC 100 determines in the second RAM area based on the data in the second ROM and RAM area in step 1254-1 (second). The set value abnormality flag is turned on to return to the caller of the first ROM area, and the process proceeds to step 1254-3 (second).

<Processing in the first ROM / RAM area>
Next, in step 1254-3 (second), the CPUC 100 determines whether the set value abnormality flag in the second RAM area is off based on the data in the second ROM and RAM area. In the case of Yes in step 1254-3 (the second), the process proceeds to the next process (the process of step 1257), and in the case of No, the CPUC 100 performs the process in the first ROM and RAM area in the step 1256 (the second). The set value error indication is set based on the data (for example, the error number is set in the register area). Next, in step 1300 (second), the CPUC 100 sets a return impossible error process, which will be described later, based on the data in the first ROM and RAM area. As described above, in the second embodiment, the non-returnable error processing and the set processing of the non-returnable error display (setting value error display) occurring are executed in the first ROM and RAM area. There is.

<Processing in the first ROM / RAM area>
Next, FIG. 25 is a flowchart of medal insertion error detection processing according to the subroutine of step 1400 (second) of FIG. 24 in the second embodiment. The difference from the present embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when the error display process related to the medal insertion error is executed, the process implemented in the second ROM area is called up, but in the second embodiment, the process is the first ROM. When an error is detected in various error detection processing in the second ROM and RAM area, information is transferred to the processing implemented in the first ROM area and executed. It is doing. When configured in this manner, error display processing, which is an essential processing even in controlling game progression, can be implemented as a program for implementing game specification (program for controlling game progression). In other words, it is possible to divert the conventionally implemented error display processing program. The inserted medal backflow error flag, the inserted medal retention error flag, and the inserted number error, which are flags in the second RAM area for transferring information indicating that an error has been detected to the error display processing implemented in the first ROM area. The flag may be directly turned off from the error display processing implemented in the first ROM area as in this example when the error is canceled, or the processing of the second ROM area, for turning off the flag. The process may be configured to be called and turned off.

<Processing in the first ROM / RAM area>
Next, FIG. 26 is a flowchart of medal payout error detection processing according to the subroutine of step 1450 (second) of FIG. 24 in the second embodiment. The difference from the present embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when the error display process related to the medal payout error is executed, the process implemented in the second ROM area is called, but in the second embodiment, the process is the first ROM. When an error is detected in various error detection processing in the second ROM and RAM area, information is transferred to the processing implemented in the first ROM area and executed. It is doing. When configured in this manner, error display processing, which is an essential processing even in controlling game progression, can be implemented as a program for implementing game specification (program for controlling game progression). In other words, it is possible to divert the conventionally implemented error display processing program. The payout medal retention error flag, which is a flag in the second RAM area for transferring information indicating that an error has been detected to the error display processing implemented in the first ROM area, is an error released. As in this example, the error display processing implemented in the first ROM area may be directly turned off, or the processing in the second ROM area may be configured to call the processing for turning off the flag and turn it off. It is also good.

<Processing in the first ROM / RAM area>
Next, FIG. 27 is a flowchart of insertion / withdrawal error detection processing according to the subroutine of step 1500 (second) of FIG. 24 in the second embodiment. The difference from the present embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when the error display process related to the insertion / withdrawal error is executed, the process implemented in the second ROM area is called up, but in the second embodiment, the process is the second process. When an error is detected in various error detection processes in the second ROM and RAM area, the information indicating that the error is detected is handed over to the processing implemented in the first ROM area. It is running. When configured in this manner, error display processing, which is an essential processing even in controlling game progression, can be implemented as a program for implementing game specification (program for controlling game progression). In other words, it is possible to divert the conventionally implemented error display processing program. The error input error flag and the abnormal payout error flag, which are flags in the second RAM for transferring information indicating that an error has been detected to the error display processing implemented in the first ROM area, have been cleared of errors. In this case, the error display processing implemented in the first ROM area may be directly turned off as in this example, or the processing for the second ROM area may be called to turn off the processing for turning off the flag. It may be configured.

<Processing in Second ROM and RAM Area>
Next, FIG. 28 is a flowchart of the game progression control process (third sheet) in the second embodiment. The differences from this embodiment are the steps 1269-1 (second) to 1269-4 (second), step 1272 (second), step 1300 (second), step 1800 (second), step 1500. (Second), step 1277-1 (second), step 1750 (second) and step 1450 (second), that is, if the displayed symbol combination is normal at step 1269, then step 1269 -1 (second), the CPUC 100 turns off the display determination abnormality flag in the second RAM area based on the data in the second ROM and RAM area, and returns to the caller of the first ROM area, step 1269-3 ( Move to 2). On the other hand, if the combination of symbols displayed in step 1269 is not normal, in step 1269-2 (second), CPUC 100 displays the display determination abnormality flag in the second RAM area based on the data in the second ROM and RAM area. Is turned on to return to the caller of the first ROM area, and the process goes to step 1269-3 (second).

<Processing in the first ROM / RAM area>
Next, in step 1269-3 (second), the CPUC 100 determines whether the display determination abnormality flag in the second RAM area is off based on the data in the first ROM and RAM area. If Yes in step 1269-3 (second), in step 1269-4 (second), the CPUC 100 calls an insertion / delivery error check process of the second ROM area based on the data in the first ROM / RAM area, The process moves to step 1500 (second). On the other hand, if No in step 1269-3 (second), the CPUC 100 sets a display determination error display based on the data in the first ROM and RAM area in step 1272 (second) (for example, the register Set the error number in the area). Next, in step 1300 (second), the CPUC 100 sets the above-mentioned unrecoverable error processing based on the data in the first ROM and RAM area. As described above, in the second embodiment, the process of setting the non-returnable error process and the occurring non-returnable error display (display determination error display) is performed in the first ROM and RAM area. There is.

<Processing in Second ROM and RAM Area>
Next, in step 1800 (second), the CPUC 100 executes an insertion / withdrawal error check process based on the data in the second ROM / RAM area, and shifts to step 1270. Note that, in the present embodiment, in the present embodiment, the second ROM area insertion / withdrawal error check processing is implemented separately for the game progress control processing (loop processing) and the timer interrupt processing (non-loop processing). The present invention is to show an example of a method of collectively implementing a payout error check-related process in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
In addition, after returning to the caller of the first ROM area at step 1270, the CPUC 100 executes the above-mentioned insertion / withdrawal error detection processing based on the data in the first ROM / RAM area at step 1500 (second). Proceed to step 1274. In the second embodiment, the insertion / withdrawal error detection process is configured to be executed in the first ROM / RAM area.

  On the other hand, when the first dispensing sensor H10s or the second dispensing sensor H20s is on in step 1277, the CPUC 100 determines the second ROM area based on the data in the first ROM / RAM area in step 1277-1 (second). The medal payout check process is called, and the process proceeds to step 1750 (second).

<Processing in Second ROM and RAM Area>
Next, in step 1750 (second), the CPUC 100 executes the medal payout check process based on the data in the second ROM and RAM area, and proceeds to step 1284. In this embodiment, the medal payout check process implemented in the present embodiment is divided into a game progress control process (loop process) and a timer interrupt process (non-loop process) in the second ROM area. It is to show an example of a method of collectively implementing related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area at step 1284, the CPUC 100 executes medal payout error detection processing described later based on the data in the first ROM and RAM area at step 1450 (second). Transfer to step 1286. In the second embodiment, the medal payout error detection process is configured to be executed in the first ROM and RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 29 is a flowchart of non-returnable error processing according to the subroutine of step 1300 (second) of FIGS. 23, 24, 28 and 30 in the second embodiment. The difference from the present embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing the non-returnable error process, the process mounted in the second ROM area is called, but in the second embodiment, the process is mounted in the first ROM area. If an error is detected in various error detection processing in the second ROM and RAM area, information indicating that the error is detected is delivered to the processing implemented in the first ROM area and executed. It is When configured in this manner, a program for implementing a game characteristic specification (for example, processing with a force to shift to a non-returnable state (that is, to make the reel-type game machine P inoperable) It can be implemented as a program for controlling the game progression.

<Processing in Second ROM and RAM Area>
Next, FIG. 30 is a flowchart of timer interrupt processing according to the subroutine of step 1600 in the second embodiment. The difference from the present embodiment is the step 1648 (second), the step 1650 (second) and the step 1654 (second), that is, when the update state of the internal random number is normal in the step 1642, In step 1648 (second), the CPUC 100 turns off the built-in random number abnormal flag in the second RAM area based on the data in the second ROM and RAM area, and returns to the caller of the first ROM area, step 1654 (second Move to). On the other hand, if the frequency of the random number update clock is not normal at step 1640 or if the update status of the internal random number is not normal at step 1642, the CPUC 100 executes the second ROM at step 1650 (second). Based on the data in the RAM area, turn on the built-in random number abnormality flag in the second RAM area, return to the caller of the first ROM area, and shift to step 1654 (second).

<Processing in the first ROM / RAM area>
Next, in step 1654 (second), the CPUC 100 determines whether the built-in random number abnormality flag is off based on the data in the first ROM / RAM area. In the case of Yes in step 1654 (the second), the process proceeds to step 1636, and in the case of No, the CPUC 100 determines the built-in random number error based on the data in the first ROM and RAM area in the step 1648 (second). Set the display (eg, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets the above-mentioned unrecoverable error processing based on the data in the first ROM and RAM area. As described above, in the second embodiment, the non-returnable error processing and the set processing of the non-returnable error display (internal random number error display) occurring are executed in the first ROM and RAM area. There is.

<Processing in the first ROM / RAM area>
Next, FIG. 31 is a flowchart of the power-off process according to the subroutine of step 1900 of FIG. 30 in the second embodiment. The difference from the present embodiment is step 1905 (second) and step 1909 (second), that is, after the power-off processed flag is turned on in step 1904, step 1905 (second), The CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the first checksum area based on the data in the first ROM and RAM area, and error detection information (for example, based on the calculated checksum). The lower one byte in the calculated checksum or the complement thereof is set in the first checksum area. Next, in step 1906, the checksum calculation processing of the second ROM area is called, and the process shifts to step 1909 (second).

<Processing in Second ROM and RAM Area>
Next, in step 1909 (second), the CPUC 100 calculates the checksum from the start address of the second RAM area to the address just before the second checksum area based on the data in the second ROM and RAM area, and calculates the checksum The error detection information based on the checksum (for example, the lower 1 byte in the calculated checksum or the complement thereof) is set in the second checksum area, and the process proceeds to step 1910. As described above, in the second embodiment, the checksum area is divided into the first checksum area and the second checksum area, and as shown in the lower part of the figure, the first checksum area is the first RAM. At the final address of the area, the second checksum area is present at the final address of the second RAM area. Further, the checksum calculation and the set in the first RAM area are configured to execute processing in the first ROM area, and the checksum calculation and the set in the second RAM area are configured to execute processing in the second ROM area.

  By configuring as described above, according to the reel-type gaming machine according to the second embodiment, the second RAM area can be referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area. In the processing of the CPUC 100 based on the program code that is configured and arranged in the second ROM area, the first RAM area is configured to be referable, and an illegal action is performed on the gaming machine such as error detection (for example, , A program for preventing fraudulent activity to prevent unauthorized access to the slot and outlet of the gaming media, etc. to obtain gaming media by unauthorized means, etc. by processing in the second ROM and RAM area By configuring so as to be able to execute, it is possible to clearly separate the processing and the area relating to the progress of the game, and as in the present embodiment, it is possible to It is easy to verify the sex.

(Summary)
The following concepts can be extracted (listed) based on the configurations shown in the above embodiments. However, the concepts listed below are merely examples, and the concepts based on the additional configurations shown in the above embodiments are of course added to these concepts, as well as the combination and separation (superordinate conceptization) of these listed concepts. May be

  First, the problems to be solved by the above embodiments will be briefly described. The program capacity for controlling the operation control of the gaming machine is strictly regulated from the upper limit of its capacity from the viewpoint of prevention of mixture of illegal programs (guarantee of program legitimacy provided by the gaming machine manufacturer), and the game characteristic specification is implemented. In addition to the program for making an unauthorized act on the gaming machine (eg, illegally accessing the slot and outlet of the game medium to obtain the game medium by illegal means, etc.) There are also a number of anti-tamper programs implemented to protect. However, under the present circumstances, there are many cases where a program for implementing gameplay specifications and a program for preventing fraudulent actions are mixedly arranged on the ROM, and as a result, it is difficult to verify the legitimacy of these programs There is a problem that

The drum-type gaming machine according to this aspect (1-1),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value It is a gaming machine characterized by being divided into at least a second data area).

  According to the reeling type gaming machine according to the present aspect (1-1), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU Since the memory map is arranged separately (in a non-consecutive arrangement of addresses) on the memory map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

The drum-type gaming machine according to this aspect (1-2),
There is one or more address values larger than the second end point address value and smaller than the third start point address value, and the program and the data of the one or more address values It is a game machine of this mode (1-1) in which special information which is not associated with anything is arranged.

  According to the reel-type game machine according to this aspect (1-2), in addition to the effects described above, the program which is present in the first control area and accessed by the CPU and which is present and read in the first control area The first block is the first block, and the second program is a program that is in the second control area and is accessed by the CPU and the second block is the data that is in the second control area and is read. Since special information not accessed by the CPU is placed between the block and the second block, the special information serves as a delimitation on the program source code or dump list, and the arrangement positions of both blocks are placed. Can be clearly separated visually. As a result, for example, by arranging as a first block = a control block for implementing a game characteristic specification, and a second block = a control block for preventing tampering, both control blocks having different functional properties are provided. Since visual separation can be clearly performed on the program source code or on the dump list, it becomes easy to artificially verify the legitimacy of both control blocks.

The drum-type gaming machine according to this aspect (1-3),
The special information is the gaming machine of the aspect (1-2) in which all bits are zero.

  According to the reel-type game machine according to this aspect (1-3), in addition to the above-described effects, when arranging special information not accessed by the CPU between the first block and the second block, Since all bits of special information are zero, this special information preferably serves as a delimiter on the program source code or on the dump list, so as to visually separate the arrangement positions of both blocks more visually it can.

The drum-type gaming machine according to this aspect (1-4),
The special information is the gaming machine of this aspect (1-2), which is a bit string in which information on the gaming machine is coded by a predetermined coding method.

  According to the reel-type game machine according to this aspect (1-4), in addition to the above-described effects, when arranging special information not accessed by the CPU between the first block and the second block, Since the special information is "information about a gaming machine", the special information serves as a break on the program source code or dump list, and the source of the program source code can be simultaneously indicated. It becomes easier to artificially verify the legitimacy of the control block.

The drum-type gaming machine according to this aspect (1-5),
The total number of bytes relating to all the programs arranged in the second control area is less than the total number of bytes relating to all the programs arranged in the first control area, and The total number of bytes related to all the data arranged in two data areas is smaller than the total number of bytes related to all the data arranged in the first data area. Game machine).

  According to the reel-type game machine according to this aspect (1-5), in addition to the above-described effects, the first block = a control block for implementing a game characteristic specification, and the second block = for preventing fraud When arranged as a control block, the data capacity for tampering prevention becomes smaller than the data capacity for implementing the game characteristic specification. Here, since data for preventing fraudulent acts are likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but the data capacity is made relatively small. By limiting it, it is possible to reduce the effort for artificially verifying the legitimacy of the data for preventing fraud.

The drum-type gaming machine according to this aspect (2),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
When the CPU executes a process according to the program arranged in the first control area, the data arranged in the first data area can be read out; The data arranged in the second data area is configured not to be read out,
When the CPU executes a process according to the program arranged in the second control area, the data arranged in the second data area can be read out; The gaming machine is characterized in that the data arranged in one data area is not read out.

  According to the reeling type gaming machine according to the aspect (2), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reel-type game machine according to this aspect (2), the program which is present in the first control area and accessed by the CPU is for the data which is present and read in the first control area. Programs that are only accessible and are in the second control area and accessed by the CPU are in the first control area because they are only accessible to the data that are in the second control area and are read out. The program accessed by the CPU and the data present in and read from the first control area are regarded as a first block, and the program existing in the second control area and accessed by the CPU and the second control area Assuming that the data to be read out is the second block, it becomes easy to secure that the first block and the second block are control blocks having different functional properties, and both control blocks It is easy to artificially verify the validity.

The drum-type gaming machine according to this aspect (3),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
The program disposed in the second control area is configured to be able to execute processing by the CPU when there is a call instruction in the program disposed in the first control area. ,
It is a game machine characterized by.

  According to the reeling type gaming machine according to the aspect (3), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reel-type game machine according to this aspect (3), the program existing in the second control area and accessed by the CPU is further called a call in the program existing in the first control area and accessed by the CPU The processing by the CPU can be executed only when there is an instruction. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, the execution timing of the cheating prevention program can be limited only when this call instruction is issued, so the cheating execution program execution timing is on the program source code or dump list. It becomes clear visually, and in particular, it becomes easy to artificially verify the legitimacy of a program for preventing fraud. Here, since the program for preventing fraudulent acts is likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but by configuring in this way, It is possible to reduce the effort for verifying a program for preventing fraud.

The drum-type gaming machine according to this aspect (4),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
In the case where there is a call instruction in the program arranged in the first control area, the CPU performs the processing according to the program arranged in the second control area. It is a gaming machine characterized in that it is configured to be able to refer to information (for example, information held in a register in the CPUC 100) stored when a call instruction is given.

  According to the reeling type gaming machine according to the aspect (4), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the aspect (4), the program existing in the second control area and accessed by the CPU is further called a call in the program existing in the first control area and accessed by the CPU When there is an instruction, processing by the CPU becomes executable. In that case, for example, information held in a register in the CPU (that is, existing in the first control area immediately before the call instruction is present) as information stored at the time of the call instruction It becomes possible to deliver the processing result (which has been processed by the program accessed from the CPU) to the program that exists in the second control area and is accessed by the CPU. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, it is possible to build a master-slave relationship between the program for implementing the gameplay specification and the program for preventing cheating, inheriting the processing result of the program for implementing the main gameplay specification, It becomes possible to execute a program for preventing cheating. Here, since the processing result of the program for implementing the main gameplay specification can be highly confidential information, it is possible to use a subordinated program for preventing cheating which can externally output information for notifying cheating. If delivered innocently, there is a risk that security may be degraded. However, since the execution timing of the program for preventing fraudulent activity can be limited to the case where this call instruction is issued, the program source code or dump may be generated. As a result of the execution timing of the program for preventing fraud becoming clear on the list as a result, the delivery timing of the processing result is also clarified on the program source code or on the dump list, in particular (processing result Artificially verify the legitimacy of the program for the prevention of Theft is facilitated. Here, since the program for preventing fraudulent acts is likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but by configuring in this way, It is possible to reduce the effort for verifying a program for preventing fraud.

The drum-type gaming machine according to the aspect (5),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
In the case where there is a call instruction in the program arranged in the first control area, the CPU performs the processing according to the program arranged in the second control area. Processing of the CPU according to the program arranged in the second control area based on the call instruction based on information stored at the time of the call instruction (for example, information held in a register in the CPUC 100) The game machine is characterized in that it is configured to be updatable.

  According to the reeling type gaming machine according to the aspect (5), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the aspect (5), the program existing in the second control area and accessed by the CPU is a call in the program existing in the first control area and accessed by the CPU When there is an instruction, processing by the CPU becomes executable. In that case, for example, information held in a register in the CPU (that is, existing in the first control area immediately before the call instruction is present) as information stored at the time of the call instruction It is possible to update the processing result (processed by the program accessed by the CPU) with the processing result processed by the program which is present in the second control area and accessed by the CPU. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, it is possible to build a master-slave relationship between the program for implementing the gameplay specification and the program for preventing cheating, and inheriting the processing result of the cheating program to be subordinate, the main game It is possible to execute a program for implementing the sex specification. Here, since the processing result of the program for implementing the main game characteristic specification can be highly confidential information, from the subordinate anti-tampering program which can externally output the information for notifying the illegitimate activity. If it is updated silently, there is a risk that the security will be reduced, but since the execution timing of the program for preventing fraudulent activity can be limited to the case where this call instruction is issued, the program source code or As a result of the execution timing of the program for preventing fraud becoming clear on the dump list as a result, the update timing of the processing result is also clarified on the program source code or on the dump list, in particular (processing It is possible to artificially verify the legitimacy of the program for the prevention of To become. Here, since the program for preventing fraudulent acts is likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but by configuring in this way, It is possible to reduce the effort for verifying a program for preventing fraud.

The drum-type gaming machine according to this aspect (6),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
In the case where there is a call instruction in the program arranged in the first control area, the CPU performs the processing according to the program arranged in the second control area. After the processing result of the CPU according to the program arranged in the second control area based on the call instruction is returned from the call instruction, the CPU follows the program arranged in the first control area. A gaming machine characterized in that it is configured to be able to refer to when performing processing.

  According to the reeling type gaming machine according to the aspect (6), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reel-type game machine according to aspect (6), the program existing in the second control area and accessed by the CPU is further called a call in the program existing in the first control area and accessed by the CPU When there is an instruction, processing by the CPU becomes executable. In that case, for example, information stored in a register in the CPU (that is, existing in the second control area immediately before returning from the call instruction) as information stored when returning from the call instruction It is possible to deliver the processing result (which has been processed by the program accessed from the CPU) to the program that exists in the first control area and is accessed by the CPU. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, it is possible to build a master-slave relationship between the program for implementing the gameplay specification and the program for preventing cheating, and inheriting the processing result of the cheating program to be subordinate, the main game It is possible to execute a program for implementing the sex specification. Here, since the program for implementing the main game characteristic specification can process highly confidential information, the processing of a subordinate cheating program that can acquire information for preventing cheating from the outside If the result is handed over silently, there is a risk that the security will be degraded. However, since the execution timing of the program for preventing fraudulent activity can be limited to this call instruction, it is possible to Or as a result of the execution timing of the program for preventing fraud becoming clear on the dump list, the delivery timing of the processing result is also clarified on the program source code or dump list, in particular ( Artificially correct the program's fraud prevention program, including the delivery It becomes easy to testify. Here, since the program for preventing fraudulent acts is likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but by configuring in this way, It is possible to reduce the effort for verifying a program for preventing fraud.

The drum-type gaming machine according to this aspect (7),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
When a first error (for example, the event that the medal payout device H becomes full with game medals shown in step 1208) is detected by the processing of the CPU according to the program arranged in the first control area To be able to execute an error process (for example, the control process for a medal full error state shown in step 1210) associated with the first error,
When a second error (for example, an event shown in step 1044, data relating to a set value is not within the normal range) is detected by the processing of the CPU according to the program arranged in the second control area (2) A gaming machine characterized in that it is configured to be able to execute error processing (for example, non-returnable error processing shown in step 1048 and step 1300) associated with an error.

  According to the reeling type gaming machine according to the aspect (7), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the aspect (7), the error processing associated with the first error processed by the program which is present in the first control area and is accessed by the CPU, and the second control area And the error processing associated with the second error processed by the program accessed by the CPU can be clearly separated on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, the error processing associated with the first error is regarded as an error that may occur on the game (that is, even if there is no cheating), and the error processing associated with the second error is cheating. It can be clarified that the error processing can be generated in the above and the roles played by the two error processing are different. Here, since the program for preventing fraudulent acts is likely to differ in specification among gaming machine manufacturers, it is highly necessary to artificially verify the legitimacy, but the necessity of error processing associated with the second error Since it is easy to verify against the error processing associated with the first error, it is possible to reduce the effort for verifying the program for preventing fraud.

The drum-type gaming machine according to aspect (8),
A gaming machine comprising a ROM (for example, a built-in ROM C110), a RAM (for example, a built-in RAM C120), and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program disposed in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When error detection is performed on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing related data stored in the first information storage area Error detection based on error detection information (for example, a method of performing a checksum check) and error detection based on error detection information on processing result data stored in the second information storage area (for example, a method of performing a checksum check) And the like are separately configured.

  According to the reeling type gaming machine according to the aspect (8), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the present aspect (8), the processing result to be processed by the program which is present in the first control area and accessed by the CPU, and which is present in the second control area The processing results processed by the program to be accessed can be stored in separate information storage areas, and in that case, when performing error detection of the stored processing results, each information storage area can be stored. Error detection can be performed separately. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game characteristic specification and the processing result processed by the program for preventing fraudulent activity are not mixedly stored, and the storage If the processed result is temporarily destroyed, it is possible to clearly know which of the two processed results is destroyed. Thus, for example, if the importance of the processing result processed by the cheating prevention program is low, even if the processing result processed by the cheating prevention program is destroyed, If the processing result processed by the program for implementing the game characteristic specification is held without being destroyed, it can be configured to continue the processing.

The drum-type gaming machine according to this aspect (9),
A gaming machine comprising a ROM (for example, a built-in ROM C110), a RAM (for example, a built-in RAM C120), and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program disposed in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When performing error detection on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing result data stored in the first information storage area An error detection is performed based on error detection information obtained by calculating the processing result data stored in the second information storage area (for example, a method of performing a checksum check). is there.

  According to the reeling type gaming machine according to the aspect (9), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the present aspect (9), the processing result to be processed by the program which is present in the first control area and accessed by the CPU, and which is present in the second control area The processing results processed by the program to be accessed can be stored in separate information storage areas, and in that case, when error detection of the stored processing results is performed, each information storage area is Error detection can be performed on the integrated one. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game characteristic specification and the processing result processed by the program for preventing fraudulent activity are not mixedly stored, and the storage If the processed result is temporarily destroyed, it can be easily known that either of the two processing results is destroyed. Thus, for example, when the importance of the processing result processed by the program for preventing fraud is high, the processing result by the program for implementing the game characteristic specification and the program for preventing fraud are processed. It is possible to configure so as to continue the process only when it is possible to simply derive that none of the process results is destroyed.

The drum-type gaming machine according to this aspect (10),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
By the processing of the CPU according to the program arranged in the first control area, a predetermined event (for example, based on an input signal from a predetermined sensor unit (for example, the first closing sensor D20s or the second closing sensor D30s) For example, it is configured to be able to determine whether or not an event of having received one game medal shown in step 1227).
An abnormal event (for example, indicated in a subroutine of step 1400) related to the game progress based on the input signal from the predetermined sensor unit by the processing of the CPU according to the program arranged in the second control area It is a gaming machine characterized in that it can be judged whether or not an insertion medal backflow error, an insertion medal retention error, etc. has occurred.

  According to the reeling type gaming machine according to the present aspect (10), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reeling type gaming machine according to the present aspect (10), it is further determined whether or not the occurrence of a normal event relating to the game progress based on the sensor signal is made by the program existing in the first control area and accessed from the CPU. The presence or absence of an abnormal event related to the game progress based on the sensor signal can be determined by the program existing in the second control area and accessed by the CPU, and in any case, the determination based on the same sensor signal It can be done. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, the same sensor signal is treated as an input signal necessary for proceeding with the game in a program for implementing a game characteristic specification, and in the program for preventing fraudulent action, the same sensor signal is illegal Since it can be handled as an input signal necessary for preventing behavior, it can be clarified that the same sensor signal is handled differently on the program source code or dump list. Here, since the program for preventing fraudulent acts is likely to differ in specification among game machine manufacturers, it is highly necessary to artificially verify the legitimacy, but the difference regarding how to handle the same sensor signal By facilitating point-to-point verification, it is possible to reduce the effort for verifying a program for preventing fraud.

The drum-type gaming machine according to this aspect (11),
A gaming machine comprising a ROM (for example, a built-in ROM C110) and a CPU (for example, CPUC 100),
An address is assigned to the ROM, and a program that manages an instruction to the CPU and data to be read according to the program are stored.
On a memory map in which the address values in the ROM are continuous in ascending order (for example, an example of a memory map of the main control chip C shown as <memory map> in the embodiment),
A first control area (for example, a first control area in a first ROM area) in which the program is arranged for the address values continuous from a first start point address value to a first end point address value;
A first data area (for example, in a first ROM area) in which the data is arranged for the address value continuing from a second start address value larger than the first end point address value to a second end point address value. The first data area),
A second control area (for example, in a second ROM area) in which the program is arranged for the address value continuing from the third start point address value to the third end point address value larger than the second end point address value. Second control area),
A second data area (for example, in the second ROM area) in which the data is arranged for the address value continuous from the fourth start address value to the fourth end address value larger than the third end address value And at least a second data area),
A control signal (for example, a hopper motor drive signal) instructing payout of gaming media by processing of the CPU according to the program arranged in the first control area and a predetermined sensor unit (for example, the first payout sensor H10s or the like) Based on the non-detection time of the second payout sensor H20s), the first abnormal event (for example, step 1279 shown in step 1279) which is an abnormal event relating to the game progress, the payout operation of one gaming medal is performed after the hopper drive. Can be judged whether or not the
By the processing of the CPU according to the program arranged in the second control area, based on the detection time of the predetermined sensor unit, a second abnormal event (for example, step 1450 This gaming machine is characterized in that it is possible to determine whether or not the occurrence of the payout medal retention error) shown in the subroutine.

  According to the reeling type gaming machine according to the present aspect (11), the program existing in the first control area and accessed by the CPU, and the program existing in the second control area and accessed by the CPU are memory Since they are arranged at a distance (in a non-consecutive arrangement of addresses) on the map, the arrangement positions of both programs can be clearly distinguished visually on the program source code or dump list. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud By arranging as a program, the arrangement position of the program for implementing the game characteristic specification and the program for preventing tampering can be clearly distinguished visually on the program source code or on the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program existing in the first control area and accessed by the CPU is located at a smaller address than the program existing in the second control area and accessed by the CPU, the CPU is executed first. It becomes easy to limit the programs to be stored in the first control area to the programs accessed by the CPU (that is, the programs for implementing the game characteristic specification).

  According to the reel-type game machine according to the present aspect (11), the “light” abnormal event related to the game progress based on the sensor signal by the program that is present in the first control area and accessed from the CPU The presence or absence can be determined, and the presence or absence of the “severe” abnormal event related to the game progress based on the sensor signal can be determined by the program existing in the second control area and accessed by the CPU, in any case In the above, it is possible to make a determination based on the same sensor signal. As a result, for example, a program existing in the first control area and accessed by the CPU = a program for implementing the game characteristic specification, a program existing in the second control area and accessed by the CPU = for preventing fraud When arranged as a program, in the program for implementing the game characteristic specification, the same sensor signal is treated as an input signal necessary for detecting an error that may occur during normal game progression, and the program for preventing fraudulent activity Can treat the same sensor signal as an input signal necessary for preventing tampering (that is, it is necessary for error detection that is unlikely to occur in the normal course of a game), therefore, on the program source code or dump list Clearly indicate that the handling of the same sensor signal is different. . Here, since the program for preventing fraudulent acts is likely to differ in specification among game machine manufacturers, it is highly necessary to artificially verify the legitimacy, but the difference regarding how to handle the same sensor signal By facilitating point-to-point verification, it is possible to reduce the effort for verifying a program for preventing fraud.

P Throttle type game machine, DU front door (door)
D door board, D10s closing acceptance sensor D20s first closing sensor, D30s second closing sensor D40 stop button, D41 left stop button D42 middle stop button, D43 right stop button D50 start lever, D60 settlement button D70 display panel, D80 door switch D90 coin shooter, D100 blocker D130 upper panel, D140 lower panel D150 decoration lamp unit, D160 reel window D170 medal insertion slot, D180 operation status indicator D190 payout number display device, D200 credit number display device D210 dosage number indicator light, D220 bet Button D230 medal receiver, D240 outlet D250 special game status display device, D260 keyhole M main control board, M10 setting door switch M20 setting key switch, M30 setting / reset button C main Control chip, M50 reel M51 left reel, M52 middle reel M53 right reel S secondary control board, S10 LED lamp S20 speaker, S30 single-body backlight S40 effect display device, SC secondary control chip E power board, E10 power switch H medal payout Device, H10s first dispensing sensor H20s second dispensing sensor, H40 hopper H50 disc, H50a disc rotating shaft H60 game medal outlet, H70 releasing biasing means H80 hopper motor K rotating body substrate, K10 rotating body motor K20 rotating body sensor IN relay substrate

Claims (1)

As ROM area,
A first control area in which the program is stored ,
A first data area in which data is stored ;
A second control area in which the program is stored ,
A second data area in which data is stored and
At least it has,
As a RAM area,
And processing result information can be stored a first data storage area of the program that is stored in the first control region,
Comprising at least a said second control region capable of storing the processing result information of the program that is stored in a second information storage area,
Based on the program stored in the first control area, it is determined whether or not the power failure has occurred, and when it is determined that the power failure has occurred, the program stored in the second control area is: The error detection information can be calculated based on the information in the RAM area, and the calculated error detection information is stored in a predetermined storage area of the second information storage area by the program stored in the second control area. After that, the loop process waiting for reset can be executed by the program stored in the first control area, and it is not judged in the loop process waiting for reset whether the voltage state is recovered or not <br A game machine characterized by

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