JP5175125B2 - Display device - Google Patents

Description

  The present invention relates to a display device.

Conventionally, a display device including a drive control unit that controls writing of a video signal is known. In addition, a display device is known in which video signals are written by a method (overlap method) in which writing is performed on the next pixel in a state where writing is performed on a predetermined pixel under the control of the drive control unit. ing.

In such a conventional display device, when writing is performed using the overlap method, the pixel in the next stage is turned on while writing to a predetermined pixel, and thus the pixel and the video that are being written with the video signal are turned on. The next-stage pixels to which no signal is written are connected to each other via the video signal line. At this time, the potential on the pixel side during writing (the potential of the data line connected to the pixel electrode) is lowered by being drawn to the pixel side of the next stage. Further, when a video signal is supplied to the data line, a parasitic capacitance may be generated between the data line and the COM wiring (common electrode wiring), and the COM potential may fluctuate. At this time, while the changed COM potential gradually returns to the potential before the change, the writing of the next pixel is started during the writing of the video signal, which is caused by the writing of the next pixel. The COM potential fluctuates again. Also,
For each pixel, a change in COM potential occurs due to the start of writing of the next pixel during writing of the video signal. For this reason, if the video signal writing period is completed before the potential before the fluctuation has been fully recovered, COM is
The video signal is not sufficiently written as much as the potential does not return.

On the other hand, since there is no next-stage pixel when writing to the final-stage pixel, the potential drop as described above does not occur in the final-stage pixel. Further, in the last pixel, the COM potential does not fluctuate due to the writing operation of the next pixel within the writing period. Therefore, for only the last pixel, the changed COM potential is sufficiently returned to the original potential within the video signal writing period. As described above, as a result of this, only the final pixel is written with a video signal more sufficiently than the other pixel, so that a luminance difference may occur between the final pixel and the other pixel. .

Therefore, conventionally, a display device for suppressing the occurrence of such a luminance difference has been disclosed (for example, see Patent Document 1). In the display device described in Patent Document 1, in order to make the degree of video signal writing to the pixels in the final stage the same as the degree of writing to pixels other than the final stage, the pixels in the final stage are actually used. A one-stage dummy pixel, dummy data line, and dummy H switch that are not displayed are connected. As a result, when writing is performed on the final stage pixel, the final stage pixel and the dummy pixel are connected to each other, so the degree of video signal writing is reduced by the amount connected to the dummy pixel. As a result, a difference in luminance between the last-stage pixel and the other-stage pixel is suppressed.

Japanese Patent No. 3297962

However, in the display device described in Patent Document 1, it is necessary to separately provide a dummy pixel, a dummy data line, and a dummy H switch in order to suppress the occurrence of the luminance difference as described above. Further, when the above-mentioned Patent Document 1 is applied to a display device configured by a block sequential method in which writing is performed for each pixel block configured by a plurality of pixels, 1
A dummy pixel block composed of a plurality of dummy pixels corresponding to the pixel block, dummy data lines, and dummy H switches must be provided separately. Therefore, in order to suppress the occurrence of a luminance difference in the pixels at the final stage, there is a problem that the plane area of the frame area of the display unit becomes larger by providing the dummy pixel block.

The present invention has been made to solve the above-described problems, and one object of the present invention is to impair the display quality of an image while suppressing an increase in the plane area of the frame area of the display unit. It is an object of the present invention to provide a display device that can suppress the occurrence of the problem.

Means for Solving the Problems and Effects of the Invention

According to one aspect of the present invention for solving the above-described problem, a display unit that includes a plurality of step portions each having pixels, each corresponding to a plurality of signal lines for writing video signals, and a plurality of signal lines A drive control unit that sequentially writes video signals to each stage portion along the arrangement direction, and the drive control unit writes video signals to a certain stage portion among the plurality of stage portions Then, when the video signal is written to the stage portion where the video signal is written next and the video signal is written to the stage portion where writing is performed last among the plurality of stage portions, an amplifier circuit for supplying the video signal is provided. Provided is a display device for switching from a first amplifier circuit for supplying a video signal to a stage portion for writing before the stage portion to a second amplifier circuit having a current supply capability lower than that of the first amplifier circuit. Is done.

According to another aspect of the present invention for solving the above-described problem, a display unit that includes a plurality of step portions each corresponding to a plurality of signal lines for writing video signals, each having a pixel, A drive controller that sequentially writes video signals to each stage along the arrangement direction of the plurality of signal lines, and the drive controller writes video signals to a certain stage among the plurality of stages. In this state, when writing is performed also to the stage portion where the video signal is written next, and the video signal is written to the stage portion where writing is performed last among the plurality of stage portions, a common potential is applied to the common electrode of the pixel. The amplifier circuit for supplying a signal has a lower current supply capability than the third amplifier circuit from the third amplifier circuit for supplying the common electrode signal to the stage portion that performs writing before the stage portion. Switch to 4th amplifier circuit Obtain display apparatus is provided.

According to another aspect of the present invention for solving the above problem, an electronic apparatus including the display device is provided.

  According to the display device and the electronic device as described above, luminance is provided between a pixel at a stage portion where writing is performed last and a pixel other than the stage portion without separately providing a dummy pixel, a dummy data line, and a dummy H switch. Since the occurrence of the difference can be suppressed, an image with high display quality can be displayed without increasing the plane area of the frame area of the display unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device according to the first embodiment of the present invention. 2 to 6 are views for explaining a detailed configuration of the liquid crystal display device according to the first embodiment of the present invention. First, with reference to FIGS. 1-6, the liquid crystal display device 1 by 1st Embodiment of this invention.
The configuration of 00 will be described. In the first embodiment, a case where the present invention is applied to a liquid crystal display device which is an example of a display device will be described.

As shown in FIG. 1, the liquid crystal display device 100 according to the first embodiment includes a display screen unit 1, a drive IC 2, a V driver 3, an H driver 4, and a backlight 5. In the display screen section 1, a plurality of pixels 1a are arranged in a matrix. FIG. 1 shows three pixels 1a for simplification of the drawing. The display screen unit 1 and the driving IC 2
These are examples of the “display unit” and “drive control unit” of the present invention, respectively.

The drive IC 2 has a function for driving the entire liquid crystal display device 100. V driver 3
A plurality of gate lines 3a and data lines 4a are connected to the H driver 4 and the H driver 4, respectively. Further, the gate line 3a and the data line 4a are arranged so as to be orthogonal to each other. The V driver 3 has a function as a drive circuit for the gate line 3a. The H driver 4 has a function of sequentially supplying a video signal to a pixel electrode 1c, which will be described later, via the data line 4a. Further, the backlight 5 is configured as a light source of a transmission region of the pixel 1a. The data line 4a is an example of the “signal line” in the present invention.

Each pixel 1a includes a pixel transistor 1b (TFT), a pixel electrode 1c, a common electrode 1d, and a storage capacitor 1e. Drain region D of the pixel transistor 1b
Are connected to the data line 4a and the source region S of the pixel transistor 1b is
It is connected to the pixel electrode 1c and one electrode of the storage capacitor 1e. The gate G of the pixel transistor 1b is connected to the gate line 3a. Further, the common electrode 1d and the storage capacitor 1e
Each of the other electrodes is connected to a COM driver 2e (see FIG. 6) described later.

As shown in FIG. 2, the H driver 4 includes a scan direction control unit 4b and a plurality of shift register units 4c (n (n = 1, 2,...) In the first embodiment). . The scan direction control unit 4b includes one inverter 4d and a plurality of switch units 4e. The scan direction control unit 4b outputs the sampling pulses (SP1, SP2,... SPn) in the order in which they are output based on the direct current CSH signal supplied from the drive IC 2 (scanning direction).
Is configured to be controllable.

Specifically, for example, when an H level CSH signal is supplied to the scan direction control unit 4b, the on / off state of the switch unit 4e is as shown in FIG. That is, the STH signal is supplied to the shift register unit (1) in the figure as the first-stage shift register unit 4c,
The SR1 signal is output from the shift register unit (1). Then, the SR1 signal is input to the next-stage shift register unit 4c (shift register unit (2)), and the SR2 signal is output. The SR2 signal is supplied to the shift register unit 4c at the next stage. That is, the signals (SR1, SR2,... Output from the shift register unit 4c in the previous stage.
.) Are sequentially supplied to the next shift register unit 4c. Sampling pulses (SP1, SP2,... SPn) are sequentially output in the order of the arrow A in the figure from the shift register unit 4c supplied with the SR signal.

Further, when an L level CSH signal is supplied to the scan direction control unit 4b, the on / off state of the switch unit 4e is opposite to that in FIG. That is, the STH signal is supplied to the shift register unit (n) in the drawing as the first-stage shift register unit 4c, and the SRn signal is output from the shift register unit (n). The SRn signal is input to the next-stage shift register unit 4c (shift register unit (n-1)) (not shown), and the SRn-1 signal is output from the shift register unit (n-1). The SRn-1 signal is supplied to the shift register unit 4c at the next stage. As a result, as in the case described above, the SR signal output from the previous shift register unit 4c is supplied to the next shift register unit 4c, and the arrow B in the figure from the shift register unit 4c supplied with the SR signal. Sampling pulses (SPn... SP2, SP1) are sequentially output in order of direction.

Each shift register unit 4c includes a shift register 4f, an inverted signal generation circuit 4g,
And a shaping circuit 4h. The inverted signal generation circuit 4h is configured to generate two-phase clock signals (CKH signal and / CKH signal) that are inverted from each other from the clock signal supplied from the driving IC 2 and to supply the clock signal to the shift register 4f. The shift registers 4f at each stage all have the same circuit configuration, while the shift registers 4f (
3), the CKH signal is supplied to one clock signal input unit, and the / CKH signal is supplied to the other clock signal input unit. Further, the even-numbered shift register 4f (see FIG. 4) is configured such that the / CKH signal is supplied to one clock signal input unit and the CKH signal is supplied to the other clock signal input unit. Yes.

Further, as shown in FIGS. 3 and 4, the inverted signal generation circuit 4g includes seven inverters 4i.
The latch circuit 4j is composed of two inverters 4i. Further, the output side of the inverter 4i is connected to one input side of the latch circuit 4j, and another inverter 4i is connected to the input side of the inverter 4i.
Is connected to the output side. The output side of one inverter 4i is connected to the other input side of the latch circuit 4i. Further, 1 is provided on each of the two output sides of the latch circuit 4j.
The input side of the inverter 4i is connected to each other.

The shift register 4f includes an inverter 4k and a latch circuit 4n including inverters 4l and 4m. Here, inverters 4k and 4l are constituted by clocked inverters whose outputs are controlled based on a clock signal. Further, on the input side of the shift register 4f (the input side of the inverter 4k (in in the figure))
Either an STH signal output from the driving IC 2 or an SR signal (SR1, SR2,... In FIG. 2) output from the previous shift register unit 4c is configured to be supplied. The output side of the inverter 4k and the input side of the latch circuit 4n are connected. The two-phase clock signal generated by the inverted signal generation circuit 4g is input to each of the inverters 4k and 4l (clocked inverter) of the shift register 4f.

Further, the shaping circuit 4h outputs signals from the shift register 4f (SP1a, SP2 in FIG. 2).
a, and a sampling pulse (SP1, SP2,.
) Is output to a switch unit 7 (see FIG. 5) described later. Also,
The output signal from the shift register 4f is output as a sampling pulse,
The SR signal (SR1, SR2,... In FIG. 2) is also output to the next-stage shift register unit 4c. The sampling pulse is a switch unit 7 (to be described later)
This is a signal for controlling on / off of FIG.

Further, as shown in FIG. 5, in the display screen unit 1, one pixel block is configured for every n pixels 1 a. Specifically, n video signal lines 6 are wired at the edge portion of the display screen unit 1, and each video signal line 6 (n lines) and each pixel 1a in one block are arranged.
Data lines 4a corresponding to (n) are connected to each other via a switch unit 7 (HSW). The n switch units 7 corresponding to each pixel 1a in one block are configured to be on / off controlled by sampling pulses (SP1, SP2,...) Output from the H driver 4. That is, the n switch units 7 are simultaneously turned on by one sampling pulse, and a video signal is supplied from the n video signal lines 6 to the pixel electrode 1c via each switch unit 7. ing. As described above, the liquid crystal display device 100 according to the first embodiment is configured to write the video signal by the block sequential writing method in which writing is performed for each block.

As shown in FIG. 6, the driving IC 2 includes a shift register 2a and a D / A converter 2.
b, a video signal amplifier circuit 2c, a timing controller 2d, a COM driver 2e, a DSD driver 2f, and a DC / DC converter 2g. Shift register 2
a is a serial data signal (DA in FIG. 6) supplied from the external module (not shown) side.
TA) is converted into a parallel signal. The D / A converter 2b has a function of converting the data signal supplied from the shift register 2a from a digital signal to an analog signal. The video signal amplifying circuit 2c is configured to amplify the analog signal supplied from the D / A converter 2b and supply it to each video signal line 6 (see FIG. 5).

Here, in the first embodiment, the video signal amplifier circuit 2 c is provided with a first amplifier circuit 2 h and a second amplifier circuit 2 i for each video signal line 6. The current supply capability (ratio of voltage change with respect to time) of the second amplifier circuit 2i is configured to be smaller than that of the first amplifier circuit 2h. That is, for example, when signals of the same magnitude are amplified by the first amplifier circuit 2h and the second amplifier circuit 2i, the data signal (video signal) amplified by the second amplifier circuit 2i is transmitted by the first amplifier circuit 2h. The degree of writing of the data signal relative to the time when it is written to the pixel electrode 1c (when it is output to the data line 4a) (the speed until the video signal is sufficiently written) is smaller than the amplified data signal. The first amplifier circuit 2h and the second amplifier circuit 2h
A switch section 2j is provided for each amplifier circuit 2i. The video signals (Video (1) to Video (n) in the figure) output for each pixel block are supplied from the switch unit 2.
By switching j, it is configured to be amplified by any one of the first amplifier circuit 2h and the second amplifier circuit 2i.

In the first embodiment, only the video signal supplied to the last pixel block is amplified by the second amplifier circuit 2i. The video signals supplied to the pixel blocks other than the final stage are each configured to be amplified by the first amplifier circuit 2h.
That is, the video signal supplied to the pixel block at the final stage is slower in speed than the video signal supplied to the pixel blocks other than the final stage.

In addition, the timing controller 2d receives a basic clock (Dot in the figure) from the module side.
(Clock) is supplied, and the supplied basic clock is divided and output to each unit. The timing controller 2d is configured to output a signal for switching the switch unit 2j of the video signal amplifier circuit 2c to the video signal amplifier circuit 2c. Thereby, each switch part 2j of the video signal amplifier circuit 2c is connected to the D / A converter 2b.
When the data signals are sequentially supplied from, the switching operation is performed all at once based on the signal output from the timing controller 2d. As described above, the first amplification circuit 2 is displayed on the display screen unit 1 supplied with the video signal by the switching of the switch unit 2j.
An image composed of a pixel block to which the video signal amplified by h is supplied and a pixel block (final stage pixel block) to which the video signal amplified by the second amplifier circuit 2i is supplied is displayed. It is configured.

Further, the COM driver 2e is configured to output an H level signal and an L level signal (CO
The M signal and the SC signal (COM / SC in the figure) are supplied to the common electrode 1d and the other electrode (see FIG. 1) of the storage capacitor 1e. The DSD driver 2f is connected to the data line 4a
Has a function for maintaining the voltage at a reference potential. The DC / DC converter 2g has a power supply voltage (
(VDD in the figure) is amplified and supplied to the COM driver 2e and the DSD driver 2f. Specifically, two signals (COMH and COML in the figure) having different sizes are supplied from the DC / DC converter 2g to the COM driver 2e, and COM
Only one of the signals is output by switching the switch unit 2k provided in the driver 2e. Similarly, from the DC / DC converter 2g to the DS
Two signals of different sizes (DSDH and DSDL in the figure) are supplied to the D driver 2f, and a switch unit provided in the DSD driver 2f in accordance with the change in the size of the output signal from the COM driver 2e Only one of the signals is output by switching 2l. The DC / DC converter 2 g has a function of supplying power to the display screen unit 1.

FIG. 7 is a view for explaining the operation of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 8 is a diagram for explaining a comparative example for the liquid crystal display device according to the first embodiment of the present invention. Next, the operation of the liquid crystal display device 100 according to the first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 7, the STH signal (see FIG. 2) is supplied from the driving IC 2 to the first-stage shift register unit 4c (shift register unit (1) in FIG. 2) via the scan direction control unit 4b. The SR1 signal and the SP1a signal (output signal) are output from the first-stage shift register unit 4c in synchronization with the first falling edge of the clock signal in a state where the STH signal is supplied. At this time, the SR1 signal is input to the next shift register unit 4c (shift register unit (2) in FIG. 2) via the scan direction control unit 4b. In addition, the SP1a signal is input to the shaping circuit 4h and is shaped by the shaping circuit 4h to obtain a sampling pulse (S
P1 signal). The SP1 signal is n corresponding to the first pixel block.
N switches 7 (see FIG. 5) are supplied, and n switches 7 corresponding to the SP1 signal are turned on during the period t1. That is, this period t1 is a video signal writing period to the pixel 1a in the first pixel block.

Further, in a state where the video signal is written to the pixel block of the first stage, the SR2 from the next stage shift register unit 4c (shift register (2) in FIG. 2) is synchronized with the first rise of the clock signal. Signal and SP2a signal are output. Then, the SP2a signal is output as the SP2 signal via the shaping circuit 4h, and the n switch units 7 corresponding to the pixel block at the next stage are turned on. At this time, the SP1 signal is still supplied, and the first-stage pixel block and the next-stage pixel block are mutually connected to the video signal line 6 (FIG. 5).
(See)).

Then, in synchronization with the next fall of the clock signal, the SP1 signal is turned off, and the SP3 signal (period t1) is output from the shift register unit 4c (3) (not shown). In this manner, each pixel block is turned on during the period t1 (one cycle of the clock signal (CKH)), and each pixel block is connected to the next pixel block during the half cycle of the clock signal. Connected. At this time, from the video signal line 6, the video signals (Video 1 and Video 2 in the figure) amplified by the video signal amplifier 2 c (see FIG. 6) every half cycle (t1 / 2) of the clock signal. ,... Are sequentially output and are sequentially supplied to the respective pixels 1a in the corresponding pixel block.

Here, in the period corresponding to the latter half of the SP1 signal, the pixel block in the next stage is connected, so that the potential of the corresponding data line 4a (VD1 in FIG. 7) is not yet written to the video signal. The voltage temporarily decreases as it is pulled by the potential difference generated between the data line 4a of the pixel block in the stage (decrease in the direction of arrow C in FIG. 7). Then, it rises again over a period until the SP1 signal is turned off. Further, the SP1 signal is supplied and the switch unit 7
Is switched to the ON state, the data line 4a, the COM wiring and the SC wiring (retention capacitor 1e
Parasitic capacitance is generated between the other electrode wiring (not shown) and the potential of the common electrode 1d changes (changes in the direction of arrow D in FIG. 7), and the potential of the changed common electrode 1d changes. Then shifts in the direction of returning to the original potential (the direction opposite to arrow D) during the ON period of the switch section.

Due to the decrease in the potential of the data line 4a (arrow C in FIG. 7) and the fluctuation in the potential of the common electrode 1d (arrow D in FIG. 7) as described above, the video for the first pixel block in the writing period of the period t1. The degree of signal writing is such that the target potential is not reached. 2
Also in the degree of video signal writing from the pixel block at the stage to the pixel block at the (n−1) stage, the potential of the data line 4a is decreased and the potential of the common electrode 1d is changed as in the first pixel block. As a result, the extent that the target potential is not reached (VD2 to VD (n
-1)).

On the other hand, only the last pixel block does not have the next pixel block that is connected to each other when the video signal is written, and therefore the potential of the data line 4a does not decrease (E in FIG. 7). . Further, since there is no fluctuation in the potential of the common electrode 1d, the degree of return of the potential of the common electrode 1d to the original potential is larger than that of the previous pixel block (the degree of return by the width F in FIG. 7 is large). Become). Therefore, the video signal can be written more sufficiently only in the final pixel block.

Here, in the first embodiment, when a video signal is supplied from the initial stage pixel block to the last stage pixel block, the video signal amplification circuit 2c is sent from the timing controller 2d.
The switch section 2j is connected to the first amplifier circuit 2h. As a result, the video signal amplified by the first amplifier circuit 2h is supplied from the first pixel block to the pixel block one stage before the final stage. When the video signal is supplied to the pixel block at the final stage, the timing controller 2d supplies a signal that connects the switch unit 2j of the video signal amplifier circuit 2c to the second amplifier circuit 2i. As a result, only the pixel block in the final stage
Since the video signal amplified by the second amplifying circuit 2i is supplied, the video signal supplied to the pixel block at the final stage is written at a speed faster than the video signal supplied to the pixel block other than the final stage. Is small. Therefore, in the writing period (t1), the degree of writing of the video signal to the pixel block at the final stage is such that it does not reach the target potential, similarly to the degree of writing to the pixel blocks other than the final stage.

In other words, in the first embodiment, the second amplifier circuit 2i writes to the pixel block at the final stage where more sufficient writing is possible, and writes to the pixel blocks other than the final stage amplified by the first amplifier circuit 2h. The video signal is adjusted to be amplified so that the degree is substantially the same.

On the other hand, in the comparative example shown in FIG. 8, the potential of the data line 4a does not decrease (FIG. 8).
With E), there is no fluctuation in the potential of the common electrode 1d. Since the video signal amplified by the same amplifier circuit is supplied to all the pixel blocks including the pixel block at the final stage, the video signal is more sufficiently written only to the pixel block at the final stage. It is.
For this reason, the potential of the data line 4a in the pixel block at the final stage reaches a higher potential than the potential of the data line 4a in the pixel block other than the final stage (G in FIG. 8). Therefore, a luminance difference is generated between the display area corresponding to the pixel block at the final stage and the display area corresponding to the pixel block other than the final stage.

FIG. 9 and FIG. 10 are diagrams for explaining an example of an electronic apparatus using the liquid crystal display device according to the first embodiment of the present invention and another example, respectively. Next, with reference to FIG. 9 and FIG. 10, an electronic apparatus using the liquid crystal display device 100 according to the first embodiment of the present invention will be described.

The liquid crystal display device 100 according to the first embodiment of the present invention, as shown in FIGS.
It can be used for a mobile phone 50 and a PC (personal computer) 60. In the mobile phone 50 of FIG. 9, the liquid crystal display device 100 according to the first embodiment of the present invention is used for the display screen 50a. Further, the PC 60 of FIG. 10 can be used for an input unit such as a keyboard 60a and a display screen 60b. In addition, by incorporating the peripheral circuit in the substrate in the liquid crystal panel, the number of parts can be greatly reduced, and the apparatus body can be reduced in weight and size.

In the first embodiment, as described above, the pixel 1 of the final block is controlled by the control of the driving IC 2.
The degree of voltage change of the video signal written to a is determined by the pixel 1a other than the final stage block.
Is configured to be smaller than the degree of voltage change of the video signal written to the pixel 1a, the degree of voltage change of the video signal written to the pixel 1a of the final stage block is written to the pixel 1a other than the final stage block. Less than the degree of voltage change of the video signal,
It is possible to prevent the writing to only the pixel 1a in the final block from being overwritten.
As a result, the video signal writing degree to the pixel 1a of the final block and the video signal writing degree to the pixels 1a other than the final block can be made substantially the same.
Therefore, since it is possible to suppress a difference in luminance between the pixel 1a in the final block and the pixel 1a other than the final block, it is possible to suppress deterioration in the display quality of the image. In addition, by controlling the video signal writing level, a luminance difference is generated between the pixel at the final stage portion and the pixels other than the final stage portion without separately providing dummy pixels, dummy data lines, and dummy H switches. Therefore, it is possible to suppress a luminance difference between the pixel 1a in the final block and the pixel 1a other than the final block without increasing the plane area of the frame region of the display screen unit 1. Can do.

In the first embodiment, the degree of voltage change (V) of the video signal written to the data line 4a of the final block when the video signal is written is controlled by the driving IC 2.
Dn) indicates that the potential reached by the data line 4a of the final block is the data line 4 other than the final block.
The degree of voltage change of the video signal written to the pixel 1a of the final block is adjusted so as to be approximately the same as the potential reached by a. By configuring in this way,
At the time of writing the video signal, the degree of writing of the video signal to the pixel 1a of the last block is substantially the same as the degree of writing of the video signal to the pixels 1a other than the last block, so It is possible to reliably suppress the occurrence of a luminance difference with the pixel 1a other than the step block.

In the first embodiment, the pixels 1 other than the final block are controlled by the driving IC 2.
The video signal written to a is amplified by the first amplifier circuit 2h, and the video signal written to the pixel 1a of the final stage block is controlled to be amplified by the second amplifier circuit 2i. Only the video signal supplied to the pixel 1a of the final stage block that is sufficiently writable in comparison with the pixel 1a is amplified by the second amplifier circuit 2i having a smaller voltage amplification ratio with respect to time than the first amplifier circuit 2h. Therefore, the degree of writing of the video signal to the pixel 1a in the final block can be easily made substantially the same as the degree of writing of the video signal to the pixel 1a other than the final block.

In the first embodiment, when the block sequential method is adopted, the degree of voltage change of the video signal written to the pixel block at the final stage is set to the level of the video signal written to the pixel blocks other than the final stage. It can be made smaller than the degree of voltage change. Therefore, compared to the conventional configuration in which a dummy pixel block including a plurality of dummy pixels must be provided, the luminance difference generated in the display screen unit 1 can be suppressed only by the control of the driving IC 2, and as a result, the display It can suppress more effectively that the plane area of the frame area | region of the screen part 1 becomes large.

(Second Embodiment)
FIG. 11 is a diagram for explaining a configuration of a liquid crystal display device according to the second embodiment of the present invention. FIG. 12 is a timing chart for explaining the operation of the liquid crystal display device according to the second embodiment of the present invention. In the liquid crystal display device 200 according to the second embodiment, FIG. 5, FIG. 7 and FIG.
1, unlike the first embodiment in which only the video signal supplied to the final pixel block is controlled to be amplified by different amplifier circuits, only the common potential signal supplied to the final pixel block is different. An example in which amplification is controlled by the amplifier circuit will be described.

As shown in FIG. 11, the liquid crystal display device 200 according to the second embodiment of the present invention includes a driving IC 2.
0 is provided. The drive IC 20 includes a shift register 20a, a D / A converter 20b, a video signal amplifier circuit 20c, a timing controller 20d, and a COM driver 20e.
And a DSD driver 20f and a DC / DC converter 20g.

Similar to the first embodiment, the shift register 20a has a function of converting a serial data signal (DATA in FIG. 11) supplied from an external module (not shown) side into a parallel signal, and a D / A converter. 20b has a function of converting the data signal supplied from the shift register 20a from a digital signal to an analog signal. Video signal amplifier circuit 20
c is configured to amplify the analog signal supplied from the D / A converter 20b and supply it to each video signal line 6 (see FIG. 5). Note that the video signal amplifier circuit 20c in the second embodiment includes a plurality of amplifier circuits 20h. The video signal supplied to each pixel block including the video signal supplied to the pixel block at the final stage is all amplified by the amplifier circuit 20h.

In addition, the timing controller 20d receives a basic clock (Dot in the figure) from the module side.
(Clock) is supplied, and the supplied basic clock is divided and output to each unit. The timing controller 20d is configured to output a signal for switching the switch unit 20h of the video signal amplifier circuit 20c to the video signal amplifier circuit 20c. As a result, each switch unit 20h of the video signal amplifier circuit 20c is connected to the D / A
When the data signals are sequentially supplied from the converter 20b, the timing controller 20d
The switching operation is performed at the same time based on the signal output from.

Further, the COM driver 20e has a function of outputting a COM signal and an SC signal (COM / SC in the figure) and supplying them to the other electrode (see FIG. 1) of the common electrode 1d and the storage capacitor 1e. The DSD driver 20f has a function for holding the data line 4a at a reference potential. The DC / DC converter 20g has a function of amplifying the power supply voltage (VDD in the figure) and supplying the amplified voltage to the COM driver 20e and the DSD driver 20f. Specifically, two signals (COMH and COML in the figure) having different sizes are supplied from the DC / DC converter 20g to the COM driver 20e, and the COM driver 20
Only one level of the signal is output by switching the switch unit 20i provided in e.

Here, in the second embodiment, the DC / DC converter 20g includes a third amplifier circuit 20i and a fourth amplifier circuit 20j having a smaller voltage amplification ratio with respect to time than the younger brother 3 amplifier circuit 20i. The third amplifier circuit 20i and the fourth amplifier circuit 20j are each configured to amplify an H level signal and an L level signal and output the amplified signal as a common potential signal (COM signal) to the COM driver 20e. .

In the second embodiment, only the common potential signal supplied to the pixel 1a of the final block is amplified by the fourth amplifier circuit 20j, and the common potential signal supplied to the pixels 1a other than the final block is It is configured to be controlled to amplify by the three amplifier circuit 20i. Specifically, the COM driver 20e has a common potential signal level (H or L) amplified by the third amplifier circuit 20i and a common potential signal level (H or L) amplified by the fourth amplifier circuit 20j. L) is provided with a switch section 20k for switching each. A switch unit 201 is provided for switching whether to output either the common potential signal amplified by the third amplifier circuit 20i or the common potential signal amplified by the fourth amplifier circuit 20j.

Further, two signals (DSDH and DSDL in the figure) having different sizes are supplied from the DC / DC converter 20g to the DSD driver 20f, and the switch unit 20m is switched to match the switching of the switch unit 20k of the COM driver 20e. Thus, only one level of signal is output. DC / DC converter 2
0 g has a function of supplying power to the display screen unit 1. Note that the switch unit 20m, the switch unit 20k, and the switch unit 201 are configured so that switching is controlled by a signal from the timing controller 20d.

In addition, when a video signal is supplied from the first pixel block to the pixel block one stage before the last stage, the switch unit 20l of the COM driver 20e from the timing controller 20d.
Is supplied with a signal connected to the third amplifier circuit 20i. As a result, the common potential signal amplified by the third amplifier circuit 20i is supplied from the first pixel block to the pixel block one stage before the final stage. When the video signal is supplied to the pixel block at the final stage, a signal for supplying the switch unit 20l of the COM driver 20e to the fourth amplifier circuit 20j is supplied from the timing controller 20d. Accordingly, since the common potential signal amplified by the fourth amplifier circuit 20j is supplied only to the pixel block at the final stage, the video signal supplied to the pixel block at the final stage is supplied to the pixel blocks other than the final stage. The ratio with respect to the time of voltage amplification becomes smaller than the supplied video signal. Then, the degree of writing of the video signal to the pixel block at the final stage is such that the target reaching potential is not reached, similarly to the degree of writing to the pixel blocks other than the final stage.

In other words, in the second embodiment, the fourth amplifier circuit 20j writes the degree of writing to the pixel block at the final stage where more sufficient writing is possible, with respect to the pixel block other than the final stage amplified by the third amplifier circuit 20i. The common potential signal is adjusted so as to amplify the signal so as to be approximately the same size as the degree. Thus, in the second embodiment, as in the first embodiment, as shown in FIG. 7, the degree of video signal writing to the pixel block at the final stage is different from that at the final stage in the writing period (t1). Similar to the degree of writing to the pixel block, the target potential is not reached.

In the second embodiment, as described above, the COM driver 20e is controlled under the control of the drive IC 20.
By controlling the voltage, the ratio of the voltage change with respect to the time of the common potential signal supplied to the common electrode 1d of the pixel 1a of the final stage block when writing to the pixel 1a is performed. By controlling so as to be smaller than the rate of voltage change with respect to time of the common potential signal supplied to the common electrode 1d of 1a, it is possible to apply to the pixel 1a in the next stage portion performed during the writing of the video signal. Common electrode 1d due to video signal writing
Even if the potential of the common potential signal varies, the ratio of the voltage change with respect to the time of the common potential signal supplied to the pixel 1a of the final block is equal to the voltage change with respect to the time of the common potential signal supplied to the pixels 1a other than the final block. Since the ratio is smaller than the ratio, only the potential of the common electrode 1d in the pixel 1a in the final stage block can be prevented from sufficiently returning to the original potential from the changed potential. That is, when the potential of the common electrode 1d of each pixel 1a fluctuates, the ratio of the time at which the potential of the common electrode 1d returns to the original potential is approximately the same in all the pixels 1a including the pixel 1a of the final stage block. Can be. Therefore, since it is possible to suppress the writing to only the pixel 1a of the final block, it is possible to make all the pixels 1a have the same degree of writing. As a result, a luminance difference is produced between the pixel 1a in the final block and the pixels 1a other than the final block by controlling the ratio of voltage amplification with respect to the time of the common potential signal supplied to each pixel 1a. Can be suppressed.

In the second embodiment, the driving IC 2 amplifies the common potential signal supplied to the pixels 1a other than the final block by the third amplifier circuit 20i, and also supplies the common potential supplied to the pixels 1a of the final block. By configuring so that the signal is amplified by the fourth amplifier circuit 20j, only the common potential signal supplied to the pixel 1a of the final stage block that is sufficiently writable as compared with the other pixels 1a. Since the amplification is performed by the fourth amplification circuit 20j having a smaller voltage amplification ratio with respect to time than the third amplification circuit 20i, the degree of video signal writing to the pixel 1a in the final block is determined based on the video for the pixels 1a other than the final block. The degree of signal writing can be substantially the same.

In the second embodiment, even when the block sequential method is adopted, the luminance difference is generated in the region corresponding to the final block by controlling the ratio of the voltage amplification with respect to the time of the common potential signal. Can be suppressed.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

For example, in the first to third embodiments, the example in which the present invention is applied to the block sequential writing method in which writing is performed for each of a plurality of pixels has been shown. However, the present invention is not limited thereto, and writing is performed for each pixel. It can also be applied to the dot sequential writing method.

In the first embodiment, an example in which a video signal is amplified by two amplifier circuits is shown. In the second embodiment, an example in which a common potential signal is amplified by two amplifier circuits is shown. Is not limited to this, the video signal is amplified by two amplifier circuits, and the common potential signal is amplified by the two amplifier circuits, so that the writing degree of the voltage change of the video signal in all the pixel blocks is approximately the same. It may be.

1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram for explaining an H driver of the liquid crystal display device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram for explaining an H driver of the liquid crystal display device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram for explaining an H driver of the liquid crystal display device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram for explaining a switch unit of the liquid crystal display device according to the first embodiment of the present invention. It is a block diagram for demonstrating the structure of drive IC of the liquid crystal display device by 1st Embodiment of this invention. 4 is a timing chart for explaining a writing operation in the liquid crystal display device according to the first embodiment of the present invention; 6 is a timing chart for explaining a comparative example with respect to a writing operation in the liquid crystal display device according to the first embodiment of the present invention; It is a figure explaining the electronic device provided with the liquid crystal display device by 1st Embodiment of this invention. It is a figure explaining the electronic device provided with the liquid crystal display device by 1st Embodiment of this invention. It is a block diagram for demonstrating the H driver by 2nd Embodiment of this invention.

Explanation of symbols

1 Display screen section (display section)
1a pixel 1d common electrode 2 drive IC (drive control unit)
2h First amplifier circuit 2i Second amplifier circuit 6 Video signal line 20e COM driver (common potential supply unit)
20g DC / DC converter (common potential signal amplifier)
20i Third amplifier circuit 20j Fourth amplifier circuit 50 Mobile phone (electronic device)
60 PC (electronic equipment)
100, 200 Liquid crystal display device

Claims (8)

A display unit corresponding to a plurality of signal lines for writing a video signal, each including a plurality of stage portions each having a pixel, and a video signal sequentially applied to each stage portion along the arrangement direction of the plurality of signal lines. A drive control unit that performs writing, and
  The drive control unit
  Among the plurality of stage parts, in a state where the video signal is written to a certain stage part, the next stage part to which the video signal is written is also written,
  When writing a video signal to the last stage part to be written among the plurality of stage parts, an amplifier circuit for supplying the video signal is provided with a video signal to the stage part to be written before the stage part. Switching from the first amplifier circuit for supply to the second amplifier circuit having a current supply capability lower than that of the first amplifier circuit.
  Display device. When the video signal is written to the stage portion where writing is performed last, when the video signal is written to the stage portion other than the stage portion where writing is performed lastly, and the arrival potential of the signal line corresponding to that stage portion The current supply capability of the second amplifier circuit is adjusted so that the ultimate potential of the signal line corresponding to the stage portion of the second amplifier circuit is approximately the same.
  The display device according to claim 1.   The second amplifier circuit has a smaller voltage amplification ratio with respect to time than the first amplifier circuit.
  The display device according to claim 1. A pixel block is formed by a plurality of pixels,
  The video signal is written for each pixel block via the signal line,
  The stage portion where writing is performed last is the pixel block where writing is performed last in one horizontal period.
  The display device according to claim 1. A display unit corresponding to a plurality of signal lines for writing a video signal, each including a plurality of stage portions each having a pixel, and a video signal sequentially applied to each stage portion along the arrangement direction of the plurality of signal lines. A drive control unit that performs writing, and
  The drive control unit
  Among the plurality of stage parts, in a state where the video signal is written to a certain stage part, the next stage part to which the video signal is written is also written,
  When writing a video signal to the last stage portion to be written among the plurality of stage portions, an amplifier circuit for supplying a common potential signal to the common electrode of the pixel is written before the stage portion. Switching from the third amplifier circuit for supplying the common electrode signal to the stage portion to be performed to the fourth amplifier circuit having a current supply capability lower than that of the third amplifier circuit.
  Display device.   The fourth amplifier circuit has a smaller voltage amplification ratio with respect to time than the third amplifier circuit.
  The display device according to claim 5. A pixel block is formed by a plurality of pixels,
  The video signal is written for each pixel block via the signal line,
  The stage portion where writing is performed last is the pixel block where writing is performed last in one horizontal period.
  The display device according to claim 5 or 6. The electronic device provided with the display apparatus of any one of Claims 1-7.

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