JP3775188B2 - Liquid crystal display device and information equipment provided with the liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to a line sequential method in which a liquid crystal display driver is mounted and sequentially driven for each block, or a driving method and a driving circuit for performing liquid crystal display by a time division method.
[0002]
[Prior art]
The field effect mobility of poly-Si is about 0.5 to 1 cm which is the field effect mobility of amorphous Si. ² About tens to 200cm compared to / Vs ² Large as / Vs. For this reason, it is possible to form peripheral circuits such as a signal circuit and a scanning circuit on the same substrate on which the liquid crystal display portion is formed by using poly-Si TFTs. Also, by using poly-Si TFTs, the peripheral circuit can be formed on the same substrate as the liquid crystal display unit, so that connection with an external peripheral circuit such as a line sequential driver is unnecessary and the resolution is high as in the prior art. A liquid crystal display device can be realized.
[0003]
However, when realizing a high-definition and high-definition liquid crystal display device, the clock frequency is as high as several tens of MHz, and the peripheral circuit, particularly the signal circuit, requires high-speed operation of several tens of MHz. However, since the operating frequency of the peripheral circuit using the poly-Si TFT is as low as about several MHz to about 10 MHz, it is difficult to realize a high-resolution liquid crystal display device.
[0004]
Thus, as a method for realizing a high-resolution and high-definition liquid crystal display device using poly-Si TFTs, for example, a block line sequential drive method using a line sequential driver has been proposed. This system uses a line-sequential driver instead of a signal circuit that requires high-speed operation, as described in the published patent publication of Japanese Patent Application Publication No. 2000-131670. The line sequential driver can operate at a high frequency of several tens of MHz, and can output a plurality of display signals at once. In the block line sequential driving method, first, the liquid crystal display unit is divided into a plurality of blocks. The drain line of each divided block is connected to a line sequential driver via an analog switch. A block control signal corresponding to each block is input to the analog switch of each block. The analog switch selected by the block control signal is turned on, and a display signal output from the line sequential driver is supplied to the liquid crystal of the pixel portion to perform liquid crystal display. Thereby, a high-resolution and high-definition liquid crystal display device is realized using poly-Si TFT liquid crystal.
[0005]
[Problems to be solved by the invention]
The block line sequential drive method described in the prior art is a control signal for a gate side drive circuit, a block control signal, a control signal for a line sequential driver, etc. between a digital I / F as display data and a liquid crystal display device. A liquid crystal display device control IC for generating is required separately. For this reason, the number of circuit components of the liquid crystal display device increases and the cost increases. In addition, since various control signals are input to the liquid crystal display device from the outside, the number of signals input to the liquid crystal display device increases. In addition, in the liquid crystal display device, there are many intersections between the common signal line for transferring the analog output signal from the line sequential driver and the lead line to the analog switch of each block, and the lead to the common signal line and the analog switch. There is concern about yield deterioration due to short circuit with wires.
[0006]
The objective of this invention is providing the liquid crystal display device which solves said subject, and its drive method.
[0007]
Another object of the present invention is to provide a liquid crystal display device that can easily correspond to a display data, a vertical synchronization signal, a horizontal synchronization signal, an effective display period signal, and a signal composed of a dot clock, and a driving method thereof. Is to provide.
[0008]
Another object of the present invention is to make it possible for a liquid crystal display device to easily cope with a digital I / F signal, and to eliminate an external circuit such as a liquid crystal display dedicated IC that is conventionally required, It is an object to provide a liquid crystal display device that can be expected to reduce power consumption and cost, and a driving method thereof.
[0009]
Another object of the present invention is to provide a liquid crystal display device that can improve the yield due to wiring defects and the like and a driving method thereof because the number of input pins to the liquid crystal display device can be greatly reduced. is there.
[0010]
[Means for Solving the Problems]
The present invention is for solving the above-mentioned problems. As a first embodiment of the present invention, a plurality of drain lines and gate lines orthogonal to each other are formed, and a liquid crystal cell and a switching element are formed at the intersection. A liquid crystal display unit having a gate scan driving circuit that divides the liquid crystal display unit into blocks including the plurality of drain lines and sequentially scans the plurality of gate lines in the liquid crystal display unit. The included drain line is connected to a common signal line through an analog switch, and the analog switch provided in the block is turned on by a block control signal given through a block control signal line, and the on state The display signal propagated through the common signal line through the analog switch is included in the block and the analog signal is turned on. A grayscale voltage having a plurality of voltage levels and a digital I are applied to a liquid crystal display device that is applied to the drain line connected to a switch and activates a liquid crystal cell on the gate line selected by the gate scan driving circuit. The gate scan driving circuit control signal for controlling the gate scan driving circuit and the block control signal are generated from the digital I / F signal and output, and activated by the block control signal. The display signal corresponding to the display data of the block is generated and output. In addition, there is a liquid crystal display unit provided with the liquid crystal display driver, forming a plurality of drain lines and gate lines orthogonal to each other, and forming a liquid crystal cell and a switching element at the intersection thereof, Dividing into blocks including drain lines, and having a gate scan driving circuit for sequentially scanning a plurality of gate lines in the liquid crystal display unit, the drain lines included in the block are connected to a common signal line through an analog switch The analog switch provided in the block is turned on by a block control signal given through a block control signal line, and the display is propagated by a common signal line through the analog switch in the on state. A signal is applied to the drain line connected to the analog switch included in the block and turned on. In the liquid crystal display device in which the liquid crystal cell on the gate line selected by the gate scan driving circuit is activated, the gate scan driving circuit is configured to be controlled by the gate scan driving circuit control signal output from the liquid crystal display driver. The line is sequentially scanned, the display signal output from the liquid crystal display driver is output to the common signal line, and the block control signal output from the liquid crystal display driver turns on the analog switch included in the block. The display signal output from the liquid crystal display driver is applied to the drain line connected to the analog switch in the on state via the common signal line to activate each block, and the liquid crystal Display.
[0011]
In addition, as a second embodiment of the present invention, there is a liquid crystal display unit in which a plurality of drain lines and gate lines orthogonal to each other are formed, and a liquid crystal cell and a switching element are formed at the intersection, and the liquid crystal display unit Is divided into blocks each including a plurality of drain lines, and a gate scan driving circuit that sequentially scans the plurality of gate lines in the liquid crystal display unit. The drain lines included in the blocks are shared via an analog switch. The analog switch connected to the communication signal line and provided in the block is turned on by a block control signal given through a block control signal line, and is turned on by a common signal line through the analog switch in the on state. A display signal to be propagated is applied to the drain line connected to the analog switch included in the block and in the on state. A liquid crystal display driver provided in a liquid crystal display device in which a liquid crystal cell on the gate line selected by the gate scan driving circuit is activated, and inputs a gradation voltage having a plurality of voltage levels and a digital I / F signal A display of the block activated by the block control signal, which is generated and output from the digital I / F signal as a signal, and a gate scan drive circuit control signal for controlling the gate scan drive circuit and the block control signal. In a liquid crystal display driver that generates and outputs the display signal corresponding to data, when a plurality of the liquid crystal display drivers are installed, the liquid crystal display driver outputs an end timing signal at the timing when the display data is finally fetched. The liquid crystal display driver receives the end timing signal output from the preceding liquid crystal display driver. In addition, by fetching the display data, it becomes possible to fetch the display data continuously from the previous stage, and the liquid crystal display driver in the first stage receives the end timing signal of the liquid crystal display driver in the last stage, and the display The liquid crystal display driver that outputs a display signal output signal for outputting a signal and receives the display signal output signal output from the first-stage liquid crystal display driver outputs the captured display data as a display signal. And In addition, there is a liquid crystal display section in which a plurality of drain lines and gate lines orthogonal to each other are formed, and a liquid crystal cell and a switching element are formed at the intersection, and the liquid crystal display section is divided into blocks including the plurality of drain lines. And a gate scan driving circuit that sequentially scans a plurality of gate lines in the liquid crystal display unit, and the drain line included in the block is connected to a common signal line via an analog switch and provided in the block. The analog switch is turned on by a block control signal given through a block control signal line, and a display signal propagated by a common signal line through the analog switch in the on state is included in the block. Applied to the drain line connected to the analog switch that has been turned on, by the gate scan driving circuit. In the liquid crystal display device in which the liquid crystal cell on the selected gate line is activated, a plurality of the liquid crystal display drivers are installed, and the gate scan driving is performed by the gate scan driving circuit control signal output from the first stage liquid crystal display driver. A circuit sequentially scans the gate lines, outputs the display signals output from the plurality of liquid crystal display drivers to the common signal lines, and the block control signals output from the first-stage liquid crystal display drivers according to the block control signals; The analog switch included in is turned on, and the display signal output from the plurality of liquid crystal display drivers is applied to the drain line connected to the analog switch in the on state via the common signal line Then, each block is activated to perform liquid crystal display.
[0012]
In addition, as a third embodiment of the present invention, there is a liquid crystal display unit in which a plurality of drain lines and gate lines orthogonal to each other are formed, and a liquid crystal cell and a switching element are formed at the intersections. A gate scan driving circuit that divides the block into blocks including q drain lines and sequentially scans a plurality of gate lines in the liquid crystal display unit, and the drain lines included in the block are connected via an analog switch. The q analog switches connected to the common signal line and included in the block are turned on by q switch control signals given through the q switch control signal lines, respectively. In response to the switch control signal, a display signal propagated by the common signal line is applied to the nth drain line of each block, and the gate scanning driving circuit is applied. A gate for controlling the gate scan driving circuit using a grayscale voltage having a plurality of voltage levels and a digital I / F signal as input signals for a liquid crystal display device in which a liquid crystal cell on the gate line selected by A scan drive circuit control signal and the switch control signal are generated from the digital I / F signal and output, and are included in each block activated by the nth switch control signal. The display signal to be applied to the line is generated and output. Also, there is a liquid crystal display unit in which a plurality of drain lines and gate lines orthogonal to each other are formed, and a liquid crystal cell and a switching element are formed at the intersection, and the liquid crystal display unit is a block including the q drain lines A gate scan driving circuit that sequentially scans a plurality of gate lines in the liquid crystal display unit, and the drain line included in the block is connected to a common signal line via an analog switch, and is connected to the block. Each of the q analog switches included is turned on by q switch control signals supplied via q switch control signal lines, and the nth switch control signal causes the block number of each block to be turned on. The gate line selected by the gate scan driving circuit by applying a display signal propagated by a common signal line to the nth drain line In the liquid crystal display device in which the liquid crystal cell is activated, the gate scan driving circuit sequentially scans the gate lines by using the liquid crystal display driver and by the gate scan driving circuit control signal output from the liquid crystal display driver. The display signal output from the liquid crystal display driver is output to the common signal line, and the analog switch included in each block is turned on by the switch control signal output from the liquid crystal display driver. The display signal output from the liquid crystal display driver is applied via the common signal line to the drain line connected to the analog switch, and each block is activated to perform liquid crystal display.
[0013]
In the first, second, and third embodiments of the present invention, the digital I / F signal that is an input signal of the liquid crystal display driver is a vertical synchronization signal that becomes effective once per frame period. A horizontal synchronization signal that becomes valid once per horizontal period, a valid display period signal that is active only during a period in which the display data is valid, and an I / F signal that includes the display data. Features. Further, the gate scanning drive circuit, the analog switch, the switching element, and the like are configured by thin film transistors using poly-Si.
[0014]
Further, as a fourth embodiment of the present invention, a central processing unit that performs a central control, performs calculation, logic, and execution determination, and transmits signals to an input device, an output device, and a storage device; The storage device used for storing instructions and data, the input device for inputting information to the information device, the information output from the inside of the information device to the outside, and the digital I / F for display The information device provided with the liquid crystal display device constituted by the output device for outputting a signal is the liquid crystal display device according to the first, second, or third embodiment of the present invention.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0016]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device 101 according to the first embodiment of the present invention. The configuration of the liquid crystal display device according to the first embodiment of the present invention will be described below.
[0017]
Each liquid crystal cell 102 in FIG. 1 includes a liquid crystal 103, a storage capacitor 104, and a switching element 105. The switching element is, for example, an N-type MOS transistor using a poly-Si TFT. In addition, a P-type MOS transistor using a poly-Si TFT, an N-type MOS transistor using amorphous Si, or A pMOS transistor may be used. In the switching element 105, the gate electrode is connected to the gate scanning line G common to the horizontal liquid crystal cell, the drain electrode is connected to the common drain line in the vertical direction, and the source electrode is connected via the liquid crystal 103. It is connected to a common electrode common to all pixels on the opposite side.
[0018]
A gate line selection signal output from the gate scanning drive circuit 106 is applied to the gate scanning line G. The gate scanning driving circuit is controlled by a gate scanning driving circuit control signal 113 output from the liquid crystal display driver, and sequentially applies a gate scanning line selection signal to each gate scanning line. In the description of the first embodiment of the present invention, the number of liquid crystal cells in the liquid crystal display unit is assumed to be m × n, so that there are n gate scanning lines. Here, the gate scanning drive circuit 106 is formed on the same substrate as the liquid crystal display unit, and this circuit is composed of a single nMOS transistor, a single pMOS transistor, or a CMOS transistor.
[0019]
For example, an arbitrary voltage level generated and output by the liquid crystal display driver 107 is applied to the common electrode. However, the voltage applied to the common electrode may be an arbitrary voltage waveform generated by an external power supply circuit.
[0020]
On the other hand, the liquid crystal display driver 107 is mounted on the same substrate on which the liquid crystal display unit is formed by a technique such as COG (chip on glass) or TAB. A digital I / F signal 110 and a gradation reference voltage 111 are input to the liquid crystal display driver 107. The digital I / F signal 110 includes, for example, a vertical synchronization signal Vsync that is valid once per frame, a horizontal synchronization signal Hsync that is valid once per horizontal scanning period, and a period during which display data is valid during the horizontal period. These are an effective display period signal Disp that becomes HI level, a synchronization signal composed of a dot clock, and display data Data. In addition, there is a signal such as LVDS as the digital I / F signal 110, but it is necessary to incorporate an LVDS receiver into the liquid crystal display driver 107. The gradation reference voltage 111 is composed of a plurality of voltage levels. The liquid crystal display driver 107 applies an analog signal voltage corresponding to p pieces of display data based on the digital I / F signal 110 and the gradation reference voltage 111 to the analog signal voltage common line 109 (D1, D2,..., Dp). Output to. The drain lines dr of the liquid crystal display device 101 are divided into p display blocks BLCK1, BLCK2,..., BLCKq, and the first to pth drain lines of each BLCK are analog sampling switches 108, respectively. Are connected to analog signal voltage common lines D1, D2,..., Dp via (sw1, sw2,..., Swp). The analog sampling switch of each BLCK is controlled to be turned on / off by a block control signal 112 (BL1, BL2,..., BLq) output from the liquid crystal display driver 107. For example, when the block control signal BL becomes Hi level, all analog sampling switches of a certain BLCK are turned on, and the analog signal voltage output from the liquid crystal display driver 107 is supplied to p drain lines via the analog signal voltage common line. Apply. When the block control signal BL becomes LOW level, the analog sampling switch is turned off, and the drain line and the analog signal voltage common line are cut off.
[0021]
When the number m of drain lines is not divisible by the number p of analog signal voltage output pins of the liquid crystal display driver 107, for example, the last BLCKq is a block having p or less drain lines. Basically, the number of drain lines dr of each BLCK may be equal to or less than the number of output pins p of the analog signal voltage line of the liquid crystal display driver.
[0022]
Next, the operation of the gate scan driving circuit 106 will be described with reference to FIGS. FIG. 2 is a timing chart for explaining the operation of the gate scan driving circuit. FIG. 3 is a block diagram illustrating the structure of the gate scan driving circuit 106.
[0023]
First, the configuration of the gate scan driving circuit will be described with reference to FIG. 301 is a shift register control signal, and 302 is a gate scanning line selection period control signal. Both the control signals 301 and 302 are included in the gate scanning drive circuit control signal 113. Reference numeral 303 denotes a shift register having n stages. 304, 305, 306, and 307 are AND circuits. The shift register 303 outputs output signals out1, out2,..., Outn shifted by one horizontal period in response to the shift register control signal 301. Each AND circuit is set to Hi level only for a period determined by the gate scanning line selection period control signal 302 based on the output signal of the shift register, and outputs it to each gate scanning line.
[0024]
Next, this operation will be described with reference to the timing chart of the gate scanning drive circuit in FIG. The liquid crystal display driver selects a start signal VST, a clock signal VCLK (horizontal cycle), and a gate scanning line G, which are shift register control signals 301, from Hsync, Vsync, Disp, and dot clocks, which are digital I / F signals. A gate scanning line selection period control signal 302 (VOE) for determining time is generated and output. The shift register 303 transfers the output signal shifted by one horizontal cycle from the start signal VST to the AND circuits 304, 305, 306, and 307. In the AND circuit, Hi level signals Gs1, Gs2,..., Gsn are sequentially applied to the gate scanning lines only for a period determined by the gate scanning line selection period control signal. Here, when the gate scanning line selection signal Gs is at a Hi level, for example, the switching element of the liquid crystal cell connected to the gate scanning line is turned on, and the analog signal voltage applied to the drain line is applied to the liquid crystal. Will be done. On the other hand, when the gate scanning line selection signal is at the LOW level, the switching element is turned off, and the liquid crystal cell holds the applied analog signal voltage. Therefore, by sequentially selecting the gate scanning lines G1 to Gn, it is possible to perform liquid crystal display for one frame.
[0025]
Next, the operation of the liquid crystal display driver 107 will be described with reference to FIGS. FIG. 4 is a block diagram of the liquid crystal display driver 107. FIG. 5 is an operation timing chart of the liquid crystal display driver 107.
[0026]
First, the configuration of the liquid crystal display driver 107 will be described with reference to the block diagram of the liquid crystal display driver 107 in FIG. 111 is a gradation reference voltage, 401 is a synchronization signal of the digital I / F signal 110, and 402 is display data of the digital I / F signal 110. The synchronization signal 401 of the digital I / F signal is Vsync, Hsync, Disp, and dot clock CK. Reference numeral 403 denotes a control signal generation circuit that generates a gate scanning drive circuit control signal 113 and a block control signal 112. The control signal generation circuit 403 includes a start signal 413 (ST_CK) of the shift register 404, an enable signal 414 (A_ENA) of the latch circuit 405, an enable signal 415 (B_ENA) of the latch circuit 406, and a selection signal 416 ( SEL), the final latch circuit 409, the decoder / analog voltage selection circuit 411, and the final latch signal 417 (LATCH) of the analog signal voltage output circuit 412 are generated. Reference numeral 407 denotes a latch circuit, and reference numeral 410 denotes a gradation voltage generation circuit that generates a gradation voltage from the gradation reference voltage 111. The shift register 404, latch circuits 405, 406, 407, selection circuit 408, final stage latch circuit 409, decoder / analog voltage selection circuit 411, and analog voltage output circuit 412 operate in synchronization with the dot clock included in the synchronization signal 401. .
[0027]
Next, the operation of the liquid crystal display driver 107 will be described with reference to the timing chart of FIG. In FIG. 5, Data is display data 402, and CK is a dot clock. S1 to Sp are output signals of each stage of the shift register 404, A1 to Ak are output signals of each stage of the latch circuit 405, B1 to Bk are output signals of the latch circuit 406, and Ck + 1 to Cp are Output signals of the latch circuit 407, L1 to Lp are output signals of the final stage latch circuit, and Y1 to Yp are output signals of the analog signal voltage output circuit 412.
[0028]
In FIG. 4, the shift register 404 outputs the latch timing signal S to the latch circuits 405, 406, and 407 from the timing next to the timing when the start signal ST_CK is Hi. Each of the latch circuits 405 and 406 is composed of k stages of latch circuits. k is smaller than the number of output pins p of the analog signal voltage of the liquid crystal display driver 107. These latch circuits 405 and 406 latch the display data 402 when the enable signals A_ENA and B_ENA are at the Hi level, respectively. Therefore, as shown in FIG. 5, the latch circuit 405 latches display data in BLCK1, BLCK3,..., And the latch circuit 406 latches display data in BLCK2, BLCK4,. Therefore, for example, the first to kth display data in the odd-numbered block is latched by the latch circuit 405, and the first to nth display data in the even-numbered block is latched by the latch circuit 406. The latch circuit 407 latches display data from the (k + 1) th to the pth in each BLCK. The latch circuit 407 is configured by a pk-stage latch circuit. Consider a case where all p Data of BLCK1 are latched and the display data of BLCK1 is latched in the final stage latch circuit 409. Since the enable signal A_ENA is at the LOW level, the latch circuit 405 holds the first to kth data of BLCK1. On the other hand, since the enable signal B_ENA is at the Hi level, the latch circuit 406 latches the 1st to kth Data of BLCK2. When the final latch signal 417 becomes Hi level, the final latch circuit 409 latches the display data of BLCK1. At this time, the selection circuit 408 outputs the output of the latch circuit 405 to the final latch circuit 409 because the selection signal SEL is at the Hi level. (The selection circuit 408 selectively outputs the output of the latch circuit 405 when the selection signal SEL is at the Hi level, and selectively outputs the output of the latch circuit 406 when the selection signal SEL is at the LOW level.) The display latched by the final latch circuit 409 The data is output to the decoder / analog voltage selection circuit 411. The decoder / analog voltage selection circuit selects one analog signal voltage level corresponding to the display data from the plurality of analog signal voltage levels generated by the gradation voltage generation circuit, and outputs the analog signal voltage output circuit 412 to the analog signal voltage output circuit 412. The analog signal voltage output circuit buffers the analog signal voltage and outputs an analog signal voltage corresponding to the display data of BLCK1 to the analog signal voltage common line 109 (D1, D2,..., Dp). Next, when the last stage latch circuit 409 latches the display data of BLCK2, the A_ENA signal becomes Hi level, the latch circuit 405 latches the 1st to kth display data of BLCK3, and the latch circuit 406 receives the B_ENA signal. Becomes the LOW level, and the display data is held. Since the selection signal SEL is at the LOW level, the selection circuit 408 outputs the output of the latch circuit 406 to the final-stage latch circuit 409. Therefore, the final latch circuit 409 latches the display data of BLCK2 latched by the latch circuit 406 and the latch circuit 407 at the timing when the final latch signal LATCH is Hi. In the meantime, the latch circuit 405 latches display data from the first of BLCK3. By repeating the above operation, even when display data for one horizontal line is input to the liquid crystal display driver 107, it is possible to output the analog signal voltage AD corresponding to each BLCK to the analog signal voltage common line 109. Become.
[0029]
Next, the operation of the liquid crystal display device 101 will be described with reference to the timing chart of FIG. Vsync, Hsync, Disp, and Data shown in the timing chart of FIG. 6 are digital I / F signals 110.
[0030]
The liquid crystal display driver 107 latches p display data from Data1 to Datap, and after latching the final data Datap of BLCK1, the analog signal voltage common line 109 (D1, D2, D3,..., Dp ), Analog signal voltages AD (1), AD (2), AD (3),..., AD (p) are output. Here, at time Tb, the final stage latch circuit 409 in FIG. 4 latches the display data, the analog signal voltage level is selected by the decoder / analog voltage selection circuit 411, and the analog signal voltage output circuit 412 stabilizes the analog signal voltage. This is the time required to output AD. On the other hand, the control signal generation circuit 403 included in the liquid crystal display driver 107 sequentially outputs the block control signal BL to each block control signal line 112. When each block control signal BL is at Hi level, the analog sampling switch 108 of each block is turned on, and the analog signal voltage AD applied to the analog signal voltage common line 109 is applied to the drain line dr of each corresponding block. Is done. Therefore, during the period when the analog signal voltage of BLCK1 is output, only the block control signal BL1 is at the Hi level, and the analog signal voltage is applied to the drain line of BLCK1. Here, the block control signal BL is set to the LOW level earlier than the end of the analog signal voltage output of the liquid crystal display driver 107 by the time Ta, and the writing of the analog signal voltage to the drain line dr is confirmed. As described above, when the block control signal BL2 is at the Hi level, an analog signal voltage corresponding to BLCK2 is output, and when the block control signal BL3 is at the Hi level, an analog signal corresponding to BLCK3 is output sequentially. As a result, an analog signal voltage can be applied to each of the BLCKs divided into q pieces. At this time, as described above, the gate scanning line selection signal is applied to the first gate scanning line by the gate scanning driving circuit, and the analog signal voltage corresponding to the display data is applied to the liquid crystal cells on the first gate scanning line. This operation is sequentially repeated from the first gate scanning line to the nth gate scanning line, thereby enabling one frame of liquid crystal display.
[0031]
Here, the gate scan driving circuit 106 sets the block control signal to the Hi level and applies the analog signal voltage to the drain line dr Tb after the gate line G is selected. This is a condition in which distortion of the gate selection voltage due to a load or the like is taken into consideration and it is assumed that the rise of the gate selection voltage requires only time Tb. Further, it takes time Tc from the time when the block control signal BLq of BLCKq which is the last block becomes LOW level until the gate scanning line G becomes non-selected. This is the time provided for sufficiently applying the analog signal voltage.
[0032]
As described above, by using the liquid crystal display driver 107 incorporating the control signal generation circuit and using the block line sequential driving method, the signal 110 input to the liquid crystal display device 101 is converted into a digital I / F signal, for example, a display A signal composed of data, a vertical synchronization signal, a horizontal synchronization signal, an effective display period signal, and a dot clock can be obtained. As a result, it is possible to easily cope with a digital I / F signal without using a conventionally dedicated liquid crystal display IC. In addition, since there is no need to input control signals such as line sequential driver control signals, gate scanning drive circuit control signals, and block control signals from the outside to the liquid crystal display device, the number of input pins of the liquid crystal display device is reduced. In addition, it is possible to improve the yield due to wiring defects and reduce power consumption. Further, since the number of external peripheral circuits for generating control signals can be reduced, cost reduction can be expected.
[0033]
Further, in the first embodiment of the present invention, control signals such as the gate scanning drive circuit control signal 113 and the block control signal 112 output from the liquid crystal display driver 107 are drawn from only one side of the liquid crystal display driver 107. These control signals are output from both ends of the liquid crystal display driver 107, and the shift register 404 included in the liquid crystal display driver 107 can be shifted in both forward and reverse directions. It becomes possible.
[0034]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
[0035]
In the second embodiment of the present invention, in a high-definition liquid crystal display device (having a large number of display pixels), a plurality of liquid crystal display drivers are used, and a block line sequential driving method is performed without using a liquid crystal display dedicated IC. It is a method. As an idea, as shown in the block diagram of the liquid crystal display device according to the second embodiment of the present invention shown in FIG. 7, for example, by connecting two liquid crystal display drivers 701 and 702, an analog output at one time In this system, the number of output signal voltages is increased and the number of blocks is decreased, thereby increasing the voltage writing time in each block and performing a block line sequential drive system in a high-definition liquid crystal display device.
[0036]
Therefore, in the liquid crystal display device 708 shown in FIG. 7, for example, when two liquid crystal display drivers are used, the number of analog signal voltage outputs is p × 2 = 2p, and each display block BLCK has 2p drain lines. It is divided into. Therefore, compared to the number of blocks when only one liquid crystal display driver 701 is used, the number of blocks when two are used is halved. The analog sampling switch 108 connected to the drain line of each block is turned on by the block control signal (BL) 112 output from the liquid crystal display driver 701 when BL1 is Hi. When the analog sampling switch 108 is turned on, the analog signal voltage is written from the liquid crystal display drivers 701 and 702 through the analog signal voltage common line 109 from the first drain line dr1 to the 2p-th drain line dr2p of BLCK1. . Accordingly, the block control signals BL1, BL2,..., BLq are sequentially selected, the analog sampling switches 108 of each BLCK are sequentially turned on, and the analog signal voltages output from the liquid crystal display drivers 701 and 702 are applied to the drain lines of each BLCK. By doing so, an analog signal voltage corresponding to display data for one horizontal line can be applied to each drain line. On the other hand, the gate scanning drive circuit 106 included in the liquid crystal display device 708 is the same as that described with reference to FIGS. 2 and 3 in the first embodiment of the present invention, and the operation is also the same. Omitted. Therefore, the liquid crystal display is performed by applying the analog signal voltage to the liquid crystal cells on the gate scanning line G selected by the gate scanning driving circuit 106 in block line order.
[0037]
The operation of the liquid crystal display driver in the second embodiment of the present invention will be described with reference to FIG. 7, FIG. 8, and FIG. FIG. 8 is a block diagram of the liquid crystal display drivers 701 and 702 included in the liquid crystal display device 708 of FIG. FIG. 9 is a timing chart of the liquid crystal display device 708.
[0038]
In FIG. 8, reference numeral 110 denotes a digital I / F signal input to the liquid crystal display driver. Reference numeral 111 denotes a gradation reference voltage, and the gradation voltage generation circuit 410 generates a plurality of levels of analog signal voltages corresponding to display data based on the reference voltage. Reference numeral 804 denotes a control signal generation circuit, which receives a gate scan driving circuit control signal 113 from a latch start signal (EIO1) 801, a latch signal (ALL_LA) 802, a block latch end signal 803, and a digital I / F signal 110. A block control signal 112, a simultaneous latch signal 805, a shift register start signal 807, latch enable signals 808 and 809, a selection signal 810, and a final latch signal 811 are generated and output. Reference numeral 404 denotes a shift register, which outputs a latch timing signal to the latch circuits 405, 406, and 407 in response to a shift register start signal. The shift register outputs a shift register end signal (EIO2) 806. The latch circuit 405, latch circuit 406, latch circuit 407, voltage selection circuit 408, final latch circuit 409, decoder / analog signal voltage selection circuit 411, and analog signal voltage output circuit 412 in the first embodiment of the present invention Since the operation is the same as that of the circuit shown in FIG.
[0039]
In the liquid crystal display device 708 shown in FIG. 7, the liquid crystal display drivers 701 and 702 are connected in the following manner. First, the shift register end signal (EIO2_1) 806 of the first-stage liquid crystal display driver 701 is input to the latch start signal (EIO1_2) 801 of the next-stage liquid crystal display driver 702. The liquid crystal display driver 702 at the next stage outputs a shift register start signal 807 after the signal is input to the latch start signal (EIO1_2) 801, and the latch circuit starts to latch data. Therefore, in the liquid crystal display device 708 of FIG. 7, the liquid crystal display driver 701 latches the first to p-th display data of each BLCK, and the next-stage liquid crystal display driver 702 displays the (p + 1) -th display data of each block. Therefore, the second p-th display data is latched. In this manner, by inputting the shift register end signal (EIO2) 806 to the latch start signal (EIO1) 801 of the next stage liquid crystal display driver, a plurality of stages of liquid crystal display drivers can be connected.
[0040]
On the other hand, the shift register end signal (EIO1) of the last-stage liquid crystal display driver 702 is input to the block latch end signal 803 of the first-stage liquid crystal display driver 701. The control signal generation circuit 804 generates a simultaneous latch signal 805 from the block latch end signal 803 and inputs it to the latch signal 802 (ALL_LA) of the liquid crystal display driver 702 located in the subsequent stage. At the same time, the shift register start signal 807 is generated, and the first-stage liquid crystal display driver 701 starts to latch the display data of the next block. The control signal generation circuit 804 of the liquid crystal display driver 702 at the subsequent stage receives the latch signal 802, generates the final latch signal 811, converts the display data held by the latch circuit into an analog signal voltage, and converts the analog signal voltage. Output to the common line 109. Further, the control signal generation circuit 804 included in the first-stage liquid crystal display driver 701 generates the final latch signal 811 so that the timing at which the subsequent-stage liquid crystal display driver 702 outputs the analog signal voltage is the same, and the analog signal voltage Is output to the analog signal voltage common line 109.
[0041]
FIG. 9 shows the operation of the liquid crystal display drivers 701 and 702 shown in FIG. 7 described above and the operation of the liquid crystal display device 708 using a timing chart. Among the signals shown in FIG. 9, Vsync is a vertical synchronization signal, Hsync is a horizontal synchronization signal, Disp is an effective display period signal, Data is display data, and both are digital I / F signals 110. included.
[0042]
First, the first-stage liquid crystal display driver 701 latches display data (1 to p) in the first half of the first block. The first-stage liquid crystal display driver 701 inputs a shift register end signal (EIO2_1) 806 to the latch start signal 801 of the next-stage liquid crystal display driver 702 near the timing at which the p-th display data is latched. As a result, the next-stage liquid crystal display driver 702 latches the display data (p + 1 to 2p) in the second half of BLCK1. At the timing when the final stage liquid crystal display driver 702 latches the final display data in BLCK1, a shift register end signal (EIO2_2) 806 is output and input to the block latch end signal of the first stage liquid crystal display driver 701. As a result, the first-stage liquid crystal display driver 701 generates a simultaneous latch signal 805 and inputs it to the latch signal 802 (ALL_LA) of each liquid crystal display driver. As a result, an analog signal voltage corresponding to BLCK1 is output from a plurality of liquid crystal display drivers. In this case, the first-stage liquid crystal display driver 701 uses analog signals corresponding to the first to pth display data. The signal voltage AD (1 to p) is output and applied to the analog signal voltage common lines D1 to Dp. The next-stage liquid crystal display driver 702 applies the analog signal voltage AD (p + 1 to 2p) corresponding to the display data from the (p + 1) th to the 2nd p to the analog signal voltage common lines Dp + 1 to D2p. During a period in which the liquid crystal display drivers 701 and 702 output AD (2p) from the analog signal voltage AD (1) corresponding to BLCK1, the liquid crystal display driver 701 sets the block control signal BL1 to the Hi level and applies to the drain line of BLCK1. Write analog signal voltage. The liquid crystal display driver sequentially outputs an analog signal voltage corresponding to BLCK selected by the block control signal BL, and by repeating this, the analog signal voltage corresponding to the display data is written to all the drain lines. Therefore, by applying the gate scanning line selection signal to the gate scanning line corresponding to the horizontal line of the analog signal voltage output from the liquid crystal display driver, the analog signal voltage corresponding to the display data is applied to the liquid crystal cell on the gate scanning line. It can be applied. Further, by sequentially applying a gate scanning line selection signal to the gate scanning lines, it is possible to display a liquid crystal for one frame. Here, the timing restrictions of the block control signal (BL) and the gate selection signal G shown in FIG. 9 are omitted because they are described in the first embodiment of the present invention.
[0043]
As described above, when a plurality of liquid crystal display drivers 701 are used to display a high-definition liquid crystal display device (having many display pixels) by the block line sequential driving method, the number of blocks is not increased. It is possible to take sufficient time to write the analog signal voltage to the corresponding drain line, and to realize high definition and high image quality display. Further, by using the liquid crystal display driver 701 having a built-in control signal generation circuit used in the second embodiment of the present invention, it is possible to easily cope with a digital I / F signal without producing a liquid crystal display dedicated IC. It becomes possible to make it. Further, the liquid crystal display driver 701 can generate control signals for each circuit included in the liquid crystal display device 701, and the number of input pins of the liquid crystal display device is reduced. As a result, the number of external circuits can be reduced and cost reduction can be expected. Furthermore, the power consumption can be reduced and the yield due to wiring defects can be improved.
[0044]
In the second embodiment of the present invention, control signals such as the gate scanning drive circuit control signal 113 and the block control signal 112 output from the liquid crystal display driver 701 are drawn from only one side of the liquid crystal display driver. These control signals are output from both ends of the liquid crystal display driver, and the shift register 404 included in the liquid crystal display driver can be shifted in both forward and reverse directions, thereby enabling various arrangements for the liquid crystal display device 708. Become. In this case, if the function of exchanging the pin positions of the latch start signal 801 and the shift register end signal 806 depending on the shift direction of the shift register 404 is provided, the expandability is further improved.
[0045]
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. 10, 11, and 12. FIG.
[0046]
FIG. 10 shows a configuration of a liquid crystal display device according to the third embodiment of the present invention. FIG. 11 is a block diagram of a liquid crystal display driver used in the liquid crystal display device according to the third embodiment of the present invention. FIG. 12 is a timing chart for explaining the operation of the liquid crystal display device according to the third embodiment of the present invention.
[0047]
As shown in FIG. 10, the liquid crystal display device 1001 according to the third embodiment of the present invention includes a liquid crystal display driver 1002, a gate scanning drive circuit 106, an analog sampling switch group 1003, and a liquid crystal cell 102. The configuration of the liquid crystal display device 1001 will be described below.
[0048]
The gate scan drive circuit 106 receives the gate scan drive circuit control signal 113 output from the liquid crystal display driver 1002 and applies the selection voltage to the gate scan line G sequentially every horizontal period. Since the operation of the gate scanning drive circuit 106 and the gate scanning drive circuit control signal 113 have been described in FIGS. 2 and 3 which are the first embodiment of the present invention, description thereof is omitted here.
[0049]
In the liquid crystal display device 1001 according to the third embodiment of the present invention, q drain lines dr are divided into p BLCKs as one block (BLCK). Therefore, when the total number of drain lines is m, the relationship of p × q = m is established. The number of analog signal voltages output from the liquid crystal display driver 1002 is p. The output of the analog signal voltage of the liquid crystal display driver 1002 is applied to the analog signal voltage common lines D1 to Dp. These analog voltage signal common lines D are connected to q drain lines dr included in each block via sw1, sw2,..., Swq included in the analog sampling switch group 1003.
[0050]
Each switch sw included in the analog sampling switch group 1003 is controlled by a block control signal 112 (BL) output from the liquid crystal display driver 1002. For example, each sw is in an on state when the block control signal BL is at a high level. An analog signal voltage output from the liquid crystal display driver 1002 is applied from the analog signal voltage common line D to the drain line dr. Here, when the block control signal BL1 becomes Hi, sw1 of each BLCK is turned on, and the analog signal voltage is applied to the first drain line dr of each BLCK via the analog signal voltage common line 109. Applied. Therefore, the block control signals BL1 to BLq are time-divided during one horizontal period and sequentially set to the Hi level, so that the analog signals are sequentially generated from the first drain line dr1 to the qth drain line drq of each BLCK. A voltage can be applied.
[0051]
Next, the configuration and operation of the liquid crystal display driver 1002 will be described using the block diagram of the liquid crystal display driver 1002 shown in FIG. Reference numeral 111 denotes a gradation reference voltage input from the outside to the liquid crystal display device 1001. Reference numeral 1101 denotes display data, and reference numeral 1102 denotes a synchronizing signal group including a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, an effective display period signal Disp, and a dot clock. Signals 1101 and 1102 are both digital I / F signals input to the liquid crystal display device 1001 from the outside. A control signal generation circuit 1103 generates various control signals from the synchronization signal 1102. Reference numerals 1104 and 1105 denote memories that store effective display data for one horizontal period. Reference numerals 1106 and 1107 denote address signals of the memories 1104 and 1105, respectively. Reference numerals 1112 and 1113 denote memory control signals for controlling reading and writing of the memories 1104 and 1105, respectively. A display data signal 1108 is read from one of the memories 1104 and 1105. Reference numeral 1109 denotes a shift register, which is constituted by a p-stage shift register when the liquid crystal display driver 1002 outputs p analog signal voltages. Reference numeral 1111 denotes a latch circuit capable of latching display data for p drain lines. Reference numeral 1110 denotes a start signal for the shift register 1109. The following circuits, which are the final latch circuit 409, the final latch signal 409, the decoder / analog signal voltage selection circuit 411, the analog signal voltage output circuit 412, the final latch signal 417, and the gradation voltage generation circuit 410, are described in the present invention. Since it is the same as that of FIG. 4 which is the first embodiment, a description thereof will be omitted, and the circuit operation of the liquid crystal display driver 1002 before this will be described.
[0052]
The memories 1104 and 1105 are controlled by a memory control signal 1112 and 1113 so that one is in a read state and the other is in a write state during one horizontal period, and the state is switched every horizontal period. Accordingly, when display data of the first horizontal line is transferred, for example, the memory 1104 is controlled to be in a write state, and the memory 1105 is controlled to be in a read state. Therefore, the display data transferred in the first horizontal line period is written in the memory 1104. In the second horizontal line period, the memory 1104 is in the read state and the memory 1105 is in the write state, so that the display data of the second horizontal line is written into the memory 1105. In the meantime, the memory 1104 reads the display data so as to correspond to the order of the output pins of the analog signal voltage by the address signal 1106 and the memory control signal 1112, and transfers it to the latch circuit 1111. For example, when outputting an analog signal voltage to be applied to the first drain line of each BLCK at the next analog signal voltage output timing, the display data is read in the order of first, q + 1, 2q + 1,..., M−q + 1. To do. Further, at the next timing, reading is performed in the order of second, q + 2,..., M−q + 2. The display data 1108 read in this manner is sequentially latched by the latch circuit 1111. At the timing when display data of q analog signal voltages is latched in the latch circuit 1111, the final latch signal 417 becomes active, and the analog signal output circuit 412 outputs the analog signal voltage to the analog signal voltage common line 109. By repeating the above operation, analog signal voltages corresponding to the drain line dr selected by the block control signal 113 can be sequentially output.
[0053]
The operation of the liquid crystal display device 1001 will be described below using the timing chart shown in FIG. Vsync, Hsync, Disp, and Data shown in FIG. 12 are a vertical synchronization signal, a horizontal synchronization signal, an effective display period signal, and display data, respectively, and are input to the liquid crystal display driver 1002. In the period in which the display data of the first line is transferred, one of the two memories 1104 and 1105 included in the liquid crystal display driver 1002 stores Data that is the display data of the first line. During the period in which the display data of the next second line is transferred, the operations of the two memories 1104 and 1105 are switched, and one memory storing the display data of the first line performs a read operation, and the other memory Stores the display data of the second line. In addition, the liquid crystal display driver 1002 applies analog signal voltages to the first, second,..., Qth drain lines dr included in each BLCK in order, so that the analog sampling switches sw1, The block control signals BL1, BL2,..., BLq are sequentially applied to the sw2,..., swq, and the analog sampling switch sw is turned on only during the high level period of the block control signal BL. When the liquid crystal display driver 1002 applies the Hi level of the block control signal BL1 to the analog sampling switch sw1, the analog voltage common lines D1, D2,..., Dp and the blocks BLCK1, BLCK2,. A first drain line is connected. During the period in which the sw1 is in the on state, the liquid crystal display driver 1002 analogizes the analog signal voltages AD (1), AD (q + 1),..., AD (m−q + 1) corresponding to the first drain line of each block. Apply to the signal voltage common lines D1, D2,..., Dp, respectively, and write an analog signal voltage corresponding to the display data to the first drain line of each BLCK. However, the block control signal becomes the LOW level earlier by the time Ta than the timing when the output of the analog signal voltage is finished, and the voltage of each drain line is determined. By repeating this operation sequentially from BL1 to BLq, the analog signal voltage corresponding to the display data can be written to all the drain lines dr. Further, the gate scanning drive circuit 106 sequentially outputs a gate scanning line selection signal to each gate scanning line G according to a gate scanning drive circuit control signal 113 output from the liquid crystal display driver 1002. In this case, for example, when the gate scanning line selection signal is at the Hi level, the switching element 105 of each liquid crystal cell 102 is turned on, and an analog signal voltage is applied to the liquid crystal. The gate scanning line selection signal becomes Hi level earlier by the time Tb than the timing when the first block control signal BL1 becomes Hi level. This is because the rise of the gate scanning line G is taken into consideration, and the analog signal voltage is applied while the gate voltage of the gate scanning line G is sufficiently raised. Further, the gate scanning line selection signal becomes the LOW level after a time Tc after the final block control signal BLq becomes the LOW level. This is necessary in order to write the analog signal voltage to the qth drain line of each BLCK in the high level period of the final block control signal BLq and to sufficiently write the analog signal voltage to the liquid crystal via the switching element 105. It ’s a great time. By repeating the above operation, it is possible to perform liquid crystal display for one frame.
[0054]
As described above, the liquid crystal display driver 1002 having at least two memories capable of storing display data of one horizontal line is used, and each analog signal voltage line D of the liquid crystal display driver is connected to each BLCK as shown in FIG. By performing time-division driving in response to the drain line, the intersection of the analog signal voltage common line and the lead-out line to the analog sampling switch sw can be drastically reduced. It can be greatly improved. Further, by using the liquid crystal display driver 1002, it is possible to easily cope with a digital I / F signal without manufacturing a liquid crystal display dedicated IC. Further, the liquid crystal display driver 1002 can generate control signals for each circuit included in the liquid crystal display device 1001, and the number of input pins of the liquid crystal display device is reduced. As a result, the number of external circuits can be reduced and cost reduction can be expected. Furthermore, the power consumption can be reduced and the yield due to wiring defects can be improved. Further, the liquid crystal display driver 1002 includes a latch start signal (EIO1) 801, a latch signal (ALL_LA) 802, a block latch end signal 803, and a simultaneous latch signal as in the liquid crystal display driver 701 used in the second embodiment of the present invention. By providing the function of 805 and shift register end signal (EIO2) 806, it becomes possible to connect a plurality of stages of liquid crystal display drivers 1002, and when a high-definition (many display pixels) liquid crystal display device is time-divisionally displayed. In addition, it is possible to take a sufficient time for one writing, and it is possible to realize high definition and high image quality display.
[0055]
In the third embodiment of the present invention, control signals such as the gate scanning drive circuit control signal 113 and the block control signal 112 output from the liquid crystal display driver 1002 are drawn from only one side of the liquid crystal display driver. These control signals are output from both ends of the liquid crystal display driver, and the shift register 1109 included in the liquid crystal display driver can be shifted in both forward and reverse directions, thereby enabling various arrangements with respect to the liquid crystal display device 1001. Become.
[0056]
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
[0057]
The fourth embodiment of the present invention is an information device provided with a liquid crystal display device that does not require a liquid crystal display-dedicated IC described in the first to third embodiments of the present invention. The information device according to the fourth embodiment of the present invention is, for example, a computer, as shown in the block diagram of the information device including the liquid crystal display device according to the fourth embodiment of the present invention shown in FIG. The main components of the information device 1301 are a liquid crystal display device 1302, a central processing unit 1303, an input device 1304, a storage device 1305, an output device 1306, and a power supply circuit 1307.
[0058]
The central processing unit 1303 serves as a central control and performs calculation, logic, and execution decisions. In addition, signals are transmitted between the input device, the output device, and the storage device. The storage device 1305 is used for storing instructions and data. The input device 1304 is where information is input to the information device, and the input information may be data or a program. The output device 1306 outputs information from the inside of the information device to the outside world, and writes the information to a printer or stores it in an auxiliary storage device such as a magnetic tape or a magnetic disk. Further, the output device 1406 outputs a digital I / F signal of the display device. For example, the display data signal and a horizontal synchronization signal that becomes effective once in one horizontal period, once in one frame period. A signal including a vertical synchronizing signal, a clock signal, a display timing signal indicating a range of effective display data, and the like which are valid at a rate of 1 is output to the liquid crystal display device 1302 which is a display device. The power supply circuit 1307 supplies power to the liquid crystal display device 1302 and other components that require the power supply of the information device 1301. The power supply circuit 1307 generates and outputs a gradation reference voltage required by the liquid crystal display device 1302.
[0059]
By using the liquid crystal display device 1302 described in the first to third embodiments of the present invention, the digital I / F signal output from the output device 1306 is simply input to the liquid crystal display device 1302 as it is. Thus, it is possible to perform display, and it is possible to delete the liquid crystal display dedicated IC which has been conventionally required. As a result, the number of circuits in the information device is reduced, and power consumption can be reduced. In addition, as a result of the reduction in the number of circuits, it is possible to realize a low-cost information device.
[0060]
As described above, according to the fourth embodiment of the present invention, the display device of the information equipment includes the liquid crystal display device described in the first embodiment of the present invention to the third embodiment of the present invention. The liquid crystal display device can be easily adapted to a digital I / F signal, and low power consumption of information equipment can be realized. Therefore, it can be considered that a large effect can be obtained by applying to a portable information terminal device such as a notebook personal computer or an electronic notebook which further requires lower power consumption among information devices.
[0061]
【The invention's effect】
In a liquid crystal display device equipped with a liquid crystal display driver and using a block line sequential drive system,
By generating a control signal of each circuit such as a gate scanning drive circuit and an analog sampling switch included in the liquid crystal display device in a control signal generation circuit inside the liquid crystal display driver, a signal input to the liquid crystal display device is converted into a digital I / F signals, for example, display data, vertical synchronization signals, horizontal synchronization signals, effective display period signals, and signals composed of dot clocks can be easily handled. In addition, since the liquid crystal display device can be easily adapted to the digital I / F signal, it is possible to delete the external circuit such as a liquid crystal display dedicated IC which has been conventionally required, thereby reducing the power consumption and the power consumption. Cost can be expected. In addition, since the number of input pins to the liquid crystal display device can be greatly reduced, an improvement in yield due to wiring defects can be expected.
[0062]
In addition, by providing a plurality of liquid crystal display drivers in the liquid crystal display device, it is possible to lengthen one writing time in the block line sequential drive method or the time-division drive method. However, it is possible to realize a high-quality display.
[0063]
In addition, by providing a memory in the liquid crystal display driver, it is possible to greatly reduce the intersection of the analog signal voltage common line in the liquid crystal display device and the leader line from the analog signal voltage common line to the analog sampling switch. Become. Thereby, it can be expected that the yield due to a short circuit between the wirings is greatly improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the gate scan driving circuit according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a gate scan driving circuit according to the first embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a liquid crystal display driver according to the first embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of the liquid crystal display driver according to the first embodiment of the present invention.
FIG. 6 is a timing chart showing a driving method of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 7 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a liquid crystal display driver according to a second embodiment of the present invention.
FIG. 9 is a timing chart showing a driving method of the liquid crystal display device according to the second embodiment of the present invention.
FIG. 10 is a diagram showing a configuration of a liquid crystal display device according to a third embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a liquid crystal display driver according to a third embodiment of the present invention.
FIG. 12 is a timing chart showing a driving method of the liquid crystal display device according to the third embodiment of the present invention.
FIG. 13 is a block diagram illustrating a configuration of an information device including a liquid crystal display device according to a fourth embodiment of the present invention.
[Explanation of symbols]
101 ... Liquid crystal display device
102 ... Liquid crystal cell
103 ... Liquid crystal
104: Holding capacity
105. Switching element
106: Gate scanning drive circuit
107: Liquid crystal display driver
108: Analog sampling switch
109 ... Analog signal voltage common line
110: Digital I / F signal
111 ... gradation reference voltage
112: Block control signal
113: Gate scanning drive circuit control signal
301: Shift register control signal
302: Gate scanning line selection period control signal
303: Shift register
304 ... AND circuit
305 ... AND circuit
306 ... AND circuit
307 ... AND circuit
401: Digital I / F signal synchronization signal
402: Digital I / F signal display data
403 ... Control signal generation circuit
404 ... shift register
405 ... Latch circuit
406... Latch circuit
407 ... Latch circuit
408 ... Selection circuit
409 ... Final latch circuit
410 ... gradation voltage generation circuit
411: Decoder / analog voltage selection circuit
412: Analog signal voltage output circuit
413 ... Shift register start signal
414 ... Latch enable signal
415 ... Latch enable signal
416 ... selection signal
417 ... Final latch signal
701 ... Liquid crystal display driver
702 ... Liquid crystal display driver
705 ... Latch signal
706: Shift register end signal
707: Block latch end signal
708 ... Liquid crystal display device
801 ... Latch start signal
802 ... Latch signal
803: Block latch end signal
804 ... Control signal generation circuit
805 ... Simultaneous latch signal
806: Shift register end signal
807 ... Shift register start signal
808 ... Latch enable signal
809 ... Latch enable signal
810 ... Selection signal
811: Final latch signal
1001 ... Liquid crystal display device
1002 ... Liquid crystal display driver
1003 ... Analog sampling switch group
1101 ... Display data signal included in digital I / F signal
1102 ... Sync signal included in digital I / F signal
1103: Control signal generation circuit
1104. Memory circuit
1105 Memory circuit
1106 Address signal
1107: Address signal
1108: Read data signal
1109: Shift register
1110: Shift register start signal
1111... Latch circuit
1112: Memory control signal
1113: Memory control signal
1301 ... Information equipment provided with a liquid crystal display device
1302 ... Liquid crystal display device
1303 ... Central processing unit
1304 ... Input device
1305: Storage device
1306 ... Output device
1307: Power supply circuit

Claims (7)

Forming a plurality of drain lines and gate lines intersecting each other, forming a liquid crystal cell and a switching element corresponding to the intersection, and dividing the liquid crystal display unit into blocks including the plurality of drain lines;
A liquid crystal display device having a gate scan driving circuit for sequentially scanning a plurality of gate lines in the liquid crystal display unit ,
The liquid crystal display unit supplies a common signal line connected to the drain line included in the block via an analog switch, and a block control for supplying a block control signal for turning on the analog switch provided in the block A signal line,
A display signal propagated by the common signal line through the analog switch that is turned on is applied to the drain line that is included in the block and connected to the analog switch that is turned on.
Oite the liquid crystal display device having liquid crystal cells of the gate line selected by the gate scanning driver circuit is activated,
An input unit for inputting a gradation voltage having a plurality of voltage levels and a digital I / F signal, a gate scan driving circuit control signal for controlling the gate scan driving circuit, and the block control signal from the digital I / F signal. a first output section for generating and outputting, in series with the liquid crystal display driver and a second output unit for generating the display signals corresponding to display data of the block to be activated is output by the block control signal Multiple
Each liquid crystal display driver outputs an end timing signal at the timing of finally fetching the display data, receives the end timing signal output by the previous stage liquid crystal display driver, and captures the display data, thereby The display data is continuously fetched from the liquid crystal display driver of
The first stage liquid crystal display driver receives the end timing signal of the last stage liquid crystal display driver and outputs a display signal output signal for outputting the display signal.
The liquid crystal display device that receives the display signal output signal output from the first-stage liquid crystal display driver outputs the captured display data as a display signal.   Forming a plurality of drain lines and gate lines intersecting each other, forming a liquid crystal cell and a switching element corresponding to the intersection, and dividing the liquid crystal display unit into blocks including the plurality of drain lines;
  A liquid crystal display device having a gate scan driving circuit for sequentially scanning a plurality of gate lines in the liquid crystal display unit,
  The liquid crystal display unit supplies a common signal line connected to the drain line included in the block via an analog switch, and a block control for supplying a block control signal for turning on the analog switch provided in the block A signal line,
  A display signal propagated by the common signal line through the analog switch that is turned on is applied to the drain line that is included in the block and connected to the analog switch that is turned on.
  In a liquid crystal display device in which a liquid crystal cell on the gate line selected by the gate scan driving circuit is activated,
  An input unit for inputting a gradation voltage having a plurality of voltage levels and a digital I / F signal, a gate scan driving circuit control signal for controlling the gate scan driving circuit, and the block control signal from the digital I / F signal. A liquid crystal display driver having a first output unit that generates and outputs and a second output unit that generates and outputs the display signal corresponding to the display data of the block activated by the block control signal is connected in series. Multiple
  The gate scan driving circuit sequentially scans the gate lines in accordance with the gate scan driving circuit control signal output from the first-stage liquid crystal display driver.
  The display signal output from the plurality of liquid crystal display drivers is supplied to the common signal line,
  A block control signal output from the first-stage liquid crystal display driver that turns on the analog switch included in the block is supplied to the block control signal line;
  The liquid crystal display device, wherein the plurality of liquid crystal display drivers apply the display signal to the drain line connected to the analog switch that is turned on via the common signal line.   A plurality of drain lines and gate lines intersecting with each other, a liquid crystal cell and a switching element are formed corresponding to the intersection, and the drain lines are divided into blocks including q (q is a positive integer). A display unit;
  A liquid crystal display device having a gate scan driving circuit for sequentially scanning a plurality of gate lines in the liquid crystal display unit,
  The liquid crystal display unit includes a common signal line connected to the drain line included in the block via an analog switch, and each switch control signal for turning on the q analog switches provided in the block. Q switch control signal lines for supplying
  A display signal is applied to the nth drain line of each block by the nth (n is a positive integer, 0 <n <q) th switch control signal through the common signal line,
  In a liquid crystal display device in which a liquid crystal cell on the gate line selected by the gate scan driving circuit is activated,
  A gradation voltage having a plurality of voltage levels and an input unit for inputting a digital I / F signal;
  A first output section for generating and outputting a gate scan drive circuit control signal for controlling the gate scan drive circuit and the switch control signal from the digital I / F signal; and activated by the nth switch control signal A plurality of liquid crystal drivers in series, each having a second output unit for generating and outputting the display signal to be applied to the nth drain line, included in each block to be
  Each liquid crystal display driver outputs an end timing signal at the timing of finally fetching the display data, receives the end timing signal output by the previous stage liquid crystal display driver, and captures the display data, thereby The display data is continuously fetched from the liquid crystal display driver of
  The first stage liquid crystal display driver receives the end timing signal of the last stage liquid crystal display driver and outputs a display signal output signal for outputting the display signal.
  The liquid crystal display device that receives the display signal output signal output from the first-stage liquid crystal display driver outputs the captured display data as a display signal.   The liquid crystal display device according to claim 1 or 3,
  The digital I / F signal that is an input signal of the liquid crystal display driver is:
  A vertical synchronization signal that becomes effective once per frame period;
  A horizontal sync signal that becomes effective once per horizontal period;
  An effective display period signal that becomes active only during a period in which the display data is valid;
  A liquid crystal display device comprising an I / F signal including the display data.   The liquid crystal display device according to claim 1 or 3,
  The liquid crystal display device, wherein the gate scanning drive circuit, the analog switch, and the switching element are formed of thin film transistors using poly-Si.   The liquid crystal display device according to claim 1 or 3,
  The liquid crystal display driver is provided on a substrate on which the liquid crystal display unit is formed. OG (Chip on A liquid crystal display device, which is installed by the Glass technology.   A central processing unit that acts as a central control, performs computation, logic, and execution decisions, and transmits signals to and from input devices, output devices, and storage devices;
  The storage device used for storing instructions and data;
  The input device for inputting information to an information device;
  In the information device including the liquid crystal display device configured to output information from the inside of the information device to the outside and further output a digital I / F signal for display,
  4. The information device according to claim 1, wherein the liquid crystal display device is the liquid crystal display device according to claim 1.

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