JP2007310222A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the flickering phenomenon of a still picture on a display device which writes an odd-numbered-line video signal to a plurality of pixels in an odd-numbered-field period, and an even-numbered-line video signal to the plurality of pixels thereover in even-numbered-field periods. <P>SOLUTION: Slew rates of buffer amplifiers 29R, 29G, and 29B can be varied and controlled and switched by a slew-rate switching circuit 28. The slew-rate switching circuit 28 switches the slew rates by odd-numbered-field periods and even-numbered-field period, based on the timing signal from a timing control circuit 30. Consequently, the odd-numbered-line video signal and even-numbered-line video signal output onto the same display line are averaged out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device in which an interlace signal is used as a video source, and odd line video signals in odd fields and even line video signals in even fields are displayed alternately on the same display line. .

  In general, interlaced signals such as NTSC are used as a kind of video source for liquid crystal display devices and organic EL display devices in order to improve resolution. As shown in FIG. 6, the interlace signal is an odd-line video signal corresponding to 240 odd lines and an even-numbered video signal corresponding to 240 even lines in the 480 lines of the display screen. It consists of line video signals. In the example of FIG. 6, the interlace signal is a signal corresponding to a still image of the character “X”.

  The frequency of one frame is 30 Hz, and one frame is composed of an odd field and an even field that are alternately switched at a frequency of 60 Hz. An odd line video signal is output in the odd field period, and an even line video signal is output in the even field period. Is output.

  By the way, on the side of a display device that receives and displays an interlace signal, the number of lines on the display screen is normally composed of 480 lines corresponding to the 480 line interlace signal. For example, an electronic viewfinder of a digital camera Thus, from the user's required specifications, the number of display lines on the display screen is set to, for example, 240 and half.

  Accordingly, in such a display device, as shown in FIGS. 6 and 7, the odd line video signal and the even line video signal of the video source are displayed overwritten on the same line for each field period. . That is, each line is formed by arranging a plurality of pixels, and odd line video signals are written to 240 lines one after another in the odd field period, and even line video signals are 240 lines in the next even field period. One after another is written to the pixel. For example, the odd line video signal A and the even line video signal B are overwritten on the first line, and the odd line video signal C and the even line video signal D are overwritten on the 240th line. In this way, in the example of FIG. 6, the character “X” is displayed on the display device.

A display device using an interlace signal is described in Patent Documents 1 to 4.
JP-A-7-261713 JP-A-7-30836 JP-A-9-265278 JP 2005-107167 A

  In the above display device, the odd line video signal corresponding to the odd field of the video source and the even line video signal corresponding to the even field are alternately displayed on the same display line.

  However, in a display device such as an organic EL display device in which the response speed of the display element is as high as several microseconds, when displaying a still image from a video source, between an odd line video signal and an even line video signal. If there is a large difference between the two, there is a problem that it is visually recognized as flickering and it is difficult to see the displayed image. For example, in the example of FIG. 6, the character pattern “X” appears to flicker up and down at a frequency of 60 Hz on the display screen.

  The present invention has been made in view of the above-described problems, and includes a plurality of pixels, writes a first video signal output from a video source in a first field period to the plurality of pixels, and a second field period. And a buffer amplifier that amplifies the first and second video signals from the video source and supplies the second video signals output from the video source to the plurality of pixels A slew rate switching circuit for switching the slew rate of the buffer amplifier so that the first and second video signals overwritten on a plurality of pixels are averaged for each of the first and second field periods. And.

  According to the present invention, the first video signal and the second video signal are averaged by switching the slew rate of the buffer amplifier, and the difference therebetween is reduced, so that the flicker phenomenon at the time of still image display is suppressed.

In addition, the present invention includes a plurality of pixels, writes the first video signal output from the video source in the first field period to the plurality of pixels, and outputs the second video signal output from the video source in the second field period. In a display device that writes video signals over a plurality of pixels,
The first and second video signals from the video source are amplified and supplied to a plurality of pixels, and the first and second video signals output from the buffer amplifier are integrated and supplied to the pixels. And an integrating circuit.

  According to the present invention, since the first and second video signals output from the buffer amplifier are integrated and then supplied to the pixels, the first video signal and the second video signal are averaged, Since the difference is reduced, the flickering phenomenon during still image display is suppressed.

  According to the display device of the present invention, in the display device that writes the odd line video signal to the plurality of pixels in the odd field period and writes the even line video signal to the plurality of pixels in the even field period, the display apparatus flickers at the time of still image display. It becomes possible to suppress the phenomenon.

  An organic EL display device according to a first embodiment of the present invention will be described with reference to the drawings. As shown in the block diagram of FIG. 1, the organic EL display device performs various kinds of signal processing on an interlaced signal input from a video source, and a plurality of pixels 11 are arranged in a matrix. The data is output to the display panel 10 including the area. In this example, the interlace signal is a digital signal, but is composed of an odd line video signal and an even line video signal as in the conventional example.

  The signal processing circuit includes a serial / parallel converter 21, an RGB matrix 22, a selection circuit 23, a color correction circuit 24, a contrast / brightness adjustment circuit 25, a gamma correction circuit 26, a D / A converter 27, and a D / A converted signal. Buffer amplifiers 29R, 29G, and 29B for amplifying RGB (R: red, G: green, B: blue) analog video signals are provided. Then, analog video signals from the buffer amplifiers 29R, 29G, and 29B are output to the display panel 10. This analog video signal is also composed of an odd line video signal corresponding to an odd field and an even line video signal corresponding to an even field.

  As in the conventional example, the display panel 10 is configured such that odd line video signals and even line video signals are alternately displayed on the same display line.

  The feature of the present invention is that the slew rates of the buffer amplifiers 29R, 29G, and 29B can be variably controlled, and the slew rates are switched by the slew rate switching circuit 28. The slew rate is an output response characteristic with respect to the inputs of the buffer amplifiers 29R, 29G, and 29B. The response speed is fast when the slew rate is high, and the response speed is slow when the slew rate is low. The slew rate switching circuit 28 switches the slew rate for every odd field period and even field period based on the timing signal from the timing control circuit 30. Thereby, since the odd line video signal and the even line video signal output on the same display line are averaged, it is possible to suppress the flicker phenomenon at the time of still image display.

  Hereinafter, the configuration and operation of each circuit will be described. The serial / parallel converter 21 converts RGB digital video signals, which are serial signals, and a YUV signal composed of a luminance signal and a color difference signal into parallel signals. Of these parallel signals, the YUV signal is converted into an RGB digital video signal by the RGB matrix 22. The RGB digital video signal output from the serial / parallel converter 21 or the RGB digital video signal converted from the YUV signal by the RGB matrix 22 is selected and output by the selection circuit 23.

  The digital video signal from the selection circuit 23 is input to a color correction circuit 24 that performs predetermined color correction. The digital video signal color-corrected by the color correction circuit 24 is input to a contrast / brightness adjustment circuit 25 that adjusts the contrast and brightness. The digital video signal whose contrast and brightness (brightness) are adjusted by the contrast / brightness adjustment circuit 25 is input to a gamma correction circuit 26 that performs gamma correction. The output of the gamma correction circuit 26 is converted into an analog video signal by the D / A converter 27.

  FIG. 2 is a circuit diagram showing the relationship between the pixel 11 of FIG. 1 and a buffer amplifier. In this example, the pixel 11 and buffer amplifier 29R corresponding to R (red) are shown, but the same applies to pixels and buffer amplifiers corresponding to other colors.

  Referring to the pixel 11, Q1 is a pixel selection TFT, the drain is connected to the video line DL, the gate is connected to the gate line GL, and the source is connected to the gate of the driving TFT (Q2). The first terminal of the storage capacitor Cs is connected to the gate of the driving TFT (Q2). A storage capacitor voltage SC is applied to the second terminal of the storage capacitor Cs. The source of the driving TFT (Q2) is connected to the power supply line PVL that supplies the positive power supply potential PVdd, and the drain thereof is connected to the anode of the organic EL element OLED. A negative power supply potential CV is applied to the cathode of the organic EL element OLED.

  The analog video signal from the D / A converter 27 is output to the video line DL through the buffer amplifier 29R controlled by the slew rate switching circuit 28, and is written in the pixel 11. That is, when the pixel selection TFT (Q1) is turned on according to the pixel selection signal output to the gate line GL, the analog video signal is applied to the gate of the driving TFT (Q2) through the pixel selection TFT (Q1). At the same time, the source / drain current flowing in the driving TFT (Q2) changes in accordance with the voltage held in the holding capacitor Cs and held in the holding capacitor Cs. The organic EL element OLED emits light with a luminance corresponding to the source / drain current, thereby displaying.

  FIG. 3 is a waveform diagram showing an operation example of the organic EL display device described above. In this operation example, the odd line video signal in the odd field period is the white level (H), and the even line video signal in the even field period is the black level (L). These signals are alternately displayed in the same manner every field period. A case where data is written to the pixel 11 on the line is shown. While the pixel selection TFT (Q1) is on, the video signal is written to the pixel 11 and held by the holding capacitor Cs.

The buffer amplifier 29R in the odd field period is set to the slew rates 1 and 2, and is set to the slew rates 3 and 4 in the even field period. Here, it is assumed that the smaller the slew rate number, the higher the slew rate. (Slew rate 1> slew rate 2> slew rate 3> slew rate 4)
In the first odd field period of FIG. 3, since the slew rate of the buffer amplifier 29R is set to the highest slew rate 1, the video signal held in the holding capacitor Cs in the pixel 11 rises rapidly, and the pixel selection When the TFT (Q1) is turned off, it is held as it is. In the next even field period, the slew rate of the buffer amplifier 29R is switched to the lowest slew rate 4, so that the voltage held in the holding capacitor Cs slightly decreases. In the next odd field period, the slew rate is switched to slew rate 2. Further, in the next even field period, the slew rate is switched to 3. The following is the repetition.

  In this way, by switching the slew rate between the odd field period and the even field period, the video signals written and held in the pixels 11 are averaged. Thereby, the change in the luminance of the organic EL element OLED is also averaged, and the flickering phenomenon at the time of still image display can be suppressed.

  Note that the slew rate switching circuit 28 has a function of determining whether the interlace signal corresponds to a still image or a moving image. When the interlace signal corresponds to a moving image, the slew rate of the buffer amplifiers 29R, 29G, and 29B The switching may be stopped.

  In this embodiment, the slew rate is switched in each of the odd and even fields. However, the present invention is not limited to this, and the line scan period or the pixel unit period which is equal to or less than the field period unit is used. The slew rate may be switched. When switching the slew rate for each line scanning period or pixel unit period, it is preferable to select and average a predetermined area instead of averaging the video signal over the entire screen. Here, the predetermined area refers to an area where the luminance changes remarkably, that is, an area where a difference between video signals of adjacent lines or adjacent pixels is large. In an area where the change in luminance is small, no flicker phenomenon appears in the first place, so the video signals do not have to be averaged. The power consumption can be reduced by selecting only the areas where the luminance change is significant and averaging the video signals. As a method for selecting an area, it is preferable to provide determination means such as a frame memory in the signal processing circuit.

  In this embodiment, the slew rate in the odd field period is set to the slew rates 1 and 2, and the slew rate in the even field period is set to the slew rates 3 and 4. However, the present invention is not limited to this. The slew rate in the field period can be freely set to slew rates 1 and 4, and the slew rate in the even field period can be freely set as slew rates 2 and 3. Furthermore, in this embodiment, the slew rate is set in four stages, but the present invention is not limited to this, and can be set to a plurality of slew rates.

  Next, an organic EL display device according to a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the slew rates of the buffer amplifiers 29R, 29G, and 29B are switched. However, in this embodiment, the slew rates of the buffer amplifiers 29R, 29G, and 29B are not switched. Is provided with an integration circuit that integrates the video signal and supplies it to the pixel 11. Other configurations are the same as those of the circuit of the first embodiment.

  As shown in FIG. 4, the example of the integrating circuit includes a resistor 32 connected to the output of the buffer amplifier 29 </ b> R and a storage capacitor Cs of the pixel 11. Thereby, since the video signal written and held in the pixel 11 is averaged, the flicker phenomenon at the time of still image display is suppressed.

  Here, the short-circuit TFT 31 may be connected to both ends of the resistor 32, and the on / off of the short-circuit TFT 31 may be controlled by the determination output signal of the still image / moving image determination circuit 33. When the interlace signal corresponds to a moving image, a signal path that bypasses the resistor 32 can be formed by short-circuiting both ends of the resistor 32, and the integration circuit can be removed.

  FIG. 5 is a waveform diagram showing an operation example of the organic EL display device described above. Also in this operation example, as in FIG. 3, the odd line video signal in the odd field period is at the white level (H), and the even line video signal in the even field period is at the black level (L). In this example, data is alternately written to the pixels 11 on the same display line. While the pixel selection TFT (Q1) is on, the video signal is written to the pixel 11 and held by the holding capacitor Cs. As apparent from the waveform of FIG. 5, since the video signal written and held in the pixel 11 is averaged, the change in the luminance of the organic EL element OLED is also averaged, and the flicker phenomenon at the time of still image display is suppressed. Is done.

1 is a circuit diagram of an organic EL display device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a relationship between a pixel and a buffer amplifier in the first embodiment of the present invention. It is a wave form diagram which shows the operation example of the organic electroluminescence display which concerns on the 1st Embodiment of this invention. FIG. 6 is a circuit diagram illustrating a relationship between a pixel and a buffer amplifier in a second embodiment of the present invention. It is a wave form diagram which shows the operation example of the organic electroluminescence display which concerns on the 2nd Embodiment of this invention. It is a figure explaining operation | movement of the display apparatus using an interlace signal. It is a functional block diagram of a display device using an interlace signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 11 Pixel 21 Serial / parallel converter 22 RGB matrix 23 Selection circuit 24 Color correction circuit 25 Contrast / brightness adjustment circuit 26 Gamma correction circuit 27 D / A converter 28 Slew rate switching circuit 29R, 29G, 29B Buffer amplifier 30 Timing control circuit 31 Short-circuit TFT
32 Resistance 33 Still image / video discriminating circuit
Cs Retention capacitor Q1 Pixel selection TFT Q2 Driving TFT

Claims (8)

A plurality of pixels, a first video signal output from the video source in the first field period is written to the plurality of pixels, and a second video signal output from the video source in the second field period is a plurality of pixels. In a display device that writes over a pixel,
A buffer amplifier that amplifies the first and second video signals from the video source and supplies them to the plurality of pixels;
A slew rate switching circuit for switching the slew rate of the buffer amplifier every predetermined period so that the first and second video signals written to the plurality of pixels are averaged. Display device. The slew rate switching circuit switches the slew rate for each of the first and second field periods, sets the slew rate of the first field period to a first slew rate, and sets the second field. The display device according to claim 1, wherein the slew rate of the period is set to a second slew rate different from the first slew rate. The display according to claim 1, wherein the slew rate switching circuit stops switching the slew rate of the buffer amplifier when the first and second video signals correspond to moving images. apparatus. A plurality of pixels, a first video signal output from the video source in the first field period is written to the plurality of pixels, and a second video signal output from the video source in the second field period is a plurality of pixels. In a display device that writes over a pixel,
A buffer amplifier that amplifies the first and second video signals from the video source and supplies them to the plurality of pixels;
And an integration circuit that integrates the first and second video signals output from the buffer amplifier and supplies the first and second video signals to the pixel. The integration circuit includes a resistor connected between the output of the buffer amplifier and the pixel, and a storage capacitor provided in the pixel for holding the first and second video signals. The display device according to claim 4. 6. The display device according to claim 4, further comprising a switching circuit for stopping the operation of the integration circuit when the first and second video signals correspond to a moving image. The pixel has a holding capacitor for holding the first and second video signals, a transistor for passing a current corresponding to the first and second video signals held in the holding capacitor, and a current flowing through the transistor. The display device according to claim 1, further comprising a light emitting element that emits light. The display device according to claim 7, wherein the light emitting element is an organic EL element.

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