JP2001209028A - Driving device of liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an unevenness of luminance in lateral lines generated by differences of charging voltages of liquid crystal cells in a liquid crystal panel when operating a simple zoom function by simultaneous selection of scanning electrode lines. SOLUTION: About a nonselected period for the later scanning signal electrode line X3 of two scanning signal electrode lines X2 and X3 selected simultaneously, the nonselected timing of the scanning signal electrode line X2 is set to t1, the nonselected timing of the scanning signal electrode line X3 is set to t2(t1<t2), specific timing between t1 to t2 is set to t12(t1<t12<t2), and the timing in 1H after t2 is set to t3(t2<t3<=1H). The counter signal voltage Vc1 is changed to Vc2 to lower the charging voltage of the liquid crystal cell during the period of t1 to t3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a liquid crystal display panel used for a television, a video monitor, and the like.
In particular, the present invention relates to a technology of a simple zoom function for enlarging a display.

[0002]

2. Description of the Related Art As one of display panels for displaying characters and images using display materials represented by liquid crystals, there is an active matrix type liquid crystal panel display device having a switching element for each display unit.

FIG. 4 is an equivalent circuit diagram showing a configuration of an active matrix type liquid crystal panel. This liquid crystal panel 5
Represents m × n display pixels 1 arranged in a matrix
And the image signal voltage corresponding to the pixel data
Are formed on a transparent substrate, and image signal electrode lines (S1 to Sm) 6 to be supplied to each pixel and scanning signal electrode lines (X1 to Xn) 7 to supply a scanning signal for performing line-sequential scanning to each display pixel 1 are formed on the transparent substrate. Things. Each display pixel 1 has a thin film transistor 2, a liquid crystal display element 3, and a storage capacitor 4.

[0004] Thin film transistor (hereinafter referred to as TFT)
Reference numeral 2 denotes a switching element having a source as a first control input terminal, a gate as a second control input terminal, and a drain as an output control terminal. The TFT 2 is selectively controlled by a selection scanning signal from a scanning signal electrode line 7 connected to a gate driver 10, and an image signal (also referred to as a pixel signal) is supplied by an image signal electrode line 6 connected to a source driver 9. The liquid crystal display element 3 is also called a liquid crystal cell, and is a liquid crystal material sandwiched between a pixel electrode and a counter electrode 8 and whose optical characteristics are changed by a voltage between the two electrodes. The storage capacitor 4 is a capacitor formed in parallel with the liquid crystal display element 3, that is, between the drain electrode (pixel electrode) of the TFT 2 and the counter electrode 8, and reduces the image display voltage _VLC stored in the liquid crystal display element 3. It is provided to control. The opposing electrode 8 has an opposing signal voltage V _{com as a} reference for the liquid crystal display element 3.
Is a common electrode for supplying the counter signal voltage V _com
Is generated by a counter signal voltage supply circuit not shown in FIG.

[0005] The source driver 9 is a drive circuit for supplying an image signal voltage _Vy to each image signal electrode line 6. The gate driver 10 is a drive circuit that supplies a selection scanning signal for performing line-sequential scanning to each scanning signal electrode line 7. The display pixel 1 for displaying one pixel in this way is formed by one TFT 2, a liquid crystal display element 3, and a storage capacitor 4 as shown by a broken line, and an active matrix type liquid crystal panel 5 is composed of a large number of display pixels. Be composed.

The image signal electrode lines 6 and the scanning signal electrode lines 7 are arranged in a matrix on a transparent substrate. The source of the TFT 2 is connected to the image signal electrode line 6, and the gate is connected to the scanning signal electrode line 7. The drain of the TFT 2 is connected to the pixel electrode of the liquid crystal display element 3 and one terminal of the storage capacitor 4. The other terminal of the storage capacitor 4 is connected to the counter electrode 8. The opposing electrode 8 is supplied with the opposing signal voltage _Vcom. Depending on the driving method of the image signal voltage from the source driver 9, a DC voltage is applied or the polarity is inverted every horizontal synchronization period (1H). The applied pulse voltage is applied.

In order to perform image display, an image signal voltage corresponding to pixel data is supplied from a source driver 9 to the source of each TFT 2 via each image signal electrode line 6, and the gate driver 10 synchronizes with this. A selected scanning voltage is supplied to the gate of each TFT 2 via the selected scanning signal electrode line 7. As a result, the selected scanning signal electrode line 7
The upper TFTs 2 are simultaneously turned on, and an image signal voltage corresponding to pixel data is supplied to each liquid crystal display element 3 and each storage capacitor 4. Then, a counter signal voltage V _com which is supplied to the counter electrode 8, the potential difference component of the image signal voltage V _y as described above is accumulated in the liquid crystal display device 3 as a final image display voltage V _LC. Even when the TFT 2 changes to the off state, the image display voltage _VLC is held for one field period in which the next image information is input. By such an operation, an image with high contrast and excellent display quality is displayed on the active matrix type liquid crystal panel.

It is standard that an image signal of a TV or the like is input to a display device having an aspect ratio of 3: 4. However, in recent years, a wide display device having an aspect ratio of 9:16 has been used. Is spreading. When a normal TV signal is displayed on the wide display device, the screen is compressed in the vertical direction due to a difference in aspect ratio, and, for example, a perfect circle becomes an ellipse. As a function of returning this to the original ratio, there is a zoom function for enlarging the display in the vertical direction.
When returning to the original ratio using such a zoom function,
The zoom ratio in the vertical direction may be set to 4/3.

In order to perform the above-described zoom function, it is necessary to interpolate an image signal corresponding to an enlargement factor in the vertical line direction of the liquid crystal panel 5 in particular. As a simple interpolation processing method, there is a method of outputting the same image signal to a plurality of lines. FIG. 5 is an explanatory diagram showing an example of driving by the simple method. Here, two out of three scanning signal electrode lines are simultaneously selected once in three times in the line sequential scanning, and the same image signal is displayed. By repeating this processing for the subsequent scanning signal electrode lines, the vertical direction can be pseudo-zoomed to 4/3 times.

Next, a driving method for realizing the zoom function will be described. Although the counter signal voltage _Vcom supplied to the counter electrode 8 may be a DC voltage, here, the polarity is inverted every horizontal synchronization period (1H) as the main amplitude component Vc of the counter signal voltage _Vcom . It is assumed that a “1H opposing inversion driving method” for supplying a voltage is used. HD shown in the upper part of FIG. 5 is a horizontal synchronizing signal, V _gh of the scanning signal electrode line X1~Xn are selective gate voltage supplied to the TFT2 of the gate scanning signal electrode lines Xi to be selected. When the liquid crystal panel 5 is of a normally white type, when the image signal voltage _Vy is at the H level, the luminance is low and the level is at the black level. The selection gate voltage _Vgh is switched by the gate driver 10 and supplied from the respective scanning signal electrode lines X1 in the selection period T0 every 1H.

Now, the scanning signal electrode lines selected at the same time are (X
2 and X3), (X6 and X7)..., And zoom processing is performed for each of the four scanning signal electrode lines. The application period of the selection gate voltage V _gh supplied to the simultaneously selected scanning signal electrode lines is equal to the time T1 for the scanning signal electrode lines (X2, X6...) In order to minimize mutual interference. age,
For the other scanning signal electrode lines (X3, X7,...), A standard time T0 is set, and a relationship of T1 <T0 is set. Here, it is estimated that various floating capacitances and parasitic capacitances exist between the display pixel 1 of the currently selected scanning signal electrode line Xi and the display pixel 1 of the adjacent scanning signal electrode line Xi-1. For this reason, the falling change of the selection gate voltage V _gh for a specific liquid crystal display element 3 affects the storage potential of another liquid crystal display element 3 via a stray capacitance or a parasitic capacitance.
In addition to these effects, a change in the image signal voltage of the image signal electrode 6 with respect to a specific liquid crystal display element 3 may affect the storage potential of another liquid crystal display element 3. In order to reduce such adverse effects, the off-time of the selected scanning voltage is controlled by providing a time difference as described above.

As shown in FIG. 5, X1, X2, X3, X4, X5, X
The line-sequential scanning is performed in the order of 6, X7, X8,. The scanning signal electrode lines (X2, X3), (X6, X
8) In the TFT2, the same image signal voltage _Vy is applied to the display pixels 1 on the adjacent upper and lower lines, so that the display pixels on the simultaneously selected scanning signal electrode lines have the same image.

In this manner, since four scanning signal electrode lines are scanned in three scans, a zoom function in which the apparent display magnification is increased by 25% is realized. The liquid crystal display element 2 is driven by an alternating current because it is a capacitive element. Therefore, the image signal voltage V output from the source driver 9
y, and the counter signal voltage V supplied to the counter electrode 8
_com has an inverted polarity for each field.

However, when an H-level image signal (black level) is output by giving a time difference to the selection period during the simultaneous selection, the selection period T1 on the X2 side is changed to the selection period T0 on the X3 side.
, The brightness of the liquid crystal display element 3 on the X3 side tends to change more in the black direction than on the X2 side. As a display screen, as shown in FIG. 6, a dark horizontal stripe appears on one of the lines selected at the same time. It is considered that this is an effect when the X2 side is deselected, and that the image signal voltage on the X3 side is eventually overshot.

In general, the driving capability of the TFT 2 has a temperature dependency, and the driving capability tends to decrease as the temperature decreases. Based on these assumptions, how the image display voltage _VLC finally charged to the simultaneously selected liquid crystal display element 3 changes at the scanning signal electrode lines X2 and X3 will be described with reference to FIG. explain. First, the scanning signal electrode line X2 side will be described. Simultaneously selected scanning signal electrode lines X2, X3
, It is necessary to provide a time difference in the scanning selection period as described above. However, especially at a low temperature, the selection period T1 having a margin so as not to cause insufficient charging of the liquid crystal display element due to a decrease in the driving current capability of the TFT2. To the scanning signal electrode line X2.

As shown in FIG. 7, the image display voltage V_LCage
The normal temperature is indicated by a solid line, and the low temperature is indicated by a dashed line.
Charge voltage within the selected period_s And Scan signal electrode line X
The image display voltage V at the moment when 2 is deselected_LCIs only ΔV
The voltage drops. This is commonly called the punch-through voltage
This is a common phenomenon of liquid crystal display panels. Select gate
Voltage V_gh, The image signal charged in the liquid crystal display element 3
Voltage V_y Is the voltage change at the falling edge that enters its own non-selection
Causes a voltage drop of ΔV. This value is within display pixel 1.
Of the stray capacitance is relevant. Image signal voltage of liquid crystal display element 3
As shown in FIG.
The gate-drain capacitance C of TFT2 _gd, Storage capacity
4 own capacity C_st, The capacitance C of the liquid crystal display element 3_LCThere
You.

Although it depends on the design of the liquid crystal panel, it is assumed here that the approximate capacitance ratio is C _gd : C _st : C _LC = 1: 5: 5 and the select gate voltage value V _gh is 25 V. The value of ΔV is
Since ΔV = C _gd / (C _gd + C _LC + C _st ) * V _gh , ΔV is ≒ 2.3 V with the above value. Since the penetration voltage ΔV occurs uniformly for all pixels, the luminance variation due to the voltage change does not affect the display quality at all. Therefore, the final image display voltage V _LC l of 7, and V _LC 1 = V _s -ΔV.

On the other hand, on the scanning signal electrode line X3 side, the selection period T0 is longer than the X2 side (T0> T1).
Insufficient charging due to temperature dependence of 2 does not occur. However, X2 side of the selection period T1 is the effect of when it is unselected, the overshoot component having a peak voltage V _o is superimposed on the image signal voltage. Therefore, the selection period T0
At the end of, it becomes a high value by the voltage V _e relative to the charging voltage V _s of the in the selection period should be. Thus, the image display voltage V _LC 2 The _{final, V LC 2 = (V s} + V
_e ) -ΔV. Final image display voltage V _LC 2 of this for the scanning signal electrode lines X3 side than V _LC 1 for X2 side + V _e
As a result, the scanning signal electrode line X3 appears as a light black horizontal stripe.

[0019]

In the conventional zoom display driving by the simultaneous selection of the scanning electrode lines having a mere selection time difference, the charging voltage is applied to the liquid crystal display element on one side of the simultaneous selection of the scanning signal electrode lines. As a result, there is a problem in that thin horizontal line luminance unevenness appears and sufficient display quality cannot be obtained.

The present invention has been made in view of such a conventional problem, and suppresses horizontal luminance unevenness by superimposing a correction voltage on the counter signal voltage _Vcom , thereby achieving high quality zoom display. It is an object of the present invention to realize a possible liquid crystal display panel driving device.

[0021]

According to a first aspect of the present invention, there are provided a plurality of scanning signal electrode lines and a plurality of image signal electrode lines arranged in a matrix on a transparent substrate; A liquid crystal cell arranged close to each intersection of image signal electrode lines and having optical characteristics that change in pixel units; a plurality of pixel electrodes for applying a voltage corresponding to a pixel signal to one surface of each liquid crystal cell; A counter electrode formed at a position facing the pixel electrode by inserting a cell; a plurality of storage capacitors connected to the pixel electrode and the counter electrode for each pixel; and a first electrode connected to the image signal electrode line. A plurality of switching elements having a control input terminal connected thereto, a second control input terminal connected between the scanning signal electrode line pixel electrodes, and a control output terminal connected to the pixel electrode; 1 control input A source driver for simultaneously supplying a pixel signal to one end; a gate driver for sequentially supplying a selection scanning signal to a second control input terminal of the plurality of switching elements; and a counter signal voltage supply for supplying a counter signal voltage to the counter electrode. A driving circuit for a liquid crystal display panel, comprising: a gate driver that simultaneously scans adjacent scanning signal electrode lines of the liquid crystal panel with respect to one scanning signal electrode line of the simultaneous scanning. The counter signal voltage supply circuit outputs a selection gate signal of T1 (<1H) and outputs a selection gate signal of a standard time T0 (T1 <T0 <1H) to the other scanning signal electrode line of the simultaneous scanning. , when said AC driving a counter electrode, a main amplitude component of the counter signal voltage V _com to the polarity inverted every horizontal synchronization period, the time from the initial position of the horizontal synchronization period T1 First outputting the main amplitude voltage Vc = Vc1, after lapse of the time T1 to the end time of the horizontal synchronization period and the second main amplitude voltage V is
It is characterized by outputting c = Vc2 (Vc2 <Vc1).

According to a second aspect of the present invention, in the driving device for a liquid crystal display panel according to the first aspect, the counter signal voltage supply circuit is connected during the 1H period for simultaneously selecting two adjacent scanning signal electrode lines. Start position t of horizontal synchronization period
When the ₀ and the selection start timing, the non-selection timing of one of the scanning signal electrode line side and t _1, the non-selection timing of the other scan signal electrode line side and _{t 2 (t 1 <t 2} ), the 1H End timing of t ₃ (t ₂ <t ₃ ≦ 1
H), and an arbitrary timing between the non-selection timing t ₁ and the non-selection timing t ₂ is t ₁₂ (t ₁ <t ₁₂ <t ₂ ).
When the, timing t ₁₂ ~t ₃ as the correction period, and outputs the counter signal voltage in a direction to lower the charging voltage of the liquid crystal cell in the correction period.

According to a third aspect of the present invention, a plurality of scanning signal electrode lines and a plurality of image signal electrode lines arranged in a matrix with respect to a transparent substrate, and each of the scanning signal electrode lines and the image signal electrode lines is provided. A liquid crystal cell that is arranged close to the intersection and whose optical characteristics change in pixel units, a plurality of pixel electrodes that apply a voltage corresponding to a pixel signal to one surface of each of the liquid crystal cells, and A counter electrode formed at a position facing the electrode; a plurality of storage capacitors connected to the pixel electrode and the counter electrode for each pixel; and a first control input terminal connected to the image signal electrode line. A second control input terminal is connected between the scanning signal electrode line and the pixel electrode;
A plurality of switching elements having a control output terminal connected to the pixel electrode; a source driver for simultaneously supplying a pixel signal to a first control input terminal of the plurality of switching elements; and a second control of the plurality of switching elements. A driving apparatus for a liquid crystal display panel, comprising: a gate driver that sequentially supplies a selection scanning signal to an input terminal; and a counter signal voltage supply circuit that supplies a counter signal voltage to the counter electrode. When scanning the scanning signal electrode lines simultaneously,
The gate driver outputs a selection gate signal for a time T1 (<1H) to one scanning signal electrode line in simultaneous scanning, and outputs a standard time T0 (T1 <T0) to the other scanning signal electrode line in simultaneous scanning. <1H) is output,
The counter signal voltage supply circuit outputs V _com = V _st at the time T1 from the initial position of the horizontal synchronization period as the counter signal voltage V _com when the counter electrode is DC driven, and after the time T1, During the time T2 from the end of the horizontal synchronization period to the end of the horizontal synchronization period, _Vcom = _Vst ± ΔVc is output.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A driving device for a liquid crystal display panel according to an embodiment of the present invention will be described with reference to the drawings. The structure of the liquid crystal display panel is the same as that shown in FIG. FIG. 1 is a timing control diagram showing a driving method in a driving device of a liquid crystal display panel according to the present embodiment.
The case of the opposing inversion type driving method is shown. FIG. 1A shows a horizontal synchronization signal HD. FIG. 1B shows a voltage waveform of the selection gate voltage _Vgh supplied to the scanning signal electrode line X2 for a short selection period among the simultaneously selected scanning signal electrode lines X2 and X3. FIG. 1C shows the scanning signal electrode lines X selected at the same time.
2 shows a voltage waveform of a selection gate voltage _Vgh supplied to the scanning signal electrode line X3 in a long selection period among X3 and X3. FIG.
(D) are shown the main amplitude component Vc of the counter signal voltage V _com supplied to the counter electrode 8, the solid line F _n and the broken line F in FIG.
_As shown by _{n + 1} , the polarity of Vc is inverted every horizontal synchronization period (1H) and every vertical synchronization period (1V). Field F
_n and F _{n + 1} have the same inversion timing,
In (d), for convenience of drawing, the changing points are displayed shifted.

FIG. 1E shows a zoom correction control signal Z _oom -C for variably controlling the opposing signal voltage V _com during the selection period of the simultaneously selected scanning signal electrode line. FIG. 1 (f)
Shows the voltage waveform of the image display voltage _VLC charged to the liquid crystal display element 3 connected to the TFT2 controlled by the selection gate voltage _Vgh of the simultaneously selected scanning signal electrode line X2. FIG. 1 (g) shows a TFT2 controlled by the selection gate voltage _Vgh of the simultaneously selected scanning signal electrode line X3.
_Shows a voltage waveform of an image display voltage _VLC charged in the liquid crystal display element 3 connected to the TFT.

The operation of the counter signal voltage, the selection gate voltage, and the image signal voltage having such waveforms will be described. The horizontal synchronization period (1) selected at the same time in FIG.
H) is _denoted by t ₀ to t ₃ . Here, t ₀ is the starting point of the selection gate voltage V _gh . t ₁ is the end point of the selection gate voltage V _gh of the scanning signal electrode lines X2. t ₂ is the end point of the selection gate voltage V _gh of the scanning signal electrode lines X3. t ₃ is 1
This is the end point of the horizontal synchronization period. t ₁₂ is opposite signal voltage V
It is the starting point of variable control of _com . As described above, the application period T1 of the selection gate voltage of the scanning signal electrode line X2 is shorter than the application period T0 of the selection gate voltage of the scanning signal electrode line X3 (T1 <T0).

The zoom correction control signal Z _00m-in FIG.
C is a period in which simultaneous selection is performed, and only in the period T2 from t ₁₂ to t _3, used the main amplitude component Vc of the counter signal voltage V _com as a control signal for variably controlling.
First, the counter signal voltage _Vcom at the time of performing the simultaneous selection is compared with the main amplitude voltage Vc1 in the correction period Tc as shown in FIG.
2 is a main amplitude voltage Vc2 reduced by ΔVc. In the correction period T2 in which the correction control of the counter signal voltage is performed, the scanning signal electrode line X2 has already entered the non-selection state and
Since T is off, TF controlled by the selection gate voltage V _gh of the scanning signal electrode X2 even if the counter signal voltage changes.
There is no change in the charging voltage _VLC to the liquid crystal display element connected to T. Therefore, as shown in FIG. 1F, the influence of the presence or absence of the correction voltage decrease ΔVc does not occur in the display pixels on the scanning signal electrode line X2. V _LC unselected state after the image display voltage V _LC is a voltage ΔV partial penetration shifted
It remains at 1.

Next, the scanning signal electrode line X3 shown in FIG.
Consider the image display voltage _VLC on the side. A broken line indicates a state before correction, and a solid line indicates a state after correction. In t ₁ which is a non-selection scanning signal electrode lines X2 side, a scanning signal electrode lines X
Since the voltage V ₀ that overshoots from the V _s state is superimposed on the image display voltage on the third side, the voltage becomes higher by V _e at t _{2 when the} selection period T 0 ends without correction. To correct this, the zoom correction control signal Z is set between t ₁ and t ₂ when the superimposed voltage of the overshoot of V ₀ occurs.
_By controlling _oom- C, the main amplitude component Vc of the opposite signal voltage _Vcom is reduced by ΔVc from the main amplitude voltage Vc1 to the main amplitude voltage Vc.
Control to 2. The potential difference V between the image signal voltage V _y and the counter signal voltage V _com which is sent during this period of the image signal electrode lines 6
_By reducing _LC by ΔVc, the charging voltage to the liquid crystal display element 3 is forcibly reduced for V _e . Then, at time t ₂ , the level is set to V _s at which no overshoot occurs.

As a result, the final image display voltage V_LCHammer
Voltage V shifted by missing voltage ΔV _LC3 and the scanning signal
Display voltage V of the display pixel on the signal electrode line X2_LCSame as 1
Voltage. Counter signal voltage V_com Main amplitude of
The polarity of the component Vc needs to be inverted for each field.
Thus, the polarity of the correction voltage is similarly inverted. This
As a result, the brightness of the horizontal streak due to the charging error in the
Are almost inconspicuous.

Next, a specific example of the counter signal voltage supply circuit for outputting such a counter signal voltage will be described with reference to FIG. The amplifier 11 shown in FIG. 2 is an operational amplifier that amplifies the polarity inversion control signal POL supplied to the inverting input terminal and supplies the common electrode voltage _Vcom to the _common electrode 8 in FIG. R1, R2, and Rv are resistors for determining the gain of the amplifier 11, and R3 and R4 are bias resistors for applying a bias voltage to the amplifier 11. The capacitor C is a coupling capacitor that is inserted into the input terminal of the counter signal voltage supply circuit and cuts off a DC component. Switch circuit 1
_{Reference numeral} 2 denotes a switch that is opened / closed under the control of the zoom correction control signal Z _oom -C and _sets the variable resistor Rv in a short-circuit state or a non-short-circuit state.

The polarity inversion control signal POL is a counter signal voltage V
_This is an input signal whose polarity is inverted every horizontal synchronization period and every vertical synchronization period from which _com is _generated . Zoom correction control signal Z _{oo m} -C is a control signal for switching control of the switch circuit 12, when "Lo" of normal operation 1 side, when "Hi" of the correction operation is switched to the 2 side.

The basic operation of the opposing signal voltage supply circuit will be described. A polarity inversion control signal POL synchronized with the horizontal synchronization signal HD is output from a timing controller (not shown), and the DC component is cut off by the capacitor C. Amplifier 1
The gain G2 at the time of correction of 1 is determined by the resistors R1 and R2 and the variable resistor Rv. The gain G1 at the time of non-correction (during normal operation) is determined by the resistors R1 and R2. Amplifier 11 for normal operation of the polarity inversion control signal POL amplified by the gain G1, supplied to the counter electrode 8 as a counter signal voltage V _{co m} having a main amplitude voltage Vc1.

In the case of simultaneous selection in the zoom display, the switch circuit 12 is controlled by the zoom correction control signal Z _oom -C.
Is performed, and the variable resistor Rv is short-circuited so that the amplifier 1
The gain of 1 is reduced to G2. In this case, a corrected amplitude voltage Vc2 lower than Vc1 is added to the DC component, and the added voltage is supplied to the common electrode 8 as the _common signal voltage _Vcom .

Here, the voltage level of the AC component of the polarity inversion control signal POL is set to _Vpol . Zoom correction control signal Z
During the period other than the simultaneous selection period when _oom- C becomes “Lo”, the switch circuit 12 is switched to the 1 side, and the variable resistor Rv
Is short-circuited. At this time, the main amplitude voltage Vc1 of the opposite signal voltage _Vcom is expressed by the following equation. Vc1 = V _pol ×
G1 = _Vpol × (R2 / R1). Therefore, the necessary gains are set so that G1 = R2 / R1.
2 may be selected.

[0035] Next zoom correction control signal Z _oom -C is "H
The switch circuit 12 is switched to the side 2 during the simultaneous selection period of i ″. The variable resistor Rv is made effective, and the amplifier 11
Is related to the variable resistor Rv. The correction amplitude voltage of the opposing signal voltage _Vcom required at this time is Vc2. As described in the description of FIG. 1, the relationship of Vc2 <Vc1 is required, and the gain G of the amplifier 11 at this time is required.
2 naturally satisfies the relationship of G2 <G1.

Vc2 = _Vpol × G2 = _Vpol × (R
2 / (R1 + Rv) = V _pol × G1 / (1+ (Rv / R
1)) is established. Therefore, G2 = G1 / (1+ (Rv /
The value of the variable resistor Rv may be adjusted so as to satisfy the relationship of R1)).

By such a correction, it is possible to reduce the horizontal line luminance unevenness of the thin line generated during the simultaneous selection period to a level that is hardly noticeable. In addition, regarding the simultaneous selection period of the scanning signal electrodes, the leading side (scanning signal electrode X2) as viewed from the line-sequential scanning direction is a short period T1, and the trailing side (scanning signal electrode X).
Although 3) has been described as a long period T0, it is also possible to set the first side (scanning signal electrode X2) in the line-sequential scanning direction to the long period T0 and the rear side (scanning signal electrode X3) to the reverse condition of the short period T1. The present invention is effective.

In the present embodiment including the conventional example, the method of driving the opposite signal voltage _Vcom with a voltage whose polarity is inverted every horizontal synchronization period (1H) and every vertical synchronization period (1V) has been described. , Instead of such an inversion drive,
A simple DC voltage may be used as the reference voltage.
Also in this case, in order to cancel the decrease in the luminance of the display pixel on the scanning signal electrode line X3, a correction voltage may be applied in the correction period as in the present embodiment.

FIG. 3 is a timing control diagram showing a driving method when the opposing signal voltage _Vcom is a DC voltage. FIG.
(A) shows the horizontal synchronization signal HD. FIG. 3 (b) shows the voltage waveform of the image signal to the scanning signal electrode lines which are simultaneously selected, and F _n is n fields, the n + 1 field and F _{n + 1.} In this driving method, the polarity of the image signal voltage V _y is inverted every field. FIG. 3C shows the waveform of the counter signal voltage _Vcom supplied to the counter electrode 8 (0
Level not shown). FIG. _{3D shows} a zoom correction control signal Z _oom -C for variably controlling the opposing signal voltage V _com during the selection period of the simultaneously selected scanning signal electrode line.

As shown in FIGS. 3B and 3C, when the image signal voltage V _ss from the source driver 9 during the simultaneous selection period has a positive polarity, the opposing signal voltage V _{com is changed} to the standard DC voltage V _st.
And a higher voltage level (V _st + ΔVc), the image signal voltage V _ss is when the negative polarity, the counter signal voltage V _com to the standard DC voltage V _st lower than the voltage level (V _st -ΔVc). For this reason, as shown in FIG. _3D , the zoom correction control signal Z _oom -C is output in the period T2, and the standard DC voltage V
_What is necessary is just to superimpose the correction voltage ΔVc around the _st in the positive or negative direction.

[0041]

As described above, according to the present invention, in a liquid crystal panel having a storage capacitor in a display pixel and one of the storage capacitors connected to a counter electrode line, a zoom as a screen enlargement function is provided. Give the display the time difference of the scanning signal electrode line,
In the case of enlargement by repetition of the simultaneous selection, by supplying the corrected voltage in the latter half of the simultaneous selection period of the opposing signal voltage, it is possible to reduce the horizontal line luminance unevenness to a level that is hardly noticeable.

[Brief description of the drawings]

FIG. 1 is a waveform chart showing a driving method (part 1) for suppressing thin horizontal line luminance unevenness during zooming in a liquid crystal display panel driving device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a counter signal voltage supply circuit used in the liquid crystal display panel driving device of the present embodiment.

FIG. 3 is a waveform chart showing a driving method (2) for suppressing thin horizontal line luminance unevenness during zooming in the liquid crystal display panel driving device according to the embodiment.

FIG. 4 is an equivalent circuit diagram showing a configuration of a liquid crystal display panel.

FIG. 5 is a waveform diagram of a selection gate voltage applied during a zoom operation.

FIG. 6 is an explanatory diagram showing a display state during a zoom operation in a conventional liquid crystal display panel driving device.

FIG. 7 is an explanatory diagram of a voltage applied to a pixel on a scanning signal electrode line selected simultaneously during a zoom operation in a conventional liquid crystal display panel driving device.

[Explanation of symbols]

 Reference Signs List 1 display pixel 2 switching element (TFT) 3 liquid crystal display element 4 storage capacitor 5 liquid crystal panel 6 image signal electrode line 7 scanning signal electrode line 8 counter electrode 9 source driver 10 gate driver 11 amplifier 12 switch circuit R1 to R4 resistance Rv variable resistance C capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 JA24 JB61 NA01 PA06 QA07 2H093 NA16 NA32 NA47 NB12 NB13 NB16 NB21 NC09 NC11 NC18 NC34 NC49 ND15 ND60 NH12 5C006 AA11 AB01 AC11 AC24 AF42 BB16 BC03 BF25 FA22 51011 GG02 GG08 JJ02 JJ03 JJ04

Claims (3)

[Claims] A plurality of scanning signal electrode lines and a plurality of image signal electrode lines arranged in a matrix with respect to a transparent substrate; and a plurality of scanning signal electrode lines and image signal electrode lines arranged in proximity to each intersection. A liquid crystal cell whose optical characteristics change in pixel units; a plurality of pixel electrodes for applying a voltage corresponding to a pixel signal to one surface of each of the liquid crystal cells; and a plurality of pixel electrodes formed at positions facing the pixel electrodes by inserting the liquid crystal cells. A plurality of storage capacitors connected to the pixel electrode and the counter electrode in pixel units; a first control input terminal connected to the image signal electrode line; A plurality of switching elements having a second control input terminal connected between the electrodes, and a control output terminal connected to the pixel electrode; and a source for simultaneously supplying a pixel signal to a first control input terminal of the plurality of switching elements. A liquid crystal display panel comprising: a driver; a gate driver that sequentially supplies a selection scanning signal to second control input terminals of the plurality of switching elements; and a counter signal voltage supply circuit that supplies a counter signal voltage to the counter electrode. When simultaneously scanning adjacent scanning signal electrode lines of the liquid crystal panel, the gate driver operates the time T1 (<1
1H), and outputs a standard time T0 (T1 <T0 <1) to the other scanning signal electrode line of the simultaneous scanning.
H), the counter signal voltage supply circuit outputs the selection signal as a main amplitude component of a counter signal voltage V _{com that} reverses its polarity every horizontal synchronization period when the counter electrode is driven by AC.
At the time T1 from the initial position of the horizontal synchronization period, the first
And outputting a second main amplitude voltage Vc = Vc2 (Vc2 <Vc1) from the elapse of the time T1 to the end time of the horizontal synchronization period. Panel drive. 2. The counter signal voltage supply circuit according to claim 1, wherein in a 1H period in which two adjacent scanning signal electrode lines are simultaneously selected, when a start position t ₀ of the horizontal synchronizing period is set as a selection start timing, one scan is performed. The non-selection timing on the signal electrode line side is t ₁ , the non-selection timing on the other scanning signal electrode line side is t ₂ (t ₁ <t ₂ ), and the end timing within 1H is t ₃ (t ₂ <t _3). ≦ 1H) and an arbitrary timing between the non-selection timing t ₁ and the non-selection timing t ₂ is t ₁₂ (t ₁ <t ₁₂ <t ₂ ),
Timing t of ₁₂ ~t ₃ as the correction period, the correction period to the driving device for a liquid crystal display panel of claim 1, wherein the outputting the counter signal voltage in a direction to lower the charge voltage of the liquid crystal cell. 3. A plurality of scanning signal electrode lines and a plurality of image signal electrode lines arranged in a matrix with respect to a transparent substrate; and a plurality of scanning signal electrode lines and image signal electrode lines arranged in close proximity to intersections of the scanning signal electrode lines and the image signal electrode lines. A liquid crystal cell whose optical characteristics change in pixel units; a plurality of pixel electrodes for applying a voltage corresponding to a pixel signal to one surface of each of the liquid crystal cells; and a plurality of pixel electrodes formed at positions facing the pixel electrodes by inserting the liquid crystal cells. A plurality of storage capacitors connected to the pixel electrode and the counter electrode in pixel units; a first control input terminal connected to the image signal electrode line; A plurality of switching elements having a second control input terminal connected between the electrodes, and a control output terminal connected to the pixel electrode; and a source for simultaneously supplying a pixel signal to a first control input terminal of the plurality of switching elements. A liquid crystal display panel comprising: a driver; a gate driver that sequentially supplies a selection scanning signal to second control input terminals of the plurality of switching elements; and a counter signal voltage supply circuit that supplies a counter signal voltage to the counter electrode. When simultaneously scanning adjacent scanning signal electrode lines of the liquid crystal panel, the gate driver operates the time T1 (<1
1H), and outputs a standard time T0 (T1 <T0 <1) to the other scanning signal electrode line of the simultaneous scanning.
H), the counter signal voltage supply circuit outputs a counter signal voltage V _com when the counter electrode is DC-driven.
As the time T1 from the initial position of the horizontal synchronization period.
Output V _com = V _st, and at time T 2 from the lapse of the time T 1 to the end of the horizontal synchronization period, V _com = V _st
A driving device for a liquid crystal display panel, which outputs ± ΔVc.