JP3150628B2 - Driving method of display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a display device used in a television or a video monitor, and more particularly to an improvement in display quality associated with a zoom function for enlarging a display.

[0002]

2. Description of the Related Art An active matrix type liquid crystal panel display device having a switching element for each display unit will be described as an example of a display device for displaying characters and images using a display material represented by liquid crystal.

FIG. 7 is a block diagram showing a conventional active matrix type liquid crystal panel display device.
In FIG. 7, reference numeral 6 denotes an image signal electrode line (S1 to Sm) for supplying a voltage corresponding to a display data signal to the pixel, and 7 denotes a scanning signal electrode line (X1) for supplying a scanning signal for performing line-sequential scanning. To Xn), 2 is a thin film transistor as a switching element controlled by a control voltage from the scanning signal electrode line 7 [hereinafter abbreviated as TFT], 3 is a liquid crystal display element as a display material, 4 is accumulated in the liquid crystal display element 3 An auxiliary capacitor for suppressing a decrease in the image voltage, a counter electrode for supplying a reference voltage to the liquid crystal display element, a source driver for supplying an image signal to each image signal electrode line, Reference numeral 10 denotes a gate driver that supplies a scanning signal to each scanning signal electrode line 7 to perform line-sequential scanning.

It is to be noted that one display pixel has one TFT 2
, A liquid crystal display element 3 and an auxiliary capacitor 4 are formed from display pixels 1 surrounded by a broken line, and an active matrix type liquid crystal panel 5 is constituted by a large number of pixels.

[0005] Image signal electrode line 6 and scanning signal electrode line 7
Are arranged in a matrix. On the other hand, the source terminal of the TFT 2 is connected to the image signal electrode line 6, the gate terminal is connected to the scanning signal electrode line 7, and the drain terminal is one of the liquid crystal display element 3 and the auxiliary capacitor 4. And the other electrode of the auxiliary capacitance 4 is T
Scan signal electrode line 7 to which the gate terminal of FT2 is connected
It is connected to the previous scanning signal electrode 7.

To display an image, a voltage corresponding to a display data signal is applied from a source driver 9 to each image signal electrode line 6.
To the source terminal of each TFT 2 via
A selected scanning voltage is supplied to the gate terminal of each TFT 2 via the scanning signal electrode line 7 selected by the gate driver 10. Thereby, each TF on the selected scanning signal electrode line is
T2 is simultaneously turned on, and each liquid crystal display element 3 and each storage capacitor 4 are turned on.
Then, a voltage corresponding to the display data signal is charged. As a result, the liquid crystal display element 3 receives an image signal voltage as image information which is a potential difference between the voltage charged in the liquid crystal display element 3 and the auxiliary capacitor 4 and the common reference voltage Vcom supplied to the common electrode 8. Stored. Even after the TFT 2 is turned off, the image information is held for one field period when the next information comes, so that an image with good contrast and excellent display quality can be displayed.

Incidentally, there is a zoom function for enlarging and displaying a screen in a manner of displaying image information. In order to perform the zoom function, it is particularly necessary to interpolate an image signal corresponding to the enlargement ratio in the vertical line direction. As a simple method, there is a method of displaying the same image signal on a plurality of vertical lines. . As a conventional example, there is a "method of driving a display device" described in JP-A-7-221371. Basically, it is related to drive control of the scanning signal electrode line 7 which is a vertical line,
FIG. 8 shows the driving method. Here, the vertical enlargement ratio is increased to 4/3 times by repeatedly selecting two of the scanning signal electrode lines 7 and displaying the same image signal once in three times in the line sequential scanning. It is.

Next, this driving operation will be described. In general, the gate reference voltage Vgl supplied to the scanning signal electrode line 7 and the common reference voltage Vcom supplied to the common electrode 8 are generally DC voltages, but here, the polarity is inverted every horizontal synchronization period (1H). And the gate reference voltage Vgl and the opposing reference voltage Vcom are supplied in an in-phase and synchronous relationship. In this figure, HD is a horizontal synchronizing signal, and Vgh is a selection gate voltage supplied to the gate terminal of the TFT 2 of the scanning signal electrode line 7 to be selected. The selection gate voltage Vgh and the gate non-selection reference voltage Vgl are supplied from the gate driver 10 as voltages switched to the respective scanning signal electrode lines. Now, the scanning signal electrode lines selected at the same time are <X2 and X3>, <X6 and X7>,... During the application period of the selection gate voltage Vgh supplied to the simultaneously selected scanning signal electrode lines, the scanning signal electrode line side <X2, X6,...> Where the auxiliary capacitor 4 and the gate terminal of the TFT 2 are connected is scanned in the other direction. The setting is shorter than the signal electrode line side <X3, X7,...>. This is for minimizing the effect of the falling change of the select gate voltage Vgh on the liquid crystal display element 3 via the storage capacitor 4. The scanning signal electrode line 7 performs line-sequential scanning for each horizontal period X1 → <X2, X3> → X4 → X5.
→ <X6, X7> → X8 →..., And the upper and lower display pixels in which the TFT 2 is controlled by the simultaneously selected scanning signal electrode lines of <X2 and X3>, <X6 and X7>,. Since the image signal voltage is applied, the display pixels on the simultaneously selected scanning signal electrode lines have the same display image. In this manner, since four scanning signal electrode lines are scanned in three scans, a zoom function in which the apparent display magnification is increased by 25% can be realized.

The image signal voltage finally charged in the liquid crystal display element 3 in such a simultaneously selected portion will be described with reference to FIGS. 7 and 9 with respect to X2 and X3 of the simultaneously selected scanning signal electrode lines. . In the panel configuration in which the auxiliary capacitance 4 is connected to the scanning signal electrode line 7, a change in the selection gate voltage Vgh in the preceding stage is capacitively coupled to the liquid crystal display element 3 via the auxiliary capacitance 4 to perform liquid crystal display. Element 3
A phenomenon occurs in which the voltage is changed. Now, as a capacitance related to a factor for changing the voltage of the liquid crystal display element, TF
The gate-drain capacitance Cgd of T2, the capacitance Cst of the auxiliary capacitance 4 itself, the capacitance Clc of the liquid crystal display element 3, and the stray capacitance Cs of the image signal electrode line 6 are listed. Although it depends on the panel design, the approximate capacitance ratio here is Cgd: Cst: Clc:
Cs = 1: 5: 5: 500, and select gate voltage value Vgh
Is assumed to be 30 V and the amplitude voltage of the gate reference voltage Vgl obtained by inverting 1H is 7 V.

Firstly, it decreases the degree of the charging voltage Vlc2 to the liquid crystal display device according to fall to enter the non-selection of their own selection gate voltage Vgh is represented by △ Va next _{△ Va = C cl / (Cgd} + Clc + Cst) * Vgh it can. This value is a phenomenon that occurs in common for all pixels, and therefore, this voltage change does not affect the quality such as display unevenness. On the other hand, the selection gate voltage Vgh is simultaneously applied to the scanning signal electrode lines X2 and X3, but the selection gate voltage Vgh2 on the scanning signal electrode line X2 is faster than the selection gate voltage Vgh3 on the scanning signal electrode line X3. Since the non-selection state is entered, the falling change of the selection gate voltage Vgh2 decreases the voltage of the liquid crystal display element 3 (X3 side) that is still in the selection period and is being charged via the auxiliary capacitor 4 (X3 side). . This final degree of reduction in the charging voltage Vlc3 to the liquid crystal display device according to the △ Vb becomes _{△ Vb = C cl / (Cgd} + Clc + Cst) * Vgh + Clc /
(Cgd + Clc + Cst + Cs) * Vgh. Here, the first item is a decrease due to the fall of the own selection gate voltage Vgh3, and the second item is a decrease that affects the selection gate voltage Vgh2 via the auxiliary capacitor 4 (X3 side). In the case of simultaneous selection, the same image signal is charged to each liquid crystal display element and should be Vlc2 = Vlc3. However, as can be seen from the equations of {Va, .DELTA.Vb},
Va <△ Vb. The potential difference ΔVab is ΔVab = ΔVa−ΔVb = −Clc / (Cgd + Clc + Cst + Cs) * Vgh ≒ −0.3V, and the charging voltage Vlc3 of the liquid crystal display element on the X3 side is X2.
It is about 0.3 V lower than the charging voltage Vlc2 of the liquid crystal display element on the side. In general, since the liquid crystal display element is driven at a low voltage of about 5 V, a display with a potential difference of 0.3 V is a level that is sufficiently recognized although the level is low. As a result, the liquid crystal display element on one of the simultaneously selected scanning signal electrode lines (here, X3, X7,...) Has a low charging voltage, so that the light-white horizontal line luminance unevenness (for the liquid crystal display element). When the applied voltage is zero, white display occurs). Therefore, as shown in FIG. 10, the display screen becomes a thin horizontal line luminance nonuniformity at a cycle of one out of four screens on the entire screen.

As an active matrix type liquid crystal panel, an example in which the gate terminal of the TFT 2 is connected to the m-th scanning signal electrode line 7 and the auxiliary capacitor 4 is connected to the (m-1) th scanning signal electrode line 7 (FIG. 7) Line sequential scanning from X1 to Xn
The gate terminal of the TFT 2 is connected to the (m-1) th scanning signal electrode line 7 and the auxiliary capacitor 4 is connected to the mth scanning signal electrode line 7 in the opposite direction. The same phenomenon applies to the configuration of the active matrix type liquid crystal panel (corresponding to the case where the line sequential scanning is performed in the direction from Xn to X1 in FIG. 7).

[0012]

As described above, in the above-described driving method, a thin horizontal line luminance unevenness occurs in the line of the simultaneous selection portion of the scanning signal electrode line, and a sufficient display quality cannot be obtained. Had.

In view of the foregoing, the present invention provides a driving method of a display device capable of suppressing a horizontal luminance unevenness and superimposing high-quality display by superimposing a correction voltage on a gate non-selection reference voltage Vgl or a counter reference voltage Vcom. The purpose is to do.

[0014]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention has a structure in which a storage capacitor is provided in a display pixel of a display panel, and one of the storage capacitors is connected to a scanning signal pole line. In the method of enlarging the screen of the display panel by repeating the partial selection of the scanning signal repeatedly, the selection gate voltage rises on one of the simultaneously selected scanning electrode lines during the period of simultaneously selecting the adjacent scanning signal electrode lines. The pixel voltage drop caused by the drop is canceled out by supplying a correction voltage variably controlled in the latter half of the simultaneous selection period of the gate non-selection reference voltage or the opposite reference voltage, so as to cancel out the operation. This makes it possible to reduce the horizontal line luminance unevenness of the thin line caused by the decrease in the pixel voltage during the simultaneous selection period to a level that is hardly noticeable.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a scanning signal electrode line and an image signal electrode line arranged in a matrix and each intersection of the scanning signal electrode line and the image signal electrode line. A pixel electrode having a display material interposed therebetween, an auxiliary capacitor electrically connected to the pixel electrode and formed so as to overlap a part of one of the adjacent scanning signal electrode lines, and the pixel signal electrode A switching element connected between the line and the pixel electrode and a disconnection control terminal connected to the scanning signal electrode line opposite to the side to which the auxiliary capacitance is connected, and corresponding to the pixel electrode with the display material interposed. A driving method for scanning a display device including counter electrodes arranged in a shape from a scanning signal electrode line side to which the auxiliary capacitance is connected, wherein a scanning selection voltage is supplied to the scanning signal electrode line at the time of selection, Selection Sometimes it is a line sequential scan in which a non-selection reference voltage is supplied, and has a period for simultaneously selecting adjacent scanning signal electrode lines, and an auxiliary capacitor is connected for a non-selection period of the scanning signal electrode lines after the simultaneous selection. The non-selection timing of the selected scanning signal electrode line side is set to t1 and the non-selection timing of the scanning signal electrode line connected to the switching element is set to t2 (where t1 <t2). The scanning is performed during a period from a timing t12 (t1 <t12 <t2) between the selection timing t1 and the non-selection timing t2 to a timing after the non-selection timing t2 and a timing t3 (t2 <t3 ≦ 1H) within one horizontal synchronization period (1H). The non-selection reference voltage of the signal electrode line or the reference voltage of the counter electrode is variably controlled.

According to this driving method, the falling of the selection gate voltage at the non-selection timing t1 on the side of the scanning signal electrode line connected to the auxiliary capacitance, which occurs during the scanning period when a plurality of scanning signal electrode lines are simultaneously selected. The effect of the voltage change occurring at the time when the image signal voltage of the display element on the side of the scanning signal electrode line connected to the switching element is reduced is reduced in the period after the non-selection timing t1. The variable voltage ΔVc is changed by the auxiliary capacitor to offset the variable voltage ΔVc with the voltage of the image signal voltage drop of the display element on the side of the scanning signal electrode line connected to the switching element. By supplying a voltage that is variably controlled so as to have a voltage amplitude in various directions, the horizontal line luminance unevenness of the thin line generated during the simultaneous selection period can be reduced to a level that is hardly noticeable. Those that can be good.

According to a second aspect of the present invention, in the first aspect, the scanning signal on the side where the switching element is formed is used instead of the driving method when scanning is performed from the side of the scanning signal electrode on the side where the auxiliary capacitance is formed. This is a driving method when scanning from the electrode side.

According to a third aspect of the present invention, in the first or second aspect, a sample-and-hold circuit of two systems per output is used as a source driver for supplying an image signal voltage to an image signal electrode line of a display device. In the case of using a two-sample hold type source driver having the above, the reference voltage of only the scanning signal electrode line, only the counter electrode, or both the scanning signal electrode and the counter electrode is variably controlled.

According to a fourth aspect of the present invention, in the third aspect, the reference voltage of the scanning signal electrode line and the counter electrode is converted into a voltage having a voltage amplitude Va which is inverted every horizontal synchronization period and every vertical synchronization period. On the other hand, the voltage amplitude Vb during the variable control period
Is set to Vb> Va.

According to a fifth aspect of the present invention, when the average DC voltage level of the voltage amplitude during the variable control period is VbDC and the average DC voltage level during the voltage amplitude Va period is VDC, ≠ VaDC.

According to a sixth aspect of the present invention, in the first or second aspect, a sample-and-hold circuit having one system per output as a source driver for supplying an image signal voltage to an image signal electrode line of a display device. When a one-sample-and-hold type source driver having the above is used, the reference voltage of only the scanning signal electrode line is variably controlled.

According to a seventh aspect of the present invention, in the sixth aspect, the reference voltage of the scanning signal electrode line and the counter electrode is inverted to a voltage of a voltage amplitude Va for each horizontal synchronization period and each vertical synchronization period. On the other hand, the voltage amplitude Vb during the variable control period
Is set to Vb <Va.

According to an eighth aspect of the present invention, in the seventh aspect, the average DC voltage level of the voltage amplitude during the variable control period is VbDC, and the average DC voltage level during the voltage amplitude Va period is VaD.
When C is set, the relationship is VbDC ≠ VaDC.

According to a ninth aspect of the present invention, in accordance with the seventh or eighth aspect, the reference voltage of the common electrode is inverted with respect to the voltage having the voltage amplitude Va obtained by inverting the reference voltage for each horizontal synchronization period and each vertical synchronization period. In the correction period in which the voltage is lower than the center voltage of the main voltage amplitude Va, a monotonically decreasing sawtooth voltage is supplied.

(Embodiment 1) FIG. 1 shows a method of driving a display device using liquid crystal according to a first embodiment of the present invention. In particular, FIG. 1 shows a source driver having two systems of sample and hold circuits per output. This is an example of a display panel using a sample hold type. In FIG. 1, (a) is a horizontal synchronizing signal HD, and (b) is a selection gate voltage Vgh supplied to the X2 and X3 lines (see FIG. 7) of the simultaneously selected scanning signal electrode lines and a gate non-selection superimposed thereon. The voltage waveform at the time of n fields with the reference voltage Vgl, and (c) at the time of the n + 1 fields with the selection gate voltage Vgh supplied to the X2 and X3 lines of the simultaneously selected scanning signal electrode lines and the gate non-selection reference voltage Vgl superimposed on it. The solid line indicates the waveform supplied to the X2 line, and the dashed line indicates the waveform supplied to the X3 line. (d) is a gate non-selection reference voltage Vgl whose polarity is inverted every horizontal synchronization period (1H) and vertical synchronization period (1V) supplied to the scanning signal electrode line, and (e) is supplied to the counter electrode. An opposite reference voltage Vcom, which is inverted in polarity every horizontal synchronization period (1H) and every vertical synchronization period (1V) and has the same phase relationship as the gate non-selection reference voltage Vgl;
(f) is a zoom correction control signal Zoom-C for varying the gate non-selection reference voltage Vgl during the period of the simultaneously selected scanning signal electrode line, and (g) is the gate non-selection reference voltage Vgl.
The polarity inversion signal POL is obtained by inverting the polarity every horizontal synchronization period (1H) and every vertical synchronization period (1V) from which the common reference voltage Vcom is generated.

The operation will be described below. The horizontal synchronization period (1H) selected simultaneously is indicated by t0 to t3, where t0 is the start point of the selection gate voltage Vgh, and t1 is the scanning signal electrode line X2.
End point of the selection gate voltage Vgh, t2 is the scanning signal electrode line X
3, the end point of the selection gate voltage Vgh, t3 is the end point of one horizontal synchronization period, and t12 is the start point of the variable control of the gate non-selection reference voltage Vgl. As described above, the selection gate voltage application period T1 of the scanning signal electrode line X2 is shorter than the selection gate voltage application period T2 of the scanning signal electrode line X3 (T1 <T
2). The correction is performed during the period T3 from t12 to t3, and the gate non-selection reference voltage V is supplied by the zoom correction control signal Zoom-C.
This is performed by variably controlling the voltage amplitude of gl.

First, the correction of the scanning signal electrode line X3 in which a thin line occurs in the n-th field shown in FIG. The gate non-selection reference voltage when performing simultaneous selection is
For the main amplitude voltage Va, the correction voltage amplitude during the correction period is △ Vc1
Decrease. At this time, when the change in the voltage at the change point related to the time after the non-selection on the scanning signal electrode line X2 is seen, t12
−Vc1 at t3, − (Va−ΔVc1) at t3, and + Va at t4, and the total voltage change is −ΔVc1− (Va− △
Vc1) + Va = 0. As a result, the effect of the decrease ΔVc1 of the correction voltage does not occur in the display pixels on the scanning signal electrode line X2. On the other hand, looking at the change in the voltage at the change point after the non-selection on the scanning signal electrode line X3,-(Va- △ Vc1) at t3, + Va at t4, and the total voltage change is-(Va- ΔVc1) + Va = + ΔVc1
Becomes The effect of the voltage change on the display pixel on the scanning signal electrode line X3 appears in the form of the capacitance ratio in the pixel as shown in the conventional example. When the TFT is not selected, the TFT is in a cut-off state. Therefore, the relevant capacitances are the gate / drain capacitance Cgd of the TFT 2, the Cst of the auxiliary capacitance 4, and the capacitance Clc of the liquid crystal display element 3 shown in FIG. Thus, the voltage change ΔV to the liquid crystal display element 3 is ΔV = + ΔVc1 * Clc / (Cst + Cgd
+ Clc), and as described above, the respective capacitance ratios are Cgd: C
Assuming that lc: Cst = 1: 5: 5, {V} + 0.45 *
It becomes a voltage value in the increasing direction of ΔVC1. This means that in the conventional example, correction can be made so that the display pixels on the scanning signal electrode line X3 can be canceled against a decrease of ΔVab = ΔVa−ΔVb = −Clc / (Cgd + Clc + Cst + Cs) * Vgh ≒ −0.3V. It is shown that. From this, the correction voltage amplitude △ Vc1 to be reduced is | △ V | = 0.45 * △ Vc1 = | △ Vab | = 0.3
Therefore, ΔVc1 ≒ 0.7V.

Next, the same applies to the (n + 1) -th field shown in FIG. The gate non-selection reference voltage at the time of performing the simultaneous selection reduces the correction voltage amplitude during the correction period by ΔVc2 with respect to the main amplitude voltage Va. At this time, the scanning signal electrode line X2
Looking at the change in the voltage at the change point after the non-selection time, the voltage at -12 is-△ Vc2 at t12, + (Va + △ Vc2) at t3, and -Va at t4, and the voltage change as a whole is-△ Vc2 +
(Va + △ Vc2) −Va = 0. As a result, the influence of the decrease ΔVc2 of the correction voltage is caused by the scan signal electrode line X2
It does not occur in the upper display pixel. On the other hand, the scanning signal electrode line X
Looking at the change in the voltage at the change point after the non-selection time in 3, the voltage becomes + (Va + △ Vc2) at t3 and −Va at t4.
The voltage change as a whole is + (Va + cVc2) −Va
= + △ Vc2, and this voltage change is equivalent to the scanning signal electrode line X
It is clear that the voltage increases in the increasing direction to the upper display pixel. However, in this case, as can be seen from the waveforms (b) and (c), the change (Vgh) of the selection gate voltage on the scanning signal electrode line X2 side in the (n + 1) th field is the change (Vgh-Va) in the nth field. ), The correction voltage ΔVc2 needs to be higher than ΔVc1.

From this, the voltage amplitude between the fields is equal to the main voltage amplitude Va, whereas the correction voltage amplitude Vb is Vb = V
a−ΔVc1 + ΔVc2> Va. Also, when viewed between fields, the center voltage of the voltage amplitude Vb in the correction period is shifted below Vc1 with respect to the center voltage of the main voltage amplitude Va, but the result of the actual experiment is the voltage in the correction period. Even if the center voltage of the amplitude Vb was matched with the center voltage of the main voltage amplitude Va, there was no particular problem. However, as a correction effect, it is better to perform both the correction voltage amplitude adjustment and the center voltage adjustment of the correction voltage amplitude. More precise correction was possible. Also,
The start point t12 of the variable control of the gate non-selection reference voltage Vgl is brought within the selection gate voltage period (t0 to t1) of the scanning signal electrode line X2 to the display pixel on the scanning signal electrode line X2 side. ΔVc1 for n fields and ΔVc2 for n + 1 fields affect the rate of change in the increasing direction. This line is a light black horizontal luminance unevenness line (white display when the voltage applied to the liquid crystal display element is zero). ), And the display quality is rather deteriorated. For this reason, the start point t12 of the variable control of the gate non-selection reference voltage Vgl is set to an intermediate point between the end point t1 of the select gate voltage Vgh of the scan signal electrode line X2 and the end point t2 of the select gate voltage Vgh of the scan signal electrode line X3. It was best to do.

Here, a method of controlling the gate non-selection reference voltage Vgl has been described as a variable control method of the correction voltage.
Experimental evaluations have shown that the same correction effect can be obtained by performing the same variable control with the opposite reference voltage Vcom or the simultaneous variable control of the gate non-selection reference voltage Vgl and the opposite reference voltage Vcom. In this case, the amounts of the correction voltages .DELTA.Vc1 and .DELTA.Vc2 are the same in the control method of the gate non-selection reference voltage Vgl and the control method of the opposite reference voltage Vcom, and the simultaneous variable control method of the gate non-selection reference voltage Vgl and the opposite reference voltage Vcom. In this case, the value was の of the single control method.

FIG. 2 shows a specific example of the correction circuit according to the first embodiment. The gate non-selection reference voltage Vgl
And the simultaneous variable control of the common reference voltage Vcom. Here, 14 is an output buffer for supplying the opposite reference voltage Vcom, 15 is an output buffer for supplying the gate non-selection reference voltage Vgl, 16 is an operational amplifier for amplifying the polarity inversion signal POL, and 17 is an analog switch for switching the gain of the operational amplifier 16 And 18 are analog switches for switching the DC bias voltage level of the operational amplifier 16. During periods other than the correction period, the DC voltage determined by the resistors R3 and R4 is supplied to the operational amplifier 16 via the analog switches 1 to 3 and the resistor that determines the gain of the operational amplifier 16 is connected to the contact 1 of the analog switch 17 3 is connected, the gain G1 is applied to the output buffers 14 and 15 via the capacitors in common with the 1H polarity inversion signal POL of the amplified amplitude voltage Va of G1 = R2 / R1. The other is supplied to the display panel as the opposite reference voltage Vcom as the voltage Vgl. on the other hand,
In the correction period of the simultaneous selection period, when the zoom correction control signal Zoom-C for correcting the thin line is supplied, the analog switches 16 and 17 are switched from the contact 1 to the contact 2, so that the DC bias voltage can be changed by the variable resistor VR2. The gain G2 changes to the amplified voltage amplitude Vb of G2 = (R2 + VR1) / R1. Here, the variable resistance V
The gain by R1 covers the increased voltage (電 圧 Vc1 + △ Vc2) from the main voltage amplitude Va in the correction voltage amplitude Vb. Since the gain G2 is always larger than the gain G1, the output voltage also has a relationship of Vb> Va. The adjustment method for the correction is the optimum correction voltage amplitude V by adjusting the variable resistor VR1.
b (△ Vc1 + Va + △ Vc2), and then the voltage amplitude Vb is applied to the variable resistor VR2 for DC bias voltage adjustment.
May be adjusted so as to be shifted by Vc1 below the center voltage of the voltage amplitude Va. By such a correction, it is possible to reduce the horizontal line luminance unevenness of the thin line generated during the simultaneous selection period to a level that is hardly noticeable.

(Embodiment 2) FIG. 3 shows a driving method of a liquid crystal display device according to a second embodiment of the present invention. In particular, a source driver has one sample-hold circuit per output as one source. This is an example of a display panel using a sample hold type. In a display panel using a one-sample-hold type source driver, when the selection gate voltage Vgh is applied to the scanning signal electrode line 7, the supply of the image signal voltage from the source driver is performed only during the retrace period in the horizontal synchronization period. Thereafter, the image signal voltage charged in the stray capacitance Cs of the image signal electrode line 6 becomes T
It becomes the supply voltage during the application period of the selection gate voltage of FT2.
Therefore, when the scanning signal electrode lines 7 are simultaneously selected, the falling change of the selection gate voltage Vgh2 causes the auxiliary capacitance 4 (X
As shown in FIG. 9, the voltage of the liquid crystal display element 3 (X3 side) during charging, which is still in the selection period, is reduced via the third side), but the voltage of the image signal charged in the stray capacitance Cs is reduced. Is low in the current supply capability to the TFT 2 connected to X3 of the scanning signal electrode line 7, the final image voltage charged in the liquid crystal display element 3 is lower than when the above-described two-sample-hold type source driver is used. Resulting in. Therefore, it is necessary to increase the correction amount for the correction voltage for suppressing the thin line. The difference from FIG. 1 is the correction voltage amplitude and the average DC voltage level during the correction period of the gate non-selection reference voltage Vgl shown in (d).

The correction of the scanning signal electrode line X3 in which a thin line occurs in the n-th field shown in FIG. Here, the solid line shows the waveform of the X2 line, and the dashed line shows the waveform of the X3 line. The gate non-selection reference voltage when the simultaneous selection is performed reduces the correction voltage amplitude in the correction period by ΔVc3 with respect to the main amplitude voltage Va. At this time, looking at the change in voltage at the change point after the non-selection time on the scanning signal electrode line X2,-△ Vc3 at t12,-(Va- △ Vc3) at t3, and + (Va- △ Vc3) at t4.
Va, and the total voltage change is − 全体 Vc3−
(Va− △ Vc3) + Va = 0. On the other hand, looking at the voltage at the changing point of the scanning signal electrode line X3 after the non-selection, the voltage becomes − (Va−ΔVc3) at t3 and + Va at t4, and the total voltage change is − (Va−ΔVc3). ) +
Va = + △ Vc3. This voltage operates to cancel the drop of the display pixel on the scanning signal electrode line X3 as described in FIG.

Next, the same applies to the (n + 1) -th field shown in (c). The solid line shows the waveform of the X2 line, and the dashed line shows the waveform of the X3 line. The gate non-selection reference voltage at the time of performing the simultaneous selection increases the correction voltage amplitude in the correction period by ΔVc4 with respect to the main amplitude voltage Va. At this time, looking at the change in the voltage at the changing point after the non-selection time on the scanning signal electrode line X2, + (Va- △ Vc4) at t12, + △ Vc4 at t3, and-△ at t4.
Va, and the voltage change as a whole is + (Va− △
Vc4) + △ Vc4−Va = 0. As a result, the effect of the decrease ΔVc2 of the correction voltage does not occur on the display pixels on the scanning signal electrode line X2. On the other hand, looking at the change in the voltage at the change point after the non-selection on the scanning signal electrode line X3, it becomes + ΔVc4 at t3, and this voltage change is applied to the display pixels on the scanning signal electrode line X3 in the increasing direction. It is clear that the value contributes. However, in this case, as can be seen from the waveforms (b) and (c), the change (Vgh) of the selection gate voltage on the scanning signal electrode line X2 side in the (n + 1) th field is the change (Vgh-Va) in the nth field. ), The correction voltage ΔVc4 needs to be higher than ΔVc3.

From this, the voltage amplitude between fields is such that the correction voltage amplitude Vb is Vb =
(Va- △ Vc3)-(Va- △ Vc4) = △ Vc4- △ Vc3
> Va. Also, when viewed between fields,
The center voltage of the voltage amplitude Vb during the correction period is shifted above Vc2 with respect to the center voltage of the main voltage amplitude Va, but the result of an actual experiment shows that the center voltage of the voltage amplitude Vb during the correction period is the main voltage amplitude. There was no particular problem even if the center voltage of Va was made to coincide with the center voltage, but as a correction effect, more precise correction was possible by performing both the correction voltage amplitude adjustment and the center voltage adjustment of the correction voltage amplitude. .

FIG. 4 shows a specific example of a correction circuit according to the second embodiment, and shows a gate non-selection reference voltage Vgl.
This is a case in which variable control is performed on. The basic operation is the same as that of the specific correction circuit in the first embodiment shown in FIG. Here, an operational amplifier 11 that supplies an independent main voltage amplitude Va and an operational amplifier 1 that supplies a correction voltage amplitude Vb
And an output buffer 15 via an analog switch 13 whose output is controlled by a zoom correction control signal Zoom-C.
The gate non-selection reference voltage Vgl is supplied to the display panel. On the other hand, the opposing reference voltage Vcom is produced by directly putting the output from the operational amplifier 11 into the output buffer 14. By such correction, the horizontal line luminance unevenness of the thin line generated during the simultaneous selection period can be reduced to an inconspicuous level.

In a display panel using a one-sample-and-hold type source driver, a correction method that contributes to the correction effect with respect to the opposing reference voltage Vcom has been found from experimental studies. FIG. 5 shows the timing and FIG. 6 shows a specific example of the correction circuit. In FIG. 5, (c) shows the opposite reference voltage V
com is a correction voltage waveform, and the correction period T is only for a period in which the reference voltage is lower than the center voltage of the main voltage amplitude Va in the simultaneous selection period (n + 1 field in the figure).
3, a correction voltage is applied to make the correction voltage amplitude ΔVc5 monotonically decrease in a sawtooth shape. By applying such a correction voltage, the potential of the opposite reference voltage Vcom is raised by the correction voltage amplitude ΔVc5 with respect to the gate non-selection reference voltage Vgl, so that the reduction of the display pixels on the scanning signal electrode line X3 is canceled. It is thought to work for. This control is shown in FIG.
In combination with the control of the gate non-selection reference voltage Vgl, the unevenness of the horizontal line luminance of thin lines generated during the simultaneous selection period can be further reduced to an inconspicuous level.

FIG. 6 is a specific example of a correction circuit for the common reference voltage Vcom. The correction is performed by the output buffer circuit 14 shown in FIG.
Perform at The output buffer circuit 14 ′ for performing the correction control is 2
It consists of a complementary configuration circuit of stages. The final output stage includes output transistors Tr1 and Tr2 and output resistors R5 and R5.
It consists of six. Here, while the reference voltage of the output transistor Tr1 and the output resistor R5 is higher than the center voltage of the main voltage amplitude Va, the reference voltage of the output transistor Tr2 and the output resistor R6 is lower than the center voltage of the main voltage amplitude Va. Output voltage during the period. The correction circuit 16 for the opposing reference voltage Vcom includes a variable resistor VR3 connected in series with the output resistor R6, and a transistor Tr3 connected in parallel with the variable resistor VR3. As the resistance value of the variable resistor VR3, a resistance value that is one or two digits larger than that of the output resistor R6 was effective. The transistor Tr3 is controlled by the zoom correction control signal Zoom-C. When the control signal is input, the transistor Tr3 is turned off, so that the substantial output resistance of the output transistor Tr2 is R6 + from the relation of R66VR3.
VR3 ≒ VR3, which greatly increases. On the other hand, when there is no control signal, the transistor Tr3 is turned on and the variable resistance
Since VB3 is shorted, the effective output resistance of output transistor Tr2 returns to the normal value of R6. As described above, by significantly increasing the charging time constant to the capacity load during the correction period T3,
The charging capacity is limited and the correction voltage amplitude ΔVc5
Can be a monotonically decreasing sawtooth-shaped correction voltage. In the first and second embodiments including the conventional example, the gate non-selection reference voltage Vgl and the opposing reference voltage Vcom are driven by voltages whose polarity is inverted every horizontal synchronization period (1H) and every vertical synchronization period (1V). Although the method has been described, even if a simple DC voltage is used as a reference voltage instead of such an inversion voltage, a correction that should be controlled in a correction period to cancel the drop of the display pixels on the scanning signal electrode line X3 is cancelled. It goes without saying that the voltage requires the driving method of the present invention. Further, as a configuration of the active matrix type liquid crystal panel, the gate terminal of the TFT 2 is the nth of the scanning signal electrode line 7, and the auxiliary capacitance 4 is the n−1 of the scanning signal electrode line 7.
In the example shown in the second connection, the reverse TFT2
It is needless to say that the present invention is also effective in a configuration of an active matrix type liquid crystal panel in which the gate terminal is connected to the (n-1) th scanning signal electrode line 7 and the storage capacitor 4 is connected to the nth scanning signal electrode line 7. Absent.

[0039]

As described above, according to the present invention,
Simultaneous selection of partial scanning signal electrode lines for zoom display as a screen enlargement function of a display panel having a configuration in which an auxiliary capacitance is provided in a display pixel of the display panel and one of the auxiliary capacitances is connected to the scanning signal electrode lines In the method performed by repeating, a pixel non-selection reference voltage or a reduction in pixel voltage caused by the fall of the selection gate voltage in one of the simultaneously selected scanning electrode lines during a period in which adjacent scanning signal electrode lines are simultaneously selected. By supplying a correction voltage that is variably controlled in the latter half of the simultaneous selection period of the opposing reference voltage and acting in the direction of canceling out, the horizontal line luminance unevenness of the thin line generated due to a decrease in the pixel voltage during the simultaneous selection period is almost eliminated. The improvement can be made to an inconspicuous level, a high-quality image display can be provided, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a timing chart of a drive waveform for suppressing a horizontal thin line during zooming in a first embodiment of the present invention (a liquid crystal panel using a two-sample-hold source driver).

FIG. 2 is a specific example of a correction circuit for suppressing a horizontal thin line during zooming according to the first embodiment;

FIG. 3 is a timing chart of a driving waveform for suppressing a horizontal thin line at the time of zooming in a second embodiment of the present invention (a liquid crystal panel using a one-sample-and-hold source driver).

FIG. 4 is a specific example of a correction circuit for suppressing a horizontal thin line during zooming according to the second embodiment;

FIG. 5 is a timing chart of an opposing reference voltage for improving a horizontal thin line during further zooming according to the second embodiment;

FIG. 6 is a specific example of an output circuit of an opposing reference voltage for improving a horizontal thin line during further zooming according to the second embodiment;

FIG. 7 is a configuration diagram of a conventional liquid crystal display panel.

FIG. 8 is a timing chart of a driving waveform during a zoom function operation in a conventional example.

FIG. 9 is an explanatory diagram of a charging voltage for a pixel on a scanning signal electrode line selected at the time of a zoom function operation in a conventional example.

FIG. 10 is an explanatory diagram showing a display state when a zoom function is operated in a conventional example.

[Explanation of symbols]

 2 Switching element (TFT) 3 Liquid crystal display element 4 Auxiliary capacitance 6 Image signal electrode line 7 Scanning signal electrode line 8 Counter electrode 11, 12, 16 Operational amplifier 13, 17, 18 Analog switch

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-53141 (JP, A) JP-A-4-351183 (JP, A) JP-A-4-145490 (JP, A) JP-A-3-53 168617 (JP, A) JP-A-2-913 (JP, A) JP-A-64-72122 (JP, A) JP-A 64-26822 (JP, A) JP-A-6-273720 (JP, A) JP-A-10-39277 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 550 G09G 3/36

Claims (9)

(57) [Claims] 1. A scanning signal electrode line and an image signal electrode line arranged in a matrix, and a pixel electrode interposed with a display material disposed close to each intersection of the scanning signal electrode line and the image signal electrode line. An auxiliary capacitor electrically connected to the pixel electrode and formed so as to overlap with a part of one of the adjacent scanning signal electrode lines, and the pixel signal electrode line and the pixel electrode connected and the disconnection control terminal are connected to each other. A display device comprising a switching element connected to a scanning signal electrode line opposite to a side to which an auxiliary capacitance is connected, and a counter electrode arranged in a form corresponding to a pixel electrode with the display material interposed therebetween. A driving method for scanning from the side of the scanning signal electrode line to which the storage capacitor is connected, wherein a scanning selection voltage is supplied to the scanning signal electrode line when selected, and a non-selection reference voltage is supplied to the scanning signal electrode line when not selected. Scanning, having a period for simultaneously selecting adjacent scanning signal electrode lines, and
The storage capacitor is connected during the non-selection period of the scanning signal electrode line.
The non-selection timing on the scanning signal electrode line side on the
The scanning signal electrode line on the side connected to the switching element
The non-selection timing on the side is defined as t2 (where t1 <t2).
And the non-selection timing t1 and the non-selection time
T12 between the timings t2 (t1 <t12 <t2)
From the non-selection timing t2 and one horizontal synchronization period
(1H) A non-selection reference voltage of the scanning signal electrode line or a reference voltage of the counter electrode is variably controlled during a timing t3 (t2 <t3 ≦ 1H) in (1H). How to drive the device. 2. A driving method in which scanning is performed from a scanning signal electrode side on which a switching element is formed, instead of a driving method when scanning is performed from a scanning signal electrode side on which an auxiliary capacitance is formed. The method for driving a display device according to claim 1. 3. When a two-sample-hold type source driver having two sample-hold circuits per output is used as a source driver for supplying an image signal voltage to an image signal electrode line of a display device, only a scanning signal electrode line is used. 3. The display device driving method according to claim 1, wherein a reference voltage of only the counter electrode or a reference voltage of both the scanning signal electrode and the counter electrode is variably controlled. 4. A voltage amplitude V in a variable control period with respect to a voltage amplitude Va obtained by inverting a reference voltage of a scanning signal electrode line and a counter electrode for each horizontal synchronization period and each vertical synchronization period.
4. The method according to claim 3, wherein b is Vb> Va. 5. The relationship of VbDC ≠ VaDC when the average DC voltage level of the voltage amplitude during the variable control period is VbDC and the average DC voltage level during the voltage amplitude Va period is VaDC. Driving method of a display device. 6. When a one-sample-hold type source driver having one sample-hold circuit per output is used as a source driver for supplying an image signal voltage to an image signal electrode line of a display device, only a scanning signal electrode line is used. 3. The method according to claim 1, wherein the reference voltage is variably controlled. 7. A voltage amplitude V in a variable control period with respect to a voltage amplitude Va obtained by inverting a reference voltage of a scanning signal electrode line and a counter electrode for each horizontal synchronization period and each vertical synchronization period.
7. The method according to claim 6, wherein b is Vb <Va. 8. The relationship of VbDC ≠ VaDC when the average DC voltage level of the voltage amplitude during the variable control period is VbDC and the average DC voltage level during the voltage amplitude Va period is VaDC. Driving method of a display device. 9. A voltage having a voltage amplitude Va obtained by inverting the reference voltage of the common electrode for each horizontal synchronization period and each vertical synchronization period, decreases monotonously in a correction period in which the voltage is lower than the center voltage of the main voltage amplitude Va. 9. The method according to claim 7, wherein a sawtooth voltage is supplied.