JP5172476B2 - Intermediate product of multilayer wiring board, manufacturing method of multilayer wiring board - Google Patents

Description

  The present invention relates to an intermediate product of a multilayer wiring board comprising a product forming region in which a plurality of product parts to be products are arranged along the plane direction, and a frame part surrounding the product forming region, and a multilayer wiring substrate The present invention relates to a method for producing a multilayer wiring board obtained from the intermediate product.

  As one of techniques for efficiently producing a wiring board, a technique of taking a large number of pieces is well known. Here, multi-cavity is a technique for obtaining a plurality of products from an intermediate product on a single wiring board. Usually, such an intermediate product has a plurality of product portions that are to be products arranged in a plane direction. The product forming region and a frame portion surrounding the product forming region. In addition, while the product part side conductor layer is formed in the surface about the product part which should become a product, the conductor layer was not formed on the surface conventionally about the frame part which does not become a product. However, in recent years, for the purpose of reducing warpage or the like, a dummy conductor layer (frame portion side conductor layer) made of plating may be provided in a solid shape on the surface of the frame portion. Moreover, what formed such a frame part side conductor layer in the mesh shape instead of the solid shape is also known conventionally (for example, refer patent document 1).

  As an intermediate product of a wiring board, an intermediate product of a multilayer wiring board in which a buildup layer is formed on the front surface and the back surface of a core substrate has been put into practical use. In the intermediate product of this multilayer wiring substrate, for example, a resin substrate (glass epoxy substrate or the like) in which a reinforcing fiber is impregnated with a resin is used as the core substrate. Then, by utilizing the rigidity of the core substrate, a buildup layer is formed by alternately laminating a resin insulating layer and a conductor layer on the front surface and the back surface of the core substrate. That is, in the intermediate product of the multilayer wiring board, the core board plays a role of reinforcement and is formed much thicker than the build-up layer. In addition, wiring (specifically, a through-hole conductor or the like) is formed through the core substrate for conduction between buildup layers formed on the front surface and the back surface. Furthermore, a semiconductor integrated circuit element (IC chip) used as a computer microprocessor or the like can be mounted on the intermediate product of the multilayer wiring board.

By the way, in recent years, with the increase in the speed of semiconductor integrated circuit elements, the signal frequency used has become a high frequency band. In this case, the wiring penetrating the core substrate contributes as a large inductance, leading to transmission loss of high-frequency signals and circuit malfunction, which hinders speeding up. In order to solve this problem, it has been proposed that the multilayer wiring board is a coreless wiring board that does not have a core board (see, for example, Patent Document 2). This coreless wiring board shortens the overall wiring length by omitting the relatively thick core board, so that the transmission loss of high-frequency signals is reduced and the semiconductor integrated circuit element can be operated at high speed. It becomes.
Japanese Unexamined Patent Publication No. 2007-180212 (see FIG. 1, FIG. 2, etc.) Japanese Patent No. 3664720

  However, since the coreless wiring substrate is manufactured by omitting the core substrate, the strength cannot be sufficiently ensured. Therefore, when the multilayer wiring board is a coreless wiring board, the strength of the intermediate product of the multilayer wiring board cannot be ensured even if the above-mentioned frame side conductor layer is provided on the surface of the frame. As a result, for example, when a semiconductor integrated circuit element or a chip capacitor is bonded to an intermediate product, when the solder used for the bonding is cooled, the heat caused by the difference in thermal expansion coefficient between the product formation region and the frame portion Since the intermediate product is warped under the influence of stress, the yield of the multilayer wiring board is lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an intermediate product of a multilayer wiring board capable of preventing warpage and improving product yield. Another object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of improving the yield.

  And as a means (means 1) for solving the above-mentioned problem, it has a structure in which a plurality of resin insulation layers are laminated, and a product forming region in which a plurality of product parts to be products are arranged along the plane direction; A frame portion surrounding the periphery of the product formation region, and formed on the main surface of each resin insulation layer as a conductor layer in the product portion side conductor layer formed in the region in the product portion and in the region in the frame portion And an intermediate product of the multilayer wiring board provided with the frame portion side conductor layer, wherein the area ratio of the product portion side conductor layer in the product formation region is not the same, and the area occupied in the product formation region is As the area ratio of the product part side conductor layer is larger, the area ratio of the frame part side conductor layer occupying the frame part existing in the same plane is set smaller, and the conductor occupying the main surface of the resin insulation layer The area ratio of the layer, the product formation There is an intermediate product of a multilayer wiring board, characterized in that set between the maximum value and the minimum value of the area ratio of the product portion side conductor layer to the range.

  Therefore, according to the intermediate product of the multilayer wiring board of means 1, the area ratio of the conductor layer occupying the main surface of the resin insulating layer is the highest value and the lowest value of the area ratio of the product part side conductor layer occupying the product formation region. Therefore, the variation in the area ratio of the conductor layer in the main surface of the resin insulating layer of each layer is reduced. As a result, the difference in thermal expansion coefficient of each layer is reduced, and the thermal stress due to the difference in thermal expansion coefficient is also reduced, so even when the above-described thermal stress is applied when connecting a component to the product side conductor layer, Intermediate products are less likely to warp. Therefore, the yield of products obtained from intermediate products can be improved.

As another means (means 2) for solving the above-mentioned problem, there is a product formation region having a structure in which a plurality of resin insulating layers are laminated, and a plurality of product parts to be products are arranged along the planar direction. A frame portion surrounding the periphery of the product formation region, and formed on the main surface of each resin insulation layer as a conductor layer in the product portion side conductor layer formed in the region in the product portion and in the region in the frame portion Frame portion side conductor layer is provided , and has a structure in which the resin insulation layer and the product portion side conductor layer in the region in the product portion are alternately laminated, and the same resin insulation layer is mainly formed. And an intermediate product of a multilayer wiring board in which each product part side conductor layer is connected only by vias whose diameters are expanded in the same direction, wherein the product on at least one resin insulation layer of the plurality of resin insulation layers In the area inside the frame, A plurality of slit-shaped non-forming region Kiwaku side conductor layer is not present is disposed on an extension of the cutting line that is set along the outline of the product portion, said product portion occupied in the product forming region The area ratio of the conductor layer is not the same, and the larger the area ratio of the product part side conductor layer in the product forming region, the larger the area of the frame part side conductor layer in the frame part existing in the same plane. There is an intermediate product of a wiring board characterized in that the ratio is set small, and the variation in the area ratio of the conductor layer occupying the main surface of the resin insulating layer is set within 15%.

  Therefore, according to the intermediate product of the multilayer wiring board of the means 2, the variation in the area ratio of the conductor layer occupying the main surface of the resin insulating layer is set within 15% and becomes small. As a result, the difference in thermal expansion coefficient of each layer is reduced, and the thermal stress due to the difference in thermal expansion coefficient is also reduced, so even when the above-described thermal stress is applied when connecting a component to the product side conductor layer, Intermediate products are less likely to warp. Therefore, the yield of products obtained from intermediate products can be improved.

  Here, “the area ratio of the product part side conductor layer in the product formation region” means the ratio (exposure) of the product part side conductor layer in the region when a predetermined region is set on the surface of the product formation region. Ratio). Similarly, “the area ratio of the frame-side conductor layer in the frame portion” is the ratio (exposure ratio) of the frame-side conductor layer in that region when a predetermined region is set on the surface of the frame portion. It shall be said. Furthermore, “the area ratio of the conductor layer in the main surface of the resin insulating layer” is the ratio (exposure ratio) of the conductor layer in the region when a predetermined region is set in the main surface of the resin insulating layer. It shall be said.

  The area ratio of the frame portion side conductor layer in the frame portion should not be limited, but is preferably set to, for example, 50% or more. If the area ratio of the frame side conductor layer is less than 50%, the difference in thermal expansion coefficient between the product formation region and the frame increases, and the thermal stress resulting from the difference in thermal expansion coefficient also increases. There is a possibility that the intermediate product is warped under the influence of stress.

  In addition, it is preferable to set so that all the area ratios of the said conductor layer which occupy for the main surface of the said resin insulation layer may become the same. In this way, there is almost no variation in the area ratio of the conductor layer occupying the main surface of the resin insulating layer, so that the thermal expansion coefficient of each layer can be made substantially constant. Therefore, since the thermal stress generated due to the difference in thermal expansion coefficient of each layer becomes almost zero, the warp of the intermediate product due to the thermal stress can be extremely reduced. “The area ratio of the conductor layer occupying the main surface of the resin insulation layer is set to be all the same” means that the area ratio is almost the same, and the area ratio is substantially the same. It also includes what has been done.

  Further, the multilayer wiring board does not have a core substrate, and has a structure in which the resin insulating layers and the product part side conductor layers in a region in the product part are alternately laminated, and the same resin insulating layer is provided. When the wiring board is formed as a main body and connects each product part side conductor layer only with vias whose diameters are expanded in the same direction, sufficient strength cannot be secured, and warping of the intermediate product of the multilayer wiring board Becomes more prominent. Therefore, when the multilayer wiring board does not have a core substrate, the area ratio of the conductor layer occupying the main surface of the resin insulation layer is between the maximum value and the minimum value of the area ratio of the product part side conductor layer occupying the product formation area. If the variation of the area ratio of the conductor layer occupying the main surface of the resin insulating layer is set to 15% or less, the warp of the intermediate product can be more effectively prevented.

  Here, the “intermediate product of the multilayer wiring board” is a concept for the finished product of the multilayer wiring board. Specifically, the frame part is removed from the product formation area and the product formation area is defined as the outer shape of the product part. A multilayer wiring board in a state where a separation process for dividing product parts is not completed by cutting along a planned cutting line set along the line. In general, the intermediate product, the product formation region, and the product portion of the multilayer wiring board are all formed in a substantially rectangular shape in plan view. Further, the area of the product portion is set to be considerably smaller than the area of the product formation region. Therefore, for example, several tens to several hundreds of product parts are arranged in the product formation region.

  On the other hand, the “frame portion” is a portion that is not a product but is separated and removed from the product formation region during manufacture, and surrounds the periphery of the product formation region. In the frame portion, a frame portion side conductor layer is formed as a so-called dummy conductor layer.

  Further, the intermediate product of the multilayer wiring board has a structure in which a plurality of resin insulating layers are laminated. The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the material for forming the resin insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Etc. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used. Note that via holes may be formed in the resin insulating layer in advance in order to form via conductors for interlayer connection.

  The conductor layer (the product part side conductor layer and the frame part side conductor layer) is patterned on the main surface of the resin insulating layer by a known method such as a subtractive method, a semi-additive method, or a full additive method. Examples of the metal material used for forming the product part side conductor layer and the frame part side conductor layer include copper, copper alloy, nickel, nickel alloy, tin, and tin alloy.

  In addition, a plurality of slit-shaped non-formation regions in which the frame-side conductor layer is not present in the region within the frame portion on at least one resin insulation layer among the plurality of resin insulation layers are used as the outline of the product portion. By arranging on the extension line of the planned cutting line set along, and by increasing the width of the non-formation region as the area ratio of the product portion side conductor layer in the product formation region is increased, The area ratio of the conductor layer occupying the main surface of the resin insulating layer may be set between the maximum value and the minimum value of the area ratio of the product part side conductor layer occupying the product formation region. In this case, since a plurality of non-formation regions are generally arranged in accordance with product parts arranged at regular intervals, the plural non-formation regions are easily arranged at regular intervals. As a result, the area ratio of the frame-side conductor layer occupying the frame part can be easily made uniform in any part of the frame part, and as a result, the variation in the area ratio of the conductor layer occupying the main surface of the resin insulating layer is further reduced. be able to. As a result, the difference in thermal expansion coefficient of each layer is further reduced, and the thermal stress due to the difference in thermal expansion coefficient is further reduced, so even if the above thermal stress is applied to the intermediate product of the multilayer wiring board, The product becomes more difficult to warp.

  Here, the plurality of slit-like non-formation regions are disposed on at least one resin insulation layer among the plurality of resin insulation layers. The depth of the non-formation region is not particularly limited. For example, the depth of the non-formation region is set equal to the width of the frame portion (the distance from the boundary portion between the frame portion and the product formation region to the outer periphery of the frame portion). Also good. That is, the frame portion side conductor layer may be divided by a plurality of non-formed regions.

  In addition, the frame portion side conductor layer is formed in a mesh shape, and the line width of the frame portion side conductor layer is set narrower as the area ratio of the product portion side conductor layer occupying the product formation region increases. Thus, the area ratio of the conductor layer occupying the main surface of the resin insulating layer may be set between the maximum value and the minimum value of the area ratio of the product portion side conductor layer occupying the product formation region. In this case, since the burden of pattern design can be reduced, it is easy to prevent cost increase.

  Here, the mesh-shaped frame portion side conductor layer may be anything as long as the region where the conductor layer is present and the region where the conductor layer is not present are regularly continuous. What cross | intersects a line pattern is suitable. More specifically, the mesh-shaped frame-side conductor layer vertically connects a plurality of first line patterns that are equally spaced from each other and a plurality of second line patterns that are also equally spaced from each other. What crosses is preferable. In this case, the line width of the line pattern should not be particularly limited, but is, for example, 0.1 mm to 1.5 mm, further 0.2 mm to 1.3 mm, particularly 0.3 mm to 1.0 mm. It is preferable to set.

  As another means (means 3) for solving the above-mentioned problem, there is a product formation region having a structure in which a plurality of resin insulation layers are laminated, and a plurality of product portions to be products are arranged along the planar direction. A frame portion surrounding the periphery of the product formation region, and formed on the main surface of each resin insulation layer as a conductor layer in the product portion side conductor layer formed in the region in the product portion and in the region in the frame portion And the area ratio of the product part side conductor layer in the product formation region is not the same, and the area ratio of the product part side conductor layer in the product formation region is large. The area ratio of the frame-side conductor layer occupying the frame section existing in the same plane is set to be small, and the area ratio of the conductor layer occupying the main surface of the resin insulation layer is set in the product formation region. Of the area ratio of the product part side conductor layer A preparation step of preparing an intermediate product of a multilayer wiring board set between a high value and a minimum value, and removing the frame portion from the product formation region and cutting along a planned cutting line in the product formation region The manufacturing method of the multilayer wiring board characterized by including the isolation | separation process which divides | segments the said product parts.

  Therefore, according to the manufacturing method of the multilayer wiring board of means 3, in the preparation step, the area ratio of the conductor layer occupying the main surface of the resin insulation layer is the maximum value of the area ratio of the product portion side conductor layer occupying the product formation area. By preparing an intermediate product set between the minimum value and the minimum value, the variation in the area ratio of the conductor layer in the main surface of the resin insulation layer of each layer is reduced. As a result, the difference in thermal expansion coefficient of each layer is reduced, and the thermal stress resulting from the difference in thermal expansion coefficient is also reduced. Therefore, even when a component is connected to the product part side conductor layer after the preparation process, even if the thermal stress due to the above-described difference in thermal expansion coefficient is applied to the intermediate product of the multilayer wiring board, the intermediate product is less likely to warp. Therefore, the yield of the multilayer wiring board obtained from the intermediate product can be improved.

As another means (means 4) for solving the above-mentioned problem, there is a product formation region having a structure in which a plurality of resin insulation layers are laminated, and a plurality of product parts to be products are arranged along the planar direction. A frame portion surrounding the periphery of the product formation region, and formed on the main surface of each resin insulation layer as a conductor layer in the product portion side conductor layer formed in the region in the product portion and in the region in the frame portion Frame portion side conductor layer is provided, and has a structure in which the resin insulation layer and the product portion side conductor layer in the region in the product portion are alternately laminated, and the same resin insulation layer is mainly formed. The product part side conductor layers are connected only by vias whose diameters are expanded in the same direction, and the frame part side is disposed in a region within the frame part on at least one resin insulating layer of the plurality of resin insulating layers. Multiple without conductor layers Slit formed area is disposed on an extension of the cutting line that is set along the outline of the product portion, the area ratio of the product portion side conductor layer to the said product forming region are not identical, the The larger the area ratio of the product portion side conductor layer in the product formation region, the smaller the area ratio of the frame portion side conductor layer in the frame portion existing in the same plane as that, the resin insulating layer A preparation step of preparing an intermediate product of a multilayer wiring board in which variation in the area ratio of the conductor layer occupying the main surface is set within 15%, removing the frame portion from the product formation region, and the product formation region And a separation step of dividing the product parts by cutting along a planned cutting line.

  Therefore, according to the multilayer wiring board manufacturing method of means 4, in the preparation step, by preparing an intermediate product in which the variation in the area ratio of the conductor layer in the main surface of the resin insulation layer is set to 15% or less, The variation in the area ratio of the conductor layer in the main surface of the resin insulation layer is reduced. As a result, the difference in thermal expansion coefficient of each layer is reduced, and the thermal stress resulting from the difference in thermal expansion coefficient is also reduced. Therefore, even when a component is connected to the product part side conductor layer after the preparation process, even if the thermal stress due to the above-described difference in thermal expansion coefficient is applied to the intermediate product of the multilayer wiring board, the intermediate product is less likely to warp. Therefore, the yield of the multilayer wiring board obtained from the intermediate product can be improved.

  Hereinafter, the manufacturing method of the multilayer wiring board concerning the means 3 and 4 is demonstrated.

  In the preparation step, the multilayer wiring in which the area ratio of the conductor layer occupying the main surface of the resin insulating layer is set between the maximum value and the minimum value of the area ratio of the product part side conductor layer occupying the product formation region An intermediate product of a multilayer wiring board is prepared in which the variation of the area ratio of the conductor layer occupying the main surface of the resin insulation layer is set to 15% or less.

  The preparation step includes a lamination step of laminating the plurality of resin insulation layers on a base material having a metal foil on one side, and a base for removing the base material and exposing the metal foil after the lamination step. After the material removal step, after the substrate removal step, a patterning step for patterning the metal foil, and after the patterning step, for connecting components on the conductor layer formed on the main surface of the outermost resin insulation layer And a process including a solder bump forming process for forming the solder bump.

  Here, as metal foil, what consists of either silver, gold | metal | money, platinum, copper, titanium, aluminum, palladium, nickel, tungsten can be mentioned, for example. In particular, the metal foil is preferably made of copper. In this way, the resistance of the metal foil can be reduced and the conductivity of the metal foil can be improved as compared with the case where the metal foil is made of another material.

  Further, in the solder bump forming step, solder bumps for connecting components are formed on the product portion side conductor layer formed on the outermost resin insulating layer. Electrical connection between the product part side conductor layer and the part is achieved through the solder bumps.

  The metal forming the solder bump may be appropriately selected according to the material of the connection terminal of the component to be mounted, but Pb-Sn solder such as 90Pb-10Sn, 95Pb-5Sn, 40Pb-60Sn, Sn- Examples thereof include Sb solder, Sn—Ag solder, Sn—Ag—Cu solder, Au—Ge solder, Au—Sn solder.

  Suitable examples of the component include a capacitor, a semiconductor integrated circuit element (IC chip), and a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process. Further, examples of the IC chip include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) and the like. Here, “semiconductor integrated circuit element” refers to an element mainly used as a microprocessor of a computer or the like.

  Thereafter, the frame portion is removed from the product formation region, and the product formation region is cut along a planned cutting line set along the outline of the product portion, thereby performing a separation step of dividing the product portions. A multi-piece product (multilayer wiring board) can be obtained.

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing a coreless wiring board 101 (multilayer wiring board) of the present embodiment. The coreless wiring substrate 101 does not have a core substrate and is a wiring substrate having a structure in which three resin insulating layers 41, 42, 43 made of epoxy resin and a wiring layer 51 made of copper are alternately stacked. The resin insulating layers 41 to 43 are interlayer insulating layers made of the same thickness (48 μm) and material.

  Terminal pads 52 are arranged in an array on the main surface 102 of the coreless wiring substrate 101 (the main surface 47 of the third-layer resin insulation layer 43). Further, the main surface 47 of the resin insulating layer 43 is almost entirely covered with the solder resist 128. The solder resist 128 has openings 129 that expose the terminal pads 52. A plurality of solder bumps 130 are disposed on the surface of each terminal pad 52. Each solder bump 130 is electrically connected to a surface connection terminal 132 of an IC chip 131 (component) having a rectangular flat plate shape. The area where the terminal pads 52 and the solder bumps 130 are formed is an IC chip mounting area 133 on which the IC chip 131 can be mounted.

  As shown in FIG. 1, BGA pads 53 are arranged in an array on the back surface 103 of the coreless wiring substrate 101 (the lower surface of the first resin insulation layer 41). Further, the lower surface of the resin insulating layer 41 is almost entirely covered with the solder resist 142. In the solder resist 142, openings 145 for exposing the respective BGA pads 53 are formed. A plurality of solder bumps 155 are disposed on the surface of each BGA pad 53, and the coreless wiring board 101 is mounted on a mother board (not shown) by each solder bump 155.

  Furthermore, each resin insulation layer 41 to 43 is provided with a via hole 146 and a via conductor 147, respectively. Each via hole 146 has an inverted frustoconical shape, and is formed by subjecting each resin insulating layer 41 to 43 to drilling using a YAG laser or a carbon dioxide gas laser. Each via conductor 147 is a conductor whose diameter is expanded in the same direction (upward in FIG. 1), and electrically connects each wiring layer 51, the terminal pad 52, and the BGA pad 53 to each other.

  Next, the intermediate product 11 of the coreless wiring substrate 101 will be described.

  As shown in FIGS. 2 and 3, the intermediate product 11 of the coreless wiring substrate 101 has a substantially rectangular shape in plan view of 213.6 mm long × 52.0 mm wide, and includes a product formation region 28 and its product formation region. 28 and a frame portion 29 surrounding the periphery of 28. In the product formation region 28, five square product parts 27 to be products (coreless wiring substrate 101) are arranged along the plane direction. The frame portion 29 has four edge portions 30 arranged so as to surround the product forming region 28 and four corner portions 31 located at a connection portion between the edge portions 30.

  As shown in FIG. 3, the wiring layer 51 (thickness: 15 μm), which is a product portion side conductor layer, is formed in a region within the product portion 27 on the main surfaces 45 to 47 of the resin insulating layers 41 to 43. Has been. Further, each terminal pad 52 (thickness 15 μm), which is a product portion side conductor layer, is formed in a region in the product portion 27 on the main surface 46 of the outermost resin insulation layer 43, and the outermost resin insulation layer. Each BGA pad 53 (thickness: 15 μm) is formed in a region in the product portion 27 on the lower surface of 41. Further, a frame portion side conductor layer 54 (thickness: 15 μm) is formed in a region in the frame portion 29 on the main surfaces 45 to 47 of the resin insulating layers 41 to 43. The frame-side conductor layer 54 is a plain conductor formed in a substantially rectangular frame shape in substantially the entire region in the frame portion 29. None of the frame-side conductor layer 54 remains in the final product, and it can be said to be a dummy conductor layer.

  As shown in FIGS. 2 and 3, the intermediate product 11 of the coreless wiring substrate 101 is cut along the outline 120 of each product portion 27. Such a line along the outline 120 is defined as a planned cutting line 121. More specifically, the planned cutting lines 121 for dividing the product parts 27 from each other are set between the outlines 120 of the adjacent product parts 27. The planned cutting line 121 for separating the frame portion 29 from the product forming region 28 is between the outer shape line 120 of the product portion 27 and the inner peripheral edge of the frame portion side conductor layer 54, and the product forming region 28. Is set at a boundary portion between the frame portion 29 and the frame portion 29.

  As shown in FIG. 2, a plurality of non-formation regions 61 in which the frame portion side conductor layer 54 does not exist are arranged in the regions in the frame portion 29 on all the resin insulating layers 41 to 43. The non-formation regions 61 are slit-like regions that are arranged at equal intervals in the respective edge portions 30 and that are arranged on an extension line of the planned cutting line 121. A part of each non-formation region 61 is disposed at a boundary portion between the edge portion 30 and the corner portion 31. In addition, since each non-formation area | region 61 is opened in the inner periphery and outer periphery of the frame part 29, the length of each non-formation area | region 61 is the width | variety (frame part side conductor layer 54 of the frame part side conductor layer 54). The distance from the inner peripheral edge of the frame portion side conductor layer 54 to the outer peripheral edge) is set equal. That is, the frame portion side conductor layer 54 is divided by the respective non-formation regions 61. The width of each non-formation region 61 is set to be equal to the interval between the outlines 120 of the adjacent product parts 27 and the interval between the outline 120 of the product part 27 and the inner peripheral edge of the frame side conductor layer 54. ing.

  In the present embodiment, the area ratio A1 of the product portion side conductor layer occupying the product formation region 28 is set so as not to be the same for each layer. Specifically, on the main surface 45 of the first resin insulating layer 41, the area ratio A1 of the product portion side conductor layer (wiring layer 51) occupying the product formation region 28 is set to 86%. . On the main surface 46 of the second resin insulation layer 42, the area ratio A1 of the product portion side conductor layer (wiring layer 51) occupying the product formation region 28 is set to 64%, and the third layer resin insulation. On the main surface 47 of the layer 43, the area ratio A1 of the product part side conductor layer (the wiring layer 51 and the terminal pad 52) occupying the product forming region 28 is set to 78%. Therefore, the maximum value of the area ratio A1 is 86%, and the minimum value of the area ratio A1 is 64%.

  In the present embodiment, as the area ratio A1 of the product portion side conductor layer provided in the resin insulation layer increases, the width of the non-formation region 61 existing in the same plane as the main surface of the resin insulation layer increases. In addition to being set, the area ratio A2 of the frame portion side conductor layer 54 occupying the frame portion 29 is set small. Specifically, on the main surface 45 of the first resin insulation layer 41, the area ratio A1 is the largest, so the width of the non-formation region 61 is set to the largest value (0.9 mm), The area ratio A2 is set to the smallest value (60%). Further, since the area ratio A1 is the smallest on the main surface 46 of the resin insulating layer 42 of the second layer, the width of the non-formation region 61 is set to the smallest value (0.3 mm), and the area ratio A2 is The largest value (100%) is set. Furthermore, since the area ratio A1 is the second largest on the main surface 47 of the resin insulation layer 43 of the third layer, the width of the non-formation region 61 is set to the second largest value (0.6 mm), The area ratio A2 is set to the second largest value (86%). Note that the area ratio A2 of the frame-side conductor layer 54 occupying the frame 29 is set to 50% or more.

  Furthermore, in this embodiment, the area ratio A3 of the conductor layer (all of the product part side conductor layer and the frame part side conductor layer 54) occupying the main surfaces 45 to 47 of the resin insulation layers 41 to 43 is the highest of the area ratio A1. It is set between the value (86%) and the minimum value (64%). Specifically, the area ratio A3 of the conductor layer (the wiring layer 51 and the frame side conductor layer 54) occupying the main surface 45 of the first resin insulating layer 41 is set to 80%. Also, the area ratio A3 of the conductor layer (the wiring layer 51 and the frame side conductor layer 54) occupying the main surface 46 of the second resin insulation layer 42 is set to 72%, and the third layer resin insulation layer 43 The area ratio A3 of the conductor layer (the wiring layer 51, the terminal pad 52, and the frame portion side conductor layer 54) occupying the main surface 47 is set to 80%. That is, the area ratio A3 of the conductor layer occupying the main surface 45 of the uppermost resin insulation layer 41 and the area ratio A3 of the conductor layer occupying the main surface 47 of the lowermost resin insulation layer 43 are the same. Yes. Moreover, since the variation of the area ratio A3 which occupies for the main surfaces 45-47 of each resin insulating layer 41-43 will be 8%, the area ratio A3 will be substantially the same.

  Next, a method for manufacturing the coreless wiring substrate 101 will be described.

  In the preparation step, the intermediate product 11 of the coreless wiring substrate 101 as shown in FIGS. 2 and 3 is prepared and prepared in advance. The intermediate product 11 of the coreless wiring substrate 101 is manufactured as follows. First, as shown in FIG. 4, a support substrate 70 having sufficient strength such as a glass epoxy substrate is prepared. Next, a sheet-like insulating resin base material made of an epoxy resin is pasted on the support substrate 70 in a semi-cured state to form the base resin insulation layer 71, so that the support substrate 70 and the base resin insulation layer 71 are separated. A base material 69 is obtained. Then, as shown in FIG. 5, the laminated metal sheet body 72 is disposed on one surface of the base material 69 (specifically, the upper surface of the base resin insulating layer 71). Here, by arranging the laminated metal sheet body 72 on the base resin insulating layer 71 in a semi-cured state, the adhesiveness is such that the laminated metal sheet body 72 is not peeled off from the base resin insulating layer 71 in the subsequent manufacturing process. Secured. The laminated metal sheet body 72 is formed by closely attaching two copper foils 73 and 74 (metal foil) in a peelable state. Specifically, the laminated metal sheet body 72 is formed by laminating the copper foils 73 and 74 via metal plating (for example, chromium plating).

  Thereafter, as shown in FIG. 6, a sheet-like insulating resin base material 40 is laminated on the laminated metal sheet body 72, and is heated under pressure using a vacuum press-bonding hot press (not shown). Thus, the insulating resin base material 40 is cured to form the first resin insulating layer 41 (lamination step). Then, as shown in FIG. 7, a via hole 146 is formed at a predetermined position of the resin insulating layer 41 by performing laser processing, and then a desmear process for removing smear in each via hole 146 is performed. Then, via conductor 147 is formed in each via hole 146 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the wiring layer 51 is patterned on the resin insulating layer 41 in the region in the product portion 27 of the intermediate product 11 by performing etching by a conventionally known method (for example, semi-additive method) (see FIG. 8). At the same time, the frame-side conductor layer 54 is patterned on the resin insulating layer 41 in the region in the frame portion 29 of the intermediate product 11, and a plurality of non-formation regions 61 in which the frame-side conductor layer 54 does not exist. Form.

  Further, the second and third resin insulation layers 42 and 43 and the wiring layer 51 are also formed by the same method as the first resin insulation layer 41 and the wiring layer 51 described above. Laminate to. Then, a solder resist 128 is formed by applying and curing a photosensitive epoxy resin on the resin insulating layer 43 on which the terminal pads 52 are formed. Next, exposure and development are performed with a predetermined mask placed, and the opening 129 is patterned in the solder resist 128. Through the above manufacturing process, a laminated body 80 in which the laminated metal sheet body 72, the resin insulating layers 41 to 43, and the wiring layer 51 are laminated on the support substrate 70 is formed (see FIGS. 9 and 10). As shown in FIG. 9, the region located on the laminated metal sheet 72 in the laminated body 80 is a wiring laminated portion 81 to be the intermediate product 11 of the coreless wiring substrate 101. As shown in FIG. 10, in the laminate 80, two blocks 82 in which three intermediate products 11 are arranged along the plane direction are arranged along the plane direction, and the periphery of each block 82 is a peripheral portion 83. Surrounded by.

  In the subsequent first separation step, the stacked body 80 is cut by a dicing device (not shown), and the surrounding area of each block 82 is removed. At this time, as shown in FIG. 10, the base resin insulating layer 71 and the support substrate 70 below the wiring laminated portion 81 are cut at the boundary between each block 82 and the surrounding portion 83. Thereby, each block 82 is divided into two blocks 82 (see FIG. 11).

  Next, the base material 69 is removed in each block 82 to expose the copper foil 73 (base material removal step). Specifically, peeling is performed at the interface between the two copper foils 73 and 74 in the laminated metal sheet body 72 to separate the wiring laminated portion 81 from the support substrate 70 (see FIG. 12). Then, as shown in FIG. 13, by patterning the copper foil 73 on the back surface 103 (lower surface) of the wiring laminated portion 81 (resin insulating layer 41) by etching, the outermost resin insulating layer A BGA pad 53 is formed in a region of the product portion 27 in 41 (patterning step). Thereafter, as shown in FIG. 14, a photosensitive resist resin is applied and cured on the resin insulating layer 41 on which the BGA pads 53 are formed, so as to cover the back surface 103 of the wiring laminated portion 81 so as to cover the solder resist. 142 is formed (solder resist forming step). Next, exposure and development are performed in a state where a predetermined mask is arranged, and the opening 145 is patterned in the solder resist 142.

  Next, solder bumps 130 for connecting IC chips are formed on the plurality of terminal pads 52 formed on the outermost resin insulating layer 43 (solder bump forming step). Specifically, a solder ball is placed on each terminal pad 52 using a solder ball mounting device (not shown), and then the solder ball is heated to a predetermined temperature and reflowed, whereby solder bumps are placed on each terminal pad 52. 130 is formed. Similarly, solder bumps 155 are also formed on the plurality of BGA pads 53 formed on the back surface 103 side of the wiring laminated portion 81.

  In the subsequent second separation step, the block 82 is cut along the boundary line between the intermediate products 11 using a dicing apparatus (not shown). Thereby, each intermediate product 11 is divided, and the intermediate product 11 of the coreless wiring substrate 101 shown in FIGS. 2 and 3 can be obtained.

  In the subsequent IC chip mounting step, the IC chip 131 is mounted on the IC chip mounting area 133 of each product part 27 (coreless wiring substrate 101) constituting the intermediate product 11. At this time, the surface connection terminals 132 on the IC chip 131 side and the solder bumps 130 on the product part 27 side are aligned. Then, by heating and reflowing each solder bump 130, the surface connection terminal 132 and the solder bump 130 are joined, and the IC chip 131 is mounted on the product portion 27.

  In the subsequent third separation step, the frame portion 29 is cut and removed from the product formation region 28 using a conventionally known cutting device or the like, and cut along the planned cutting line 121 in the product formation region 28. Thereby, the product parts 27 are divided into a plurality of coreless wiring boards 101 (see FIG. 1).

  Next, an evaluation method for the warp of the intermediate product of the coreless wiring board and the result will be described.

  First, a plurality of measurement samples (see FIG. 15) were prepared as follows. The intermediate product 11 of this embodiment was cut to prepare a measurement sample in which the longitudinal and lateral lengths were halved. In Example 1, the variation in the area ratio A3 of the conductor layer occupying the main surface of the first layer (resin insulating layer 41), the second layer (resin insulating layer 42), and the third layer (resin insulating layer 43) is 15%. It is a sample for measurement set within% (8%). In addition, a measurement sample in which the variation in the area ratio A3 was set to 0% was prepared, and these were designated as Comparative Examples 1, 2, and 3. Furthermore, a measurement sample in which the variation in the area ratio A3 was set to be larger than 15% was prepared, and this was designated as Comparative Examples 4, 5, 6, 7, 8, and 9. The variation of the area ratio A3 of Comparative Example 4 is set to 22%, the variation of the area ratio A3 of Comparative Example 5 is set to 17%, and the variation of the area ratio A3 of Comparative Examples 6 to 9 is set to 17%. Has been.

  Next, each measurement sample (Example 1, Comparative Examples 1 to 9) was heated from room temperature (25 ° C.) to 190 ° C. And the amount of curvature of each sample for measurement was measured, respectively. Specifically, the measurement sample was placed on a support table (not shown), and the height from the surface of the support table to the location where the lift amount was the largest in the measurement sample was measured as the amount of warpage.

  As a result of measuring the warpage amount, the warpage amount of Comparative Example 4 was 10.3 μm, the warpage amount of Comparative Example 5 was 7.7 μm, the warpage amount of Comparative Example 6 was 8.0 μm, and the warpage amount of Comparative Example 7 was 8 0.2 μm, the warpage amount of Comparative Example 8 was 8.5 μm, and the warpage amount of Comparative Example 9 was 8.7 μm. On the other hand, the warpage amount of Example 1 was 2.7 μm, and the warpage amounts of Comparative Examples 1 to 3 were 0 μm. From the above, it was confirmed that the warpage amounts of Example 1 and Comparative Examples 1 to 3 were smaller than those of Comparative Examples 4 to 9. Therefore, it was proved that if the variation of the area ratio A3 is within 15%, the intermediate product is hardly warped.

  A plurality of measurement samples (see FIG. 16) were prepared as follows. In each measurement sample, the area ratio A1 of the product-side conductor layer occupying the product formation region 28 is set to be constant (86% for the first layer, 64% for the second layer, 78% for the third layer). The area ratio A2 of the frame portion side conductor layer 54 occupying the frame portion 29 is set in a plurality of ways. For example, a measurement sample in which the area ratio A2 is set to 50% or more on each of the resin insulating layers 41 to 43 was prepared, and this was used as Example 2. In addition, the area ratio A2 of Example 2 is set to 77% for the first layer and 100% for the second layer and the third layer. Further, a measurement sample in which the area ratio A2 was set to less than 50% on the resin insulating layer 41 was prepared, and this was designated as Comparative Example 10. The area ratio A2 of Comparative Example 10 is set to 43% for the first layer, 100% for the second layer, and 69% for the third layer. Furthermore, a measurement sample in which the area ratio A2 was set to less than 50% on the resin insulating layers 41 and 43 was prepared, and this was designated as Comparative Example 11. The area ratio A2 of Comparative Example 11 is set to 1% for the first layer, 73% for the second layer, and 26% for the third layer. Moreover, the sample for a measurement which set area ratio A2 to less than 50% on each resin insulating layer 41-43 was prepared, and this was made into Comparative Examples 12-16. The area ratio A2 of Comparative Example 12 is set to 40% in each layer, the area ratio A2 of Comparative Example 13 is set to 30% in each layer, and the area ratio A2 of Comparative Example 14 is set to 20% in each layer. The area ratio A2 of Comparative Example 15 is set to 10% in each layer, and the area ratio A2 of Comparative Example 16 is set to 0% in each layer.

  Next, each measurement sample (Example 2, Comparative Examples 10 to 16) was heated from room temperature (25 ° C.) to 190 ° C., and the amount of warpage of each measurement sample was measured. As a result of measuring the warpage amount, the warpage amount of Comparative Example 10 is 4.5 μm, the warpage amount of Comparative Example 11 is 13.8 μm, the warpage amount of Comparative Example 12 is 9.0 μm, and the warpage amount of Comparative Example 13 is 9 μm. The warping amount of Comparative Example 14 was 9.4 μm, the warping amount of Comparative Example 15 was 9.7 μm, and the warping amount of Comparative Example 16 was 10.0 μm. On the other hand, the amount of warpage in Example 2 was 2.0 μm. From the above, it was confirmed that the warpage amount of Example 2 was smaller than the warpage amounts of Comparative Examples 10-16. Therefore, it has been proved that if the area ratio A2 is set to 50% or more on each of the resin insulating layers 41 to 43, the intermediate product is hardly warped.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the intermediate product 11 of the coreless wiring substrate 101 of the present embodiment, the variation in the area ratio A3 of the conductor layer occupying the main surfaces 45 to 47 of the resin insulation layers 41 to 43 is set to 8%. Get smaller. As a result, the thermal expansion coefficient difference of each layer is reduced and the thermal stress due to the thermal expansion coefficient difference is also reduced. Therefore, when the solder bump 130 used for connecting the IC chip 131 is cooled, the thermal stress described above is reduced. Even if added, the intermediate product 11 is less likely to warp. Therefore, the yield of the product (coreless wiring board 101) obtained from the intermediate product 11 can be improved.

  (2) In this embodiment, on the respective resin insulation layers 41 to 43, the product portion side conductor layer (the wiring layer 51 and the terminal pad 52) is patterned, and at the same time, the frame portion side conductor layer 54 (and the non-formation region). 61) is formed, the manufacturing process of the coreless wiring substrate 101 can be shortened. In addition, since the non-formation region 61 is a relatively simple region such as a slit shape, the burden of pattern design can be reduced, and the cost of the coreless wiring substrate 101 can be easily prevented.

  In addition, you may change this embodiment as follows.

  -Although the non-formation area | region 61 of the said embodiment was arrange | positioned on the extended line of the planned cutting line 121 set along the external shape line 120 of the product part 27 in the frame part 29, it is from the extended line of the planned cutting line 121 You may arrange | position in the position shifted | deviated to the plane direction.

  In the intermediate product 11 of the coreless wiring substrate 101 of the above embodiment, the frame-side conductor layer 54 formed in a plain shape is formed in the region in the frame portion 29. The intermediate product may be a frame side conductor layer having a different form from the conductor layer 54. FIG. 17 shows the intermediate product 151. In the intermediate product 151, a frame portion side conductor layer 152 formed in a mesh shape is formed in a region in the frame portion 29. In this case, as the area ratio A1 of the product-side conductor layer occupying the product formation region 28 increases, the main surface 45 of each resin insulating layer 41 to 43 is set by narrowing the line width of the frame-side conductor layer 54. The area ratio A3 of the conductor layer occupying ˜47 is set between the maximum value and the minimum value of the area ratio A1. In this case, since the burden of pattern design can be reduced, it is easy to prevent cost increase.

  In the manufacturing method of the coreless wiring substrate 101 of the above embodiment, the solder bumps 130 for connecting the IC chip are formed on the plurality of terminal pads 52 formed on the outermost resin insulating layer 44. The pad 52 may be a BGA pad to be mounted on another connection component such as a motherboard, and solder bumps may be formed on the BGA pad. In this case, a terminal pad for connecting an IC chip is formed on the back surface 103 side of the wiring laminated portion 81.

  In the product part side conductor layer forming step of the above embodiment, the BGA pad 53 is formed by patterning the copper foil 73 by etching. However, the BGA pad 53 may be separately formed after the copper foil 73 is completely removed by etching.

  In the laminating process of the above embodiment, the resin insulating layer 41 may be formed after forming a metal layer to be the BGA pad 53 on the copper foil 73. In this case, after forming the via hole 146 exposing the metal layer in the resin insulating layer 41, the via conductor 147 is formed in the via hole 146. In this way, the copper foil 73 can be completely removed by etching to expose the metal layer, and the metal layer can be used as the BGA pad 53.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) It has a structure in which a plurality of resin insulating layers are laminated, and includes a product forming region in which a plurality of product parts to be products are arranged along the plane direction, and a frame part surrounding the product forming region. A multilayer in which a product part side conductor layer formed in a region in the product part as a conductor layer and a frame part side conductor layer formed in a region in the frame part are provided on the main surface of each resin insulating layer It is an intermediate product of a wiring board, and the area ratio of the product part side conductor layer occupying the product formation area is not the same, and the area ratio of the product part side conductor layer occupying the product formation area is larger, The area ratio of the frame-side conductor layer occupying the frame section existing in the same plane is set to be small, and the product occupying the area ratio of the conductor layer occupying the main surface of the resin insulation layer in the product formation region Maximum area ratio and maximum area ratio The area ratio of the conductor layer occupying the main surface of the uppermost resin insulation layer and the area ratio of the conductor layer occupying the main surface of the lowermost resin insulation layer are the same as each other. An intermediate product for multilayer wiring boards, characterized in that

  (2) A product formation region that does not have a core substrate and is formed mainly of the same resin insulation layer, and in which a plurality of product parts to be products are arranged along the plane direction, and surrounds the periphery of the product formation region A product portion side conductor layer formed in a region in the product portion as a conductor layer and a frame portion side conductor layer formed in a region in the frame portion on a main surface of each resin insulating layer. Provided and has a structure in which the resin insulation layer and the product part side conductor layer in the region in the product part are alternately laminated, and each product part side conductor layer is connected only by a via expanded in the same direction. Intermediate product of the multilayer wiring board, the area ratio of the product part side conductor layer occupying in the product formation region is not the same, and the area ratio of the product part side conductor layer in the product formation region is larger In the same plane The area ratio of the frame part side conductor layer occupying the frame part is set to be small, and the area ratio of the conductor layer occupying the main surface of the resin insulation layer is the same as that of the product part side conductor layer occupying the product formation region. An intermediate product of a multilayer wiring board characterized by being set between the maximum value and the minimum value of the area ratio.

The schematic sectional drawing which shows schematic structure of the coreless wiring board in this embodiment. The schematic plan view which shows the intermediate product of a coreless wiring board. FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. Explanatory drawing which shows the manufacturing method of a coreless wiring board. The table | surface which shows the area ratio of each layer of Example 1 and Comparative Examples 2-9. The table | surface which shows the area ratio of each layer of Example 2 and Comparative Examples 10-16. The schematic plan view which shows the intermediate product of the coreless wiring board in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11,151 ... Intermediate product 27 ... Product part 28 ... Product formation area 29 ... Frame part 41, 42, 43 ... Resin insulation layer 45, 46, 47 ... Main surface 51 of resin insulation layer ... Conductor layer and product Wiring layer 52 as part side conductor layer ... Terminal pad 54, 152 as conductor layer and product part side conductor layer ... Frame part side conductor layer 61 as conductor layer ... Non-forming region 69 ... Base material 73, 74 ... Metal foil Copper foil 101 as a coreless wiring board 120 as a multilayer wiring board ... Outline line 121 ... Planned cutting line 130 ... Solder bump 131 ... IC chip 146 as a component ... Via hole 147 as a via ... Via conductor A1 as a via ... Area ratio of product part side conductor layer A2 ... Area ratio of frame part side conductor layer A3 ... Area ratio of conductor layer

Claims (7)

It has a structure in which a plurality of resin insulation layers are laminated, and is composed of a product forming region in which a plurality of product parts to be products are arranged along the plane direction, and a frame portion surrounding the periphery of the product forming region. The main surface of the resin insulation layer is provided with a product part side conductor layer formed in a region in the product part as a conductor layer and a frame part side conductor layer formed in a region in the frame part, and the region in the product part The product insulation side and the product part side conductor layer are alternately laminated, and each product part side is formed only by vias formed mainly from the same resin insulation layer and having a diameter expanded in the same direction. An intermediate product of a multilayer wiring board to which a conductor layer is connected ,
A plurality of slit-shaped non-formation regions in which the frame portion side conductor layer does not exist in the region in the frame portion on at least one resin insulation layer among the plurality of resin insulation layers along the outline of the product portion It is placed on the extension line of the planned cutting line,
The area ratio of the product part side conductor layer in the product formation region is not the same,
As the area ratio of the product part side conductor layer occupying the product formation region is larger, the area ratio of the frame part side conductor layer occupying the frame part existing in the same plane as it is set,
An intermediate product of a multilayer wiring board, wherein the variation in the area ratio of the conductor layer occupying the main surface of the resin insulation layer is set within 15%. The intermediate product of the multilayer wiring board according to claim 1 , wherein the area ratio of the conductor layer occupying the main surface of the resin insulating layer is set to be the same. The intermediate product of the multilayer wiring board according to claim 1 or 2 , wherein an area ratio of the frame-side conductor layer occupying the frame portion is set to 50% or more. As the area ratio of the product portion side conductor layer to the prior SL product forming region is increased, by setting a large width of the non-forming region, the area ratio of the conductive layer to the main surface of the resin insulating layer The multilayer wiring board according to any one of claims 1 to 3 , wherein the multilayer wiring board is set between a maximum value and a minimum value of an area ratio of the product portion side conductor layer in the product formation region. Intermediate product. By forming the frame portion side conductor layer in a mesh shape and setting the line width of the frame portion side conductor layer to be narrow as the area ratio of the product portion side conductor layer occupying in the product formation region is increased, The area ratio of the conductor layer occupying the main surface of the resin insulation layer is set between the maximum value and the minimum value of the area ratio of the product-side conductor layer occupying the product formation region. Item 5. The intermediate product of the multilayer wiring board according to any one of Items 1 to 4 . It has a structure in which a plurality of resin insulation layers are laminated, and is composed of a product forming region in which a plurality of product parts to be products are arranged along the plane direction, and a frame portion surrounding the periphery of the product forming region. The main surface of the resin insulation layer is provided with a product part side conductor layer formed in a region in the product part as a conductor layer and a frame part side conductor layer formed in a region in the frame part, and the region in the product part The product insulation side and the product part side conductor layer are alternately laminated, and each product part side is formed only by vias formed mainly from the same resin insulation layer and having a diameter expanded in the same direction. A conductor layer is connected, and a plurality of slit-shaped non-formation regions in which the frame-side conductor layer does not exist in the region within the frame portion on at least one resin insulation layer of the plurality of resin insulation layers are the product portion. Along the outline of Disposed on the extension of the constant has been cutting line, wherein no area ratio of the occupied product forming region product portion side conductor layer is the same, a large area ratio of the product portion side conductor layer to the said product forming region The area ratio of the frame-side conductor layer occupying the frame portion existing in the same plane is set smaller, and the variation in the area ratio of the conductor layer occupying the main surface of the resin insulating layer is 15%. A preparation process for preparing an intermediate product of a multilayer wiring board set within
A separation step of dividing the product portions by removing the frame portion from the product formation region and cutting along a planned cutting line in the product formation region. Production method. The preparation step includes
A laminating step of laminating the plurality of resin insulating layers on a substrate having a metal foil on one side;
Substrate removal step of removing the substrate and exposing the metal foil after the lamination step,
After the base material removal step, a patterning step for patterning the metal foil,
According to claim 6, characterized in that it consists of the following patterning step, the solder bump forming step of forming a solder bump for component connection on the conductor layer formed on the main surface of the outermost layer of the resin insulating layer Manufacturing method of multilayer wiring board.

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