JP5269757B2 - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring substrate with high reliability by preventing a resin insulating layer from cracking. <P>SOLUTION: The multilayer wiring substrate 10 has a wiring laminate portion 30 formed by alternately laminating a plurality of resin insulating layers 21 to 24 composed principally of the same resin insulating material and a plurality of conductor layers 26 into a multilayer structure. The resin insulating layer 21 as an outermost layer has a plurality of openings 37 formed on the side of a lower surface 32 of the wiring laminate portion 30. A lower-stage metal conductor portion 45a constituting a mother substrate connection terminal 45 is positioned in an opening 37 formed in the resin insulating layer 21. An upper-stage metal conductor portion 45b constituting the mother substrate connection terminal 45 is formed on the lower-stage metal conductor portion 45a and resin insulating layer 21 to cover an opening edge of the opening 37. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a multilayer wiring board having a multilayer structure in which a plurality of resin insulation layers and a plurality of conductor layers mainly composed of the same resin insulation material are alternately laminated, and having no so-called core board. is there.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a semiconductor package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the semiconductor package is mounted on a motherboard.

  As an IC chip mounting wiring board constituting this type of package, a multilayer wiring board in which build-up layers are formed on the front surface and the back surface of a core substrate has been put into practical use. In this multilayer wiring substrate, for example, a resin substrate (such as a glass epoxy substrate) in which a reinforcing fiber is impregnated with a resin is used as a core substrate. Then, by utilizing the rigidity of the core substrate, a buildup layer is formed by alternately laminating a resin insulating layer and a conductor layer on the front surface and the back surface of the core substrate. That is, in this multilayer wiring board, the core board plays a role of reinforcement and is formed much thicker than the build-up layer. In addition, wiring (specifically, a through-hole conductor or the like) is formed through the core substrate for conduction between buildup layers formed on the front surface and the back surface.

  By the way, in recent years, with the increase in the speed of semiconductor integrated circuit elements, the signal frequency used has become a high frequency band. In this case, the wiring penetrating the core substrate contributes as a large inductance, leading to transmission loss of high-frequency signals and circuit malfunction, which hinders speeding up. In order to solve this problem, it has been proposed that the multilayer wiring board is a board that does not have a core board (see, for example, Patent Document 1). Since this multilayer wiring board has a shorter overall wiring length by omitting a relatively thick core substrate, the transmission loss of high-frequency signals is reduced, and the semiconductor integrated circuit element can be operated at high speed. It becomes.

  In the manufacturing method disclosed in Patent Literature 1, a metal foil is disposed on one surface of a temporary substrate, and a build-up layer formed by alternately laminating a plurality of conductor layers and a plurality of resin insulating layers on the metal foil. Form. Thereafter, the metal foil is separated from the temporary substrate to obtain a structure in which a build-up layer is formed on the metal foil. Then, the metal foil is removed by etching to expose the surface of the outermost layer of the build-up layer (the surface of the resin insulating layer and the surfaces of the plurality of connection terminals), thereby manufacturing a multilayer wiring board.

JP 2007-158174 A (FIG. 7 etc.)

  By the way, in the above-mentioned Patent Document 1, there is a multilayer wiring board formed so that the surface of a connection terminal having a relatively large area (for example, a mother board connection terminal connected to a motherboard) is flush with the outermost resin insulation layer. It is disclosed. In this multilayer wiring board, stress may be applied to the boundary portion between the mother board connection terminal and the resin insulating layer. For this reason, as shown in FIG. 19, there arises a problem that a crack 103 occurs on the resin insulating layer 102 side starting from a boundary portion between the mother board connection terminal 101 and the resin insulating layer 102.

  Patent Document 1 discloses a multilayer wiring board in which a solder resist is formed on the outermost layer of the buildup layer. In the multilayer wiring board, the stress applied to the boundary portion between the mother board connection terminal and the resin insulating layer is relieved by coating the outer peripheral part on the surface side of the mother board connection terminal with the solder resist. However, when a solder resist is formed on the outermost layer in a multilayer wiring board, the solder resist and each resin insulation layer of the inner layer have different thermal expansion coefficients, so that the board warps according to the difference in the thermal expansion coefficients. Resulting in. In this case, a configuration (for example, a reinforcing plate) for suppressing the warpage is separately required, and as a result, the manufacturing cost of the multilayer wiring board increases.

  The present invention has been made in view of the above problems, and an object thereof is to provide a highly reliable multilayer wiring board by preventing the occurrence of cracks in a resin insulating layer.

And as a means (means 1) for solving the above-mentioned problem, it has a laminated structure in which a plurality of resin insulation layers mainly composed of the same resin insulation material and a plurality of conductor layers are alternately laminated to form a multilayer structure, A plurality of first main surface side connection terminals are arranged on the first main surface side of the laminated structure, and a plurality of second main surface side connection terminals are arranged on the second main surface side of the laminated structure, The plurality of conductor layers are multilayer wiring boards formed on the plurality of resin insulation layers and connected by via conductors whose diameter is increased toward the first main surface side or the second main surface side, A plurality of openings are formed in the outermost resin insulation layer exposed on the second main surface side of the multilayer structure, and the plurality of second main surface side connection terminals are located in the openings. The lower metal conductor portion in a state of covering the lower metal conductor portion and the opening edge of the opening. Fine said have a two-stage structure composed of an upper metal conductor portion formed on the outermost resin insulation layer, the upper metal conductor portion is larger in area than the lower metal conductor portion, said lower metal conductor portion There is a multilayer wiring board characterized in that the area is larger than the end face of the via conductor connected thereto .

  Therefore, according to the invention described in the above means, a plurality of resin insulation layers and a plurality of conductor layers mainly composed of the same resin insulation material are alternately laminated, and a multilayer wiring board is formed as a coreless wiring board not including a core board. ing. In this multilayer wiring board, the plurality of second main surface side connection terminals provided on the second main surface side of the multilayer structure have a two-stage structure including a lower metal conductor portion and an upper metal conductor portion. The lower metal conductor portion constituting the second main surface side connection terminal is located in the opening formed in the outermost resin insulating layer in the exposed state, and the upper metal metal portion constituting the second main surface side connection terminal. The conductor part is formed on the lower metal conductor part and the outermost resin insulating layer so as to cover the opening edge of the opening part. If it does in this way, since it will become the shape where the boundary part of a lower metal conductor part and a resin insulating layer was block | closed by the upper metal conductor part, the stress added to the boundary part is relieved. For this reason, the risk of cracks occurring in the resin insulation layer is reduced, and the reliability of the multilayer wiring board is improved as compared with the conventional case.

In the invention described in the above-described means, the upper stepped metal conductor portion larger in area than the lower metal conductor portion, the lower metal conductor portion has a size area than the end face of the via conductor connected to it. If you like this, since the cross-sectional area of the stepwise conductor portion from the via conductor disposed inside the multilayer wiring board is increased, effectively dispersed to the stress acting between the resin insulating layer and a conductor portion be able to. For this reason, generation | occurrence | production of a crack can be prevented reliably and the reliability of a multilayer wiring board can be improved more.

  The thickness corresponding to the outermost main surface of the outermost resin insulation layer that is exposed on the second main surface side of the multilayer structure to the nearest conductor layer is larger than the thickness of the other resin insulation layers in the multilayer structure. Larger is preferred. This makes it possible to reliably form the second main surface side connection terminal so that the lower metal conductor portion is positioned in the opening formed in the outermost resin insulating layer, and the stress is relieved, thereby reducing the stress. The cracks described in 1 can be suppressed.

  The plurality of second main surface side connection terminals having a two-stage structure preferably have a concave terminal outer surface, and more preferably the deepest portion of the terminal outer surface reaches the lower metal conductor portion. When the second main surface side connection terminal is formed in this way, the contact area of the solder with respect to the outer surface of the terminal is increased, so that the strength of the solder connection can be increased.

The plurality of second main surface side connection terminals having a two-stage structure may be a plurality of mother substrate connection terminals whose connection target is a mother substrate and has a larger area than the first main surface side connection terminals. In this case, the mother board connection terminal having a relatively large area can be reliably connected to the mother board.
Further, the second main surface side connection terminal may be provided on the main surface side to which the mother board is connected, or may be provided on the opposite side of the main surface, for example, on the main surface side on which the IC chip is mounted. Good.

  The via conductors formed in the plurality of resin insulation layers may all have a shape whose diameter is increased from the second main surface side toward the first main surface side. Conversely, the via conductors formed in the plurality of resin insulation layers may have a shape whose diameter is increased from the first main surface side toward the second main surface side. In this way, a coreless wiring board that does not have a core board can be manufactured relatively easily.

  The upper metal conductor portion may have a structure in which the upper surface and the side surface of the copper layer constituting the main body are covered with a plating layer other than copper. If it does in this way, since solder can be formed so that the upper surface and side of the upper metal conductor part in the 2nd principal surface side connecting terminal may be covered, it will become easy to form a solder fillet of a suitable shape at the time of component joining.

  The plurality of resin insulation layers are preferably formed using the same build-up material mainly composed of a resin insulation material not imparting photocurability, for example, a cured product of a thermosetting resin insulation material. . In this case, the outermost resin insulation layer on which each connection terminal is formed is made of the same build-up material as the inner resin insulation layer, so that the interval between the connection terminals can be reduced. High integration of the multilayer wiring board is possible.

  Preferred examples of the material for forming the resin insulation layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins and polyimide resins, thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins and polypropylene resins. Is mentioned. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer is mainly made of copper and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a conductor layer and connection terminals can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a conductor layer can be formed by printing a conductive paste or the like.

  As a manufacturing method of a multilayer wiring board, while preparing a support substrate formed by laminating and arranging a metal foil on one side, the first main surface side connection terminal or the second main surface side connection terminal A laminated structure in which a plurality of resin insulation layers and a plurality of conductor layers are alternately laminated after the metal conductor portion forming step for forming a lower metal conductor portion on the metal foil and the metal conductor portion forming step. A build-up process for forming a body, a base material removal process for removing the supporting base material to expose the metal foil after the build-up process, and the build-up process, while leaving the lower metal conductor part A connection terminal forming step of forming the second main surface side connection terminal having a two-stage structure by selectively etching away the metal foil in the laminated structure to form an upper metal conductor portion. A. When the multilayer wiring board is manufactured as described above, the lower metal conductor portion of the second main surface side connection terminal can be positioned in the opening formed in the outermost resin insulating layer. Further, the upper metal conductor portion can be formed on the lower metal conductor portion and the outermost resin insulating layer so as to cover the opening edge of the opening. When the second main surface side connection terminals are formed in this way, the risk of cracks occurring in the resin insulating layer can be reduced, and a multilayer wiring board with higher reliability than conventional can be easily and reliably manufactured. it can.

Sectional drawing which shows schematic structure of the multilayer wiring board in one embodiment. The top view which shows schematic structure of a multilayer wiring board. The top view which shows schematic structure of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Sectional drawing which shows schematic structure of the multilayer wiring board in another embodiment. Sectional drawing which shows schematic structure of the multilayer wiring board in another embodiment. Sectional drawing which shows schematic structure of the multilayer wiring board in another embodiment. Sectional drawing which shows schematic structure of the multilayer wiring board in another embodiment. The expanded sectional view which shows the conventional multilayer wiring board.

  Hereinafter, an embodiment in which the present invention is embodied in a multilayer wiring board will be described in detail with reference to the drawings. FIG. 1 is an enlarged cross-sectional view showing a schematic configuration of the multilayer wiring board of the present embodiment. 2 is a plan view of the multilayer wiring board as viewed from the upper surface side, and FIG. 3 is a plan view of the multilayer wiring board as viewed from the lower surface side.

  As shown in FIG. 1, a multilayer wiring board 10 is a coreless wiring board formed without including a core board, and is composed of four resin insulating layers 21, 22, 23, 24 and a conductor layer 26 made of copper are alternately laminated to have a multilayered wiring layer 30 (laminated structure). Each of the resin insulating layers 21 to 24 is formed using a build-up material mainly composed of a resin insulating material that is not imparted with photocurability, specifically, a cured product of a thermosetting epoxy resin. In the multilayer wiring board 10, a plurality of connection terminals 41 and 42 (first main surface side connection terminals) are arranged on the upper surface 31 side (first main surface side) of the wiring laminated portion 30.

  As shown in FIG. 1 and FIG. 2, in the multilayer wiring board 10 of the present embodiment, the connection target is an IC chip as the plurality of connection terminals 41 and 42 arranged on the upper surface 31 side of the wiring laminated portion 30. There are an IC chip connection terminal 41 and a capacitor connection terminal 42 whose connection target is a chip capacitor. On the upper surface 31 side of the wiring laminated portion 30, the plurality of IC chip connection terminals 41 are arranged in an array in a chip mounting region 43 provided in the central portion of the substrate. The capacitor connection terminal 42 is a connection terminal having a larger area than the IC chip connection terminal 41, and is disposed on the outer peripheral side of the chip mounting region 43.

  On the other hand, as shown in FIGS. 1 and 3, on the lower surface 32 side (second main surface side) of the wiring laminated portion 30, a plurality of LGA (land grid array) objects to be connected are mother boards (mother boards). Connection terminals 45 (mother substrate connection terminals as second main surface side connection terminals) are arranged in an array. These mother board connection terminals 45 are connection terminals having a larger area than the IC chip connection terminal 41 and the capacitor connection terminal 42 on the upper surface 31 side.

  Via holes 33 and filled via conductors 34 are provided in the resin insulating layers 21, 22, 23, and 24, respectively. Each via conductor 34 has a shape whose diameter is increased in the same direction (from the lower surface side to the upper surface side in FIG. 1), and each conductor layer 26, IC chip connection terminal 41, capacitor connection terminal 42, and mother The board connection terminals 45 are electrically connected to each other.

  On the upper surface 31 side of the wiring laminated portion 30, an opening 35 is formed in the fourth resin insulating layer 24 exposed in the outermost layer, and the height of the upper surface is within the opening 35. The IC chip connection terminal 41 is formed in such a state that it is lower than the surface (reference surface). Further, the IC chip connection terminal 41 has a structure in which only the upper surface of the main copper layer is covered with a plating layer 46 (specifically, a nickel-gold plating layer) other than copper. The IC chip is flip-chip connected to the exposed upper surface of the IC chip connection terminal 41 via a solder bump (not shown).

  The capacitor connection terminal 42 is mainly composed of a copper layer, and is formed so that the height of the upper surface thereof is higher than the surface of the resin insulating layer 24. That is, in the multilayer wiring board 10 of the present embodiment, the height of the upper surface of the IC chip connection terminal 41 and the upper surface of the capacitor connection terminal 42 are different, and the height of the upper surface of the capacitor connection terminal 42 having a relatively large area. Is higher than the height of the upper surface of the IC chip connection terminal 41 having a relatively small area. In addition, the capacitor connection terminal 42 has a structure in which the upper surface and side surfaces of the main copper layer are covered with a plating layer 47 other than copper (specifically, a nickel-gold plating layer). On the capacitor connection terminal 42, an external terminal of the chip capacitor is connected via solder (not shown).

  On the lower surface 32 side of the wiring laminated portion 30, a plurality of openings 37 are formed in the outermost resin insulating layer 21 in an exposed state, and a mother board connection terminal 45 corresponds to the plurality of openings 37. Has been placed. Specifically, the mother board connection terminal 45 is formed on the lower metal conductor 45a and the resin insulating layer 21 so as to cover the lower metal conductor 45a located in the opening 37 and the opening edge of the opening 37. It has a two-stage structure consisting of the upper metal conductor portion 45b. In the mother board connection terminal 45, the lower metal conductor portion 45a has a larger area than the end surface of the via conductor 34 connected thereto, and the upper metal conductor portion 45b has a larger area than the lower metal conductor portion 45a. . Furthermore, the upper metal conductor portion 45b has a structure in which the upper surface and side surfaces of the copper layer constituting the main body are covered with a plating layer 48 (specifically, a nickel-gold plating layer) other than copper. A motherboard is connected to the mother board connection terminal 45 via solder (not shown).

  Further, on the lower surface 32 side of the wiring laminated portion 30, the thickness L1 corresponding to the outermost main surface 21a of the outermost resin insulating layer 21 in the exposed state to the nearest conductor layer 26 (in this embodiment, the resin insulating layer) 21) is larger than the thickness L2 of the other resin insulating layers 22 to 24 in the wiring laminated portion 30. In the multilayer wiring board 10 of the present embodiment, the lower metal conductor portion 45 a of the mother board connection terminal 45 is positioned inside the opening 37 by forming the outermost resin insulating layer 21 thick.

  The multilayer wiring board 10 having the above configuration is manufactured, for example, by the following procedure.

  First, in the build-up process, a support substrate (such as a glass epoxy substrate) having sufficient strength is prepared, and the resin insulating layers 21 to 24 and the conductor layer 26 are built-up on the support substrate to form the wiring laminated portion 30. Form.

  More specifically, as shown in FIG. 4, a base resin insulating layer 51 is formed by attaching a sheet-like insulating resin base material made of an epoxy resin on the support substrate 50, whereby the support substrate 50 and the base resin are formed. A base material 52 made of the insulating layer 51 is obtained. Then, as shown in FIG. 5, the laminated metal sheet body 54 is disposed on one surface of the base material 52 (specifically, the upper surface of the base resin insulating layer 51). Here, by arranging the laminated metal sheet body 54 on the base resin insulating layer 51, the adhesiveness to the extent that the laminated metal sheet body 54 is not peeled off from the base resin insulating layer 51 in the subsequent manufacturing process is ensured. The laminated metal sheet body 54 is formed by closely attaching two copper foils 55 and 56 (a pair of metal foils) in a peelable state. Specifically, the laminated metal sheet body 54 in which the copper foil 55 and the copper foil 56 are disposed is formed through metal plating (for example, chromium plating, nickel plating, titanium plating, or a composite plating thereof).

  Thereafter, the lower metal conductor portion 45a in the mother board connection terminal 45 is formed on the laminated metal sheet body 54 (metal conductor portion forming step). Specifically, as shown in FIG. 6, a dry film for forming a plating resist is laminated on the upper surface of the laminated metal sheet body 54, and the dry film is exposed and developed. As a result, a plating resist 57 having a predetermined pattern corresponding to the lower metal conductor portion 45a is formed. Then, electrolytic copper plating is selectively performed in a state where the plating resist 57 is formed to form the lower metal conductor portion 45a on the laminated metal sheet body 54, and then the plating resist 57 is peeled off (see FIG. 7).

  Thereafter, the sheet-like resin insulation layer 21 is disposed so as to wrap the laminated metal sheet body 54 on which the lower metal conductor portion 45a is formed, and the resin insulation layer 21 is attached. (See FIG. 8). Here, the resin insulating layer 21 is in close contact with the laminated metal sheet body 54 and the lower metal conductor portion 45a, and is in close contact with the base resin insulating layer 51 in the peripheral region of the laminated metal sheet body 54, whereby the laminated metal sheet body 54 is obtained. Is sealed.

Then, as shown in FIG. 9, for example, excimer laser, UV laser, CO ₂ laser, or the like is used to perform laser processing to a predetermined position of the resin insulating layer 21 (position above the lower metal conductor portion 45 a). A via hole 33 is formed. Next, a desmear process is performed to remove smear in each via hole 33 using an etching solution such as a potassium permanganate solution. As the desmear process, in addition to treatment with an etchant, for example it may perform processing of plasma ashing using O ₂ plasma.

  After the desmear process, via conductors 34 are formed in the via holes 33 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Furthermore, the conductor layer 26 is patterned on the resin insulating layer 21 by performing etching by a conventionally known method (for example, a semi-additive method) (see FIG. 10).

In addition, the second to fourth resin insulation layers 22 to 24 and the conductor layer 26 are also formed by the same method as that for the first resin insulation layer 21 and the conductor layer 26 described above. Laminate to. A plurality of openings 35 are formed by laser drilling the outermost resin insulation layer 24 (see FIG. 11). Next, a desmear process for removing smear in each opening 35 with a potassium permanganate solution, O ₂ plasma, or the like is performed.

  By the build-up process described above, the wiring laminate 60 in which the laminated metal sheet body 54, the resin insulating layers 21 to 24, and the conductor layer 26 are laminated on the base material 52 is formed. As shown in FIG. 11, a region located on the laminated metal sheet body 54 in the wiring laminated body 60 is a portion that becomes the wiring laminated portion 30 of the multilayer wiring board 10. Further, a part of the conductor layer 26 exposed by the opening 35 in the wiring laminated body 60 becomes the IC chip connection terminal 41.

  Thereafter, electroless copper plating is performed to form an entire plating layer covering the opening 35 of the resin insulating layer 24 and the resin insulating layers 21 to 24 (entire plating step). The copper plating is also formed on the inner surface of the opening 35 at this time.

  Then, a plating resist forming dry film is laminated on the upper surface of the wiring laminate 60, and exposure and development are performed on the dry film, whereby a pattern having an opening at a location corresponding to the capacitor connection terminal 42 is obtained. A resist is formed. Thereafter, by selectively performing pattern plating in a state in which a plating resist is formed, a filled via conductor is formed inside a part of the plurality of openings 35, and the capacitor connection terminal 42 is provided above the filled via conductor. (Filled via conductor forming step).

  After the filled via conductor forming step, as shown in FIG. 12, the entire plated layer is removed while leaving the filled via conductor 63 and the capacitor connection terminal 42 by patterning by a semi-additive method (full plated layer removing step).

  The entire plating layer removing step, the wiring laminate 60 is cut by a dicing apparatus (not shown), and the peripheral region of the wiring laminated portion 30 is removed (cutting step). At this time, as shown in FIG. 12, at the boundary between the wiring laminated portion 30 and the surrounding portion 64 (the boundary indicated by the arrow in FIG. 12), the base material 52 (the support substrate 50 and the underlying substrate) located below the wiring laminated portion 30. The whole resin insulating layer 51) is cut. By this cutting, the outer edge portion of the laminated metal sheet 54 sealed with the resin insulating layer 21 is exposed. That is, due to the removal of the peripheral portion 64, the close contact portion between the base resin insulating layer 51 and the resin insulating layer 21 is lost. As a result, the wiring laminated portion 30 and the base material 52 are connected via the laminated metal sheet body 54 only.

  Here, as shown in FIG. 13, by peeling at the interface between the pair of copper foils 55 and 56 in the laminated metal sheet body 54, the substrate 52 is removed from the wiring laminated portion 30, and the wiring laminated portion 30 ( The copper foil 55 on the lower surface of the resin insulating layer 21) is exposed (base material removing step).

  Thereafter, on the lower surface 32 side of the wiring laminated portion 30, the upper metal conductor portion 45b is formed by partially etching away the copper foil 55 while leaving the lower metal conductor portion 45a, thereby forming the mother having a two-stage structure. Substrate connection terminals 45 are formed (connection terminal formation step). Specifically, a dry film for forming an etching resist is laminated on the upper surface 31 and the lower surface 32 of the wiring laminated portion 30, and the dry film is exposed and developed. As a result, the upper surface 31 of the wiring laminated portion 30 forms an etching resist that covers the entire surface, and the lower surface 32 forms an etching resist having a predetermined pattern that covers a portion corresponding to the upper metal conductor portion 45b. In this state, the wiring laminated portion 30 is etched to remove the unnecessary copper foil 55, thereby forming the upper metal conductor portion 45 b on the lower metal conductor portion 45 a and the resin insulating layer 21. As a result, a mother board connection terminal 45 having a two-stage structure including the lower metal conductor portion 45a and the upper metal conductor portion 45b is formed (see FIG. 14).

  Thereafter, the surface of the IC chip connection terminal 41, the surface of the capacitor connection terminal 42, and the surface of the mother board connection terminal 45 are sequentially subjected to electroless nickel plating and electroless gold plating, whereby nickel-gold plating layers 46 and 47 are applied. , 48 are formed (plating process). The multilayer wiring board 10 of FIG. 1 is manufactured through the above steps.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the multilayer wiring board 10 of the present embodiment, the lower metal conductor 45a constituting the mother board connection terminal 45 is positioned in the opening 37 formed in the outermost resin insulation layer 21 in the exposed state. The upper metal conductor portion 45 b constituting the mother board connection terminal 45 is formed on the lower metal conductor portion 45 a and the resin insulating layer 21 so as to cover the opening edge of the opening portion 37. If it does in this way, since the boundary part of the lower metal conductor part 45a and the resin insulating layer 21 becomes a shape closed with the upper metal conductor part 45b, the boundary part is reinforced and the stress applied to the boundary part is relieved. . In addition, since the boundary portion is non-linear, various chemicals and the like are less likely to enter the substrate through the boundary portion. As a result, the risk of cracks occurring in the resin insulating layer 21 is reduced, and the reliability of the multilayer wiring board 10 is improved as compared with the conventional case.

  (2) In the multilayer wiring board 10 of the present embodiment, the upper metal conductor portion 45b is formed to have a larger area than the lower metal conductor portion 45a, so that the strength and heat dissipation of the connection terminal can be increased. The lower metal conductor portion 45a has a larger area than the end face of the via conductor 34 connected thereto. In this case, since the areas of the conductor portions 45a and 45b gradually increase from the via conductor 34 disposed inside the multilayer wiring board 10, the stress acting between the resin insulating layer 21 and the conductor portions 45a and 45b is increased. It can be dispersed efficiently. Further, since the mother board connection terminal 45 has a two-stage structure composed of the lower metal conductor part 45a and the upper metal conductor part 45b, the thickness of the connection terminal 45 is increased, and the strength of the wiring board itself is improved. For this reason, generation | occurrence | production of a crack can be prevented reliably and the reliability of the multilayer wiring board 10 can be improved more.

  (3) In the multilayer wiring board 10 of the present embodiment, on the lower surface 32 side of the wiring laminated portion 30, this corresponds to from the outer principal surface 21 a of the outermost resin insulating layer 21 in the exposed state to the nearest conductor layer 26. The thickness L1 is larger than the thickness L2 of the other resin insulating layers 22 to 24 in the wiring laminated portion 30. In this way, the mother board connection terminal 45 can be reliably formed so that the lower metal conductor portion 45a is located in the opening 37 formed in the outermost resin insulating layer 21.

  (4) In the multilayer wiring board 10 of the present embodiment, the upper metal conductor portion 45b of the mother board connection terminal 45 has a structure in which the upper surface and side surfaces of the main copper layer are covered with the plating layer 48. The solder can be formed so as to cover the upper metal conductor portion 45b. Therefore, a solder fillet having a suitable shape is easily formed at the time of component joining.

  (5) In the multilayer wiring board 10 of the present embodiment, the plurality of connection terminals 41 and 42 formed on the upper surface 31 side of the wiring laminated portion 30 have different upper surface heights for each type of connection target. Specifically, an IC chip connection terminal 41 whose connection target is an IC chip and a capacitor connection terminal 42 whose connection target is a chip capacitor are present as the plurality of connection terminals 41 and 42. Is lower than the surface of the resin insulating layer 24 exposed at the outermost layer, and the capacitor connection terminal 42 is higher than the surface of the resin insulating layer 24. In this way, solder bumps for flip chip connection of the IC chip can be reliably formed on the IC chip connection terminal 41, and the IC chip can be reliably connected. Moreover, the solder for connecting the chip capacitor can be reliably formed on the capacitor connection terminal 42, and the chip capacitor can be reliably connected.

  (6) In the multilayer wiring board 10 of the present embodiment, an opening 35 is formed in the resin insulating layer 24 exposed to the upper surface 31 side of the wiring laminated portion 30, and the upper surface has a high height in the opening 35. The IC chip connection terminal 41 is formed in such a state that the height is lower than the surface of the resin insulating layer 24. If it does in this way, a solder ball can be easily positioned in opening 35 on IC chip connection terminal 41, and formation of a solder bump on IC chip connection terminal 41 can be performed more certainly.

  (7) In the multilayer wiring board 10 of the present embodiment, the capacitor connection terminal 42 can have solder attached to the upper surface and side surfaces thereof. Therefore, it is possible to reliably form a solder fillet having a relatively large and suitable shape at the time of component joining. In addition, since the IC chip connection terminal 41 has a structure in which the upper surface thereof is covered with the plating layer 46, solder bumps can be reliably formed on the upper surface of the IC chip connection terminal 41. Here, the interval between the capacitor connection terminals 42 is wider than the interval between the IC chip connection terminals 41, and the capacitor connection terminals 42 are relatively large in size, so that the chip capacitors are formed by the solder formed on the upper and side surfaces of the capacitor connection terminals 42. Can be securely connected with sufficient strength. On the other hand, since the intervals between the IC chip connection terminals 41 are narrow, if the solder bumps swell in the lateral direction (substrate plane direction) of the IC chip connection terminals 41, a short circuit between the terminals becomes a problem. On the other hand, in the present embodiment, solder bumps are formed only on the upper surface of the IC chip connection terminal 41, and the solder bumps do not bulge in the lateral direction, so a short circuit between the terminals via the solder bumps is avoided. be able to.

  (8) In the multilayer wiring board 10 of the present embodiment, the plurality of resin insulation layers 21 to 24 are formed using the same build-up material mainly composed of a cured product of a resin insulation material not imparted with photocurability. Has been. That is, the outermost resin insulation layers 21 and 24 are formed of the same build-up material having the same insulating properties as the inner resin insulation layers 22 and 23. For this reason, the terminal interval of each connection terminal 41, 42, 45 can be narrowed, and the multi-layer wiring board 10 can be highly integrated. Moreover, in the multilayer wiring board 10, since the solder resist is not formed in the outermost layer, the warp of the multilayer wiring board 10 caused by the difference in thermal expansion coefficient between the resin insulating layers 21 to 24 and the solder resist is avoided. be able to.

  In addition, you may change embodiment of this invention as follows.

  In the multilayer wiring board 10 of the above embodiment, the outer surface of the mother board connection terminal 45 is a flat surface, but is not limited to this. For example, like the multilayer wiring board 10A shown in FIG. 15, the terminal outer surface 45c of the mother board connection terminal 45 may be formed in a concave shape. In this multilayer wiring board 10A, the upper metal conductor portion 45b constituting the mother board connection terminal 45 has a ring shape and is arranged so as to cover the boundary between the lower metal conductor portion 45a and the resin insulating layer 21. Even if the mother board connection terminal 45 is configured in this manner, the boundary portion between the lower metal conductor portion 45a and the resin insulating layer 21 is blocked by the upper metal conductor portion 45b, so that the stress applied to the boundary portion is relieved. For this reason, the risk of cracks occurring in the resin insulating layer 21 can be reduced, and the reliability of the multilayer wiring board 10A is improved. Furthermore, since the contact area with the solder on the terminal outer surface 45c of the mother board connection terminal 45 is increased, the strength of the solder connection can be increased. Further, as in the multilayer wiring board 10B shown in FIG. 16, the mother board connection terminal 45 may be formed so that the deepest part of the concave terminal outer surface 45c reaches the lower metal conductor part 45a. When the mother board connection terminal 45 is configured in this manner, the contact area with the solder on the terminal outer surface 45c increases, so that the strength of the solder connection can be increased. In addition, when the terminal outer surface 45c of the mother board connection terminal 45 has a concave shape, it is possible to easily position the solder balls and the connection pins.

  In the multilayer wiring boards 10, 10 </ b> A, and 10 </ b> B of the above embodiment, the capacitor connection terminals 42 formed on the upper surface 31 side are patterned by the semi-additive method, but even if the patterns are formed by the subtractive method Good. In this case, as in the multilayer wiring board 10C shown in FIG. 17, the capacitor connection terminal 42A is formed in a trapezoidal cross section having a larger area on the lower surface than on the upper surface. By doing so, the contact area between the capacitor connection terminal 42A and the resin insulating layer 24 is increased, so that the terminal strength can be sufficiently ensured. Further, like the multilayer wiring board 10C, the IC chip connection terminal 41A may be formed by the filled via conductor 63 filled in the opening 35. Further, like the multilayer wiring board 10 </ b> D shown in FIG. 18, similarly to the IC chip connection terminal 41, the capacitor connection terminal 42 </ b> B may be formed so as to be exposed in the opening 35. The capacitor connection terminal 42B has substantially the same height as the IC chip connection terminal 41.

  In the above embodiment, the plurality of conductor layers 26 formed on the plurality of resin insulation layers 21 to 24 are connected to each other by the via conductors 34 whose diameter increases from the lower surface 32 side toward the upper surface 31 side. It is not limited to this. The via conductors 34 formed in the plurality of resin insulation layers 21 to 24 may have a shape whose diameter is increased in the same direction, and the plurality of conductor layers 26 are formed by via conductors whose diameter is increased from the upper surface 31 side toward the lower surface 32 side. May be connected to each other.

  In the above embodiment, the plating layers 46, 47, 48 covering the connection terminals 41, 42, 45 are nickel-gold plating layers, but may be any plating layer other than copper. -You may change into other plating layers, such as a palladium- gold plating layer.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) It has a laminated structure in which a plurality of resin insulating layers mainly composed of the same resin insulating material and a plurality of conductor layers are alternately laminated to form a multilayer structure, and there are a plurality of laminated structures on the first main surface side. First main surface side connection terminals are arranged, a plurality of second main surface side connection terminals are arranged on the second main surface side of the laminated structure, and the plurality of conductor layers are formed of the plurality of resin insulation layers. Formed on the first main surface side or connected to the first main surface side or the second main surface side by a via conductor whose diameter is increased, and is exposed on the second main surface side of the multilayer structure. A plurality of openings are formed in the outermost resin insulation layer in a state, and the plurality of second main surface side connection terminals are formed by connecting a lower metal conductor portion located in the opening and an opening edge of the opening. An upper metal formed on the lower metal conductor and the outermost resin insulation layer in a covered state Has a two-stage structure comprising a conductive portion, wherein the upper metal conductor portion, a multilayer wiring board characterized by having a structure to cover the upper and side surfaces of the copper layer constituting the principal plating layer other than copper.

  (2) In the technical idea (1), at least two types of first main surface side connection terminals having different connection objects exist on the first main surface side, and an upper surface of the first main surface side connection terminal. The multilayer wiring board is characterized in that the height of the wiring board is different for each type of connection object.

  (3) It has a laminated structure in which a plurality of resin insulating layers mainly composed of the same resin insulating material and a plurality of conductor layers are alternately laminated to form a multilayer structure, and a plurality of layers are provided on the first main surface side of the laminated structure. First main surface side connection terminals are arranged, a plurality of second main surface side connection terminals are arranged on the second main surface side of the laminated structure, and the plurality of conductor layers are formed of the plurality of resin insulation layers. A multilayer wiring board formed by connecting via conductors whose diameter is increased toward the first main surface or the second main surface, the metal foil being peelable on one side A metal conductor part forming step of preparing a support base material formed by laminating and forming a lower metal conductor part in the first main surface side connection terminal or the second main surface side connection terminal on the metal foil; After the metal conductor portion forming step, a plurality of resin insulation layers and a plurality of conductor layers are alternated. A buildup process for forming a laminated structure by stacking and multilayering, a base material removal process for removing the support base material and exposing the metal foil after the buildup process, and after the buildup process The second main surface side connection terminal having a two-stage structure is formed by selectively etching away the metal foil in the multilayer structure while leaving the lower metal conductor part to form an upper metal conductor part. The manufacturing method of the multilayer wiring board characterized by including the connection terminal formation process to perform.

DESCRIPTION OF SYMBOLS 10,10A-10D ... Multilayer wiring board 21-24 ... Resin insulating layer 21a ... Outer main surface 26 ... Conductor layer 30 ... Wiring laminated part as laminated structure 31 ... Upper surface as 1st main surface 32 ... 2nd main surface 34 ... Via conductor 37 ... Opening 41, 41A ... IC chip connection terminal as first main surface side connection terminal 42, 42A, 42B ... Capacitor connection terminal as first main surface side connection terminal 45 ... Second Mother board connection terminal 45a as a main surface side connection terminal Lower metal conductor part 45b Upper metal conductor part 45c Terminal outer surface

Claims (4)

A laminated structure in which a plurality of resin insulation layers mainly composed of the same resin insulation material and a plurality of conductor layers are alternately laminated to form a multilayer structure; Main surface side connection terminals are arranged, a plurality of second main surface side connection terminals are arranged on the second main surface side of the multilayer structure, and the plurality of conductor layers are formed on the plurality of resin insulation layers. A multilayer wiring board connected by via conductors whose diameter is increased toward the first main surface side or the second main surface side,
A plurality of openings are formed in the outermost resin insulation layer in an exposed state on the second main surface side of the multilayer structure,
The plurality of second main surface side connection terminals are disposed on the lower metal conductor portion and the outermost resin insulation layer in a state of covering the opening edge of the opening and the lower metal conductor portion located in the opening portion. the two-stage structure consisting of formed an upper metal conductor portion possess,
The multilayer wiring board, wherein the upper metal conductor portion has an area larger than the lower metal conductor portion, and the lower metal conductor portion has an area larger than an end surface of a via conductor connected thereto .   The thickness corresponding to the outermost main surface of the outermost resin insulation layer that is exposed on the second main surface side of the laminated structure to the nearest conductor layer is that of the other resin insulation layers in the laminated structure. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is larger than the thickness. Wherein the plurality of second main surface side connecting terminals having the two-stage structure, prior Symbol multilayer wiring according to claim 1 or 2 terminal outer surface of the second main surface side connecting terminal is characterized in that a concave substrate. Wherein the plurality of second main surface side connecting terminals having the two-stage structure, together with the terminal outer surface of the front Stories second main surface side connecting terminal is concave, the deepest portion of the terminal outer surface to said lower metal conductor portion The multilayer wiring board according to claim 1 , wherein the multilayer wiring board is formed.

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