JP5167785B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including an LDMOS transistor.

  Conventionally, for example, Patent Document 1 has proposed a semiconductor device having element regions in which source layers and drain layers are alternately formed in stripes. Specifically, Patent Document 1 proposes a semiconductor device including the element region, an outer peripheral region provided on the outer periphery of the element region, and a trench surrounding the element region and the outer peripheral region.

In the element region, a plurality of Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistors are electrically connected in parallel, and the LDMOS transistor and other surrounding elements are separated by one trench. In such a configuration, the entire LDMOS transistor surrounded by the trench operates simultaneously.
JP-A-2005-332891

  In recent years, a high-speed switching application such as a switching power supply and an output stage of a high-speed communication driver have to satisfy the conflicting requirements of high speed and low noise generation. In order to meet such a demand, it is required to accurately control the switching waveform of the LDMOS transistor. This will be described with reference to FIG.

  FIG. 10 shows the time change of the drain-source voltage of the LDMOS transistor in which the element structure in which the source layer and the drain layer are arranged in a stripe shape in the conventional technique is surrounded by one trench. Since noise is generated at the edge portions of the rising edge 31 and the falling edge 32 of the drain-source voltage shown in this figure, the rising edge 31 and the falling edge 32 of these voltage waveforms are smoothly changed to bring the voltage waveform closer to a sine wave. Thus, it is known in principle that both high speed and low noise can be achieved.

  However, in practice, it is not easy to reduce the noise by the high-speed switching operation of the LDMOS transistor. In the low-speed switching operation, the waveform can be controlled by the circuit. However, in the high-speed switching operation, the circuit operation cannot keep up with the switching speed, so that the circuit cannot reduce the noise.

  On the other hand, as a method of smoothing the rising 31 and falling 32 of the voltage waveform, there is a method of adjusting the resistance value of the gate resistance connected to the LDMOS transistor. However, in the conventional technique, all element regions surrounded by one trench operate simultaneously. For this reason, even if the resistance value of the gate resistance is changed, the entire voltage waveform changes, and the rising 31 and falling 32 portions of the voltage waveform cannot be controlled separately. Therefore, it is difficult to bring the voltage waveform close to a sine wave.

  Therefore, the LDMOS transistor surrounded by one trench is divided into a plurality of blocks, which are connected in parallel, and the resistance value of the gate resistance connected to the gate of each block is changed. Thereby, it is considered that the rising and falling edges 31 and 32 of the voltage waveform can be controlled separately by adjusting the switching speed of the LDMOS transistors in each block.

  However, when the LDMOS transistor is divided into blocks, each block must be surrounded by a trench and insulated from each block. As a result, it is necessary to secure an isolation region width for insulating and separating each block, and there is a problem that the area of the chip cannot be used effectively.

  An object of the present invention is to provide a semiconductor device capable of smoothing a switching voltage waveform of an LDMOS transistor without increasing the isolation region width.

  In order to achieve the above object, according to the first aspect of the present invention, the semiconductor substrate (1) is disposed on the insulating film (3), and on the opposite side of the semiconductor substrate (1) from the insulating film (3) side. A plurality of element regions (15) in which LDMOS transistors (5) including source electrodes (13) and drain electrodes (14) alternately arranged in a stripe shape are formed are provided, and each of the plurality of element regions (15) is provided. Is surrounded by a dividing trench (16) that is provided on the semiconductor substrate (1) and reaches the insulating film (3), and any one of the plurality of element regions (15) surrounded by the dividing trench (16). In addition, along the drain electrode (14) or the source electrode (13) between the insulating film (3) and the source electrode (13) and at least one between the insulating film (3) and the drain electrode (14). Semiconductor Wherein the isolation trench extending through the plate (1) reaches the insulating film (3) (17) is formed.

  According to this, since the isolation trench (17) is provided in the semiconductor substrate (1) in the element region (15) surrounded by one dividing trench (16), The LDMOS transistor (5) can be insulated and separated into a plurality of regions. In this case, since it is not necessary to divide the element region (15) for each block and surround it with a trench, it is not necessary to secure an isolation region width for insulating and separating the LDMOS transistor (5). Therefore, the LDMOS transistor (5) in the element region (15) can be insulated and separated into a plurality of regions by the isolation trench (17) without increasing the isolation region width.

  In addition, since each region in the element region (15) can be connected to different potentials, the switching speed of each region can be controlled. Thereby, the switching voltage waveform of the LDMOS transistor (5) can be smoothed.

  In the invention according to claim 2, the LDMOS transistor (5) has the gate electrode (11) along the source electrode (13) or the drain electrode (14) and is surrounded by the dividing trench (16). In the element region (15), gate resistors (20 to 22) having different values are connected to the gate electrodes (11) in the regions separated by the isolation trench (17), respectively. 22) is connected to the same electrode (23).

  In this way, by switching the resistance value of the gate resistance (20-22) in each region surrounded by the dividing trench (16) and the isolation trench (17), switching of the LDMOS transistor (5) in each region is performed. Each speed can be controlled. As a result, the switching voltage waveform of the LDMOS transistor (5) can be smoothed, and as a result, can be brought close to a sine wave.

  According to a third aspect of the present invention, a buried layer (28) is provided between the semiconductor substrate (1) and the insulating film (3), and the dividing trench (16) and the separating trench (17) are formed in the buried layer ( 28), and is formed so as to reach the insulating film (3).

  Thus, by providing the buried layer (28), other elements such as a bipolar transistor can be formed on the semiconductor substrate (1).

In the invention described in claim 1 , the sides (16a, 16b) parallel to the source electrode (13) and the drain electrode (14) of the dividing trench (16) are alternately arranged in the element region (15). The insulating film (3) is provided between the terminal electrode (13) and the drain electrode (14) to be disposed and the insulating film (3).

  As a result, the region occupied by the element region (15) can be further reduced, and an increase in the chip area can be prevented.

According to a fourth aspect of the present invention, the isolation trench (17) may be separated from the dividing trench (16).

According to the fifth aspect of the present invention, an oxide film (18) is formed on at least the side wall of the isolation trench (17) out of the dividing trench (16) and the isolation trench (17), and the oxide film (18). A conductor (19) is formed on the substrate, and either the drain potential or the source potential of the LDMOS transistor (5) is input via the oxide film (18) and the conductor (19). And a control circuit (29) for generating a gate control signal for switching and driving the LDMOS transistor (5) using the potential of.

  Thus, the drain potential and the source potential of the LDMOS transistor (5) can be reflected in the generation of a signal to be input to the gate electrode (11) of the LDMOS transistor (5), and the switching voltage of the LDMOS transistor (5) can be reflected. The accuracy of the waveform can be improved.

In the invention according to claim 6 , an oxide film (18) is formed on at least the side wall of the isolation trench (17) among the dividing trench (16) and the isolation trench (17), and the oxide film (18). A conductor (19) is formed on the substrate, and a constant potential for changing the current path between the drain and the source of the LDMOS transistor (5) is applied to the conductor (19). It is characterized by becoming.

  Thus, the resistance between the drain and the source can be changed by changing the current path between the drain and the source of the LDMOS transistor (5). Thereby, the switching voltage waveform of the LDMOS transistor (5) can be finely controlled.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention. 2A is a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB ′ in FIG. Hereinafter, a description will be given with reference to FIGS. 1 and 2.

As shown in FIG. 2A, the semiconductor device is formed on an SOI substrate 4 configured by sandwiching an insulating film 3 between an element formation substrate 1 and a support substrate 2. An N-type silicon substrate is used as the element formation substrate 1, and a silicon substrate is used as the support substrate 2. Further, for example, SiO ₂ is adopted as the insulating film 3. Of the SOI substrate 4, an LDMOS transistor 5, a CMOS transistor, and a BIP (bipolar) transistor are formed on the element formation substrate 1. The element formation substrate 1 corresponds to the semiconductor substrate of the present invention.

  As shown in FIG. 2A, N-type regions 6 and P-type regions 7 are alternately formed on the surface layer portion of the N− type element formation substrate 1. N-type region 6 corresponds to the drain of LDMOS transistor 5, and P-type region 7 corresponds to the source of LDMOS transistor 5.

  Among these, the LOCOS oxide film 8 is formed on a part of the surface of the N-type region 6. In addition, N + type source regions 9 are formed on the surface layer portion of the P type region 7 so as to be separated from each other. The surface outside the LOCOS oxide film 8 in the N-type region 6, the surface of the N− type element formation substrate 1, the surface outside the N + type region in the P-type region 7, and the surface of the N + type region Is covered with an interlayer insulating film 10. A gate electrode 11 is formed on the interlayer insulating film 10. The gate electrode 11 is covered with a gate insulating film 12.

  A source electrode 13 is formed on part of the surface of the P-type region 7 and the surface of the N + type source region 9, and a drain electrode 14 is formed on the surface of the N-type region 6. That is, the source electrode 13 and the drain electrode 14 are alternately arranged in a stripe shape.

  The LDMOS transistor 5 having such a configuration is formed in an element region 15 in a certain range, and a plurality of element regions 15 are provided. Although two element regions 15 are illustrated in FIG. 1, a large number of element regions 15 are actually provided.

  Each element region 15 is surrounded by a dividing trench 16 as shown in FIG. As shown in FIG. 2B, the dividing trench 16 is provided in the element forming substrate 1 and reaches the insulating film 3. Thereby, each element region 15 is insulated from each other by the dividing trench 16.

  According to this, the element region 15 is insulated from the adjacent element region 15 by two dividing trenches 16 including a dividing trench 16 surrounding itself and a dividing trench 16 surrounding the adjacent element region 15. . As a result, even if the dividing trench fails in one element region 15, the other element regions 15 are surrounded by the dividing trenches 16, so that insulation of the other element regions 15 is ensured.

  That is, the region between the dividing trenches 16 serves as a shield region, and also serves to prevent a potential change generated at the output stage of each element region 15 from propagating to the other element regions 15.

  Further, as shown in FIG. 2A, an isolation trench 17 that electrically isolates the element region 15 is formed in any one of the plurality of element regions 15. The isolation trench 17 penetrates the element formation substrate 1 along the drain electrode 14 or the source electrode 13 between at least one of the insulating film 3 and the source electrode 13 and between the insulating film 3 and the drain electrode 14. It is provided so as to reach the insulating film 3.

  In FIG. 1, the dividing trench 16 and the isolation trench 17 are indicated by black lines, but this indicates the arrangement location of the isolation trench 16 and the isolation trench 17, and the source electrode 13 and It does not indicate that it is formed on the drain electrode 14.

  In the present embodiment, the isolation trench 17 is provided in a portion of the element forming substrate 1 where the drain electrode 14 is formed on the surface. That is, in the element region 15 surrounded by the dividing trench 16, the isolation trench 17 reaching the insulating film 3 is formed between the insulating film 3 and the drain electrode 14 in the element forming substrate 1. The isolation trench 17 is connected to the dividing trench 16. As a result, a plurality of electrically insulated regions are formed in one dividing trench 16.

In the isolation trench 17, an oxide film 18 such as SiO ₂ is formed on the side wall of the isolation trench 17, and a conductor 19 such as PolySi is formed on the oxide film 18. The conductor 19 is surrounded by an oxide film 18, and a LOCOS oxide film 8 is formed so as to cover the oxide film 18 exposed from the element formation substrate 1. Note that only the oxide film 18 may be formed in the isolation trench 17.

  In the element region 15, gate resistors 20 to 22 having different values are connected to the gate electrodes 11 in the respective regions separated by the isolation trench 17. Each of the gate resistors 20 to 22 is connected to the same electrode 23. Of course, the gate resistor 24 is also connected to the gate electrode 11 in the element region 15 where the isolation trench 17 is not formed, and is connected to the same electrode 23.

  In FIG. 1, only the gate resistors 20 to 22 and 24 are illustrated, but actually, the gate resistors 20 to 22 and 24 are connected to the gate electrode 11 of each element region 15.

  Further, as shown in FIG. 1, a contact region 25 is provided between each element region 15 surrounded by the dividing trench 16. The contact region 25 corresponds to a portion of the element formation substrate 1 between the element regions 15 where the gate insulating film 12 is opened. A shield electrode 26 is formed so as to cover the contact region 25.

  The shield electrode 26 is an electrode for performing a leak check of each element region 15 surrounded by the dividing trench 16. Further, by connecting the shield electrode 26 to a constant potential, a region of the element formation substrate 1 connected to the contact region 25 is connected to a constant potential. Thereby, it is possible to prevent a high-speed potential change occurring in the element region 15 from propagating to the other element regions 15.

  In addition to the LDMOS transistor 5, the semiconductor device is also provided with an element region 27 in which devices such as a CMOS transistor and a BIP transistor are formed. The element region 27 is surrounded by the dividing trench 16 and is insulated from other regions.

  Similarly to the above, the element region 27 provided with the CMOS transistor and the like and the other element region 15 are separated by two dividing trenches 16. With this configuration, it is possible to prevent a high-speed potential change generated in the LDMOS transistor 5 in each element region 15 from propagating to a device such as a CMOS transistor. The above is the configuration of the semiconductor device according to the present embodiment.

  Next, the operation of the semiconductor device will be described. As shown in FIG. 1, each element region 15 is surrounded by a demarcation trench 16 within a certain range, and further within the range surrounded by the demarcation trench 16, along the drain electrode 14, is the element formation substrate. 1, the isolation trench 17 is provided, and the element region 15 is subdivided. That is, the switching speed of the LDMOS transistor 5 in each region differs because the area of the LDMOS transistor 5 is different.

  In addition, gate resistors 20 to 22 and 24 having different values are connected to each element region 15 and each region separated in the element region 15. When the resistance values of the gate resistors 20 to 22 and 24 are different, the switching speed of the LDMOS transistor 5 in each region is different.

  Therefore, the switching voltage waveform of the entire LDMOS transistor 5 is adjusted by utilizing the fact that the areas of the LDMOS transistors 5 are different and the resistance values of the gate resistors 20 to 22 and 24 connected to the LDMOS transistors 5 are different. Since the area of the LDMOS transistor 5 can be roughly determined by the dividing trench 16 and the isolation trench 17 as described above, the resistance values of the gate resistors 20 to 22 and 24 connected to each region are adjusted.

  As a result, not all the LDMOS transistors 5 in each region are operated at the same time as in the prior art, but the LDMOS transistor 5 can be operated in accordance with the weights of the resistance values of the gate resistors 20 to 22 and 24 for each region. . Therefore, when the resistance values of the gate resistors 20 to 22 and 24 are changed, the entire voltage waveform between the drain and the source of the LDMOS transistor 5 in the semiconductor device does not change, but among the voltage waveforms shown in FIG. For example, only the rising 31 portion and the falling 32 portion can be adjusted independently. In this way, by adjusting the resistance values of the gate resistors 20 to 22 and 24 connected to the respective regions, the voltage waveform shown in FIG. 10 can be brought close to a sine wave.

  As described above, in the present embodiment, the element region 15 is surrounded by the dividing trench 16, and the element region 15 is further insulated and isolated from any of the element regions 15 surrounded by the dividing trench 16. A feature is that an isolation trench 17 is provided.

  Thereby, the LDMOS transistor 5 in one element region 15 can be subdivided into a plurality of regions. In this case, since the isolation trench 17 is provided in the element region 15 surrounded by the dividing trench 16, the isolation region width for forming the isolation trench 17 is not required, and the LDMOS transistor 5 is arranged in a plurality of regions. Can be separated.

  Since the gate resistors 20 to 22 and 24 having different resistance values can be connected to the respective regions of the LDMOS transistor 5 having different areas, the switching voltage waveform of the entire LDMOS transistor 5 can be made smooth, and as a result, a sine wave. Can be approached.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. FIG. 3 is a cross-sectional view of the semiconductor device according to the present embodiment and corresponds to a cross section taken along line AA ′ of FIG. As shown in this figure, in the present embodiment, an N + type buried layer 28 is provided between the insulating film 3 and the element formation substrate 1. The buried layer is a layer used when a device such as a CMOS transistor is formed.

  As described above, when the buried layer 28 is provided in the semiconductor device, as shown in FIG. 3, the isolation trench 17 is formed so as to penetrate the buried layer 28 and reach the insulating film 3. Although not shown, the dividing trench 16 is also formed so as to penetrate the buried layer 28 and reach the insulating film 3. As described above, a configuration using the buried layer 28 can be employed.

(Third embodiment)
In the present embodiment, only different portions from the above embodiments will be described. FIG. 4 is a plan view of the semiconductor device according to the present embodiment. As shown in this figure, the dividing trench 16 has sides 16 a and 16 b parallel to the source electrode 13 and the drain electrode 14. The sides 16 a and 16 b are arranged along the terminal source electrode 13 or the drain electrode 14 that are alternately arranged in the element region 15.

  Note that the sides 16 a and 16 b indicate a part of each side of the rectangular layout projected onto the element formation substrate 1 when the dividing trench 16 is viewed from the element formation substrate 1 side to the support substrate 2 side.

  In this embodiment, since the drain electrode 14 is terminated in the element region 15, the sides 16 a and 16 b of the dividing trench 16 are arranged along the terminated drain electrode 14. Thereby, the occupation area of the element region 15 can be reduced.

(Fourth embodiment)
In the present embodiment, only different parts from the first embodiment will be described. FIG. 5 is a plan view of the semiconductor device according to the present embodiment. As shown in this figure, the isolation trench 17 is separated from the dividing trench 16. In this way, the separation trench 16 and the isolation trench 17 can be separated from each other.

(Fifth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. In each of the above embodiments, the isolation trench 17 is disposed between the insulating film 3 and the drain electrode 14 in the element region 15. However, in this embodiment, the isolation trench 17 is isolated between the insulating film 3 and the source electrode 13. It is characterized by arranging the trench 17 for use.

  FIG. 6 is a plan view of the semiconductor device according to the present embodiment. As shown in this figure, the isolation trench 17 is provided between the source electrode 13 and the insulating film 3 in the element formation substrate 1. As described above, the isolation trench 17 can be disposed in the element formation substrate 1 where the source electrode 13 is formed. Even if the isolation trench 17 is arranged in this way, a plurality of electrically insulated regions can be formed in one dividing trench 16.

(Sixth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. In each of the above embodiments, the isolation trench 17 is disposed at a position where either the drain electrode 14 or the source electrode 13 is disposed. In the present embodiment, the insulating film 3 and the drain electrode are disposed in the element region 15. 14 and the insulating film 3 and the source electrode 13 are both provided with isolation trenches 17.

  FIG. 7 is a plan view of the semiconductor device according to the present embodiment. As shown in this figure, the isolation trenches 17 are provided in the element formation substrate 1 both between the insulating film 3 and the drain electrode 14 and between the insulating film 3 and the source electrode 13. . As described above, the isolation trench 17 can be provided at a location corresponding to both the source electrode 13 and the drain electrode 14 instead of either one.

(Seventh embodiment)
In the present embodiment, only different portions from the above embodiments will be described. FIG. 8 is a schematic diagram of the semiconductor device according to the present embodiment. As shown in this figure, the conductor 19 and the gate electrode 11 in the isolation trench 17 are connected to the control circuit 29, respectively.

  If the isolation trench 17 is provided between the insulating film 3 and the drain electrode 14, information on the potential of the drain of the LDMOS transistor 5 is input to the conductor 19 via the oxide film 18 and input to the control circuit 29. Is done. Similarly, if the isolation trench 17 is provided between the insulating film 3 and the source electrode 13, information on the potential of the source of the LDMOS transistor 5 is input to the control circuit 29 via the oxide film 18 and the conductor 19. .

  The control circuit 29 inputs either the drain potential or the source potential of the LDMOS transistor 5 through the oxide film 18 and the conductor 19, and uses the potential to switch the gate of the LDMOS transistor 5 for switching. A control signal is generated, and this gate control signal is input to the gate electrode 11. The control circuit 29 includes the gate resistors 20 to 22 and 24 shown in FIG. 1 and outputs a gate control signal through the gate resistors 20 to 22 and 24. The control circuit 29 is formed on the same element formation substrate 1 as the LDMOS transistor 5.

  Thus, by acquiring the information on the potential of the LDMOS transistor 5 using the control circuit 29, the information on the potential can be reflected in the generation of the gate control signal input to the gate electrode 11. Thereby, the accuracy of the switching voltage waveform of the LDMOS transistor 5 can be further improved.

  When acquiring information on the potential of the LDMOS transistor 5 as in this embodiment, the conductor 19 is preferably provided only in the isolation trench 17. When the conductor 19 is provided in the dividing trench 16, information on the LDMOS transistor 5 in another region insulated by the conductor 19 is included. For this reason, the conductor 19 can be disposed in all of the dividing trench 16 and the isolation trench 17, but in order to individually acquire only the information on the drain potential of the LDMOS transistor 5 and only the information on the source potential, It is desirable that the conductor 19 is formed only in the isolation trench 17. In this case, the oxide film 18 is formed in the dividing trench 16.

  Further, in the embodiment shown in FIG. 8, the control circuit 29 is connected to the conductor 19 and the gate electrode 11 in one isolation trench 17, but the other conductors in the isolation trench 17 not shown. 19 and other gate electrodes 11 can be connected to the control circuit 29. As a result, the potential information in the LDMOS transistor 5 in each region can be acquired.

(Eighth embodiment)
In the present embodiment, only different portions from the above embodiments will be described. FIG. 9 is a schematic diagram of the semiconductor device according to the present embodiment. As shown in this figure, the conductor 19 in the isolation trench 17 is connected to the control electrode 30. A constant potential for changing a current path between the drain and source of the LDMOS transistor 5 from the control electrode 30 is applied to the conductor 19. Thereby, the resistance between the drain and the source can be changed, and the switching voltage waveform of the LDMOS transistor 5 can be finely controlled.

(Other embodiments)
In each of the above embodiments, the semiconductor device provided with the gate resistors 20 to 22 and 24 is shown, but the semiconductor device and the gate resistors 20 to 22 and 24 may be separated. In this case, the gate resistances 20 to 22 and 24 are not provided in the semiconductor device, and are connected to the gate resistances 20 to 22 and 24 via the wiring outside the semiconductor device.

  In each of the above-described embodiments, the SOI substrate 4 or the insulating film 3 and the element formation substrate 1 are illustrated as being provided with the buried layer 28. However, the SOI substrate 4 may not be used. . That is, the support substrate 2 may not be provided, and the element formation substrate 1 and the buried layer 28 may be provided on the insulating film 3.

  The element structure of the LDMOS transistor 5 shown in FIG. 2, FIG. 3, FIG. 8, and FIG. 9 is an example, and other element structures may be used.

  About each embodiment, while each can be implemented independently, it can also carry out combining each embodiment. For example, by combining the third embodiment and the sixth embodiment, the isolation trench 17 is disposed both between the insulating film 3 and the drain electrode 14 and between the insulating film 3 and the source electrode 13, The sides 16 a and 16 b of the dividing trench 16 can be arranged between the terminal electrode of the drain electrode 14 and the source electrode 13 arranged alternately and the insulating film 3. Further, the control circuit 29 shown in the seventh embodiment may be applied to the semiconductor device of another embodiment. In this way, the embodiments can be combined.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. (A) is A-A 'sectional drawing of FIG. 1, (b) is B-B' sectional drawing of FIG. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. It is a top view of the semiconductor device concerning a 4th embodiment of the present invention. It is a top view of the semiconductor device concerning a 5th embodiment of the present invention. It is a top view of the semiconductor device concerning a 6th embodiment of the present invention. It is the schematic of the semiconductor device which concerns on 7th Embodiment of this invention. It is the schematic of the semiconductor device which concerns on 8th Embodiment of this invention. It is a figure for demonstrating a subject, and is a figure which showed the time change of the drain-source voltage of an LDMOS transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Element formation substrate, 3 ... Insulating film, 5 ... LDMOS transistor, 11 ... Gate electrode, 13 ... Source electrode, 14 ... Drain electrode, 15 ... Element region, 16 ... Dividing trench, 16a, 16b ... Dividing trench Sides, 17 ... isolation trenches, 18 ... oxide film, 19 ... conductor, 20-22, 24 ... gate resistance, 23 ... electrode, 28 ... buried layer, 29 ... control circuit.

Claims (6)

A semiconductor substrate (1) is disposed on the insulating film (3), and source electrodes (13) disposed alternately in stripes on the opposite side of the semiconductor substrate (1) from the insulating film (3) side; and A plurality of element regions (15) in which LDMOS transistors (5) including a drain electrode (14) are formed are provided,
Each of the plurality of element regions (15) is provided in the semiconductor substrate (1) and surrounded by a dividing trench (16) reaching the insulating film (3),
In any one of the plurality of element regions (15) surrounded by the dividing trench (16), between the insulating film (3) and the source electrode (13) and between the insulating film (3) and the An isolation trench that penetrates the semiconductor substrate (1) along the drain electrode (14) or the source electrode (13) and reaches the insulating film (3) at least between the drain electrode (14) and the drain electrode (14) (17) is formed ,
The source electrodes (16a, 16b) parallel to the source electrode (13) and the drain electrode (14) in the dividing trench (16) are alternately arranged in the element region (15). 13) and the drain electrode (14), the semiconductor device being provided between the terminal electrode and the insulating film (3) . The LDMOS transistor (5) has a gate electrode (11) along the source electrode (13) or the drain electrode (14),
In the element region (15) surrounded by the dividing trench (16), gate resistors (20 to 22) having different values for the gate electrodes (11) in the respective regions separated by the separating trench (17). Are connected to each other, and the gate resistors (20 to 22) are connected to the same electrode (23). A buried layer (28) is provided between the semiconductor substrate (1) and the insulating film (3),
The cutting trench (16) and the isolation trench (17) are formed so as to penetrate the buried layer (28) and reach the insulating film (3). 2. The semiconductor device according to 2. The isolation trench (17) The semiconductor device according to any one of claims 1 to 3, characterized in that spaced with the dividing trench (16). Of the dividing trench (16) and the isolation trench (17), an oxide film (18) is formed at least on the side wall of the isolation trench (17), and a conductor ( 19) is formed,
Either the drain potential or the source potential of the LDMOS transistor (5) is input through the oxide film (18) and the conductor (19), and the LDMOS transistor (5) is input using these potentials. the semiconductor device according to any one of claims 1 to 4, characterized in that a control circuit for generating a gate control signal for switching driving (29) the. Of the dividing trench (16) and the isolation trench (17), an oxide film (18) is formed at least on the side wall of the isolation trench (17), and a conductor ( 19) is formed,
A constant potential for changing a current path between a drain and a source of the LDMOS transistor (5) is applied to the conductor (19). 5. The semiconductor device according to any one of 4 .

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