JP5154375B2 - Digital processing circuit - Google Patents

Description

  The present invention relates to a digital processing circuit with a test function having a logic circuit such as a digital signal processor (hereinafter referred to as “DSP”) and a delta-sigma modulator (hereinafter referred to as “DSM”).

FIG. 4 is a block diagram showing a conventional digital processing circuit 10.
The digital processing circuit 10 with a test function includes a serial audio interface (hereinafter referred to as “SAI”) 11, a DSP 12, a DSM 13, and a parallel-serial converter (hereinafter referred to as “P / S converter”) 14. I have.

  The SAI 11 has a function of serially parallel-converting and outputting pulse code modulation (hereinafter referred to as “PCM”) data serially input from the outside, and a tester is connected to the input side of the SAI 11. A test terminal PIN1 is provided. A DSP 12 is connected to the output side of the SAI 11, and a DSM 13 and a P / S converter 14 are connected to the output side of the DSP 12. On the output side of the P / S converter 14, a test terminal PIN2 for connecting a tester and outputting a test result is provided.

  Conventionally, in such a digital processing circuit 10, a test pattern is input serially to test whether the logic unit operates normally. For example, using a tester (not shown), test data is serially input from the test terminal PIN 1 and converted into parallel by the SAI 11. This data is input to the DSP 12, and 16-bit data is oversampled by 8 times every 256 clocks in the DSP 12, and 19-bit data is output as a processing result.

  The processing result is further oversampled 64 times by the DSM 13, and 5-bit data is output as the processing result. On the other hand, the processing result of the DSP 12 is also output to the test terminal PIN2, and it is tested whether the DSP 12 operates normally by collating with the reference value by the tester. However, as for the processing result of the DSM 13, it is necessary to serially transfer 5 bits of data with 4 clocks.

  Such techniques relating to logic circuit testing are described, for example, in the following documents.

JP 2001-229046 A

  In Patent Document 1, a test circuit is provided in a logic LSI chip, the internal state of the DSP is temporarily transferred to a storage device at a specified breakpoint, and further transferred to a host device such as a personal computer. A case is described in which it is easy to verify the internal state in the DSP real-time processing.

  However, in the conventional digital processing circuit 10, as described above, when the 5-bit data is output by oversampling the DSM 13 64 times, the 5-bit serial data is converted into 4 clocks (256 clocks / 64 Times) must be transferred. In this case, there is a problem that testing of the DSM 13 mounted on the digital processing circuit 10 becomes impossible due to the limit of the serial transfer capability.

  In order to solve such a problem, for example, a digital processing circuit 10A with a test function as shown in FIG. 5 has been proposed.

  FIG. 5 is a block diagram showing another conventional digital processing circuit 10A. Elements common to those in FIG. 4 showing the conventional digital processing circuit 10 are denoted by common reference numerals.

  In the digital processing circuit 10A of FIG. 5, a selector 15 is added to the digital processing circuit 10 of FIG. A DSP 12 and a DSM 13 are connected to the input side of the selector 15, and a P / S converter 14 is connected to the output side. The selector 15 selects an input signal based on the select signal st and outputs it to the P / S converter 14.

  When testing the digital processing circuit 10A, it is as follows. For example, using a tester (not shown), test data is serially input from the test terminal PIN 1 and converted into parallel by the SAI 11. This data is input to the DSP 12, and 16-bit data is oversampled by 8 times every 256 clocks in the DSP 12, and 19-bit data is output as a processing result.

  The processing result is further oversampled 64 times by the DSM 13, and 5-bit data is output as the processing result. Here, 5-bit data must be serially transferred in 4 clocks, but cannot be transferred as it is due to the limit of serial transfer capability. Therefore, the 5-bit output data of the DSM 13 is divided into upper 1 bit and lower 4 bits and input to the selector 15, and when the selector 15 is switched, the upper 1 bit test and the lower 4 bit test are divided into two tests. It is the composition which performs.

  As a result, the DSP 12 test performed by selecting the DSP 12 processing result by the select signal st, the DSM 13 upper bit test performed by selecting the upper bit of the DSM 13 processing result, and the DSM 13 processing result The test is performed three times for the convenience of the lower bit test of the DSM 13 performed by selecting the lower bit.

  As a result, the digital processing circuit 10A in FIG. 5 can test the DSM 13 that could not be performed in the digital processing circuit 10 in FIG. There was a problem of bringing about an increase.

  The digital processing circuit of the present invention includes a first logic unit that inputs a test signal, performs a predetermined logic process based on the test signal, and outputs a first processing result of n bits (n: positive integer). Are connected in cascade to the first logic unit, input the first processing result, perform logic processing based on the first processing result, and perform m-bit (m; positive integer) second In the first test mode, a second logic unit that outputs a processing result, a shift register that sequentially takes in a specific m1 bit of the second processing result and outputs it at a predetermined timing, and a select signal. The first processing result and the output of the shift register are selected, and in the second test mode, the remaining m2 bits (m2 = m−m1) of the second processing result are selected and tested. result And a selector for outputting.

The present invention has the following effects.
The digital processing circuit according to the present invention includes a shift register that sequentially takes in a specific m1 bit of the second processing result of the second logic unit and outputs it at a predetermined timing, and a select signal. Sometimes, the selector selects the first processing result and the output of the shift register, and in the second test mode, selects the remaining m2 bits (m2 = m−m1) of the second processing result. Therefore, it is possible to test the logic unit in two convenient tests. For this reason, the test time can be shortened compared to the conventional case where three tests are required.

  The best mode for carrying out the invention will become apparent from the following description of the preferred embodiments when read in conjunction with the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a configuration diagram showing a digital processing circuit 20 according to the first embodiment of the present invention.

  The digital processing circuit 20 is a circuit with a test function having a large-scale integrated circuit such as a DSP 22 or a DSM 23. In the digital processing circuit 20, a test signal PIN1 for inputting a start signal start for notifying the start of a logic test, a clock signal clk for synchronizing the entire circuit, and PCM data such as sound by a tester (not shown) is provided in the SAI 21. It is connected to the. The SAI 21 converts test data input serially into parallel data, and an output side thereof is connected to a first logic unit (for example, DSP) 22.

  The DSP 22 performs digital signal processing at high speed and outputs a first processing result dsp (out). The output side oversamples the digital signal at a sufficiently high frequency, re-quantizes noise, and performs second quantization. The second logic unit (for example, DSM) 23 that outputs the processing result dsm (out) is connected to one terminal of the selector 25.

  The output side of the DSM 23 is connected to the shift register 24 (for example, SR) and the other terminal of the selector 25. The output side of the SR 24 is connected to one terminal of the selector 25.

  The selector 25 selects and outputs an input signal according to the select signal st. The output side of the selector 25 is connected to a P / S converter 26 that converts parallel data into serial data, and a test terminal PIN2 is further connected. The test terminal PIN2 is connected to a tester (not shown), and test result data t (out) is output. The output test result data is compared with an expected value by a tester (not shown) to determine whether or not the logic circuit to be tested is normal.

(Test method of Example 1)
The test according to the first embodiment includes a first test mode and a second test mode. The first test mode is a mode for testing the DSP 22 and the upper bits of the DSM 23, and the second test mode is a mode for testing the lower bits of the DSM 23.

  FIG. 2 is a timing chart of the first test mode in the digital processing circuit 20 of FIG.

  In the digital processing circuit 20 of FIG. 1, the DSP 22 and the DSM 23 are tested as follows.

  Via a test terminal PIN1, a start signal start for notifying the start of a logic test from a tester and a clock signal clk for synchronizing the entire circuit are input. PCM data such as audio is serially input to the SAI 21 in synchronization with the clock signal clk. The SAI 21 converts this into parallel data and outputs it to the DSP 22. The DSP 22 executes predetermined digital signal processing based on the input test data, and outputs a first result dsp (out) of n bits (for example, 19 bits) every 32 clocks.

  The DSM 23 takes in the first processing result dsp (out) of n bits (for example, 19 bits) output from the DSP 22, performs oversampling processing, and performs the second processing result of m bits (for example, 5 bits). dsm (out) is output. The second processing result dsm (out) is, for example, 8 data of 5 bits every 4 clocks. If an attempt is made to output the second processing result dsm (out) serially to the tester, m bits (for example, 5 bits) must be transferred in 4 clocks, making transfer impossible.

  Therefore, of the m-bit (for example, 5 bits) second processing result dsm (out), the m1 bit (for example, 1 bit) is sequentially taken into the SR 24 every four clocks, and is held by repeating shift and storage. , Is output by a trigger signal from the P / S converter 26 every 32 clocks, and is input to one terminal of the selector 25 together with the first processing result. The remaining m2 bits (for example, 4 bits) are input to the other terminals of the selector 25.

  Since the first test mode is set for the selector 25 and the P / S converter 26 by the select signal, the output of the SR 24 and the first processing result are selected and output to the P / S converter 26. (Route of tr1 in FIG. 1). In the P / S converter 26, the parallel data is converted into serial data and output to the test terminal PIN2. The output test result data is compared with an expected value by a tester (not shown) to determine whether or not the logic circuit to be tested is normal.

  FIG. 3 is a timing chart of the second test mode in the digital processing circuit 20 of FIG.

  In the test mode 2, PCM data such as voice is serially input to the SAI 21 from the tester via the test terminal PIN1, and the SAI 21 converts this into parallel data and outputs it to the DSP 22, and the DSP 22 inputs the test Based on the data, predetermined digital signal processing is executed, and a first processing result dsp (out) of n bits (for example, 19 bits) is output every 32 clocks.

  The DSM 23 takes in the first processing result dsp (out) of n bits output from the DSP 22, performs oversampling processing, and performs eight second processing results of m bits (for example, 5 bits) every four clocks. dsm (out) is output.

  Next, m1 bits (for example, 1 bit) of m bits (for example, 5 bits) of output data dsm (out) are input to the SR 24 as the second processing result, and the remaining m2 (for example, 4 bits). ) Is input to the other terminal of the selector 25.

  A select signal st is input to the selector 25 and the P / S converter 26, and the second test mode is set. When the second test mode is set, the selector 25 selects the remaining m2 bits of the second processing result and sends them to the P / S converter 26 (route tr2 in FIG. 1). . The P / S converter 26 converts the parallel data into serial data and outputs it to the test terminal PIN2. The output test result data is compared with an expected value by a tester (not shown) to determine whether or not the logic circuit to be tested is normal.

(Effect of Example 1)
According to the first embodiment, the digital processing circuit 20 includes a DSP 22 that outputs a first processing result dps (out), a DSM 23 that outputs a second processing result dsm (out), and a second processing result dsm. The specific m1 bits of (out) are sequentially fetched and output at a predetermined timing, and the output of the first processing result dps (out) and SR24 is selected in the first test mode by the select signal and the select signal. In the second test mode, the selector 25 selects the m2 bit (m2 = m−m1) of the second processing result dsm (out). Part testing is possible. For this reason, the test time can be shortened compared to the conventional case where three tests are required.

(Modification)
The present invention is not limited to the above-described embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (c) are available as usage forms and modifications.

  (A) The first logic unit and the second logic unit are not limited to the DSP 22 and the DSM 23, respectively. Other logic circuits may be used.

  (B) In the first embodiment, the input data is described as an example of PCM data such as voice, but it may be image processing data or the like.

  (C) In the first embodiment, 1-bit data is sequentially input to the SR 24. However, the data is not limited to 1 bit, and a plurality of bits may be used.

It is a block diagram which shows the digital processing circuit 20 in Example 1 of this invention. 2 is a timing chart of a first test mode in the digital processing circuit 20 of FIG. 1. 3 is a timing chart of a second test mode in the digital processing circuit 20 of FIG. 1. 1 is a configuration diagram showing a conventional digital processing circuit 10. FIG. It is a block diagram which shows the other conventional digital processing circuit 10A.

Explanation of symbols

10, 10A Digital processing circuit 11 SAI
12 DSP
13 DSM
14 P / S converter 15 Selector 20 Digital processing circuit 21 SAI
22 DSP
23 DSM
24 SR
25 Selector 26 P / S Converter

Claims (4)

A first logic unit that inputs a test signal, performs predetermined logic processing based on the test signal, and outputs a first processing result of n bits (n; a positive integer);
The second logic unit is connected in cascade to the first logic unit, inputs the first processing result, performs predetermined logic processing based on the first processing result, and performs m-bit (m: positive integer) second. A second logic unit that outputs the processing result of
A shift register that sequentially captures specific m1 bits of the second processing result and outputs them at a predetermined timing;
In response to the select signal, the first processing result and the output of the shift register are selected in the first test mode, and in the second test mode, the remaining m2 bits ( a selector that selects m2 = m−m1) and outputs a test result;
A digital processing circuit comprising: The digital processing circuit according to claim 1 comprises:
The digital processing circuit according to claim 1, further comprising a parallel-serial converter that converts the test result of the parallel signal output from the selector into a serial signal and outputs the serial signal.   The digital processing circuit according to claim 1, wherein the first logic unit is a digital signal processor.   The digital processing circuit according to claim 1, wherein the second logic unit includes a delta-sigma modulator.

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