JP2006250824A - Semiconductor integrated circuit and data analysis method for the semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To debug a serial interface, using a simple measuring apparatus. <P>SOLUTION: The circuit is constituted of a deserializer, a decoding circuit, a memory, a trigger control circuit, a writable control circuit, etc. The deserializer is input with serial data which signed parallel data produced with a signed circuit are series-converted and converts the serial data into coded parallel data. The decoding circuit decodes data. The decoding circuit decodes the signed parallel data into parallel data and outputs error detection signal, when there are errors. The coded parallel data converted with the deserializer is written in the memory, in turn. The trigger control circuit responds to the error detection signal, outputs command for adding an error flag to the coded parallel data which the error contained in the memory is detected and outputs a writing stop signal. The writing control circuit responds to the writing stop signal and stops the writing motion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a data analysis function of a high-speed serial interface, and a data analysis method in the semiconductor integrated circuit.

  In recent years, information processing devices such as personal computers, server devices, and communication devices have become widespread due to the rapid spread of the Internet. Information processing devices are always required to have a higher level of information processing capability. Techniques for improving the information processing capability include increasing the data processing speed in the apparatus and increasing the bandwidth in data transmission. With the demand for higher information processing speed, the bandwidth of data handled by a semiconductor integrated circuit (LSI: Large Scale Integration) mounted on an information processing apparatus has also increased dramatically. Therefore, the demand for high-speed interfaces between LSIs is increasing.

  While speeding up LSI data transfer, many adverse effects due to the parallel interface have come out. In order to suppress this adverse effect, a serial interface has been adopted as a method for securing a data transmission band. This trend is gradually increasing with respect to data transmission inside personal computers. For example, in recent personal computers, Serial ATA corresponding to IDE has been adopted. In addition, there is a tendency that PCI-Express corresponding to AGP or PCI bus is adopted.

  As a technology indispensable for realizing a high-speed serial interface such as Serial ATA and PCI-Express, there is a serial-parallel conversion technology (hereinafter referred to as SERDES). In order to realize SERDES, a circuit block in which a serializer that converts parallel data for data transmission into serial data and a deserializer that converts serial data into parallel data are integrated (Hereinafter referred to as a SERDES circuit), and data transfer is executed using an interface equipped with the SERDES circuit.

  FIG. 1 is a block diagram illustrating a configuration of a physical layer of PCI-Express. As shown in FIG. 1, the PCI-Express includes a transmission block 101 and a reception block 102. Referring to FIG. 1, a transmission block 101 is a transmission side block, and a reception block 102 is a reception side block. In PCI-Express, since the transmission path is not used in both directions, the transmission / reception link is configured by combining this figure and the circuit in which the signal transmission direction is opposite. In a high-speed serial interface such as PCI-Express, a technique called SERDES in which circuits such as a serializer 105 and a deserializer 112 of a transmission / reception block are integrated is adopted. In PCI-Express, a method of transferring data not only by one link but also by a plurality of links of two links, four links, and eight links is defined. FIG. 1 is an example of two links. Although not shown in FIG. 1, it is assumed that the transmission block 101 and the reception block 102 are mounted on separate LSIs and exchange signals between the LSIs.

  In PCI-Express, when data is transferred via a transmission path, the data transferred from the upper layer is stored in the input FIFO 103 of the transmission block 101. Next, the data is transferred to the 8B10B encoding circuit 104. In high-speed serial transmission such as PCI-Express, a system called 8B10B encoding system is employed to serialize parallel data. The 8B10B encoding method is a method of treating 8-bit parallel data as one lump and converting this lump into a 10-bit code.

  The data converted to 10 bits is transferred to the serializer 105. The serializer 105 is a circuit that converts low-speed parallel data into high-speed serial data for sending out to one transmission line. In PCI-Express, data is output at 3.125 Gbit / s. The 3.125 GHz transmission clock is generated by the synthesizer circuit 107 from the 156.25 MHz reference clock. The serial data generated by the serialization 105 is output to the transmission path 108 by the output buffer 106.

  Serial data output from the transmission block is input to the reception block 102 via the transmission path 108 and the input buffer 110. The clock recovery circuit 111 recovers the clock from the received serial data. In high-speed serial transmission of the order of several Gbits / s, the waveform is considerably broken on the transmission path of the board, so that data cannot be sampled correctly even if a clock signal synchronized with the data is sent separately. Therefore, a clock synchronized with a change in received data is reproduced. In the case of PCI-Express, a clock synchronized with data is reproduced by a 3.125 GHz clock generated by the synthesizer circuit 109 from a 156.25 MHz reference clock.

  Serial data sent via one transmission path is converted into low-speed parallel data of 10 bits by the deserializer circuit 112. Subsequently, the data is returned to 8-bit data by the 8B10B decoding circuit 113.

  When a transmission line drawn on a printed circuit board is transmitted at a high speed exceeding 2 Gbit / s, a loss in the printed pattern cannot be ignored, which greatly affects the signal waveform. In such a transmission line, if the H level or L level continues for a long time and then a short change occurs, the level cannot be lowered sufficiently or cannot be raised sufficiently, resulting in malfunction.

  In order to suppress such malfunctions, in high-speed serial transmission, the transfer density is adjusted by 8B10B encoding. Data transmitted by high-speed serial transmission is converted by the 8B10B encoding circuit 104 into a 10-bit code so that the same level does not continue for a long time on the transmission path. As a result, data having a long H level or L level is not transmitted, and malfunction can be avoided. The 10-bit data to be converted from 8-bit data is determined by a standard code table.

  In the 8B10B decoding circuit 113, the disparity is verified simultaneously with the conversion according to the code table. Disparity is the difference between the number of 1s and 0s in a data block. In the 8B10B encoding method, the disparity is one of 0 (5 1s and 0s), +2 (6 1s and 4 0s), and -2 (4 1s and 6 0s). The continuous disparity is a disparity with respect to the total of all the codes so far, and is either +1 or -1. For example, if the disparity is not 0, +2, or -2, the symbol is an error. An error also occurs when the disparity is +2 (−2) and the continuous disparity is +1 (−1).

  The data converted into 8 bits is stored in the output FIFO 114. In the case of PCI-Express, data may be transferred through a plurality of links. Although each link operates independently, there is no guarantee that the link wiring length is the same. Therefore, even if the transmission side transmits to all the links simultaneously, there is no guarantee that the reception side will receive the calls simultaneously. When using two or more links, it is necessary to cover this difference at the upper level. Therefore, a certain amount of data is stored in the output FIFO 114 and the timing between the links is aligned and output on the parallel side.

  In 8B10B encoding, 12 special characters are added to the code in addition to the 8-bit 256 characters, and the special characters are used as control signals. When the transmission side starts data transfer, it adds a special character indicating the beginning of the data. The receiving side recognizes the start of data reception by detecting special characters from the data string during decoding. The inter-link synchronous read control circuit 115 and the output FIFO 114 realize data synchronization between links by reading out the data from the output FIFOs of all the links with reference to the code indicating the head of the data.

JP 2003-224469 A

  Compared with the conventional bus type connection, SERDES has a configuration in which a SERDES circuit is provided at both ends of a transmission path for transmitting serial data. Therefore, the information processing apparatus adopting SERDES has a complicated interface, which leads to an increase in verification items and a longer development period in the development stage. For this reason, the time that can be spent on the debugging work using the substrate on which the SERDES circuit is actually mounted is pressed.

  A high-speed serial interface employs a low-amplitude differential digital circuit. Low-amplitude differential digital circuits have high data rates and are generated by periodic power supply modulation on the substrate and power plane, crosstalk from peripheral circuits, and impedance mismatch in the transmission path. Various jitters greatly affect transmission quality.

  The quality of the transmission path is monitored by checking whether the data corresponding to the code table has arrived or whether the disparity matching is maintained in the 8B10B decoding circuit 113 on the receiving side. When a 10-bit data pattern not included in the code table is detected, or when a disparity mismatch is detected, a data error occurs. An error also occurs when the interlink read control circuit 115 cannot synchronize data between links because the control code does not arrive correctly. As the transmission signal follows the trend of higher speed and lower voltage, the effect of loss increases, and data errors often occur at the initial stage of substrate production due to problems such as pattern-dependent jitter.

  In order to improve the quality of the transmission path and eliminate errors, analysis on the actual machine is required. FIG. 2 is a diagram in which a measuring instrument is inserted as an example of an operation for debugging a transmission line. As an analysis work, a transmission signal on the transmission side is input to a digital oscilloscope 201 that can observe a signal on the order of GHz, and an eye pattern of the signal at the end of the transmission path is observed. The eye pattern is useful for measuring the overall signal quality at the end of the transmission line. Thereby, the influence by systematic and random distortion can be known, and the time when the signal is considered to be effective can be known. The opening of the eye pattern above and below the receiver threshold level indicates a margin for noise during sampling. The extent of the transition region across the receiver threshold level indicates jitter between the peaks of the data signal. Jitter occurs when the logic state of the signal transitions. Jitter is reduced by taking measures against noise in the wiring and the transmission side LSI, and the opening of the eye pattern is increased by excluding the mismatched portion of the impedance of the transmission path.

  When there is an error detected on the receiving side due to a specific transmission pattern, or when an error occurs in a specific bit in the transmitted 8-bit parallel data, the pattern or bit may be specified. , Leading to early error resolution. Therefore, it is desirable to be able to grasp the parallel data that has caused the error and the patterns before and after that in order to efficiently proceed with debugging.

  When observing parallel data, a logic analyzer 202 is used as a measuring instrument. In order to observe with a logic analyzer, the data signal 204 immediately after being converted into parallel is output to the outside of the LSI. An error detection signal 203 is also output to the outside as a trigger signal for the logic analyzer. Write the received parallel data to the logic analyzer memory, stop when an error is detected, and observe the parallel data that caused the error and the data before and after.

  This method has the following problems. The data rate after parallel conversion falls to about 1/10 to 1/20 of the serial clock. For example, in the case of PCI Express, the data rate on the serial transmission line is 3.125 Gbit / s, and when converted to 10-bit parallel data, it is 312.5 Mbit / s. When converted into 20-bit parallel data, it becomes 156.25 Mbit / s. It is necessary to observe a 10-bit to 20-bit signal of 156.25 M to 312.5 MHz per link. Logic analyzers that can observe multi-bit signals on the order of several hundred MHz are very expensive. Also, in order to input a signal to the logic analyzer, a pin for outputting a parallel data signal is required for the LSI, and it is necessary to install a connector by pulling it out on the board. And lead to an increase in package cost.

  Furthermore, with the increase in the speed of transmission lines and the reduction in voltage, advanced design techniques have been required for the boards on which the transmission lines are wired and mounted. For example, noise countermeasures are becoming more important than conventional techniques. In many cases, a substrate made with insufficient countermeasures against noise may cause an operation failure unexpectedly, necessitating long-term debugging or revision of the substrate. As for the debugging operation of the substrate, in the case of the conventional low-rate signal, the probe of the measuring instrument can be directly applied to the signal and the waveform can be observed. However, as described above, a measuring instrument that can observe a high-speed signal of several Gbps is very expensive and the test cost is very high. It is desirable to shorten the development period and to efficiently debug the substrate.

  In serial interface debugging, there is a demand for a technique that enables efficient serial interface debugging without using expensive measuring instruments.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

In order to achieve the above object, according to the present invention, encoded parallel data generated by an encoding circuit that converts m (m is a natural number) bit data into n (n is a natural number greater than m) bit data is converted. A deserializer that receives serial data converted into serial data and converts the serial data into the encoded parallel data;
A circuit for decoding the n-bit data into the m-bit data, wherein the encoded parallel data converted by the deserializer is decoded into decoded parallel data, and the encoding converted by the deserializer A decoding circuit that outputs an error detection signal when there is an error in the parallel data; and
A memory for sequentially writing the encoded parallel data converted by the deserializer;
Trigger that outputs an instruction to add an error flag to the encoded parallel data in which an error stored in the memory is detected in response to the error detection signal and outputs a write stop signal at a predetermined timing A control circuit;
And a write control circuit that stops the write operation in response to the write stop signal.

  Taking the case where the above-described decoding circuit is an 8B10B decoding circuit as an example, in order to easily analyze data when an error occurs in the data transmitted to and received from the SERDES circuit, the input (= serial parameter) of the receiving side 8B10B decoding circuit is performed. A certain amount of 10B data before decoding which is an output of the circuit) is continuously stored in the memory before an error occurs. Then, the writing to the memory is stopped by an error detection signal generated when the 8B10B decoding circuit detects an error.

  According to the present invention, it is possible to provide an LSI that enables efficient serial interface debugging without using an expensive measuring instrument in serial interface debugging.

According to the present invention, when a data error failure occurs in an LSI employing a high-speed serial interface such as PCI-Express or Serial ATA, the dependency of the data pattern and the tendency of data corruption Therefore, when analyzing the data after parallel reconversion, a function equivalent to that of a conventional expensive logic analyzer can be realized by a circuit mounted in the LSI, so that inexpensive analysis can be realized.
More specifically, since valuable error information is included in the input of the 8B10B decoding circuit on the receiving side, reception signals (patterns) before and after the occurrence of an error can be secured by this action. In addition, the data stored in the memory is read out as serial data prepared separately from the memory without using the fastest serial data. It can be obtained without cost.

  In addition, according to the present invention, the JTAG interface can be applied to the analysis data output interface, so the conventional test signal output terminals provided in the LSI for observing parallel data can be reduced. It is possible to reduce the number of pins of the LSI and the package cost.

[Configuration of First Embodiment]
Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following embodiment, a case where the high-speed serial interface is configured to support PCI-Express will be described as an example. Note that this does not clearly indicate that the present invention is compatible only with PCI-Express.

  FIG. 3 is a block diagram illustrating the configuration of the semiconductor integrated circuit of the present invention in the first embodiment. Referring to FIG. 3, a second SERDES circuit 2 shows a configuration of a normal SERDES circuit, and a first SERDES circuit 1 shows a configuration of a SERDES circuit including a data analysis unit 20 of the present invention. In the circuit block shown in FIG. 3, circuit blocks denoted by the same reference numerals in the first SERDES circuit 1 and the second SERDES circuit 2 have the same configuration. Therefore, in the following description, the description of the overlapping part between the first SERDES circuit 1 and the second SERDES circuit 2 is omitted. In addition, the circuit shown in FIG. 3 is exemplified by a combination of the first SERDES circuit 1 and the second SERDES circuit 2, but this does not limit the configuration of the present invention. Absent. For example, the first SERDES circuits 1 may be connected to each other via the transmission line 15. In the following description of FIG. 3, the case where the transmission path is one link will be described as an example so that the present invention can be easily understood.

  As shown in FIG. 3, the output path 17 of the first SERDES circuit 1 and the second SERDES circuit 2 includes an input FIFO 3, an 8B10B encoding circuit 4, a serializer circuit 5, an output buffer 6, and a synthesizer circuit 7. It is comprised including. The input path 16 of the first SERDES circuit 1 and the second SERDES circuit 2 includes a synthesizer circuit 8, an input buffer 9, a deserializer circuit 10, a clock recovery circuit 11, an 8B10B decoding circuit 12, an output FIFO 13, and a link. And an inter-synchronous readout circuit 14. Further, the first SERDES circuit 1 includes a data analysis unit 20. A detailed description of the configuration of the data analysis unit 20 will be described later.

  The input FIFO 3 is a storage circuit that stores data transferred from an upper layer. The 8B10B encoding circuit 4 is an encoding circuit that serializes parallel data based on the 8B10B encoding method. The 8B10B encoding circuit 4 treats 8-bit parallel data as one lump, converts this lump into a 10-bit code, and outputs it.

  The serializer circuit 5 is a data conversion circuit that converts low-speed parallel data into high-speed serial data for sending out to one transmission line.

  The synthesizer circuit 7 and the synthesizer circuit 8 are clock generation circuits that generate a transmission clock based on a reference clock. As shown in FIG. 3, the serializer circuit 5 described above outputs serial data to the output buffer 6 in synchronization with the transmission clock supplied from the synthesizer circuit 7.

  The serial data output from the transmission block is input to the reception block via the transmission path 15. The input buffer 9 receives serial data supplied via the transmission path 15 and outputs it to the deserializer circuit 10 and the clock recovery circuit 11. The deserializer circuit 10 is a data conversion circuit that converts serial data sent via the transmission path 15 into low-speed parallel data of 10 bits.

  The clock recovery circuit 11 is a clock generation circuit that generates a clock based on received serial data. In high-speed serial transmission on the order of several Gbit / s, the waveform collapses on the transmission path of the board. Therefore, even if a clock signal synchronized with the received data is sent separately, the data cannot be sampled correctly. Therefore, the clock recovery circuit 11 generates a synchronized clock from a change in received data and supplies it to the 8B10B decoding circuit 12. For example, in the case of PCI Express, a clock synchronized with data is generated by a 3.125 GHz clock generated by the synthesizer circuit 8 from a reference clock of 156.25 MHz.

  The 8B10B decoding circuit 12 is a decoding circuit that converts 10-bit parallel data supplied from the deserializer circuit 10 into 8-bit parallel data. Data transmitted by high-speed serial transmission is converted into a 10-bit code by the above-described 8B10B encoding circuit 4 so that the same level does not continue for a long time on the transmission path. The 8B10B encoding circuit 4 converts 8-bit data into 10-bit data based on a standard code table.

  The 8B10B decoding circuit 12 converts 10-bit data into 8-bit data according to the code table. In addition, the 8B10B decoding circuit 12 performs data conversion from 10 bits to 8 bits, and at the same time, the disparity is verified. Disparity is the difference between the number of 1s and 0s in a data block. In the 8B10B encoding method, the disparity is one of 0 (5 1s and 0s), +2 (6 1s and 4 0s), and -2 (4 1s and 6 0s). The continuous disparity is a disparity with respect to the total of all the codes so far, and is either +1 or -1. For example, if the disparity is not 0, +2, or -2, the symbol is an error. An error also occurs when the disparity is +2 (−2) and the continuous disparity is +1 (−1).

  The output FIFO 13 is a storage circuit that stores data converted into 8 bits. For example, in the case of PCI Express, data may be transferred through a plurality of links. Although each link operates independently, there is no guarantee that the link wiring length is the same. For this reason, even if transmission is simultaneously performed for all links, there may be cases where the reception side does not receive calls simultaneously. Therefore, when using two or more links, it is necessary to cover this difference at the top. Therefore, when data is transferred through a plurality of links, appropriate data transmission is realized by storing a certain amount of data in the output FIFO 13 and outputting the data to the parallel side at the same timing between the links.

The inter-link synchronous read circuit 14 is a data read control circuit that reads out data from the output FIFOs 13 of all the links. In 8B10B encoding, 12 special characters are added to the code in addition to the 8-bit 256 characters, and the special characters are used as control signals. When the transmission side starts data transfer, it adds a special character indicating the beginning of the data. The receiving side recognizes the start of data reception by detecting special characters from the data string during decoding. The inter-link synchronous read control circuit 14 and the output FIFO 13 realize data synchronization between links by reading out data from the output FIFOs of all the links with reference to the code indicating the head of the data.
Referring to FIG. 3, the first SERDES circuit 1 and the second SERDES circuit 2 are connected via a transmission line 15. As shown in FIG. 3, the serial data output from the output path 17 of the second SERDES circuit 2 is supplied to the input path 16 of the first SERDES circuit 1 through the transmission path 15. Similarly, the serial data output from the output path 17 of the second SERDES circuit 2 is supplied to the input path 16 of the first SERDES circuit 1 via the transmission line 15.

  As shown in FIG. 3, the output path 17 of the first SERDES circuit 1 and the output path 17 of the second SERDES circuit 2 have the same connection relationship. Therefore, in the description of the output path 17, connection of each block will be described with reference to the first SERDES circuit 1. The input FIFO 3 is connected to an upper layer (not shown) of the SERDES circuit. The input FIFO 3 is connected to the serializer circuit 5 via the 8B10B encoding circuit 4. The serializer circuit 5 is connected to a synthesizer circuit 7 and supplied with a data clock generated by the synthesizer circuit 7. Further, the serializer circuit 5 is connected to the output buffer 6. The output buffer 6 is connected to the input path 16 of the reception block (second SERDES circuit 2) via the transmission path 15.

  The first SERDES circuit 1 includes a data analysis unit 20, and the data analysis unit 20 is connected to the input path 16. The input buffer 9 of the input path 16 is connected to the transmission line 15 and receives serial data supplied via the transmission line 15. As shown in FIG. 3, the input buffer 9 is connected to the deserializer circuit 10 and the clock recovery circuit 11. The clock recovery circuit 11 is connected to the synthesizer circuit 8. The clock recovery circuit 11 generates a data clock based on the serial data supplied from the input buffer 9 and the clock supplied from the synthesizer circuit 8, and supplies the data clock to the 8B10B decoding circuit 12.

  The deserializer circuit 10 is connected to the 8B10B decoding circuit 12 and the data analysis unit 20. The deserializer circuit 10 generates 10-bit parallel data based on the serial data output from the input buffer 9 and supplies the 10-bit parallel data to the 8B10B decoding circuit 12 and the data analysis unit 20. ing. Further, the 8B10B decoding circuit 12 is connected to the output FIFO 13 and the data analysis unit 20. When the 8B10B decoding circuit 12 detects an error occurring in the data when executing the 8B10B decoding, the 8B10B decoding circuit 12 outputs an error detection signal 32 to the data analysis unit 20.

  The output FIFO 13 is connected to the interlink synchronous readout circuit 14. The interlink synchronous read circuit 14 is connected to the data analysis unit 20 and a lower layer circuit block (not shown). The inter-link synchronous readout circuit 14 determines that a data error has occurred when the data between the links cannot be synchronized because the control code has not arrived correctly, and analyzes the link error detection signal 33 for data analysis. To the unit 20.

  The data analysis unit 20 of the present embodiment holds error analysis data based on the 10-bit parallel data 31 supplied from the deserializer circuit 10 and the error detection signal 32 supplied from the 8B10B decoding circuit 12. To do. The data analysis unit 20 also holds error analysis data based on the link error detection signal 33 even when the link error detection signal 33 is output from the interlink synchronous readout circuit 14. The configuration of the data analysis unit 20 will be described below with reference to the drawings.

  FIG. 4 is a block diagram illustrating a detailed configuration of the first SERDES circuit 1 including the data analysis unit 20 described above. FIG. 4 shows a configuration for two links. The output path is not shown because it is the same as the output path 16 of FIG. As described above, the circuit diagram in FIG. 3 exemplifies a circuit composed of one link transmission path. This configuration does not limit the present invention. When data transmission is performed using a plurality of links, the effects of the present invention can be exhibited by adopting a configuration in which each input path 16 is connected to the data analysis unit 20. In the following description, a circuit including one data analysis unit 20 will be described as an example, but this does not limit the number of data analysis units 20 of the present invention. For example, in the case where a plurality of data analysis units 20 can be configured, the effects of the present invention can be achieved even in a configuration in which an arbitrary number of input paths 16 are grouped and one data analysis unit 20 is provided for each group. It is possible to demonstrate.

  As shown in FIG. 4, the data analysis unit 20 is an analyzer function for observing parallel data when a data error is detected. In the circuit block shown in FIG. 4, a circuit block having the same reference numeral as that used in the description of the first SERDES circuit 1 or the second SERDES circuit 2 in FIG. 3 is the same as that shown in FIG. It is the same composition. Therefore, in the following description, the description is omitted about the overlapping part.

  Referring to FIG. 4, the first SERDES circuit 1 of this embodiment includes a deserializer circuit 10, a clock recovery circuit 11, a synthesizer circuit 8, an 8B10B decoding circuit 12, an output FIFO 13, and an inter-link synchronous readout circuit 14. And a data analysis unit 20. The data analysis unit 20 includes a control unit 21, a memory 22, and a read control circuit 23. The control unit 21 includes a trigger control circuit 24 and a write control circuit 25.

  As shown in FIG. 4, the trigger control circuit 24 is connected to the 8B10B decoding circuit 12. The trigger control circuit 24 is connected to the inter-link synchronous readout circuit 14. The write control circuit 25 is connected to the trigger control circuit 24 and the deserializer circuit 10. The write control circuit 25 is further connected to the memory 22, and writes 10-bit parallel data 31 output from the deserializer circuit 10 into the memory 22. The memory 22 is connected to the read control circuit 23.

  The write control block 21 is a circuit block that specifies error analysis data based on the 10-bit parallel data 31 and the error detection signal 32 output from the 8B10B decoding circuit. As shown in FIG. 4, the control unit 21 includes a trigger control circuit 24 and a write control circuit 25. The trigger control circuit 24 is a trigger signal generation circuit that generates a write stop signal 34 in response to at least one of the error detection signal 32 and the link error detection signal 33.

  The write control circuit 25 is a control circuit that controls writing of 10-bit parallel data supplied from the deserializer circuit 10 to the memory 22.

  The memory 22 is a storage device that stores 10-bit parallel data output from the write control circuit 25. The memory 22 starts to write 10-bit parallel data from the head address corresponding to the write control by the write control circuit 25. When the write control circuit 25 reaches the bottom address of the memory 22, it returns to the top address again and continues writing. As a result, the memory 22 functions as a FIFO that holds a history of received parallel data corresponding to the size.

  The read control circuit 23 is a control circuit that controls the output of data in the memory 22 in accordance with a read signal from a subsequent circuit (not shown). The output memory contents are taken into a PC or the like. By analyzing the causal relationship between the pattern that caused the error and the pattern before and after the error in the PC that fetched the memory contents, the same function as an expensive logic analyzer can be realized with a circuit installed in the LSI. .

[Operation of First Embodiment]
The operation of this embodiment will be described below. As described above, the deserializer circuit 10 converts the serial data received from the transmission path 15 into 10-bit parallel data, and transfers it to both the 8B10B composite circuit 12 and the write control circuit 25. When enabled, the write control circuit 25 starts writing 10-bit parallel data from the top address of the memory 22, and when it reaches the bottom address, returns to the start address and continues writing. The memory 22 functions as a FIFO that holds a history of received parallel data corresponding to the size.

  On the other hand, the 10-bit parallel data input to the 8B10B composite circuit 12 is converted to 8 bits and then written to the output FIFO 13, and the subsequent processing proceeds. When the parallel data is converted into 8 bits, the 8B10B composite circuit 12 always checks the reliability of the parallel data by matching with the code table and matching the disparity. When a pattern not included in the code table is detected or a disparity mismatch is detected, an error signal is asserted and notified to the trigger control circuit 24. The trigger control circuit 24 adds an error flag to the parallel data that is the cause of the error stored in the memory 22 to clearly indicate it. Then, a write stop signal for the memory 22 is generated and input to the write control circuit 25. When the write control circuit 25 detects a write stop signal from the trigger control circuit 24, the write control circuit 25 stops writing to the memory 22. With this operation, the 10-bit parallel data that has caused the error detection in the 8B10B composite circuit 25 and the data received before and after that are stored in the memory 22 after the writing is stopped.

  The operation of the deserializer circuit 10 will be described below. The deserializer circuit 10 receives serial data transmitted via the transmission path 15 and converts the received serial data into 10-bit parallel data. Then, the converted 10-bit parallel data is supplied to the 8B10B decoding circuit 12 and the write control circuit 25.

  As a result, the deserializer circuit 10 converts the serial data received via the transmission path 15 into parallel data, and supplies the parallel data to the 8B10B decoding circuit 12 and also supplies it to the write control circuit 25 of the data analysis unit 20. Will be.

  The operation of the 8B10B decoding circuit will be described below. The 8B10B decoding circuit 12 receives the 10-bit parallel data supplied from the deserializer circuit 10 and verifies the disparity of the received 10-bit parallel data. If no error is detected as a result of the verification, the 8B10B decoding circuit 12 further converts the received 10-bit parallel data into 8-bit parallel data based on the standard code table. The 8B10B decoding circuit 12 determines whether 8-bit parallel data matches the code table during data conversion. At the time of data conversion, an error is also detected if 8-bit parallel data does not match the code table. As a result of the determination, when the code table matches (when no error is detected), the 8B10B decoding circuit 12 sends 8-bit parallel data to the output FIFO 13 in response to not detecting the error. Output.

  When there is an error as a result of the disparity verification, or when the 8-bit parallel data does not match the code table at the time of data conversion, the 8B10B decoding circuit 12 uses all 8-bits or a specific code of 8 bits. Parallel data is output to the output FIFO 13. Furthermore, in this case (when there is an error as a result of the disparity verification or when the 8-bit parallel data does not match the code table at the time of data conversion), the 8B10B decoding circuit 12 detects the error. An error signal is generated based on the error. The 8B10B decoding circuit 12 associates the error signal with the parallel data in which an error has occurred and notifies the trigger control circuit 24 of the correlation.

  Thus, the 8B10B decoding circuit 12 converts the 10-bit parallel data output from the deserializer circuit 10 into 8-bit parallel data, detects an error in the parallel data, and trigger control circuit 24 Will be supplied.

  The operation of the trigger control circuit will be described below with reference to FIG. Referring to FIG. 5, the trigger control circuit 24 monitors reception of an error signal output from the 8B10B decoding circuit 12. In step S101, the trigger control circuit 24 determines whether or not the error detection signal 32 is output from the 8B10B decoding circuit 12. If the error detection signal 32 is received as a result of the determination, the process proceeds to step S102. If the error detection signal 32 has not been received, the process returns to continue monitoring the error detection signal 32.

  In step S102, the trigger control circuit 24 specifies error information of 10-bit parallel data in which an error has occurred based on the error detection signal 32 output from the 8B10B decoding circuit 12. In step S103, the trigger control circuit 24 instructs the write control circuit 25 to add an error flag to the 10-bit parallel data based on the specified error information. In step S104, the trigger control circuit 24 generates the write stop signal 34 in response to the instruction to add the error flag. In step S105, the trigger control circuit 24 supplies the generated write stop signal 34 to the write control circuit 25 at a predetermined timing. Although not shown in FIG. 5, the trigger control circuit 24 performs the same operation when the link error detection signal 33 is output from the inter-link synchronous readout circuit 14. The “predetermined timing” at which the trigger control circuit in step S105 supplies the stop signal to the write control circuit can be changed by the user. The time from receiving the error signal output from the 8B10B decoding circuit in step S101 to supplying the stop signal in step S105 can be changed by the user.

  Thereby, the trigger control circuit 24 responds to the error detection signal 32 output from the 8B10B decoding circuit 12 (or the link error detection signal 33 output from the inter-link synchronous read circuit 14) of the write control circuit 25. The operation can be stopped at a predetermined timing.

  The operation of the write control circuit 25 will be described below with reference to FIG. The write control circuit 25 receives 10-bit parallel data output from the deserializer circuit 10. Referring to FIG. 6, in step S201, it is determined whether the setting of the write control circuit 25 is enabled. If the setting is not enabled, the process ends. If the write control circuit 25 is enabled in step S201, the process proceeds to step S202. In step S202, the write control circuit 25 executes data writing from the highest address in the free area of the memory.

  In step S <b> 203, the write control circuit 25 determines whether the final address of the memory 22 has been reached. As a result of the determination, if the final address has not been reached, writing from the upper address of the free area is continued. As a result of the determination, when the final address is reached, the write control circuit 25 writes data from the highest address of the memory 22 (step S204). As a result, the memory 22 functions as a FIFO that holds a history of received parallel data corresponding to the size.

  In step S205, the write control circuit 25 determines whether a write stop signal output from the trigger control circuit 24 has been received. As a result of the determination, if the write stop signal has not been received, the process returns to step S202, and the data writing is continued. When the write stop signal is received, the process proceeds to step 206, waits for the time set by the user, and after the time set by the user has elapsed, the process proceeds to step S207. In step S207, the write control circuit 25 stops writing to the memory 22 in response to the received write stop signal.

  As a result, the write control circuit 25 can write the parallel data in which an error has occurred and the data before and after the parallel data to the memory 22. The data analyzing unit 20 can analyze the error factor pattern without using an expensive measuring device by outputting the data held in the memory 22 from a predetermined terminal.

[Second Embodiment]
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 is a block diagram illustrating the configuration of the second embodiment. Referring to FIG. 7, the data analysis unit 20 of the first SERDES circuit 1 of the second embodiment is configured to further include a JTAG controller circuit 26 and a selector 27 in addition to the data analysis unit 20 of the first embodiment. ing.

  In the second embodiment, the data stored in the memory 22 is output to the outside of the device as low-speed serial data of several Mbps from the JTAG interface. JTAG is a standard method of a boundary scan test, which is one of LSI inspection methods. Recently, it has been widely adopted in various LSIs including CPUs. The LSI corresponding to JTAG has a JTAG controller circuit 26 and an interface composed of five terminals called TAP (Test Access Port) in addition to a circuit that performs the original function. The interface is used for input / output and control of test data. In the first SERDES circuit 1 in the second embodiment, this input / output terminal is used for data output of the memory 22.

  The selector 27 switches whether the five input / output terminals of the JTAG interface are connected to the JTAG controller circuit 26 for a normal boundary scan test or to the read control circuit 23 for outputting data in the memory 22. . When executing the analysis according to the present invention, the selector 27 switches the terminal connection to the read control circuit 23. The read control circuit sequentially outputs data in the memory 22 in response to a read signal from the JTAG jig. The memory contents are taken into a PC or the like via a JTAG jig, and the pattern causing the error and the causal relationship with the pattern before and after the pattern are analyzed.

  In the second embodiment, an example in which the JTAG interface is used as a terminal for reading analysis data from the memory 22 to the outside of the LSI has been described. By sharing the terminals with the widely used boundary scan test, it is possible to avoid an increase in the total terminals of the LSI. Further, there is an advantage that a jig for reading out to an external PC can be used. In practicing the present invention, it is not always necessary to use the JTAG terminal, and it is sufficient if there is a terminal that can read the analysis data in the memory 22. If there are a total of four terminals: a terminal for inputting a synchronous clock, a terminal for outputting data from the LSI, an input terminal for prompting data output, and an output terminal for indicating the status of data, data can be output from the memory.

  Further, the position at which the error factor pattern is stored in the memory 22 can be adjusted by increasing or decreasing the timing of the write stop signal 34 output from the trigger control circuit 24 to the write control circuit 25. . It is possible to hold more patterns before the error factor pattern arrives in the memory 22 or to focus on the behavior after the error factor.

  The enable control of the write control circuit 25, the output timing of the write stop signal of the trigger control circuit 24, and the switching control of the selector 27 are the values of registers provided in the first SERDES circuit 1 and control signals from external terminals. Therefore, the configuration can be variably changed.

  Here, a specific example in which JTAG is used as an interface of a self-diagnosis test function (BIST) built in the device will be described. In the following embodiments, the same configuration and operation as those described in the JTAG standard (IEEE 1149.1) are applied. As described in the above embodiment, the present invention can be realized without using a JTAG interface. As will be described in the following specific examples, the present invention has an advantage that the data in the memory 22 can be read without increasing the number of terminals by using a JTAG interface as the reading means.

  FIG. 8 is a circuit diagram illustrating a specific configuration of a device having a JTAG function. A device having a JTAG function has a serial interface called TAP (Test Access Port). The TAP is composed of five signal lines, and executes input / output of instructions for test logic, test data, test result data, and the like. A device having a JTAG function performs a JTAG test by controlling these signal lines from an external computer.

  Referring to FIG. 8, the device of the present embodiment includes terminals (28 to 32) connected to the five signal lines. The test data input terminal 28 receives a TDI (Test Data In) signal and supplies it to the instruction register and the read control circuit 23. The TDI signal is a signal for serially inputting an instruction or data to the test logic. The read control circuit 23 samples the TDI signal at the rising edge of the TCK signal. The test data output terminal 29 outputs a TDO (Test Data Out) signal supplied via the selector 27. The TDO signal is a signal for serially outputting data from the test logic, and the output is updated at the rising edge of the TCK signal. The clock supply terminal 31 receives a TCK (Test Clock) signal and supplies the clock to the TAP controller 26 and the read control circuit 23. The control signal supply terminal 30 receives a TMS (Test Mode Select) signal and supplies it to the TAP controller. The TMS signal is a signal for controlling the test operation, and is sampled by the TPA controller 26 at the rising edge of the TCK signal. The reset signal supply terminal 32 supplies a TRST (Test Reset) signal to the TAP controller. The TRST signal is a signal that asynchronously resets the TAP controller.

  The TAP controller 26 is a 16-state machine (sequential circuit) that controls the boundary scan register by a TMS (Test Mode Select) signal and a TCK (Test Clock) signal, and provides a central function of the JTAG test. The instruction register reads and decodes the instruction bits for the TAP controller. In response to the command, the device having the JTAG function causes the device to execute various functions. The types of instructions to be implemented and the assignment of instruction codes are classified as essential instructions, optional instructions that do not need to be implemented, and private instructions that the designer may decide freely.

FIG. 9 is a flowchart illustrating the operation of the device shown in FIG. In this embodiment, an instruction code (instruction code) is determined as a private instruction in order to use a terminal for a TAP controller having a JTAG function for reading data in the built-in memory. By inputting it to the instruction register, the internal memory read test mode is set in the TAP controller. When the built-in memory read test mode is entered, the TAP controller enables the read control circuit and switches the output of the test data output terminal 29 to the data signal from the read control.
As shown in FIG. 8 described above, the read control circuit 26 is supplied with TCK and TDI. Here, referring to FIG. 9, when the read control circuit 26 detects that TDI is low at the rising edge of TCK, the test data output terminal 29 reads the data in the built-in memory bit by bit in synchronization with TCK from the beginning. Output to.
To return to normal from the test mode, enter the instruction code and give instructions from the outside. As a result, the data in the memory 22 can be read without increasing the number of terminals.

FIG. 1 is a block diagram in which a PCI-Express physical layer is realized by SERDES according to the prior art. FIG. 2 is a diagram illustrating a state in which a measuring device is connected to analyze parallel data of SERDES according to the prior art. FIG. 3 is a circuit diagram illustrating a configuration of the SERDES circuit according to the first embodiment. FIG. 4 is a circuit diagram showing a detailed configuration of the SERDES circuit according to the first embodiment. FIG. 5 is a flowchart showing the operation of the trigger control circuit. FIG. 6 is a flowchart showing the operation of the write control circuit. FIG. 7 is a circuit diagram showing a configuration of the SERDES circuit of the second embodiment. FIG. 8 is a circuit diagram showing a specific configuration of the SERDES circuit according to the second embodiment. FIG. 9 is a timing chart illustrating the operation of the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st SERDES circuit 2 ... 2nd SERDES circuit 3 ... Input FIFO
DESCRIPTION OF SYMBOLS 4 ... 8B10B encoding circuit 5 ... Serializer circuit 6 ... Output buffer 7 ... Synthesizer circuit 8 ... Synthesizer circuit 9 ... Input buffer 10 ... Deserializer circuit 11 ... Clock reproduction circuit 12 ... 8B10B decoding circuit 13 ... Output FIFO
DESCRIPTION OF SYMBOLS 14 ... Interlink synchronous read circuit 15 ... Transmission path 16 ... Input path 17 ... Output path 20 ... Data analysis part 21 ... Control part 22 ... Memory 23 ... Read-out control circuit 24 ... Trigger control circuit 25 ... Write control circuit 26 ... JTAG controller Circuit 27 ... Selector 28 ... Test data input terminal 29 ... Test data output terminal 30 ... Control signal input terminal 31 ... Clock supply terminal 32 ... Reset signal supply terminal

Claims (16)

Serial data obtained by serially converting encoded parallel data generated by an encoding circuit that converts m (m is a natural number) bit data into n (n is a natural number greater than m) bit data is input and the serial data is input. A deserializer for converting data into the encoded parallel data;
A circuit for decoding the n-bit data into the m-bit data, wherein the encoded parallel data converted by the deserializer is decoded into decoded parallel data, and the encoding converted by the deserializer A decoding circuit that outputs an error detection signal when there is an error in the parallel data; and
A memory for sequentially writing the encoded parallel data converted by the deserializer;
Trigger that outputs an instruction to add an error flag to the encoded parallel data in which an error stored in the memory is detected in response to the error detection signal and outputs a write stop signal at a predetermined timing A control circuit;
A semiconductor integrated circuit comprising: a write control circuit that stops a write operation in response to the write stop signal. 2. The semiconductor integrated circuit according to claim 1, further comprising a read control circuit that reads the encoded parallel data from the memory in response to a data read command. The semiconductor integrated circuit according to claim 2,
The read control circuit converts the encoded parallel data stored in the memory into serial data for analysis and outputs the data. Semiconductor integrated circuit The semiconductor integrated circuit according to claim 3, further comprising a JTAG controller;
A selector having an output terminal connected to each of the JTAG controller and the read control circuit and connected to a TAP interface;
The selector connects the read control circuit and the TAP interface in response to a switching command input from the outside,
The read control circuit converts the parallel data read from the memory through the selector into the analysis serial data and outputs the serial data to the TAP interface. The semiconductor integrated circuit according to claim 4,
The write control circuit executes the writing of the encoded parallel data in the empty area of the memory in the order supplied from the deserializer circuit, and writes the encoded parallel data to the final address of the memory. And writing from the head address of the memory. In the semiconductor integrated circuit according to claim 4 or 5,
The encoding circuit converts the encoded parallel data, which is 10-bit parallel data, into the decoded parallel data, which is 8-bit parallel data, corresponding to the 8B10B encoding method, and the conversion operation thereof The error detection signal is output based on a code table used at the time of the semiconductor integrated circuit. The semiconductor integrated circuit according to claim 6,
The decoding circuit performs disparity verification when converting the encoded parallel data into the decoded parallel data, and outputs the error detection signal based on a result of the disparity verification. Characteristic semiconductor integrated circuit. 8. The semiconductor integrated circuit according to claim 7, further comprising:
Comprising a link synchronous read control circuit,
The inter-link synchronous read control circuit synchronizes data between different links based on a control code attached to data supplied via a plurality of links, and an error detection signal when the control code does not arrive correctly Output
The trigger control circuit adds an error flag to the encoded parallel data in which an error stored in the memory is detected in response to the error detection signal output from the inter-link synchronous read control circuit. A semiconductor integrated circuit characterized by outputting a command and outputting a write stop signal at a predetermined timing. (A) Serial data obtained by serially converting encoded parallel data generated by an encoding circuit that converts m (m is a natural number) bit data into n (n is a natural number greater than m) bit data is input. Converting the serial data into the encoded parallel data;
(B) When the n-bit data is decoded into the m-bit data, the converted encoded parallel data is decoded into decoded parallel data and the converted encoded parallel data Outputting an error detection signal when there is an error in
(C) sequentially writing the converted encoded parallel data into a memory;
(D) In response to the error detection signal, an instruction for adding an error flag to the encoded parallel data in which an error stored in the memory is detected is output, and a write stop signal is output at a predetermined timing. Output step;
(E) A data analysis method comprising a step of stopping a write operation in response to the write stop signal. The data analysis method according to claim 9, further comprising: (f) a step of reading the encoded parallel data from the memory in response to a data read command. The data analysis method according to claim 10,
The step (f)
A data analysis method comprising a step of converting the encoded parallel data stored in the memory into serial data for analysis and outputting the data. The data analysis method according to claim 11,
The step (f)
A data analysis method comprising a step of converting the parallel data read from the memory into the analysis serial data and outputting the converted serial data via a TAP interface. The data analysis method according to claim 12, wherein
The step (c) includes:
Writing the encoded parallel data in the empty area of the memory in the order in which the serial data is converted to the encoded parallel data, and writing the encoded parallel data to the last address of the memory In this case, the data analysis method includes a step of writing from the start address of the memory. The data analysis method according to claim 12 or claim 13,
The step (a) includes:
The encoding circuit converts the encoded parallel data, which is 10-bit parallel data, into the decoded parallel data, which is 8-bit parallel data, corresponding to the 8B10B encoding system,
The step (b)
A data analysis method comprising a step of outputting the error detection signal based on a code table used in the conversion operation. The data analysis method according to claim 14, wherein
The step (b)
A step of executing disparity verification when converting the encoded parallel data into the decoded parallel data, and outputting the error detection signal based on a result of the disparity verification; Data analysis method. The data analysis method according to claim 15, wherein
The step (b)
A step of synchronizing data between different links based on a control code attached to data supplied via a plurality of links, and outputting an error detection signal when the control code does not arrive correctly. Data analysis method.

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