KR100665918B1 - Line interface apparatus for burn-in test system - Google Patents

Abstract

A line interface device for a burn-in test system is provided to offer a fast and stable operation with a small number of transfer lines in the burn-in test system, and solve a noise problem caused from a control signal by transmitting the control signal and a data signal at the same time while connecting a PC and a buffer board of the burn-in test system in an LVDS(Low Voltage Differential Signaling) mode. A PCI(Peripheral Component Interconnect) card(20) is installed to the PC, and includes a sequence controller(210) controlling output order of the control and data signal, an 8b/10b encoder/decoder(230,240), a sync clock generator(220) generating the clock signal by detecting the signal received from test equipment, a register(260) storing a decoding result by synchronizing with the generated clock sign, and a latch(250) changing a signal transfer direction according to the signal transfer mode by control of the sequence controller. The buffer board(40) outputs the signal by converting a signal transfer mode between the PCI card and a memory device. A board interface card(50) is installed to each board mounted to the test equipment, and includes the sequence controller(510), the sync clock generator(520), and the 8b/10b encoder/decoder(540,530).

Description

Line Interface Apparatus for Burn-in Test System

1 is a schematic configuration diagram of a burn-in test system to which a line interface device according to the present invention is applied;

2 is a configuration diagram of a line interface device according to the present invention;

3A and 3B are detailed circuit diagrams and output signal timing diagrams of the synchronous clock generator shown in FIG. 2;

4 is a view for explaining an example of a test method in a burn-in test system having a line interface device according to the present invention;

5 is a view for explaining another example of the test method in the burn-in test system having a line interface device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: PC 20: PCI Card

30: test equipment 40: buffer board

50: board interface card 210, 510: sequence control unit

220, 520: Synchronous clock generator 230, 540: 8b / 10b encoder

240, 530: 8b / 10b decoder 250: latch

260: register 2210: address transition detection circuit

2220, first delay means 2230, second delay means

2240 logic elements

The present invention relates to a line interface device, and more particularly, to a line interface device for improving signal transmission and reception quality between a PC and a test board in a burn-in test system.

Generally, burn-in test system receives test condition, command, test data, etc. by user's operation, receives test condition, command, etc. from PC and PC that receives test result, performs test and transmits the result to PC. Consists of test equipment.

The PC and the test equipment are connected by a buffer board provided in the test equipment, and the buffer board transfers command signals and data received from the PC to each board mounted in the test equipment. Currently, the burn-in test system connects an interface card (PCI card) in the PC and an interface card of the buffer board in the test equipment with a TTL transmission line, for example, to interface the PC with the test equipment.

During burn-in test, the PC accesses the test equipment several times to perform the read / write operation for equipment operation, configuration change, and the collection of test results.In case the length of the line connecting the PC and the buffer board becomes long, This can cause problems such as equipment malfunction. In particular, when noise occurs during the transmission of control commands, errors may occur in the test process, so that the test results are not reliable, and this problem is further exacerbated in test equipment that performs a large amount of data processing.

In a burn-in test system, on the other hand, testing a large number of boards in a short period of time requires processing a large amount of data, which requires extending the bus line width or increasing the data transfer rate. However, when a device capable of high-speed operation such as an emitter coupled logic (ECL) or low voltage differential signaling (LVDS) device is used to improve the data transmission speed, the test system production cost increases. In addition, the application of a structure for generating a stable signal to solve the noise problem causes a decrease in the operating speed.

In addition, when testing a large number of boards at the same time, there is a problem that the clock skew occurs toward the board farther away from the test board.

The present invention has been made to solve the above-mentioned disadvantages and problems, there is a technical problem to provide a line interface device capable of high speed and stable operation with a small transmission line in the burn-in test system.

Another technical problem of the present invention is to connect the PC of the burn-in test system and the buffer board by the LVDS method and adopt the 8b / 10b encoding / decoding method to transmit the control signal and the data signal at the same time. The problem lies in solving the problem and enabling test operation with the correct synchronization without using an internal clock.

The line interface device according to an embodiment of the present invention for achieving the above-described technical problem is a test condition, a command, test data, etc. is input, and receiving a test condition, command, etc. from the PC and the PC receiving the test result A line interface device for a burn-in test system including test equipment for performing a test and transmitting the result to a PC, the output sequence of control signals and data signals for performing a test on a plurality of boards mounted on the test equipment. A sequence control unit for controlling a sequence; an 8b / 10b encoder for encoding a control signal and a data signal input to the PC 10 under the control of the sequence control unit; decoding the data received from the test equipment under the control of the sequence control unit. 8b / 10b decoder detects signals received from the test equipment A synchronous clock generator for generating a signal, a register for storing a decoding result of the 8b / 10b decoder in synchronization with a clock signal generated by the synchronous clock generator, and a signal transmission direction under the control of the sequence controller according to a signal transmission / reception mode A PCI card installed in the PC, the latch including the switch; A buffer board converting and outputting a signal transmission method between the PCI card and a memory device; And a sequence controller for controlling an output order of a control signal for writing data to each board or reading data written to each board, and a synchronous clock generator for detecting a signal input through the buffer board and generating a clock signal. An 8b / 10b decoder for decoding a signal received through the buffer board in synchronization with a clock signal generated by the synchronous clock generator, and 8b / for encoding and transmitting the signal to the buffer board under control of the sequence controller. It includes a 10b encoder, the board interface card is installed on each board mounted on the test equipment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a burn-in test system to which a line interface device according to the present invention is applied.

As shown in the figure, the burn-in test system to which the present invention is applied receives test conditions, commands, and the like from a PC 10 and a PC that receive test results, commands, test data, and the like, by a user's operation. Is performed by the test equipment 30 to perform the test and transfer the result to the PC. The PC 10 and the test equipment 30 are interconnected by the PCI card 20 and the buffer board 40, and the buffer board 40 receives the command signals received from the PC 10 through the PCI card 20. The data is transferred to each board mounted in the test equipment.

In the present invention, the PCI card 20 and the buffer board 40 transmit and receive signals in an LVDS manner. The LVDS method has the advantage of transmitting and receiving signals using fewer wires, has a variation range of about 300mV or less, and is configured in pairs so as not to be sensitive to noise. It also guarantees transmission speeds of up to 100 MHz, although somewhat different depending on the length of the line.

On the other hand, the buffer board 40 transmits and receives a signal through the board interface card 50 and the corresponding line, respectively installed on a plurality of boards, this line is preferably connected to the backplane board (motherboard) of each board. In another exemplary embodiment of the present invention, a signal between the buffer board 40 and each board interface card 50 may be directly transmitted and received by a programmable logic device such as a field programmable gate array (FPGA), or terminated when the number of boards is large. It can also be implemented to send and receive signals through the device. The buffer board 40 buffers a signal received from the PCI card 20 by the LVDS method, converts the signal into a TTL signal, and transmits the signal to each board interface card 50. Then, after buffering the signal output from each board interface card 50 is converted to LVDS method and transmitted to the PCI card (20).

In the present invention, an 8b / 10b encoder / decoder is used to transmit control signals and data signals from the PC 10 to the test equipment 30 so as not to use separate control lines vulnerable to noise problems. The 8b / 10b encoding / decoding method is a method of encoding and transmitting 8-bit data into 10-bit data at the transmitting side and decoding 10-bit data into 8-bit original data at the receiving side. This method can improve the reliability of signal transmission by data.

In addition, the present invention provides a signal transition detection in synchronizing the PCI card 20 with the board interface card 50 when receiving signals by the 8b / 10b encoding / decoding method and the LVDS method. The synchronous clock is generated by the method, and the clock is generated by causing the PCI card 20 and the board interface card 50 to output control signals and data by using the clock.

2 is a configuration diagram of a line interface device according to the present invention.

As illustrated, the PCI card 20 includes a sequence controller 210, a synchronous clock generator 220, an 8b / 10b encoder 230, an 8b / 10b decoder 240, a latch 250, and a register 260. The board interface card 50 includes a sequence controller 510, a synchronous clock generator 520, an 8b / 10b decoder 530, and an 8b / 10b encoder 540.

The sequence controller 210 of the PCI card 20 controls an output order of a control signal and a data signal for performing a test operation for each board. The synchronous clock generator 220 outputs a pulse to be used as a synchronous clock signal whenever the received signal changes. The 8b / 10b encoder 230 encodes a control signal and a data signal input to the PC 10 under the control of the sequence controller 210, and the 8b / 10b decoder 240 is received from the test equipment 30. The data is decoded under the control of the sequence controller 210. The decoding result is stored in the register 260, and the synchronous clock generator 220 detects the decoded signal to generate a synchronous clock. The latch 250 changes the signal flow direction of the LVDS transmission line under the control of the sequence controller 210.

The buffer board 40 converts the LVDS signal received from the PCI card 20 into a TTL signal, or converts the TTL signal received from the board interface card 50 into an LVDS signal and outputs the signal. .

Meanwhile, the 8b / 10b decoder 530 of the board interface card 50 performs decoding on the signal received from the PCI card 20 through the buffer board 40 under the control of the sequence controller 510. The decoded signal is input to the board in synchronization with the clock signal generated by the synchronous clock generator 520 under the control of the sequence controller 510. In addition, the 8b / 10b encoder 540 encodes the data read from the board under the control of the sequence controller 510, and the encoded signal is transmitted to the buffer board 40.

3A and 3B are detailed circuit diagrams and output signal timing diagrams of the synchronous clock generator shown in FIG.

The synchronous clock generators 220 and 520 are circuits for detecting and outputting a pulse when a received signal changes, and may be implemented as a signal transition detection circuit 2210.

In a preferred embodiment of the present invention, the synchronous clock generators 220 and 520 may be configured to include a signal transition detection circuit 2210, a plurality of delay means 2220 and 2230, and a signal transition detection circuit 2210 according to a data transmission scheme. The output signal of each delay means may be used as the logic element 2240 to output the low level signal only when all the input signals are at the low level. Here, the logic device 2240 is preferably implemented with an OR gate.

When two delay means are implemented, for example, the timing diagram of the signal output from each node n1 to n5 is shown in FIG. 3B. When a signal is input to the node 1 (n1) at time t1, the signal transition detection circuit 2210 detects the change in the input signal and outputs a pulse to the node 2 (n2) according to the signal transition state. The signal of the node 2 (n2) is input to the first delay means 2220, the pulse signal delayed at time t2 is output to the node 3 (n3), the signal of the node 3 (n3) to the second delay means 2230 The pulse signal inputted and delayed at time t3 is outputted to the node 4 (n4). The signals of the node 2 (n2), the node 3 (n3), and the node 4 (n4) are input to the logic element 2240 and output to the node 5 (n5).

4 is a view for explaining an example of a test method in a burn-in test system having a line interface device according to the present invention.

In the burn-in test system, there is a method of reading the data recorded on the test target board as one of the test methods, and for this purpose, the data recorded on each board in the test equipment 30 according to the read command of the PCI card 20. Is read and transmitted to the PC 10.

The command of the PC 10 for data reading is encoded by the 8b / 10b encoder 230 under the control of the sequence controller 210 and transmitted to the buffer board 40 along the LVDS transmission line through the latch 250. do.

Referring to FIG. 4, after the idle state command IDLE, the stop operation command NOP, and the address start command ADS, the address signal and the check sum signal ADD (L), ADD (H), and SUM are The read command RD is transmitted after the NOP command. The command is converted into a TTL signal by the buffer board 40 and transmitted to the board interface card 50. The 8b / 10b decoder 530 of the board interface card 50 transmits the received command to the sequence controller 510. By decoding, the decoded result is input to each board in synchronization with a clock signal generated by the synchronous clock generator 520.

In general, since the LVDS transmission line is bidirectional and is set in a direction in which data is transmitted from the PCI card 20 to the buffer board 40 in the normal state, when the read command RD is transmitted, the sequence control unit 210 is transmitted. Must change the direction of the latch 250 to the receive mode. After the direction of the latch 250 is switched to the reception mode, the read command RD is also recognized by the board interface card 50 of the test apparatus 30, so that the sequence controller 510 of the board interface card 50 buffers the buffer. Switch the mode of the board 40 to the receive mode.

As such, after the latch 250 and the buffer board 40 are switched to the reception mode, the board interface card 50 transmits the data group read from the board to the buffer board 40 together with the read start (RDS) command. do. Accordingly, the buffer board 40 converts the TTL signal into an LVDS signal and transmits the signal to the PCI card 20 through the latch 250. More specifically, after the data read from the board by the read command RD is encoded by the 8b / 10b encoder 530, a plurality of data groups (G2 codes) consisting of DAT (L), DAT (H) and SUM, respectively In FIG. 4, four data groups (G2-1 to G2-4) are illustrated in FIG. 4.

Next, the 8b / 10b decoder 240 of the PCI card 20 decodes the received data and stores it in the register 260.

Subsequently, the board interface card 50 transmits a verification start (VFS) command and status values DAT (L), DAT (H), and SUM, and sends a buffer board (NOP command and IDLE command) to complete a read operation. 40) to the PCI card 20. Accordingly, the read test operation is completed, and the signal transmission directions of the latch 250 and the buffer board 40 are switched back to the transmission mode.

The state value transmitted after the verify start command is stored in the register 260 and used to confirm a test result of the board. In the verification, all the checksum results for the data and the command signal (K code) verification results are transmitted to the PCI card 200. Here, the command signal error can be confirmed by the 8b / 10b encoder 530. Since each command signal has only a specified value, an unexpected value is inputted when an error occurs, thereby confirming whether or not the error occurs.

Meanwhile, after the read command RD of the PCI card, a read latency time RD may exist until the read start command RS is transmitted from the board interface card 50.

5 is a view for explaining a writing method in a burn-in test system having a line interface device according to the present invention.

In the burn-in test system, there is a write method for writing data to a test target board as one of the test methods. For this purpose, the test equipment 30 writes data to each board according to a write command of the PCI card 20. .

The command of the PC 10 for data writing is encoded by the 8b / 10b encoder 230 under the control of the sequence controller 210 and transmitted to the buffer board 40 along the LVDS transmission line through the latch 250. do.

Referring to FIG. 5, after the idle state command IDLE, the stop operation command NOP, and the address start command ADS, the address signal and the check sum signal ADD (L), ADD (H), and SUM are After the NOP command, the write command WD and the plurality of data groups G2-1 to G2-4 each consisting of DAT (L), DAT (H), and SUM are transmitted.

These commands and data are converted into a TTL signal by the buffer board 40 and transmitted to the board interface card 50. The 8b / 10b decoder 530 of the board interface card 50 sequences the received commands and data. Decoded by the control of the controller 510, the decoded data is written to each board in synchronization with the clock signal generated by the synchronous clock generator 520.

After the data is recorded in this manner, in order to confirm whether data recording is normally performed, a verification command VFY is transmitted from the PCI card 10 to the board interface card 50. When the verification command VFY is transmitted, the sequence control unit 210 of the PCI card 20 switches the signal transmission / reception direction of the latch 250 to the reception mode, and the sequence control unit 510 of the board interface card 50 buffers the buffer. Switch the signal transmission / reception direction of the board 40 to the reception mode.

Thereafter, the board interface card 50 transmits the verification results DAT (L), DAT (H), and SUM to the buffer board 40 together with the verification start (VFS) command. Accordingly, the buffer board 40 converts the TTL signal into an LVDS signal and transmits the signal to the PCI card 20 through the latch 250. Next, the 8b / 10b decoder 240 of the PCI card 20 decodes the received verification result data and stores it in the register 260.

Next, the NOP instruction and IDLE instruction for completing the write operation from the board interface card 50 to the PCI card 20 are transmitted to the PCI card 20 through the buffer board 40. Accordingly, the write test operation is completed, and the signal transmission directions of the latch 250 and the buffer board 40 are switched back to the transmission mode.

Meanwhile, after the verify command VFY of the PCI card, a read latency time RD may exist until the verify start command VFS is transmitted from the board interface card 50.

In a preferred embodiment of the present invention, the buffer board 40 is preferably installed in the center of the test equipment, in which case the line distribution between the buffer board and the board can be equalized.

In addition, the above has been described with an example in which a pair of 8b / 10b encoders / decoders are provided in the PCI card 20 and the board interface card 50, but the present invention is not limited thereto. It is also possible to install in pairs or more. If 8b / 10b encoder / decoder is provided with one pair, LVDS transmission line is composed of 10 pairs (total 20 lines), and if 8b / 10b encoder / decoder is provided with two pairs, LVDS transmission line Consists of 20 pairs (40 lines total).

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, data can be transmitted at high speed and high quality while minimizing the number of transmission lines between the PC and the test equipment of the burn-in test system. In particular, since it does not use a separate transmission line for transmitting control signals, it is resistant to noise, and by using a synchronous clock using signal transition detection, it is possible to prevent clock skew from occurring and is not affected by the distribution pattern of the board. The data transfer rate can be maintained at a high speed.

In addition, by performing the test by the read / write operation using the transmission line, and then transmits the verification result to the PC, it is possible to immediately process when an error occurs, thereby improving the test efficiency.

Claims (12)

A burn-in test system including a test equipment for inputting test conditions, commands, test data, and the like, and receiving test results, commands, and the like from the PC to perform tests and transmitting the test results to the PC. As a line interface device for A sequence controller for controlling an output order of a control signal and a data signal for performing a test on a plurality of boards mounted in the test equipment, and 8b for encoding a control signal and a data signal input to a PC under the control of the sequence controller / 10b encoder, an 8b / 10b decoder for decoding the data received from the test equipment under the control of the sequence control unit, a synchronous clock generator for detecting a signal received from the test equipment to generate a clock signal, generating the synchronous clock A register in which a decoding result of the 8b / 10b decoder is stored in synchronization with a clock signal generated by the unit; and a latch configured to switch a signal transmission direction under control of the sequence control unit according to a signal transmission / reception mode, and installed in the PC. PCI card; A buffer board converting and outputting a signal transmission method between the PCI card and a memory device; And A sequence control unit for controlling the output order of a control signal and a data signal for writing data to or reading data from each board; and a synchronous clock for detecting a signal input through the buffer board to generate a clock signal A generator, an 8b / 10b decoder for decoding a signal received through the buffer board in synchronization with the clock signal generated by the synchronization clock generator, for encoding the signal under the control of the sequence controller and transmitting the encoded signal to the buffer board. A board interface card including an 8b / 10b encoder and installed on each board mounted in the test equipment; Line interface device for a burn-in test system comprising a. The method of claim 1, And at least one pair of 8b / 10b encoders / decoders respectively installed on the PCI card and the board interface card. The method of claim 1, And the synchronizing clock generator is a signal transition detection circuit. The method of claim 1, The synchronous clock generator includes a signal transition detection circuit; A plurality of delay means for delaying and outputting a signal output from said signal transition detecting circuit for a predetermined time, each connected in series; And A logic element for inputting an output signal of each of the signal transition detection circuit and the plurality of delay means to output a low level signal only when all the input signals are low level; Line interface device for a burn-in test system comprising a. The method of claim 4, wherein And said logic element is an OR gate. The method of claim 1, And the PCI card and the buffer board are connected by an LVDS transmission line. The method of claim 1, And the buffer board and each of the plurality of boards are connected by a TTL transmission line. The method of claim 1, And the latch switches to a reception mode under the control of a sequence controller installed in the PCI card when a read command is transmitted from the PCI card to the buffer board. The method of claim 8, When the read command is transmitted from the buffer board to the board interface card, the buffer board switches to a reception mode under the control of a sequence controller installed in the board interface card. . The method of claim 1, And the latch switches to a reception mode under the control of a sequence controller installed in the PCI card when a verification command is transmitted from the PCI card to the buffer board. The method of claim 10, When the verification command is transmitted to the board interface card through the buffer board, the buffer board switches to a reception mode under the control of a sequence controller installed in the board interface card. Device. The method of claim 1, And the buffer board and each of the plurality of boards are connected through a backplane of the board.

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