JP5138221B2 - 誤り訂正符号をmin−sum復号化する方法 - Google Patents
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/658—Scaling by multiplication or division
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
- H03M13/112—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1191—Codes on graphs other than LDPC codes
- H03M13/1194—Repeat-accumulate [RA] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1191—Codes on graphs other than LDPC codes
- H03M13/1194—Repeat-accumulate [RA] codes
- H03M13/1197—Irregular repeat-accumulate [IRA] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
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Description
LDPC符号は、最初に、1960年代にGallagerによって述べられた。LDPC符号は、シャノン限界に驚く程近いパフォーマンスを有する。符号長Nおよび次元Kを有するバイナリ(N,K)LDPC符号は、(N−K)行およびN列のパリティ検査行列Hによって定義される。行列Hの大半のエントリは、ゼロであり、ごく少数のエントリが1であるため、行列Hは、疎である。行列Hの各行は、チェックサムを表し、各列は、変数、たとえば、ビットまたはシンボルを表す。Gallagerによって述べられたLDPC符号は、正則である。すなわち、パリティ検査行列Hは、一定の重みの行および列を有する。
従来のBP復号化について図1に示すように、検査ノードプロセッサ110およびビットノートプロセッサ120が順次動作し、その間、信頼性メッセージをビリーフ伝播原理に基づいて互いに渡し合う。ここで、Uch130は、通信路からの対数尤度比である。BPデコーダの実際の実装に関する主な問題は、「双曲線正接」関数に複雑性が非常に高い計算が必要な、検査ノードプロセッサに起因する。
Uch,n:通信路出力によって生成されるビットnの対数尤度比(LLR)
U(i) mn:検査mからビットノードnに送られるビットnのLLR
V(i) mn:ビットノードnから検査ノードmに送られるビットnのLLR
V(i) n:各反復において計算されるビットnの事後確率LLR
i=1かつ最大反復数をImaxと設定する。各mおよびn毎に、V(0) mn=Uch,nと設定する。
水平ステップにより、1≦n≦Nおよび各m∈M(n)毎に、下式(3)を処理する。
硬判定および終了判定基準をテストする。(^)W(i)=[(^)W(i) n]を、V(i) n>0の場合には(^)W(i) n=1となり、その他の場合には(^)W(i)=0となるように生成する(ここで、(^)は、その後ろの文字の上に^が付されることを意味している)。H(^)w(i)の場合、または最大反復回数に達した場合、(^)W(i)を復号化符号語(decoded codeword)として出力し、復号反復を終了し、その他の場合にはi=i+1と設定してステップ1に戻る。
(^)W(i)を復号化符号語として出力する。
図2に示すように、従来のmin−sum復号化は、双曲線正接関数の積を、min−sum演算として近似することによって検査ノードプロセッサ210での従来のBP復号化を簡易化する。min−sumの検査ノードでの更新規則は、下式(6)と変更される。
図3に示すように、従来の正規化min−sum復号化は、検査ノードプロセッサ210によって生成されるメッセージを正規化する(310)ことによってmin−sum復号化を向上させる。ここで、「A」300は、正規化係数を表す。正規化min−sum復号化の検査ノードでの更新規則は、下式(7)である。
2D正規化min−sumデコーダの解析は、先行技術によるデコーダよりも良いパフォーマンス、より低い複雑性、および復号速度のトレードオフを示す。
Claims (11)
- ビットノードプロセッサによって生成されるメッセージを正規化することと、
検査ノードプロセッサによって生成されるメッセージを正規化することと
を含み、
前記ビットノードプロセッサの正規化係数は、ビットノードの重みに依存し、前記検査ノードプロセッサおよび前記ビットノードプロセッサの正規化係数は、復号反復回数に依存する
誤り訂正符号をmin−sum復号化する方法。 - 前記誤り訂正符号は、LDPC符号である請求項1に記載の方法。
- 前記LDPC符号は、正則である請求項2に記載の方法。
- 前記LDPC符号は、非正則である請求項2に記載の方法。
- 前記誤り訂正符号は、正則RA符号である請求項1に記載の方法。
- 前記誤り訂正符号は、非正則RA符号である請求項1に記載の方法。
- 前記ビットノードプロセッサの前記正規化係数は、前記検査ノードプロセッサによって生成されるメッセージのみを正規化する請求項1に記載の方法。
- 前記検査ノードプロセッサの前記正規化係数は、第1の所定復号反復回数に依存し、残りの復号反復中は、一定である請求項1に記載の方法。
- 前記検査ノードプロセッサの前記正規化係数は、前記ビットノードプロセッサからのメッセージのみを正規化する請求項1に記載の方法。
- 前記ビットノードプロセッサの前記正規化係数は、第1の復号反復所定回数に依存し、残りの復号反復中は、一定である請求項1に記載の方法。
- ビットノードプロセッサの前記正規化係数は、すべての復号反復中で一定である請求項1に記載の方法。
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US11/134,545 | 2005-05-20 | ||
US11/134,545 US7562279B2 (en) | 2005-05-20 | 2005-05-20 | 2D-normalized min-sum decoding for ECC codes |
PCT/JP2006/309209 WO2006123543A1 (en) | 2005-05-20 | 2006-04-27 | Normalized belief propagation decoding |
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JP2008541496A JP2008541496A (ja) | 2008-11-20 |
JP5138221B2 true JP5138221B2 (ja) | 2013-02-06 |
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US (1) | US7562279B2 (ja) |
EP (1) | EP1884023B1 (ja) |
JP (1) | JP5138221B2 (ja) |
CN (1) | CN101107782B (ja) |
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WO2006120844A1 (ja) | 2005-05-13 | 2006-11-16 | Nec Corporation | Ldpc符号化方式によるエンコーダ及びデコーダ |
US7797613B1 (en) * | 2006-02-22 | 2010-09-14 | Aquantia Corporation | Digital implementation of an enhanced minsum algorithm for error correction in data communications |
US20080109698A1 (en) * | 2006-07-25 | 2008-05-08 | Legend Silicon | Hybrid min-sum decoding apparatus with low bit resolution for ldpc code |
US20110173509A1 (en) * | 2006-09-18 | 2011-07-14 | Availink, Inc. | Bit mapping scheme for an ldpc coded 16apsk system |
US8369448B2 (en) * | 2006-09-18 | 2013-02-05 | Availink, Inc. | Bit mapping scheme for an LDPC coded 32APSK system |
FR2912574B1 (fr) * | 2007-02-13 | 2010-09-17 | Commissariat Energie Atomique | Procede de decodage a passage de messages et a convergence forcee. |
US8151171B2 (en) * | 2007-05-07 | 2012-04-03 | Broadcom Corporation | Operational parameter adaptable LDPC (low density parity check) decoder |
KR101492595B1 (ko) * | 2007-05-21 | 2015-02-11 | 라모트 앳 텔-아비브 유니버시티 리미티드 | 메모리 효율적인 ldpc 디코딩 |
CN101453220B (zh) * | 2007-12-03 | 2012-02-01 | 华为技术有限公司 | 用于重复累积码编码的交织方法和编码方法及相应设备 |
US8156409B2 (en) * | 2008-02-29 | 2012-04-10 | Seagate Technology Llc | Selectively applied hybrid min-sum approximation for constraint node updates of LDPC decoders |
US8370711B2 (en) | 2008-06-23 | 2013-02-05 | Ramot At Tel Aviv University Ltd. | Interruption criteria for block decoding |
CN101803205B (zh) * | 2008-08-15 | 2013-12-18 | Lsi公司 | 近码字的ram列表解码 |
JP5489552B2 (ja) | 2009-06-19 | 2014-05-14 | 三菱電機株式会社 | 復号方法及び復号装置 |
JP5365601B2 (ja) * | 2010-09-30 | 2013-12-11 | 株式会社Jvcケンウッド | 復号装置および復号方法 |
CN102412843B (zh) * | 2011-07-28 | 2013-06-19 | 清华大学 | 自适应的归一化最小和ldpc译码方法及译码器 |
JP2013070133A (ja) * | 2011-09-21 | 2013-04-18 | Jvc Kenwood Corp | 復号装置および復号方法 |
JP5631846B2 (ja) * | 2011-11-01 | 2014-11-26 | 株式会社東芝 | 半導体メモリ装置および復号方法 |
KR101926608B1 (ko) | 2012-08-27 | 2018-12-07 | 삼성전자 주식회사 | 경 판정 디코딩 방법 및 이를 이용한 저밀도 패리티 체크 디코더 |
US20140313610A1 (en) * | 2013-04-22 | 2014-10-23 | Lsi Corporation | Systems and Methods Selective Complexity Data Decoding |
CN103607208A (zh) * | 2013-11-25 | 2014-02-26 | 上海数字电视国家工程研究中心有限公司 | 基于归一化修正因子序列的ldpc最小和译码方法 |
EP2892157A1 (en) * | 2014-01-02 | 2015-07-08 | Alcatel Lucent | Offset Min-Sum decoding of LDPC codes |
US10263640B2 (en) * | 2017-04-04 | 2019-04-16 | Seagate Technology Llc | Low density parity check (LDPC) decoder with pre-saturation compensation |
US10171110B1 (en) | 2017-07-03 | 2019-01-01 | Seagate Technology Llc | Sequential power transitioning of multiple data decoders |
CN107968657B (zh) * | 2017-11-28 | 2021-05-18 | 东南大学 | 一种适用于低密度奇偶校验码的混合译码方法 |
US10892777B2 (en) | 2019-02-06 | 2021-01-12 | Seagate Technology Llc | Fast error recovery with error correction code (ECC) syndrome weight assist |
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US7418468B2 (en) * | 2004-02-13 | 2008-08-26 | University Of Alberta | Low-voltage CMOS circuits for analog decoders |
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EP1884023B1 (en) | 2009-11-18 |
CN101107782A (zh) | 2008-01-16 |
CN101107782B (zh) | 2010-08-25 |
WO2006123543A1 (en) | 2006-11-23 |
US7562279B2 (en) | 2009-07-14 |
US20060282742A1 (en) | 2006-12-14 |
EP1884023A1 (en) | 2008-02-06 |
JP2008541496A (ja) | 2008-11-20 |
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