JP5137461B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a substrate having an SOI (Silicon On Insulator) structure in which a semiconductor layer is thinned from a crystalline semiconductor substrate and bonded to a different substrate. In particular, the present invention relates to a bonded SOI technology, and more particularly to a method for manufacturing an SOI substrate in which a single crystal or polycrystalline semiconductor layer is bonded to a substrate having an insulating surface such as glass. Further, the present invention relates to a display device or a semiconductor device using a substrate having such an SOI structure.

  Instead of a silicon wafer produced by thinly cutting a single crystal semiconductor ingot, a semiconductor substrate (SOI substrate) called a silicon on insulator having a thin single crystal semiconductor layer on an insulating layer is provided. It has been developed and is becoming popular as a substrate for manufacturing microprocessors and the like. This is because integrated circuits using an SOI substrate are attracting attention as reducing parasitic capacitance between the drain of the transistor and the substrate, improving the performance of the semiconductor integrated circuit, and reducing power consumption.

  As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (for example, see Patent Document 1). In the hydrogen ion implantation separation method, a microbubble layer is formed at a predetermined depth from the surface by injecting hydrogen ions into a silicon wafer, and the microbubble layer is used as a cleavage plane, so that a thin silicon film is formed on another silicon wafer. Bond layers (SOI layers). In addition to performing heat treatment for peeling the SOI layer, an oxide film is formed on the SOI layer by heat treatment in an oxidizing atmosphere, and then the oxide film is removed, and then heat treatment is performed in a reducing atmosphere at 1000 to 1300 ° C. It is said that it is necessary to increase the bonding strength by performing the above.

  On the other hand, attempts have been made to form an SOI layer on an insulating substrate such as glass. As an example of an SOI substrate in which an SOI layer is formed on a glass substrate, a thin single crystal silicon layer formed on a glass substrate having a coating film by using a hydrogen ion implantation separation method is known (Patent Document 2). And Patent Document 3). Also in this case, a microbubble layer is formed at a predetermined depth from the surface by implanting hydrogen ions into the single crystal silicon piece, and after bonding the glass substrate and the single crystal silicon piece, the microbubble layer is used as a cleavage plane to form silicon. A thin silicon layer (SOI layer) is formed on the glass substrate by peeling the piece.

On the other hand, as a structure of a thin film transistor (TFT) on an insulating substrate such as a glass substrate, a base insulating film, an active layer, a gate insulating film, a gate electrode, an interlayer insulating film, and a wiring are formed on the glass substrate. Structure is mentioned. In order to increase the response speed of the TFT, the design rule of the entire TFT is reduced, or silicide regions are formed in the source region and the drain region of the active layer of the TFT, and the electric resistance and the source region of the source region and the drain region are formed. In addition, the contact resistance between the drain region and the wiring is lowered.
US Pat. No. 6,372,609 JP 11-163363 A US Pat. No. 7,119,365

  In the process of forming a TFT, the silicide region may be heated when forming an interlayer insulating film or wiring after forming the silicide region. Alternatively, depending on the environment in which the TFT is used, the TFT generates heat and is heated by the silicide region.

  When the silicide region is heated, the metal element contained in the silicide region may diffuse into the channel formation region in the active layer. When the metal element diffuses into the channel formation region, an increase in leakage current occurs and causes deterioration of TFT characteristics.

  Therefore, the present invention increases the response speed by forming the single crystal semiconductor layer and the silicide region, and increases the response speed by suppressing the diffusion of the metal element from the silicide region to the channel formation region of the TFT. An object is to manufacture a highly reliable semiconductor device.

  In the present invention, in order to increase the response speed of the TFT, an SOI layer is formed on an insulating substrate such as glass, and an active layer of the TFT is formed using the SOI layer, and silicide is formed in the source region and the drain region in the active layer. Form a region. Since the active layer is formed of a single crystal semiconductor layer and a silicide region is formed, the response speed of the TFT is increased.

  In order not to diffuse the metal element contained in the silicide region into the channel formation region, a non-single-crystal semiconductor film such as an amorphous semiconductor film or a microcrystal is formed between the source region, the drain region, and the insulating substrate. A semiconductor film is formed. The metal element from the silicide region is absorbed by the non-single-crystal semiconductor film, whereby the metal element can be prevented from diffusing into the channel formation region, and the reliability of the TFT is improved.

  The present invention includes a substrate, a bonding layer, an insulating film on the bonding layer, a single crystal semiconductor layer on the insulating film, a channel formation region in the single crystal semiconductor layer, and a low concentration impurity. A region, a silicide region, a non-single-crystal semiconductor film containing a rare gas element between the insulating film and the silicide region, a gate insulating film, a gate electrode, and a gate electrode on the single-crystal semiconductor layer The present invention relates to a semiconductor device having a sidewall on a side surface, wherein the non-single-crystal semiconductor film suppresses diffusion of a metal element in the silicide region into the channel formation region.

  According to the present invention, a non-single crystal semiconductor film is formed over a semiconductor substrate, an insulating film is formed over the non-single crystal semiconductor, and ions containing hydrogen are implanted into the semiconductor substrate. A separation layer having a porous structure is formed, a bonding layer is formed on the insulating film, and the semiconductor substrate and a substrate having an insulating surface are overlaid with the bonding layer interposed therebetween. The single crystal semiconductor layer and the non-single crystal semiconductor are subjected to heat treatment for separating the semiconductor substrate with the separation layer while causing a crack in the layer and leaving the single crystal semiconductor layer on the substrate having the insulating surface. The film is etched to form the single crystal semiconductor layer into an island-shaped single crystal semiconductor layer, and a part of the non-single-crystal semiconductor film is formed as a source region and a drain region of the island-shaped single crystal semiconductor layer. Formed to overlap the area A gate insulating film and a gate electrode having a width smaller than that of the gate insulating film are formed on the island-shaped single crystal semiconductor layer, and one conductivity type is formed in the island-shaped single crystal semiconductor layer using the gate electrode as a mask. An impurity element to be added is added to form a channel formation region under the gate electrode, and a low concentration impurity element, the gate electrode and the gate insulating film are formed in the region where the impurity element is added through the gate insulating film. A high concentration impurity region that is the source region and the drain region is formed in a region that is not formed, a sidewall is formed on a side surface of the gate electrode, and the gate electrode, the sidewall, and the island-shaped single crystal semiconductor layer are formed Forming a metal film, forming a silicide region in the source region and the drain region, and forming the silicide layer with the non-single-crystal semiconductor film. There a method for manufacturing a semiconductor device, wherein a metallic element in the de region from diffusing into the channel formation region is suppressed.

  In the present invention, the single crystal semiconductor layer is a single crystal silicon layer.

  In the present invention, the non-single-crystal semiconductor film is any one of an amorphous semiconductor film, a microcrystalline semiconductor film, and a polycrystalline semiconductor film, and the non-single-crystal semiconductor film contains silicon or germanium.

  In the present invention, the metal element is any one of nickel, tungsten, titanium, and cobalt.

  In the present invention, the bonding layer is formed of silicon oxide.

  In the present invention, the rare gas element is any one of argon, krypton, and xenon.

  According to the present invention, a substrate having an SOI structure with excellent crystallinity can be obtained by performing a plurality of heat treatments when bonding a crystalline semiconductor layer separated from a single crystal or polycrystalline semiconductor substrate to a supporting substrate. . Even when the support substrate and the crystalline semiconductor layer to be bonded have different thermal characteristics such as a strain point and a thermal expansion coefficient, the heat treatment for forming the bond and the subsequent heat treatment are performed at different temperatures and / or different processing times. As a result, an SOI substrate with reduced strain and excellent crystallinity can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the structure of the present invention described below, the same reference numerals are used in common in different drawings.

[Embodiment 1]
FIGS. 1A to 1B and FIGS. 2A to 2D illustrate a substrate having an SOI structure according to this embodiment, a semiconductor device manufactured using the SOI substrate, and manufacturing methods thereof. 2 (C), FIG. 3 (A) to FIG. 3 (C), FIG. 4 (A) to FIG. 4 (B), FIG. 5 (A) to FIG. 5 (B), and FIG. C), FIG. 7 (A) to FIG. 7 (B), FIG. 8 (A) to FIG. 8 (C), FIG. 9 (A) to FIG. 9 (E), FIG. 10 (A) to FIG. This will be described with reference to FIGS. 11 (A) to 11 (B).

  First, a structure of a substrate having an SOI structure will be described with reference to FIGS. 1A to 1B and FIGS. 2A to 2C.

  In FIG. 1A, a supporting substrate 100 has an insulating property or an insulating surface, and is a glass substrate used for the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass (“ Also referred to as “alkali-free glass substrate”.

That is, the support substrate 100 has a thermal expansion coefficient of 25 × 10 ⁻⁷ / ° C. to 50 × 10 ⁻⁷ / ° C. (preferably 30 × 10 ⁻⁷ / ° C. to 40 × 10 ⁻⁷ / ° C.) and is strained. A glass substrate having a point of 580 ° C. to 680 ° C. (preferably 600 ° C. to 680 ° C.) can be used. In addition, a quartz substrate, a ceramic substrate, a metal substrate whose surface is coated with an insulating film, and the like are also applicable.

  An LTSS (Low Temperature Single Crystal Semiconductor) layer 101 is a single crystal semiconductor layer, and typically, single crystal silicon (single crystal silicon) is applied.

  In addition, as the LTSS layer 101, a crystalline semiconductor made of a compound semiconductor such as silicon, germanium, gallium arsenide, indium phosphide, or the like that can be peeled off from a single crystal semiconductor substrate or a polycrystalline semiconductor substrate by a hydrogen ion implantation separation method. Layers can also be applied.

  A bonding layer 102 having a smooth surface and forming a hydrophilic surface is provided between the support substrate 100 and the LTSS layer 101. The bonding layer 102 is a layer having a smooth surface and a hydrophilic surface. As the material capable of forming such a surface, an insulating layer formed by a chemical reaction is preferable. For example, an oxide semiconductor film formed by a thermal or chemical reaction is suitable. This is because the smoothness of the surface can be ensured if the film is mainly formed by a chemical reaction.

  The bonding layer 102 which has a smooth surface and forms a hydrophilic surface is provided with a thickness of 0.2 nm to 500 nm. With this thickness, it is possible to smooth the surface roughness of the film formation surface and ensure the smoothness of the growth surface of the film.

  If the LTSS layer 101 is made of silicon, silicon oxide formed by heat treatment in an oxidizing atmosphere, silicon oxide grown by the reaction of oxygen radicals, chemical oxide formed by an oxidizing chemical solution, etc. can do.

  In the case of using chemical oxide as the bonding layer 102, the thickness may be 0.1 nm to 1 nm. In addition, silicon oxide deposited by a chemical vapor deposition method can be preferably used as the bonding layer 102. In this case, a silicon oxide film manufactured by a chemical vapor deposition method using an organosilane gas is preferable.

As the organic silane gas, ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₃ ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane It is possible to use a silicon-containing compound such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ). it can.

  The bonding layer 102 is provided on the LTSS layer 101 side and can be bonded even at room temperature by being in close contact with the surface of the support substrate 100. In order to form a stronger bond, the support substrate 100 and the LTSS layer 101 may be pressed. In order to bond the support substrate 100 and the bonding layer 102 which are different materials, the surface is cleaned. When the cleaned surfaces of the support substrate 100 and the bonding layer 102 are brought into close contact with each other, a bond is formed by an attractive force between the surfaces.

  Further, when a treatment for attaching a large number of hydrophilic groups to the surface of the support substrate 100 is added, it becomes a more preferable aspect to form a bond. For example, the surface of the support substrate 100 is preferably made hydrophilic by oxygen plasma treatment or ozone treatment.

  Thus, when the process which makes the surface of the support substrate 100 hydrophilic is added, the hydroxyl group of a surface acts and a bond is formed by a hydrogen bond. Furthermore, when the bonded surfaces are brought into close contact with each other and heated at a temperature of room temperature or higher, the bonding strength can be increased.

  As a process for bonding the support substrate 100 and the bonding layer 102 which are different materials, the surface to be bonded may be cleaned by irradiation with an ion beam of an inert gas such as argon. By irradiation with an ion beam, unbound species are exposed on the surface of the support substrate 100 or the bonding layer 102 to form a very active surface.

  When the activated surfaces are brought into close contact with each other, the support substrate 100 and the bonding layer 102 can be bonded at a low temperature. The method of activating the surface to form a bond is preferably performed in a vacuum because the surface needs to be highly cleaned.

  The LTSS layer 101 is formed by slicing a crystalline semiconductor substrate. For example, when a single crystal silicon substrate is used as the single crystal semiconductor substrate, ion implantation is performed in which hydrogen or fluorine is ion-implanted to a predetermined depth of the single crystal silicon substrate, and then heat treatment is performed to separate the surface single crystal silicon layer. It can be formed by a peeling method. Alternatively, a method may be applied in which single crystal silicon is epitaxially grown on porous silicon (porous silicon), and then the porous silicon layer is cleaved and peeled off with a water jet. The thickness of the LTSS layer 101 is 5 nm to 500 nm, preferably 10 nm to 200 nm.

  FIG. 1B illustrates a structure in which a barrier layer 103 and a bonding layer 102 are provided over a supporting substrate 100. By providing the barrier layer 103, it is possible to prevent the mobile ion impurity such as an alkali metal or an alkaline earth metal from diffusing from the glass substrate used as the support substrate 100 and contaminating the LTSS layer 101. A bonding layer 102 is preferably provided over the barrier layer 103.

  By providing the support substrate 100 with a plurality of layers having different functions of the barrier layer 103 that prevents impurity diffusion and the bonding layer 102 that secures bonding strength, the selection range of the support substrate can be expanded. It is preferable to provide the bonding layer 102 also on the LTSS layer 101 side. That is, when the LTSS layer 101 is bonded to the support substrate 100, it is preferable to provide the bonding layer 102 on one or both of the surfaces on which the bonding is formed, whereby the bonding strength can be increased.

  FIG. 2A illustrates a structure in which an insulating layer 104 is provided between the LTSS layer 101 and the bonding layer 102. The insulating layer 104 is preferably an insulating layer containing nitrogen. For example, one or a plurality of films selected from a silicon nitride film, a silicon nitride film containing oxygen, or a silicon oxide film containing nitrogen can be stacked.

  For example, as the insulating layer 104, a stacked film in which a silicon oxide film containing nitrogen and a silicon nitride film containing oxygen are stacked from the LTSS layer 101 side can be used. While the bonding layer 102 has a function of forming a bond with the support substrate 100, the insulating layer 104 prevents the LTSS layer 101 from being contaminated by impurities.

  Note that the silicon oxide film containing nitrogen has a composition with a higher oxygen content than nitrogen, and the concentration range is oxygen of 55 to 65 atomic%, nitrogen of 1 to 20 atomic%, This means that Si is contained in the range of 25 to 35 atomic% and hydrogen is contained in the range of 0.1 to 10 atomic%. Further, the silicon nitride film containing oxygen has a composition containing more nitrogen than oxygen, and the concentration ranges of oxygen are 15 to 30 atomic%, nitrogen is 20 to 35 atomic%, and Si is 25 to 35 atomic%, and hydrogen is included in the range of 15 to 25 atomic%.

  FIG. 2B illustrates a structure in which the bonding layer 102 is provided over the supporting substrate 100. A barrier layer 103 is preferably provided between the support substrate 100 and the bonding layer 102. This is to prevent contamination of the LTSS layer 101 by diffusion of mobile ion impurities such as alkali metal or alkaline earth metal from the glass substrate used as the support substrate 100. In the LTSS layer 101, a silicon oxide layer 105 formed by direct oxidation is formed. This silicon oxide layer 105 forms a bond with the bonding layer 102, and the LTSS layer is fixed on the support substrate 100. The silicon oxide layer 105 is preferably formed by thermal oxidation.

  FIG. 2C illustrates another structure in which the bonding layer 102 is provided over the support substrate 100. A barrier layer 103 is provided between the support substrate 100 and the bonding layer 102.

  In FIG. 2C, the barrier layer 103 includes one layer or a plurality of layers. For example, a silicon nitride film or an oxygen-containing silicon nitride film that has a high effect of blocking ions such as sodium is used as a first layer, and a silicon oxide film or a nitrogen oxide film containing nitrogen is provided as a second layer thereon. .

  The first layer of the barrier layer 103 is an insulating film having a purpose of preventing the impurity portion from being diffused and is a dense film, whereas the second layer has an internal stress of the first layer film on the upper layer. One purpose is to relieve stress so that it does not act. By providing the barrier layer 103 on the supporting substrate 100 in this manner, the selection range of the substrate when bonding the LTSS layer can be expanded.

  A bonding layer 102 is formed on the barrier layer 103 and fixes the support substrate 100 and the LTSS layer 101.

  FIGS. 3A to 3C and FIG. 4B illustrate a method for manufacturing a substrate having an SOI structure illustrated in FIGS. 1A to 1B and 2A to 2C. A) to FIG. 4B, FIG. 5A to FIG. 5C, FIG. 6A to FIG. 6C, FIG. 7A to FIG. 7B, and FIG. Description will be made with reference to FIG.

  Ions accelerated by an electric field are implanted to a predetermined depth from the cleaned surface of the semiconductor substrate 106 to form a separation layer 107 (see FIG. 3A). The depth of the separation layer 107 formed on the semiconductor substrate 106 is controlled by the ion acceleration energy and the ion incident angle. A separation layer 107 is formed in a depth region close to the average ion penetration depth from the surface of the semiconductor substrate 106. For example, the thickness of the LTSS layer is 5 nm to 500 nm, preferably 10 nm to 200 nm, and the acceleration voltage when ions are implanted is determined in consideration of such a thickness. Ion implantation is preferably performed using an ion doping apparatus. That is, a doping method is used in which a plurality of ion species generated by converting the source gas into plasma are implanted without mass separation.

In the case of the present embodiment, it is preferable to implant ions having one or more identical atoms and different mass numbers. In the ion doping, an acceleration voltage of 10 keV to 100 keV, preferably 30 keV to 80 keV, a dose amount of 1 × 10 ¹⁶ / cm ² to 4 × 10 ¹⁶ / cm ² , and a beam current density of ² μA / cm ² or more, preferably 5 μA / cm ^It may be ² or more, more preferably 10 μA / cm ² or more.

In the case of implanting hydrogen ions, it is preferable to include H ⁺ , H ₂ ⁺ , and H ₃ ⁺ ions and to increase the ratio of H ₃ ⁺ ions. When hydrogen ions are implanted, H ⁺ , H ₂ ⁺ , H ₃ ⁺ ions are included, and if the ratio of H ₃ ⁺ ions is increased, the implantation efficiency can be increased and the implantation time can be shortened. Can do. Thus, hydrogen of 1 × 10 ²⁰ / cm ³ (preferably 5 × 10 ²⁰ / cm ³ ) or more can be contained in the region of the separation layer 107 formed in the semiconductor substrate 106.

  When a high-concentration hydrogen injection region is locally formed in the semiconductor substrate 106, the crystal structure is disturbed to form minute vacancies, and the separation layer 107 can have a porous structure. In this case, a volume change of minute cavities formed in the separation layer 107 occurs by heat treatment at a relatively low temperature, and a thin LTSS layer can be formed by cleaving along the separation layer 107.

Even when ions are mass-separated and implanted into the semiconductor substrate 106, the separation layer 107 can be formed in the same manner as described above. Also in this case, it is preferable to selectively implant ions having a large mass number (for example, H ₃ ⁺ ions) because the same effect as described above can be obtained.

In addition to hydrogen, an inert gas such as deuterium or helium can be selected as a gas that generates ionic species that generate ions. By using helium as the source gas and an ion doping apparatus that does not have a mass separation function, an ion beam having a high ratio of He ⁺ ions can be obtained. By implanting such ions into the semiconductor substrate 106, minute vacancies can be formed, and a separation layer 107 similar to the above can be provided in the semiconductor substrate 106.

  In forming the separation layer 107, ions must be implanted under a high dose condition, and the surface of the semiconductor substrate 106 may become rough. Therefore, a dense film may be provided on the surface into which ions are implanted. For example, a protective film against ion implantation may be provided with a thickness of 50 nm to 200 nm using a silicon nitride film or oxygen containing silicon nitride film.

  Next, a silicon oxide film is formed as a bonding layer 102 on a surface where bonding with the supporting substrate 100 is formed (see FIG. 3B). The thickness of the silicon oxide film may be 10 nm to 200 nm, preferably 10 nm to 100 nm, more preferably 20 nm to 50 nm.

  As the silicon oxide film, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas as described above is preferable. In addition, a silicon oxide film manufactured by a chemical vapor deposition method using silane gas can be used. In film formation by a chemical vapor deposition method, for example, a film formation temperature of 350 ° C. or lower is applied as a temperature at which degassing does not occur from the separation layer 107 formed over the single crystal semiconductor substrate. Further, a heat treatment temperature higher than a film formation temperature is applied to the heat treatment for peeling the LTSS layer from the single crystal or polycrystalline semiconductor substrate.

  The support substrate 100 and the surface of the semiconductor substrate 106 on which the bonding layer 102 is formed face each other and are brought into close contact with each other to form a bond (FIG. 3C). The surface where the bond is formed is sufficiently cleaned. Then, a bond is formed by bringing the support substrate 100 and the bonding layer 102 into close contact with each other. Bonding is considered to be caused by van der Waals force in the initial stage, and by pressing the support substrate 100 and the semiconductor substrate 106, a strong bond can be formed by hydrogen bonding.

  In order to form a good bond, the surface may be activated. For example, the surface on which the junction is formed is irradiated with an atomic beam or an ion beam. When an atomic beam or an ion beam is used, an inert gas neutral atom beam or inert gas ion beam such as argon can be used. In addition, plasma irradiation or radical treatment is performed. Such surface treatment makes it possible to increase the bonding strength between different kinds of materials even at a temperature of 200 ° C. to 400 ° C.

  A first heat treatment is performed in a state where the semiconductor substrate 106 and the supporting substrate 100 are overlapped. By the first heat treatment, the semiconductor substrate 106 is separated while leaving a thin semiconductor layer (LTSS layer) over the supporting substrate 100 (FIG. 4A). The first heat treatment is preferably performed at a temperature equal to or higher than the deposition temperature of the bonding layer 102 and is preferably performed at a temperature of 400 ° C. or higher and lower than 600 ° C. By performing heat treatment in this temperature range, a volume change occurs in minute holes formed in the separation layer 107, and the semiconductor layer can be cleaved along the separation layer 107. Since the bonding layer 102 is bonded to the support substrate 100, the same crystalline LTSS layer 101 as the semiconductor substrate 106 is fixed on the support substrate 100.

  Next, second heat treatment is performed in a state where the LTSS layer 101 is bonded to the supporting substrate 100 (FIG. 4B). The second heat treatment is preferably performed at a temperature that is higher than the first heat treatment temperature and does not exceed the strain point of the support substrate 100. Alternatively, it is preferable to increase the treatment time of the second heat treatment even if the first heat treatment and the second heat treatment are at the same temperature. In the heat treatment, the support substrate 100 and / or the LTSS layer 101 may be heated by heat conduction heating, convection heating, radiation heating, or the like. An electric heating furnace, a lamp annealing furnace, or the like can be applied as the heat treatment apparatus. The second heat treatment may be performed by changing the temperature in multiple stages. A rapid thermal annealing (RTA) apparatus may be used. When heat treatment is performed using an RTA apparatus, the substrate can be heated to a temperature near or slightly higher than the strain point of the substrate.

  By performing the second heat treatment, the stress remaining in the LTSS layer 101 can be relieved. That is, the second heat treatment relieves thermal distortion caused by a difference in expansion coefficient between the support substrate 100 and the LTSS layer 101. The second heat treatment is also effective for recovering the crystallinity of the LTSS layer 101 whose crystallinity is impaired by ion implantation. Further, the second heat treatment is effective for recovering damage to the LTSS layer 101 that occurs when the semiconductor substrate 106 is bonded to the support substrate 100 and then divided by the first heat treatment. Further, by performing the first heat treatment and the second heat treatment, the hydrogen bond can be changed to a stronger covalent bond.

  Chemical mechanical polishing (CMP) treatment may be performed for the purpose of further flattening the surface of the LTSS layer 101. The CMP treatment can be performed after the first heat treatment or after the second heat treatment. However, if it is performed before the second heat treatment, the surface of the LTSS layer 101 can be planarized and a damaged layer on the surface caused by the CMP treatment can be repaired by the second heat treatment.

  In any case, by performing the first heat treatment and the second heat treatment in combination as in this embodiment, a crystalline semiconductor layer having excellent crystallinity on a thermally fragile support substrate such as a glass substrate Can be provided.

  Through the steps of FIGS. 3A to 3C and FIGS. 4A to 4B, the SOI substrate shown in FIG. 1A is formed.

  A method for manufacturing the substrate having the SOI structure illustrated in FIG. 1B will be described with reference to FIGS.

  3A to 3B, the separation layer 107 is formed in the semiconductor substrate 106, and the semiconductor substrate 106 is bonded to the surface to be bonded to the support substrate 100. Layer 102 is formed.

  Next, the support substrate 100 over which the barrier layer 103 and the bonding layer 102 are formed and the bonding layer 102 of the semiconductor substrate 106 are closely attached to form a bond (FIG. 7A).

  In this state, a first heat treatment is performed. The first heat treatment is preferably performed at a temperature equal to or higher than the deposition temperature of the bonding layer 102 and is preferably performed at a temperature of 400 ° C. or higher and lower than 600 ° C. As a result, a volume change occurs in the minute holes formed in the separation layer 107, and the semiconductor substrate 106 can be cleaved. An LTSS layer 101 having the same crystallinity as the semiconductor substrate 106 is formed over the supporting substrate 100 (FIG. 7B).

  Next, second heat treatment is performed in a state where the LTSS layer 101 is bonded to the support substrate 100. The second heat treatment is preferably performed at a temperature that is higher than the first heat treatment temperature and does not exceed the strain point of the support substrate 100. Alternatively, it is preferable to increase the treatment time of the second heat treatment even if the first heat treatment and the second heat treatment are at the same temperature. In the heat treatment, the support substrate 100 and / or the LTSS layer 101 may be heated by heat conduction heating, convection heating, radiation heating, or the like. By performing the second heat treatment, the stress remaining in the LTSS layer 101 can be relieved, and it is also effective in recovering the damage of the LTSS layer 101 that occurs when the division is performed by the first heat treatment.

  As described above, the SOI substrate illustrated in FIG. 1B is formed.

  Next, a method for manufacturing a substrate having an SOI structure illustrated in FIG. 2A will be described with reference to FIGS.

  First, the separation layer 107 is formed in the semiconductor substrate 106 based on the manufacturing process illustrated in FIG.

  Next, the insulating layer 104 is formed on the surface of the semiconductor substrate 106. The insulating layer 104 is preferably an insulating layer containing nitrogen. For example, one or a plurality of films selected from a silicon nitride film, a silicon nitride film containing oxygen, or a silicon oxide film containing nitrogen can be stacked.

  Further, a bonding layer 102 silicon oxide film is formed over the insulating layer 104.

  The support substrate 100 and the surface of the semiconductor substrate 106 where the bonding layer 102 is formed face each other and are brought into close contact with each other to form a bond (FIG. 8B).

  In this state, a first heat treatment is performed. The first heat treatment is preferably performed at a temperature equal to or higher than the deposition temperature of the bonding layer 102 and is preferably performed at a temperature of 400 ° C. or higher and lower than 600 ° C. As a result, a volume change occurs in the minute holes formed in the separation layer 107, and the semiconductor substrate 106 can be cleaved. An LTSS layer 101 having the same crystallinity as the semiconductor substrate 106 is formed over the supporting substrate 100 (FIG. 8C).

  Next, second heat treatment is performed in a state where the LTSS layer 101 is bonded to the support substrate 100. The second heat treatment is preferably performed at a temperature that is higher than the first heat treatment temperature and does not exceed the strain point of the support substrate 100. Alternatively, it is preferable to increase the treatment time of the second heat treatment even if the first heat treatment and the second heat treatment are at the same temperature. In the heat treatment, the support substrate 100 and / or the LTSS layer 101 may be heated by heat conduction heating, convection heating, radiation heating, or the like. By performing the second heat treatment, the stress remaining in the LTSS layer 101 can be relieved, and it is also effective in recovering the damage of the LTSS layer 101 that occurs when the division is performed by the first heat treatment.

  As shown in FIGS. 8A to 8C, when the insulating layer 104 is formed over the semiconductor substrate 106, impurities are prevented from being mixed into the LTSS layer 101 by the insulating layer 104, so that the LTSS layer 101 is contaminated. Can be prevented.

  5A to 5C show a process of manufacturing a SOI structure substrate having an LTSS layer by providing a bonding layer on the support substrate side.

  First, ions accelerated by an electric field are implanted to a predetermined depth into the semiconductor substrate 106 on which the silicon oxide layer 105 is formed, so that the separation layer 107 is formed (FIG. 5A). The silicon oxide layer 105 may be formed by depositing a silicon oxide layer on the semiconductor substrate 106 by a sputtering method or a CVD method. When the semiconductor substrate 106 is a single crystal silicon substrate, the semiconductor substrate 106 is formed by thermal oxidation. May be. In this embodiment mode, the semiconductor substrate 106 is a single crystal silicon substrate, and the silicon oxide layer 105 is formed by thermally oxidizing the single crystal silicon substrate.

  Ions are implanted into the semiconductor substrate 106 in the same manner as in FIG. By forming the silicon oxide layer 105 on the surface of the semiconductor substrate 106, it is possible to prevent the surface from being damaged by ion implantation and the flatness from being impaired.

  The support substrate 100 on which the barrier layer 103 and the bonding layer 102 are formed and the surface of the semiconductor substrate 106 on which the silicon oxide layer 105 is formed are closely attached to form a bond (FIG. 5B).

  In this state, a first heat treatment is performed. The first heat treatment is preferably performed at a temperature equal to or higher than the deposition temperature of the bonding layer 102 and is preferably performed at a temperature of 400 ° C. or higher and lower than 600 ° C. As a result, a volume change occurs in the minute holes formed in the separation layer 107, and the semiconductor substrate 106 can be cleaved. An LTSS layer 101 having the same crystallinity as that of the semiconductor substrate 106 is formed over the supporting substrate 100 (FIG. 5C).

  Next, second heat treatment is performed in a state where the LTSS layer 101 is bonded to the support substrate 100. The second heat treatment is preferably performed at a temperature that is higher than the first heat treatment temperature and does not exceed the strain point of the support substrate 100. Alternatively, it is preferable to increase the treatment time of the second heat treatment even if the first heat treatment and the second heat treatment are at the same temperature. In the heat treatment, the support substrate 100 and / or the LTSS layer 101 may be heated by heat conduction heating, convection heating, radiation heating, or the like. By performing the second heat treatment, the stress remaining in the LTSS layer 101 can be relieved, and it is also effective in recovering the damage of the LTSS layer 101 that occurs when the division is performed by the first heat treatment.

  As described above, the SOI substrate shown in FIG. 2B is formed.

  6A to 6C show other examples in the case where a bonding layer is provided on the support substrate side and the LTSS layer is bonded.

  First, the separation layer 107 is formed over the semiconductor substrate 106 (FIG. 6A). Ion implantation for forming the separation layer 107 is performed using an ion doping apparatus. In this step, ions having different mass numbers accelerated by an electric field are accelerated by a high electric field and irradiated onto the semiconductor substrate 106.

  At this time, since the flatness of the surface of the semiconductor substrate 106 may be impaired by ion irradiation, the silicon oxide layer 105 is preferably provided as a protective film. The silicon oxide layer 105 may be formed by thermal oxidation, or chemical oxide may be applied. Chemical oxide can be formed by immersing the semiconductor substrate 106 in an oxidizing chemical solution. For example, when the semiconductor substrate 106 is treated with an aqueous solution containing ozone, chemical oxide is formed on the surface.

  Alternatively, a silicon oxide film containing nitrogen, a silicon nitride film containing oxygen, or a silicon oxide film formed using TEOS may be used as the protective film.

  The support substrate 100 is preferably provided with a barrier layer 103. As the barrier layer 103, by providing the barrier layer 103, the mobile ion impurity such as alkali metal or alkaline earth metal is prevented from diffusing from the glass substrate used as the support substrate 100 to prevent the LTSS layer 101 from being contaminated. be able to.

  The barrier layer 103 is composed of one layer or a plurality of layers. For example, a silicon nitride film or an oxygen-containing silicon nitride film that has a high effect of blocking ions such as sodium is used as a first layer, and a silicon oxide film or a nitrogen oxide film containing nitrogen is provided as a second layer thereon. .

  The first layer of the barrier layer 103 is an insulating film having a purpose of preventing the impurity portion from being diffused and is a dense film, whereas the second layer has an internal stress of the first layer film on the upper layer. One purpose is to relieve stress so that it does not act. By providing the barrier layer 103 on the supporting substrate 100 in this manner, the selection range of the substrate when bonding the LTSS layer can be expanded.

  The support substrate 100 provided with the bonding layer 102 over the barrier layer 103 is bonded to the semiconductor substrate 106 (FIG. 6B). The surface of the semiconductor substrate 106 is in a state where the silicon oxide layer 105 provided as a protective film is removed with hydrofluoric acid to expose the semiconductor surface. The outermost surface of the semiconductor substrate 106 may be in a state terminated with hydrogen by treatment with a hydrofluoric acid solution. When bonding is formed, a hydrogen bond is formed by surface-terminated hydrogen, and a favorable bond can be formed.

  Alternatively, a bond may be formed in a vacuum so that dangling bonds are exposed on the outermost surface of the semiconductor substrate 106 by irradiation with ions of an inert gas.

  In this state, a first heat treatment is performed. The first heat treatment is preferably performed at a temperature equal to or higher than the deposition temperature of the bonding layer 102 and is preferably performed at a temperature of 400 ° C. or higher and lower than 600 ° C. As a result, a volume change occurs in the minute holes formed in the separation layer 107, and the semiconductor substrate 106 can be cleaved. An LTSS layer 101 having the same crystallinity as the semiconductor substrate 106 is formed over the supporting substrate 100 (FIG. 6C).

  Next, second heat treatment is performed in a state where the LTSS layer 101 is bonded to the support substrate 100. The second heat treatment is preferably performed at a temperature that is higher than the first heat treatment temperature and does not exceed the strain point of the support substrate 100. Alternatively, it is preferable to increase the treatment time of the second heat treatment even if the first heat treatment and the second heat treatment are at the same temperature.

  In the heat treatment, the support substrate 100 and / or the LTSS layer 101 may be heated by heat conduction heating, convection heating, radiation heating, or the like. By performing the second heat treatment, the stress remaining in the LTSS layer 101 can be relieved, and it is also effective in recovering the damage of the LTSS layer 101 that occurs when the division is performed by the first heat treatment.

  In this manner, the SOI substrate shown in FIG. 2C is formed.

  According to the present embodiment, it is possible to obtain the LTSS layer 101 having a strong bonding strength at the joint even if the support substrate 100 has a heat-resistant temperature of 700 ° C. or lower, such as a glass substrate. As the support substrate 100, it is possible to apply various glass substrates used for the electronic industry called non-alkali glass such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass. That is, a single crystal semiconductor layer can be formed over a substrate whose one side exceeds 1 meter. Using such a large area substrate, not only a display device such as a liquid crystal display but also a semiconductor integrated circuit can be manufactured.

  Next, a semiconductor device formed using the above SOI structure and a manufacturing method thereof are illustrated in FIGS. 9A to 9E, FIGS. 10A to 10D, and FIGS. This will be described with reference to FIG.

  First, the non-single-crystal semiconductor film 125 is selectively formed on the surface of the semiconductor substrate 106.

  The non-single-crystal semiconductor film 125 is selectively formed in a region overlapping with a source region and a drain region of the TFT. This is because a metal element contained in a silicide region formed in the source region and the drain region is moved and absorbed (referred to as “gettering” in this specification) by the non-single-crystal semiconductor film 125.

  As the non-single-crystal semiconductor film 125, for example, an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film may be used. The non-single-crystal semiconductor film 125 may be formed using a semiconductor containing silicon (Si) or germanium (Ge).

  As the amorphous semiconductor film, amorphous silicon (Si), amorphous germanium (Ge), or amorphous silicon germanium (SiGe) can be used.

  A microcrystalline semiconductor film (microcrystalline semiconductor film) is included in a semi-amorphous semiconductor film, but a semi-amorphous semiconductor (also referred to as “Semi-amorphous Semiconductor (SAS)” in this specification) film is an amorphous semiconductor. And a semiconductor including an intermediate structure between semiconductor (including single crystal and polycrystal) films having a crystal structure. This semi-amorphous semiconductor film is a semiconductor film having a third state that is stable in terms of free energy, and is a crystalline film having short-range order and lattice distortion, and has a grain size of 0.5 to 20 nm. And can be dispersed in the non-single-crystal semiconductor film.

One example of the semi-amorphous semiconductor film is a semi-amorphous silicon film. The semi-amorphous silicon film has its Raman spectrum shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of (111) and (220) that are derived from the Si crystal lattice in X-ray diffraction are observed. The Further, in order to terminate dangling bonds (dangling bonds), at least 1 atomic% or more of hydrogen or halogen is contained. In this specification, such a silicon film is referred to as a semi-amorphous silicon film for convenience. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a good semi-amorphous semiconductor film can be obtained.

The semi-amorphous silicon film can be obtained by glow discharge decomposition of a gas containing silicon (silicon). A typical gas containing silicon (Si) is SiH ₄ , and Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Semi-amorphous silicon is also obtained by diluting and using hydrogen or a gas containing silicon (silicon) with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. The film can be easily formed. It is preferable to dilute the gas containing silicon (silicon) in the range of a dilution rate of 2 to 1000 times. Furthermore, a gas containing silicon (silicon) is mixed with a carbide gas such as CH ₄ or C ₂ H ₆ , a germanium gas such as GeH ₄ or GeF ₄ , F _2, etc. You may adjust to 5-2.4 eV or 0.9-1.1 eV.

  As the microcrystalline semiconductor film, microcrystalline germanium (Ge) or microcrystalline silicon germanium (SiGe) can be used.

  As the polycrystalline semiconductor film, polycrystalline silicon (Si), polycrystalline germanium, or polycrystalline silicon germanium (SiGe) can be used.

  The non-single-crystal semiconductor film 125 contains a rare gas element such as argon (Ar), krypton (Kr), or xenon (Xe). By forming the non-single-crystal semiconductor film 125 containing such a rare gas element, the metal element can be efficiently moved and absorbed (referred to as “gettering” in this specification).

  If the concentration of the rare gas element contained in the semiconductor film is too small, the effect of gettering the metal element cannot be obtained. Therefore, a concentration that allows gettering may be selected.

  In this embodiment, as the non-single-crystal semiconductor film 125, an amorphous silicon film containing 1 atom% of argon (Ar) is formed with a thickness of 5 nm to 100 nm by a CVD method or a sputtering method. Here, a sputtering method is used to form an amorphous silicon film containing argon with a film formation pressure of 0.3 Pa and a film thickness of 30 nm.

  The non-single-crystal semiconductor film 125 is formed in a stripe shape so as to overlap with a source region and a drain region which are formed later.

  After the non-single-crystal semiconductor film 125 is formed, the insulating film 131 is formed. In this embodiment, as the insulating film 131, a silicon oxide film containing nitrogen is formed with a thickness of 100 nm, and a silicon nitride film containing oxygen is formed with a thickness of 150 nm.

Further, after forming the insulating film 131, hydrogen ions are implanted to form the separation layer 107. In this embodiment mode, the hydrogen ion implantation conditions are an applied voltage of 80 keV and a dose of 2.5 × 10 ¹⁶ / cm ² . Thereby, the separation layer 107 is formed at a depth of 100 nm to 300 nm from the surface of the semiconductor substrate 106.

  Next, the surface of the insulating film 131 is planarized by a CMP (Chemical-Mechanical Polishing) method. Since the non-single-crystal semiconductor film 125 is formed, a step is formed on the surface of the insulating film 131. Polishing is performed so that this step is eliminated.

  Next, the bonding layer 102 is formed over the planarized insulating film 131 (see FIG. 9A).

  After the structure shown in FIG. 9A is obtained, the support substrate 100 and the surface of the semiconductor substrate 106 on which the bonding layer 102 is formed face each other and are brought into close contact with each other (see FIG. 9B). .

  2B and 2C, the bonding layer 102 may be formed on the supporting substrate 100 instead of the semiconductor substrate 106, or the semiconductor substrate may be formed as shown in FIG. The bonding layer 102 may be formed on both the support 106 and the support substrate 100.

  In addition, as illustrated in FIGS. 1B, 2 </ b> B, and 2 </ b> C, a barrier layer 103 may be provided over the support substrate 100. For example, a silicon nitride layer and a silicon oxide layer may be stacked as the barrier layer 103. When a barrier layer is provided on the support substrate 100, contamination of the LTSS layer 101 can be prevented. Note that a silicon nitride layer containing oxygen, an aluminum nitride layer, or an aluminum nitride layer containing oxygen may be used instead of the silicon nitride layer.

  A first heat treatment is performed in a state where the semiconductor substrate 106 and the supporting substrate 100 are overlapped. As the first heat treatment, for example, the semiconductor substrate 106 and the support substrate 100 may be heated to 400 to 600 ° C. By the first heat treatment, the semiconductor substrate 106 is separated leaving the thin semiconductor layer (LTSS layer) 101 over the supporting substrate 100 (see FIG. 9C). When force is applied to the semiconductor substrate 106 and the support substrate 100 in different directions, the LTSS layer 101 is formed on the support substrate.

  Next, the LTSS layer 101 is thinned to a desired thickness. The thinning method includes a CMP method or an etching method. In this embodiment mode, the film is thinned by dry etching.

  The thickness of the LTSS layer 101 is preferably 5 nm to 500 nm, preferably 10 nm to 200 nm, more preferably 10 nm to 60 nm. The thickness of the LTSS layer 101 can be appropriately set by controlling the depth of the separation layer 107 and the conditions for thinning. In this embodiment, the LTSS layer is formed to a thickness of 50 nm by dry etching.

A p-type impurity element such as boron, aluminum, or gallium is added to the LTSS layer 101 in order to control the threshold voltage. For example, boron as a p-type impurity element may be added at a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ .

  The LTSS layer 101 is etched to form island-shaped single crystal semiconductor layers 121 separated into island shapes in accordance with the arrangement of the active layers (see FIG. 9D).

  Note that etching is performed so that the non-single-crystal semiconductor film 125 overlaps with a source region and a drain region of the active layer at this time.

  Then, the gate insulating film 110 and the gate electrode 111 are formed over the island-shaped single crystal semiconductor layer 121 (see FIG. 9E). The width of the gate insulating film 110 is made larger than the width of the gate electrode 111 in order to form a low concentration impurity region in a later step. If it is not necessary to form a low-concentration impurity region, the gate insulating film 110 and the gate electrode 111 may have the same width, or the gate insulating film 110 may be formed using the island-shaped single crystal semiconductor layer 121, the non-single-crystal It may be formed so as to cover the crystalline semiconductor film 125 and the insulating film 131.

  The gate insulating film 110 may be formed using any one of a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, and a silicon nitride film containing oxygen. In this embodiment, the silicon oxide film is formed with a thickness of 10 nm to 10 nm. A gate insulating film 110 is formed using a film having a thickness of 100 nm.

  The gate electrode 111 may be formed using tungsten (W), tantalum (Ta), titanium (Ti), aluminum (Al), or the like.

  Next, an impurity element imparting one conductivity is introduced into the island-shaped single crystal semiconductor layer 121 using the gate electrode 111 as a mask. Examples of the impurity element 141 imparting n-type include phosphorus (P) and arsenic (As). As the impurity element 142 imparting p-type, boron (B) can be given. Note that when the impurity element 141 imparting n-type or the impurity element 142 imparting p-type is added to the island-shaped single crystal semiconductor layer 121, the island-shaped single crystal semiconductor layer 121 which is not added is covered with a mask. Do not add unwanted impurity elements.

  By the addition of the impurity element 141 that imparts n-type conductivity and the impurity element 142 that imparts p-type conductivity, a region below the gate electrode 111 is formed in a region not covered with the channel formation region 115, the gate electrode 111, and the gate insulating film 110. High-concentration impurity regions 143 and 144 that are a source region and a drain region are formed. The high-concentration impurity region 143 is an n-type high-concentration impurity region because it includes the impurity element 141 imparting n-type conductivity. On the other hand, the high-concentration impurity region 144 is a p-type high-concentration impurity region because it includes the impurity element 142 imparting p-type conductivity.

  An n-type low-concentration impurity region 114 is formed in the island-shaped single crystal semiconductor layer 121 in a region to which the impurity element 141 imparting n-type conductivity is added through the gate insulating film 110. On the other hand, a p-type low-concentration impurity region 117 is formed in a region of the island-shaped single crystal semiconductor layer 121 to which the impurity element 142 imparting p-type conductivity is added through the gate insulating film 110 (FIG. 10A). )reference).

In this embodiment mode, for example, phosphorus (P) is used as the n-type impurity element 141 and is added at an applied voltage of 20 keV and a dose of 1.0 / cm ² . As a result, the high concentration impurity region 143 contains phosphorus at a concentration of 3 × 10 ²¹ / cm ³ .

  Next, an insulating film is formed so as to cover the insulating film 131, the island-shaped single crystal semiconductor layer 121, the gate insulating film 110, and the gate electrode 111. In this embodiment, a silicon oxide film containing nitrogen is formed by a CVD method. Further, anisotropic etching is performed to form sidewalls 112 on the side surfaces of the gate electrode 111 (see FIG. 10B).

  Next, the insulating film 131, the island-shaped single crystal semiconductor layer 121, and the gate electrode 111 are covered with the sidewall 112, and a metal film 137 is formed (see FIG. 10C). As the metal film 137, nickel (Ni), tungsten (W), titanium (Ti), cobalt (Co), or the like may be used. In this embodiment, as the metal film 137, a nickel film is formed with a thickness of 20 nm by a sputtering method.

  After that, for example, by performing heat treatment at 350 ° C. or higher, the exposed island-shaped single crystal semiconductor layer 121, that is, the high-concentration impurity regions 143 and 144 that are the source region and the drain region, and the metal film 137 are reacted. Thus, the silicide region 113 is formed.

  After the silicide region 113 is formed, the unreacted metal film 137 is removed by etching, for example, wet etching using a chemical solution such as sulfuric acid or nitric acid. Even if a slight residue remains when the unreacted metal film 137 is etched, the sidewall 112 is provided, so that a short circuit between the gate electrode 111 and the island-shaped single crystal semiconductor layer 121 can be prevented.

  Next, an interlayer insulating film 116 is formed. The interlayer insulating film 116 is formed by forming a BPSG (Boron Phosphorus Silicon Glass) film or coating an organic resin typified by polyimide. A contact hole 127 is formed in the interlayer insulating film 116 (see FIG. 11A). Since heat is applied to the entire element when the interlayer insulating film 116 is formed, the metal element in the silicide region 113 may diffuse into the channel formation region 115, but a non-single-crystal semiconductor existing under the silicide region 113. Gettering is performed by the film 125. This suppresses the channel formation region 115 from being contaminated by the metal element.

  After that, a wiring 119 is formed in accordance with the contact hole 127 (see FIG. 11B). The wiring 119 may be formed of aluminum or an aluminum alloy, and the upper layer and the lower layer may be formed of a metal film such as molybdenum, chromium, or titanium as a barrier metal. The wiring 119 is electrically connected to the silicide region 113.

  In this manner, an n-channel TFT and a p-channel TFT can be manufactured using the LTSS layer 101 bonded to the support substrate 100 as an active layer. Since the LTSS layer 101 used for the active layer is a single crystal semiconductor having a constant crystal orientation, a TFT capable of high-speed driving can be obtained. Further, by forming the silicide region 113, a TFT capable of driving at higher speed can be manufactured.

  The TFT manufactured according to this embodiment mode can be driven at high speed, and the metal element from the silicide region 113 does not diffuse into the channel formation region 115.

  As described above, according to this embodiment, a semiconductor device with high driving speed and high reliability can be obtained at the same time.

[Embodiment 2]
In this embodiment, a method for manufacturing a semiconductor device, which is different from that in Embodiment 1, will be described with reference to FIGS. In addition, the same thing as Embodiment 1 shall show with the same code | symbol.

  First, the insulating film 135, the non-single-crystal semiconductor film 125, and the insulating film 131 are formed over the semiconductor substrate 106. As the insulating film 136, a silicon oxide film and a silicon oxide film containing nitrogen are formed with a thickness of 5 nm or less. If the thickness of the insulating film 136 is increased, a metal element in the silicide region is less likely to move to the non-single-crystal semiconductor film 125 in a later step, and thus the thickness of the insulating film 136 is set to 5 nm or less.

  Next, based on FIG. 9A, the separation layer 107 is formed in the semiconductor substrate 106, and the bonding layer 102 is formed over the insulating film 131 (see FIG. 12A).

  After the structure shown in FIG. 12A is obtained, the support substrate 100 and the surface of the semiconductor substrate 106 on which the bonding layer 102 is formed face each other and are brought into close contact with each other (see FIG. 12B). .

  2B and 2C, the bonding layer 102 may be formed on the supporting substrate 100 instead of the semiconductor substrate 106, or the semiconductor substrate may be formed as shown in FIG. The bonding layer 102 may be formed on both the support 106 and the support substrate 100.

  In addition, as illustrated in FIGS. 1B, 2 </ b> B, and 2 </ b> C, a barrier layer 103 may be provided over the support substrate 100. For example, a silicon nitride layer and a silicon oxide layer may be stacked as the barrier layer 103. When a barrier layer is provided on the support substrate 100, contamination of the LTSS layer 101 can be prevented. Note that a silicon nitride layer containing oxygen, an aluminum nitride layer, or an aluminum nitride layer containing oxygen may be used instead of the silicon nitride layer.

  A first heat treatment is performed in a state where the semiconductor substrate 106 and the supporting substrate 100 are overlapped. As the first heat treatment, for example, the semiconductor substrate 106 and the support substrate 100 may be heated to 400 to 600 ° C. By the first heat treatment, the semiconductor substrate 106 is separated leaving the thin semiconductor layer (LTSS layer) 101 over the supporting substrate 100 (see FIG. 12C). When force is applied to the semiconductor substrate 106 and the support substrate 100 in different directions, the LTSS layer 101 is formed on the support substrate.

  Next, the LTSS layer 101 is thinned to a desired thickness. The thinning method includes a CMP method or an etching method. In this embodiment mode, the film is thinned by dry etching.

  The thickness of the LTSS layer 101 is preferably 5 nm to 500 nm, preferably 10 nm to 200 nm, more preferably 10 nm to 60 nm. The thickness of the LTSS layer 101 can be appropriately set by controlling the depth of the separation layer 107 and the conditions for thinning. In this embodiment, the LTSS layer is formed to a thickness of 50 nm by dry etching.

A p-type impurity element such as boron, aluminum, or gallium is added to the LTSS layer 101 in order to control the threshold voltage. For example, boron as a p-type impurity element may be added at a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ .

  The LTSS layer 101 is etched to form island-shaped single crystal semiconductor layers 121 separated into island shapes in accordance with the arrangement of the active layers (see FIG. 12D).

  Further, an n-channel TFT and a p-channel TFT are formed based on the manufacturing steps shown in FIGS. 9E, 10A to 10D, and 11A to 11B. To do.

  In the n-channel TFT, a channel formation region 115, a low-concentration impurity region 114, and a silicide region 113 are formed in an island-shaped single crystal semiconductor layer 121 which is an active layer, and further, a gate insulating film 110, a gate electrode 111 and sidewalls 112 are formed on the side surfaces of the gate electrode 111.

  In the p-channel TFT, a channel formation region 115, a low-concentration impurity region 117, and a silicide region 113 are formed in an island-shaped single crystal semiconductor layer 121 that is an active layer, and further, a gate insulating film 110, a gate electrode 111 and sidewalls 112 are formed on the side surfaces of the gate electrode 111.

  An interlayer insulating film 118 is formed so as to cover the TFT, and a wiring 119 that is electrically connected to the silicide region 113 is formed over the interlayer insulating film 118 (see FIG. 12D).

  Since heat is applied to the entire element when the interlayer insulating film 116 is formed, the metal element in the silicide region 113 may diffuse into the channel formation region 115, but a non-single-crystal semiconductor existing under the silicide region 113. Gettering is performed by the film 125. This suppresses the channel formation region 115 from being contaminated by the metal element. Since the thickness of the insulating film 135 is as thin as 5 nm or less, gettering of the metal element to the non-single-crystal semiconductor film 125 is not suppressed.

  As described above, according to this embodiment, a semiconductor device with high driving speed and high reliability can be obtained.

[Embodiment 3]
In this embodiment, a semiconductor device including an SOI substrate and a TFT manufactured based on Embodiments 1 to 2 will be described with reference to FIGS.

  FIG. 13 illustrates a microprocessor 200 as an example of a semiconductor device. The microprocessor 200 includes an arithmetic circuit 201 (also referred to as an ALU), an arithmetic circuit controller 202 (ALU Controller), an instruction analyzer 203 (Instruction Decoder), an interrupt controller 204 (Interrupt Controller), and a timing controller. 205 (Timing Controller), register 206 (Register), register controller 207 (Register Controller), bus interface 208 (Bus I / F), ROM 209 (Read Only Memory), and ROM interface 210 (ROM I / F) F).

  An instruction input to the microprocessor 200 via the bus interface 208 is input to the instruction analysis unit 203, decoded, and then input to the arithmetic circuit control unit 202, interrupt control unit 204, register control unit 207, and timing control unit 205. The The arithmetic circuit control unit 202, the interrupt control unit 204, the register control unit 207, and the timing control unit 205 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control unit 202 generates a signal for controlling the operation of the arithmetic circuit 201.

  The interrupt control unit 204 processes an interrupt request from an external input / output device or a peripheral circuit based on its priority or mask state during execution of the program of the microprocessor 200. The register control unit 207 generates an address of the register 206, and reads and writes the register 206 according to the state of the microprocessor 200. The timing control unit 205 generates a signal that controls the operation timing of the arithmetic circuit 201, the arithmetic circuit control unit 202, the instruction analysis unit 203, the interrupt control unit 204, and the register control unit 207. For example, the timing control unit 205 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits.

  Note that the microprocessor 200 illustrated in FIG. 13 is only an example in which the configuration is simplified, and actually, the microprocessor 200 may have various configurations depending on the application.

  In such a microprocessor 200, since an integrated circuit is formed by a single crystal semiconductor layer (LTSS layer) having a fixed crystal orientation bonded to a supporting substrate and a TFT having a silicide region, only the processing speed is increased. Thus, low power consumption can be achieved. In addition, since the metal element in the silicide region is gettered by the non-single-crystal semiconductor film, a highly reliable semiconductor device can be obtained.

  Next, an example of a semiconductor device having an arithmetic function capable of transmitting and receiving data without contact will be described with reference to FIGS.

  FIG. 14 shows an example of a computer (hereinafter referred to as “RFCPU”) that operates by transmitting and receiving signals to and from an external device by wireless communication. The RFCPU 211 has an analog circuit unit 212 and a digital circuit unit 213. The analog circuit unit 212 includes a resonance circuit 214 having a resonance capacitance, a rectifier circuit 215, a constant voltage circuit 216, a reset circuit 217, an oscillation circuit 218, a demodulation circuit 219, and a modulation circuit 220. The digital circuit unit 213 includes an RF interface 221, a control register 222, a clock controller 223, a CPU interface 224, a CPU 225 (Central Processing Unit), a RAM 226 (Random Access Memory), and a ROM 227 (Read Only Memory: Read-only memory).

  The operation of the RFCPU 211 having such a configuration is roughly as follows. A signal received by the antenna 228 generates an induced electromotive force by the resonance circuit 214. The induced electromotive force is charged in the capacitor unit 229 through the rectifier circuit 215. The capacitor 229 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor.

  The capacitor portion 229 does not need to be integrally formed with the RFCPU 211, and may be attached to a substrate having an insulating surface constituting the RFCPU 211 as a separate component.

  The reset circuit 217 generates a signal that resets and initializes the digital circuit unit 213. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 218 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 216. The demodulating circuit 219 formed of a low-pass filter binarizes fluctuations in the amplitude of an amplitude modulation (ASK) reception signal, for example.

  The modulation circuit 220 transmits transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal. The modulation circuit 220 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 214. The clock controller 223 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the CPU 225. The power supply management circuit 230 monitors the power supply voltage.

  A signal input from the antenna 228 to the RFCPU 211 is demodulated by the demodulation circuit 219 and then decomposed into a control command and data by the RF interface 221. The control command is stored in the control register 222. The control command includes reading of data stored in the ROM 227, writing of data to the RAM 226, calculation instructions to the CPU 225, and the like.

  The CPU 225 accesses the ROM 227, RAM 226, and control register 222 via the CPU interface 224. The CPU interface 224 has a function of generating an access signal for any of the ROM 227, the RAM 226, and the control register 222 from an address requested by the CPU 225.

  As a calculation method of the CPU 225, a method in which an OS (operating system) is stored in the ROM 227, and a program is read and executed at the time of activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the method using both hardware and software, a method in which a part of processing is performed by a dedicated arithmetic circuit and the remaining arithmetic operations are executed by the CPU 225 using a program can be applied.

  In such an RFCPU 211, an integrated circuit is formed by a single crystal semiconductor layer (LTSS layer) having a constant crystal orientation bonded to an insulating surface and a TFT having a silicide region. Power consumption can be reduced. In addition, since the metal element in the silicide region is gettered by the non-single-crystal semiconductor film, a highly reliable semiconductor device can be obtained.

  In the RFCPU shown in FIG. 14, since not only the processing speed but also the power consumption can be reduced, long-time operation can be guaranteed even if the capacity portion 229 for supplying power is downsized. Although FIG. 14 shows the form of the RFCPU, an IC tag may be used as long as it has a communication function, an arithmetic processing function, and a memory function.

Sectional drawing which shows the structure of the board | substrate which has SOI structure. Sectional drawing which shows the structure of the board | substrate which has SOI structure. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a substrate having an SOI structure. FIG. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device using a substrate having an SOI structure. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device using a substrate having an SOI structure. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device using a substrate having an SOI structure. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device using a substrate having an SOI structure. FIG. 9 is a block diagram illustrating a structure of a microprocessor obtained using a substrate having an SOI structure. The block diagram which shows the structure of RFCPU obtained by the board | substrate which has SOI structure.

Explanation of symbols

100 Support substrate 101 LTSS layer 102 Bonding layer 103 Barrier layer 104 Insulating layer 105 Silicon oxide layer 106 Semiconductor substrate 107 Separating layer 110 Gate insulating film 111 Gate electrode 112 Side wall 113 Silicide region 114 Low concentration impurity region 115 Channel forming region 116 Interlayer insulation Film 117 Low-concentration impurity region 118 Interlayer insulating film 119 Wiring 121 Island-like single crystal semiconductor layer 125 Non-single-crystal semiconductor film 127 Contact hole 131 Insulating film 135 Insulating film 136 Insulating film 137 Metal film 141 Impurity element 142 Impurity element 143 High concentration impurity Region 144 High-concentration impurity region 200 Microprocessor 201 Arithmetic circuit 202 Arithmetic circuit controller 203 Instruction analyzer 204 Interrupt controller 205 Timing controller 206 Register 207 Register controller 2 08 Bus interface 209 ROM
210 ROM interface 211 RFCPU
212 Analog circuit unit 213 Digital circuit unit 214 Resonance circuit 215 Rectifier circuit 216 Constant voltage circuit 217 Reset circuit 218 Oscillation circuit 219 Demodulation circuit 220 Modulation circuit 221 RF interface 222 Control register 223 Clock controller 224 CPU interface 225 CPU
226 RAM
227 ROM
228 Antenna 229 Capacitor 230 Power management circuit

Claims (5)

A bonding layer on the substrate;
An insulating film on the bonding layer;
A non-single-crystal semiconductor film containing a rare gas element in part on the insulating film;
A single crystal semiconductor layer on the insulating film and the non-single crystal semiconductor film;
In the single crystal semiconductor layer, a channel formation region, a low concentration impurity region, a silicide region,
A gate insulating film on the single crystal semiconductor layer;
A gate electrode on the gate insulating film;
Side walls on the side surfaces of the gate electrode,
Have
The non-single crystal semiconductor film is provided under the silicide region,
The semiconductor device, wherein the non-single-crystal semiconductor film suppresses diffusion of a metal element in the silicide region into the channel formation region. In claim 1,
The semiconductor device, wherein the single crystal semiconductor layer is a single crystal silicon layer. In claim 1 or claim 2,
The non-single-crystal semiconductor film is an amorphous semiconductor film, a microcrystalline semiconductor film, or a polycrystalline semiconductor film,
The semiconductor device, wherein the non-single-crystal semiconductor film contains silicon or germanium. In any one of Claims 1 thru | or 3,
The semiconductor device is characterized in that the metal element is any one of nickel, tungsten, titanium, and cobalt. In any one of Claims 1 thru | or 4,
The semiconductor device is characterized in that the bonding layer is formed of silicon oxide.

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