JP5137424B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, a semiconductor device in which a thin film transistor (TFT) is formed over a substrate having an insulating surface such as glass and the thin film transistor is used as a switching element or the like has been actively produced. In the thin film transistor, an island-shaped semiconductor film is formed over a substrate having an insulating surface by a CVD method, a photolithography process, or the like, and a part of the island-shaped semiconductor film is used as a channel formation region of the transistor. Is provided. (For example, Patent Document 1)

A schematic diagram of a general thin film transistor is shown in FIG. First, the thin film transistor includes an island-shaped semiconductor film 903 over an insulating film 902 that functions as a base film over a substrate 901, and a gate through the gate insulating film 904 so as to cross the island-shaped semiconductor film 903. A conductive film 905 functioning as an electrode is provided. The semiconductor film 903 includes a channel formation region 903a formed in a region overlapping with the conductive film 905 and an impurity region 903b which forms a source region or a drain region. In addition, a conductive film 907 for forming a source electrode or a drain electrode is provided so as to be electrically connected to the impurity region 903b. Note that FIGS. 17B and 17C show cross-sectional structures between C _{1 and} D _{1 and} between C _{2 and} D ₂ in FIG. 17A, respectively.
JP 08-018055

  However, when the semiconductor film is provided in an island shape, a step is generated at the end portion of the semiconductor film, which causes a problem that the gate insulating film cannot be sufficiently covered. In particular, in recent years, in order to improve the low power consumption and operation speed of a thin film transistor, it has been desired to reduce the thickness of the gate insulating film. It becomes a remarkable problem. When the gate insulating film cannot be sufficiently covered at the end portion of the semiconductor film, the conductive film forming the gate electrode may contact the semiconductor film at the end portion of the semiconductor film to cause a short circuit. In addition, due to the thinning of the gate insulating film at the end of the channel formation region of the semiconductor film, current leakage at the end of the channel formation region of the gate electrode and the semiconductor film causes problems such as deterioration of transistor characteristics. To do.

  In addition, when fixed charges are trapped at the edge of the semiconductor film due to the breakdown of the gate insulating film or the manufacturing process, the characteristics of the channel formation region at the edge change compared to the center of the semiconductor film. This causes a problem that affects the characteristics of the thin film transistor.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the influence of the characteristics of the end portion of the channel formation region of the semiconductor film on the characteristics of the transistor is reduced.

  A semiconductor device of the present invention includes an island-shaped semiconductor film formed over a substrate, and a conductive film that forms a gate electrode provided over the semiconductor film via a gate insulating film. Has a channel formation region, a first impurity region for forming a source region or a drain region, and a second impurity region. The channel formation region is formed in a region overlapping with the gate electrode traversing the island-shaped semiconductor film. The first impurity region is provided adjacent to the channel formation region, and the second impurity region is provided adjacent to the channel formation region and the first impurity region. In addition, the first impurity region and the second impurity region have different conductivity types, and the second impurity region and the channel formation region have different conductivity types or the same conductivity type. It is characterized in that the impurity elements contained in the impurity region and the channel formation region have different concentrations.

  In the above structure, the second impurity region is provided at an end portion of the semiconductor film and adjacent to a region overlapping with the gate electrode. The second impurity region may be provided in a region that does not overlap with the gate electrode, or may be provided in a region that does not overlap or a region that overlaps.

  In addition, a semiconductor device of the present invention includes a first semiconductor film and a second island-shaped semiconductor film formed in an island shape on a substrate, and a gate insulating film on the first semiconductor film and the second semiconductor film. The first semiconductor film includes a first channel formation region provided in a region overlapping with the gate electrode via the gate insulating film, a first channel formation region, A first impurity region that forms a source region or a drain region provided adjacent to each other, and a second impurity region provided adjacent to the first channel formation region and the first impurity region; The second island-shaped semiconductor film includes a second channel formation region provided in a region overlapping with the gate electrode through the gate insulating film, a third impurity region for forming a source region or a drain region, Between the channel forming region and the third impurity region It is characterized by having a fourth impurity region provided adjacent to. The first impurity region and the second impurity region, the third impurity region, and the fourth impurity region have different conductivity types, and the second impurity region and the fourth impurity region have substantially the same concentration. It is characterized by having an impurity element.

  Further, in the method for manufacturing a semiconductor device of the present invention, an island-shaped semiconductor film is formed over a substrate, a conductive film functioning as a gate electrode is formed through the gate insulating film so as to cross the semiconductor film, and the semiconductor film A first impurity element is introduced into the semiconductor film by using the conductive film as a mask, a resist is selectively formed at an end portion of the semiconductor film, and the first impurity element has a conductivity type different from that of the first impurity element in the semiconductor film using the resist and the conductive film as a mask. In the semiconductor film, a channel formation region is formed in a region overlapping with the conductive film in the semiconductor film, and the first impurity element having the same conductivity type as the second impurity element is adjacent to the channel formation region. An impurity region is formed, and a second impurity region having the same conductivity type as the first impurity element is formed so as to be adjacent to the channel formation region and the first impurity region. The second impurity region is formed adjacent to a region which is an end portion of the semiconductor film and overlaps with the conductive film.

  In the method for manufacturing a semiconductor device of the present invention, the first semiconductor film and the second semiconductor film are formed in an island shape over the substrate, and the gate is formed so as to cross the first semiconductor film and the second semiconductor film. A conductive film functioning as a gate electrode is formed through an insulating film, a first impurity element is introduced into the first semiconductor film and the second semiconductor film using the conductive film as a mask, and an end portion of the first semiconductor film A first resist is formed so as to cover the entire surface of the second semiconductor film, and a second impurity having a conductivity type different from that of the first impurity element is formed in the first semiconductor film using the first resist and the conductive film as a mask. By introducing the element, a first channel formation region is formed in a region overlapping with the conductive film in the first semiconductor film, and the second impurity element and the conductivity type are adjacent to the first channel formation region. Forming a first impurity region which is the same as the first channel; A second impurity region having the same conductivity type as the first impurity element is formed adjacent to the formation region and the first impurity region, and an insulating film is formed so as to be in contact with the side surface of the conductive film. A second resist is formed so as to cover the entire surface of the semiconductor film, and a third impurity element having a conductivity type different from that of the second impurity element is introduced into the second semiconductor film using the conductive film and the insulating film as a mask. Accordingly, in the second semiconductor film, a second channel formation region is formed in a region overlapping with the conductive film, and the first impurity element and the conductivity type are formed in a region adjacent to the second channel formation region and overlapping with the insulating film. Is formed, and a third impurity region having the same conductivity type as that of the third impurity element is formed so as to be adjacent to the fourth impurity region.

  By providing an impurity region having a conductivity type different from that of the source region or the drain region adjacent to the end portion of the island-shaped semiconductor film overlapping with the conductive film functioning as a gate electrode, the end of the channel formation region of the semiconductor film The influence of the characteristics of the portion on the transistor can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
In this embodiment, an example of a semiconductor device of the present invention will be described with reference to drawings.

A semiconductor device described in this embodiment is illustrated in FIG. Incidentally, FIG. 1 (A) is a top view of the semiconductor device shown in this embodiment, in FIG. 1 (B) a sectional view at _A 1 -B ₁ in FIG. 1 _(A), the A 2 -B ₂ A cross-sectional view is shown in FIG. 1C, and a cross-sectional view at A ₃ -B ₃ is shown in FIG.

  The semiconductor device described in this embodiment includes a semiconductor film 103 provided in an island shape over a substrate 101 with an insulating film 102 interposed therebetween, and a gate electrode provided over the semiconductor film 103 with a gate insulating film 104 interposed therebetween. A thin film transistor including a conductive film 105 that forms a gate electrode, an insulating film 106 provided to cover the gate insulating film 104 and the conductive film 105, and a conductive film 107 that forms a source electrode or a drain electrode provided over the insulating film 106 (FIGS. 1A to 1D).

  The conductive film 105 forming the gate electrode is provided so as to cross the island-shaped semiconductor film 103. Note that here, the conductive film 105 is provided with a stacked structure of the first conductive film 105a and the second conductive film 105b; however, the present invention is not limited to this, and a single layer or a stacked structure of three or more layers is used. It may be provided.

  The semiconductor film 103 provided in an island shape includes a channel formation region 103 a provided in a region overlapping with the conductive film 105 and the gate insulating film 104, a region that does not overlap with the conductive film 105, and the channel formation region 103 a A first impurity region 103b that forms a source region or a drain region provided adjacent to each other and a region that does not overlap with the conductive film 105 and is provided adjacent to the channel formation region 103a and the first impurity region 103b. A second impurity region 103c is provided.

  In addition, the conductive film 107 which forms a source electrode or a drain electrode is provided so as to be electrically connected to the first impurity region 103 b through an opening formed in the insulating film 106.

  The first impurity region 103b and the second impurity region 103c are provided to have different conductivity types. For example, when the first impurity region is provided to have an n-type conductivity type, the second impurity region is provided to have a p-type conductivity type, and the first impurity region is set to a p-type conductivity type. In the case where the second impurity region is provided so as to have n-type conductivity, the second impurity region is provided.

  Thus, by providing the second impurity region 103c having a conductivity type different from that of the first impurity region 103b adjacent to the channel formation region at the end of the semiconductor film overlapping with the conductive film 105, the first impurity region 103b is provided. The adjacent portion of the second impurity region 103c has a high resistance due to the pn junction. As a result, the influence of the electrical characteristics of the channel formation region formed in the end portion of the semiconductor film overlapping with the conductive film 105 on the electrical characteristics of the transistor can be reduced.

  In a conventional thin film transistor, a transistor 151 (hereinafter referred to as a channel formation region) having the end portion of the semiconductor film 103 as a channel formation region due to poor coverage of the gate insulating film or accumulation of some charge accompanying a manufacturing process at the end portion of the semiconductor film overlapping the conductive film 105. The transistor 152 (also referred to as “edge transistor 151”) and a transistor 152 (hereinafter also referred to as “main transistor 152”) having the central portion of the semiconductor film 103 as a channel formation region can be regarded as a structure connected in parallel. Accordingly, the equivalent circuit is as shown in FIG. 18A, and the characteristics of the entire transistor (edge transistor 151 + main transistor 152) affect not only the characteristics of the main transistor 152 but also the characteristics of the edge transistor 151. It was.

  On the other hand, the structure described in this embodiment can also be regarded as a structure in which the main transistor 152 and the edge transistor 151 are connected in parallel. However, by providing the second impurity region 103c, an equivalent circuit is illustrated in FIG. B). Since the resistance between the first impurity region 103b and the second impurity region 103c is increased, the influence of the characteristics of the edge transistor 151 on the characteristics of the entire transistor can be reduced.

  Note that in the above structure, the second impurity region 103c and the channel formation region 103a may be provided to have different conductivity types. In this case, the portion where the channel formation region 103a and the second impurity region 103c at the end of the semiconductor film overlapping with the conductive film 105 are adjacent to each other has a high resistance due to the pn junction, and the characteristics of the edge transistor 151 become the characteristics of the entire transistor. It is possible to reduce the influence.

The second impurity region 103 c may be provided so as to be adjacent to the channel formation region 103 a provided at the end portion of the island-shaped semiconductor film 103. In FIG. 1, the second impurity region 103 c is an end portion of the rectangular semiconductor film 103 on the side overlapping with the conductive film 105 (both end portions parallel to A ₁ -B ₁ in FIG. 1A). However, the present invention is not limited to this. For example, it may be selectively formed in the vicinity of the end portion of the semiconductor film 103 and the region overlapping with the conductive film 105 (FIG. 12A). Here, the second impurity region 103 c is provided adjacent to a region which is an end portion of the semiconductor film 103 and overlaps with the conductive film 105. In addition, the second impurity region 103c may be formed in a region that does not overlap with the conductive film 105 and a region that overlaps with the conductive film 105 (FIG. 12B).

Next, an example of a method for manufacturing the semiconductor device illustrated in FIG. 1 will be described with reference to the drawings. 2 is a cross-sectional view taken along line A ₁ -B ₁ in FIG. 1A, and FIG. 3 is a cross-sectional view taken along line A ₃ -B ₃ in FIG.

  First, an island-shaped semiconductor film 103 is formed over the substrate 101 with an insulating film 102 interposed therebetween, and a gate insulating film 104 is formed to cover the island-shaped semiconductor film 103 (FIGS. 2A and 3A). )).

  The substrate 101 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a ceramic substrate or a stainless steel substrate), and a semiconductor substrate such as a Si substrate. In addition, as the plastic substrate, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfine (PES), or acrylic can be selected. Alternatively, an SOI (Silicon On Insulator) substrate may be used.

  The insulating film 102 is formed of silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0), or the like using a CVD method, a sputtering method, or the like. It is formed using an insulating material. For example, in the case where the insulating film 102 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. In this manner, by forming the insulating film 102 functioning as a blocking layer, an alkali metal such as Na or an alkaline earth metal from the substrate 101 can be prevented from adversely affecting an element formed thereon. Note that the insulating film 102 may be omitted when quartz is used for the substrate 101.

  The semiconductor film 103 is formed using an amorphous semiconductor film or a crystalline semiconductor film. The crystalline semiconductor film is obtained by crystallizing an amorphous semiconductor film formed over the insulating film 102 by heat treatment or laser light irradiation, or after amorphizing the crystalline semiconductor film formed over the insulating film 102. , Recrystallized materials, and the like. Alternatively, an island-shaped single crystal semiconductor film may be provided using an SOI (Silicon On Insulator) substrate.

When crystallization or recrystallization is performed by laser light irradiation, an LD-excited continuous wave (CW) laser (YVO ₄ , second harmonic (wavelength 532 nm)) can be used as a laser light source. The second harmonic is not particularly limited to the second harmonic, but the second harmonic is superior to higher harmonics in terms of energy efficiency. When the semiconductor film is irradiated with the CW laser, energy is continuously given to the semiconductor film. Therefore, once the semiconductor film is in a molten state, the molten state can be continued. Furthermore, the solid-liquid interface of the semiconductor film can be moved by scanning with a CW laser, and crystal grains that are long in one direction can be formed along the direction of this movement. The solid laser is used because the output stability is higher than that of a gas laser or the like, and stable processing is expected. Note that not only the CW laser but also a pulse laser having a repetition frequency of 10 MHz or more can be used. When a pulse laser with a high repetition frequency is used, the semiconductor film can be kept in a molten state if the laser pulse interval is shorter than the time from when the semiconductor film is melted until solidification occurs. A semiconductor film including crystal grains that are long in the direction can be formed. Other CW lasers and pulse lasers with a repetition frequency of 10 MHz or more can also be used. For example, examples of the gas laser include an Ar laser, a Kr laser, and a CO ₂ laser. Examples of the solid-state laser include a YAG laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a Y ₂ O ₃ laser, and a YVO ₄ laser. Further, there are ceramic lasers such as YAG laser, Y ₂ O ₃ laser, GdVO ₄ laser, and YVO ₄ laser. Examples of the metal vapor laser include a helium cadmium laser. In addition, it is preferable to emit laser light in TEM ₀₀ (single transverse mode) in a laser oscillator because energy uniformity of a linear beam spot obtained on the irradiated surface can be improved. In addition, a pulsed excimer laser may be used.

As the gate insulating film 104, silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x>y> 0), silicon nitride oxide (SiNxOy) (x>y> 0), or the like is used. Such an insulating layer is formed by a vapor deposition method or a sputtering method. In addition, the semiconductor film 103 is contained in an atmosphere containing oxygen (for example, in an atmosphere containing oxygen (O ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe), or oxygen and hydrogen (H ₂ ). And a rare gas atmosphere) or an atmosphere containing nitrogen (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or nitrogen, hydrogen, and a rare gas. The gate insulating film 104 can also be formed by performing high-density plasma treatment in an atmosphere or an atmosphere containing NH ₃ and a rare gas and oxidizing or nitriding the surface of the semiconductor film 103.

The high density plasma treatment is performed in an atmosphere of the gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the electron temperature of plasma is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor film 103) formed on the substrate 101 is low, damage to the object to be processed can be prevented. . In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide film or a nitride film formed by oxidizing or nitriding an object to be irradiated using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. As a frequency for forming plasma, a high frequency such as a microwave (2.45 GHz) can be used. By forming the gate insulating film 104 by oxidizing or nitriding the surface of the semiconductor film 103 by high-density plasma treatment, the density of defect states serving as traps for electrons and holes can be reduced. Further, disconnection or the like of the gate insulating film 104 can be reduced also at the end portion of the semiconductor film 103.

Note that a low-concentration impurity element may be introduced into the semiconductor film 103 in advance in order to control a threshold value or the like. In this case, the impurity element is also introduced into a region to be a channel formation region later in the semiconductor film 103. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the entire surface of the semiconductor film 103 as an impurity element so as to be contained at a concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ / cm ³ .

  Next, a conductive film 125 is formed over the gate insulating film 104. Here, an example in which the first conductive film 125a and the second conductive film 125b are stacked as the conductive film 125 is illustrated (FIGS. 2B and 3B). Needless to say, the conductive film 125 may have a single layer structure or a stacked structure including three or more layers.

  The conductive film 125 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Alternatively, an alloy material or a compound material containing these elements as a main component can be used. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used. For example, the conductive film 125 is formed using a stacked structure of a first conductive film 125a and a second conductive film 125b, tantalum nitride is used as the first conductive film 125a, and tungsten is used as the second conductive film 125b. Form. Note that in the case where the conductive films 125 are stacked, the above materials can be combined freely.

  Next, the conductive film 125 (here, a conductive film 125a (herein, a stacked structure of the first conductive film 125a and the second conductive film 125b)) is selectively etched, so that the conductive film 105 (here, the conductive film) functions as a gate electrode. 105a and a conductive film 105b), and then an impurity element 121 is introduced into the semiconductor film 103 using the conductive film 105 as a mask, whereby an impurity region 123 is formed in the semiconductor film 103 (FIG. 2C ), FIG. 3 (C)). Here, since the impurity element is introduced after the conductive film 105 is formed so as to cross the island-shaped semiconductor film 103, the impurity region 123 is formed in a region of the semiconductor film 103 that does not overlap with the conductive film 105.

As the impurity element 121, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into the semiconductor film 103 as the impurity element 121 so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , so that an impurity region 123 exhibiting n-type is formed.

  Next, after a resist 108 is selectively provided on part of an end portion of the semiconductor film 103 provided in an island shape, an impurity element 122 is introduced into the semiconductor film 103 using the resist 108 and the conductive film 105 as a mask. Thus, a channel formation region 103a, a first impurity region 103b, and a second impurity region 103c are formed in the semiconductor film (FIGS. 2D and 3D). As a result, a thin film transistor is formed.

  The channel formation region 103a is formed in a region where the conductive film 105 that forms a gate electrode overlaps with the semiconductor film 103, and a first impurity region 103b that functions as a source region or a drain region is formed adjacent to the channel formation region 103a. Then, the second impurity region 103c is formed at the end of the semiconductor film 103 and adjacent to the channel formation region 103a and the first impurity region 103b. Note that here, a portion where the impurity element 122 is not introduced becomes the second impurity region 103c.

  Specifically, the second impurity region 103c is formed at both ends that overlap when the conductive film 105 crosses the semiconductor film 103, and between the second impurity regions 103c formed at both ends. The first impurity regions 103b are formed adjacent to each other. Note that the second impurity region 103c is not necessarily formed in the entire end portion of the semiconductor film 103, and is in contact with the channel formation region 103a and the first impurity region 103b as illustrated in FIG. It is also possible to provide it at a part of the end. In this case, the second impurity region 103 c can be formed in a desired shape by selectively forming the resist 108 and controlling the position where the impurity element 122 is implanted into the semiconductor film 103.

As the impurity element 122, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an impurity element having a conductivity type different from that of the impurity element 121 is used as the impurity element 122. Here, as the impurity element 122, boron (B) is introduced into the semiconductor film 103 so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , and the first impurity region 103b exhibiting p-type conductivity is formed. Form.

  Next, an insulating film 106 is formed so as to cover the conductive film 105, the gate insulating film 104, and the like, and the conductive film 107 functioning as a source electrode or a drain electrode is selectively formed over the insulating film 106 (FIG. 2). E), FIG. 3 (E)). The conductive film 107 is provided so as to be electrically connected to the first impurity region 103 b which forms a source region or a drain region of the semiconductor film 103.

  As the insulating film 106, silicon oxide, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0), or the like formed by a CVD method, a sputtering method, or the like is used. it can. Alternatively, a single layer or a stacked structure including an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin can be used. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The oxazole resin is, for example, photosensitive polybenzoxazole. Photosensitive polybenzoxazole has a low dielectric constant (dielectric constant 2.9 at room temperature 1 MHz) and high heat resistance (differential thermal analysis (TGA) thermal decomposition temperature 550 ° C. at a temperature increase of 5 ° C./min). The material has a low water absorption rate (0.3% at room temperature for 24 hours). Oxazole resin has a low relative dielectric constant (about 2.9) compared to the relative dielectric constant (about 3.2 to 3.4) of polyimide, etc., so that the generation of parasitic capacitance is suppressed and high speed operation is performed. Can do. Here, as the insulating film 106, a single layer or a stack of silicon oxide, silicon oxynitride (SiOxNy) (x> y> 0), or silicon nitride oxide (SiNxOy) (x> y> 0) formed by a CVD method is used. Form. Further, an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin may be stacked.

  The conductive film 107 can have a single-layer structure or a stacked structure formed using one kind of element selected from aluminum, tungsten, titanium, tantalum, molybdenum, nickel, and neodymium, or an alloy containing a plurality of such elements. For example, the conductive film formed using an alloy containing a plurality of the elements can be formed using an aluminum alloy containing titanium, an aluminum alloy containing neodymium, or the like. In the case of providing a stacked structure, for example, an aluminum layer or an aluminum alloy layer as described above may be stacked between titanium layers.

  Through the above steps, a semiconductor device can be manufactured.

  Note that although the case where the conductive film 105 for forming the gate electrode covers and crosses the end portion of the semiconductor film 103 is shown in this embodiment mode, the conductive film 105 does not cover the end portion of the semiconductor film 103. A structure may also be employed in which the semiconductor film 103 is provided so as to cross (FIG. 12C). In this case, a channel formation region 103a is formed in the semiconductor film 103 which overlaps with the conductive film 105, and a first impurity region 103b which forms a source region or a drain region so as to be adjacent to the channel formation region 103a is formed. A second impurity region 103c is formed adjacent to the region 103a and the first impurity region 103b. The second impurity region 103c is an end portion of the semiconductor film 103 and is provided with the first impurity region 103b interposed therebetween. Further, the second impurity region 103c and the channel formation region 103a may be provided to have different conductivity types.

  As shown in this embodiment mode, even in the case where a fixed charge is formed at the end portion of the semiconductor film due to a poor coating of the gate insulating film or a process, a different conductivity is adjacent to the source region or the drain region. By providing the type impurity region, the influence of the edge transistor can be reduced.

(Embodiment 2)
In this embodiment, a semiconductor device and a manufacturing method thereof which are different from those in the above embodiment will be described with reference to drawings. Specifically, a case where a plurality of transistors having different conductivity types is provided will be described.

A semiconductor device shown in this embodiment mode is illustrated in FIGS. Incidentally, FIG. 4 (A) shows a top view of the semiconductor device shown in this embodiment, in FIG. 4 (B) a sectional view of _a 1 -b ₁ in FIG. 4 _(A), the in a 2 -b ₂ A cross-sectional view is shown in FIG. 4C, and a cross-sectional view at a ₃ -b ₃ is shown in FIG. 4D.

  The semiconductor device described in this embodiment includes a semiconductor film 203 and 213 provided in an island shape over a substrate 201 with an insulating film 202 interposed therebetween, and a gate insulating film 204 provided over the semiconductor films 203 and 213. A conductive film 205 for forming the gate electrode, insulating films 206a and 206b provided over the semiconductor films 203 and 213 so as to cover the conductive film 205, and a source electrode or a source electrode provided over the insulating film 206 And a conductive film 207 for forming a drain electrode (FIGS. 4A to 4D).

  The conductive film 205 forming the gate electrode is provided so as to cross the island-shaped semiconductor films 203 and 213. In addition, an insulating film 211 (also referred to as a sidewall) is provided in contact with the side surface of the conductive film 205. Note that here, the conductive film 205 is provided with a stacked structure of the first conductive film 205a and the second conductive film 205b; however, the present invention is not limited to this, and a single layer or a stacked structure of three or more layers is used. It may be provided.

  The island-shaped semiconductor film 203 includes a channel formation region 203a provided in a region overlapping with the conductive film 205 with the gate insulating film 204 interposed therebetween, and a channel formation region 203a that does not overlap with the conductive film 205. A first impurity region 203b that forms a source region or a drain region provided adjacent to each other and a region that does not overlap with the conductive film 205 and is provided adjacent to the channel formation region 203a and the first impurity region 203b. A second impurity region 203c is provided.

  The semiconductor film 213 provided in an island shape includes a channel formation region 213 a provided in a region overlapping with the conductive film 205 and the gate insulating film 204, a region not overlapping with the conductive film 205, and the channel formation region 213 a A fourth impurity region 213c provided adjacent to the conductive film 205 and a third impurity that forms a source region or a drain region provided adjacent to the fourth impurity region 213c. And a region 213b.

  The fourth impurity region 213 c forms an LDD region, and is provided below the insulating film 211 provided between the channel formation region 213 a and the third impurity region 213 b and in contact with the side surface of the conductive film 205. Is formed.

  When the conductive film 205 is provided with a stacked structure of the first conductive film 205a and the second conductive film 205b, the first conductive film 205a formed below is the second conductive film formed above. Alternatively, the fourth impurity region 213c may overlap with the first conductive film 205a and may not overlap with the second conductive film 205b. With such a structure, the on-current characteristics of the transistor can be improved.

  In this embodiment, the first impurity region 203b formed in the semiconductor film 203 is formed to be an impurity region having a different conductivity type from that of the second impurity region 203c. In addition, the first impurity region 203b formed in the semiconductor film 203 is formed to be an impurity region having a different conductivity type from the third impurity region 213b and the fourth impurity region 213c formed in the semiconductor film 213. .

  That is, the second impurity region 203c formed in the semiconductor film 203, the third impurity region 213b and the fourth impurity region 213c formed in the semiconductor film 213 have the same conductivity type. In this case, the impurity elements contained in the second impurity region 203c and the third impurity region 213b, or in the second impurity region 203c and the fourth impurity region 213c may be formed to have the same concentration. . As a result, in the manufacturing process, the second impurity region 203c and the third impurity region 213b, or the second impurity region 203c and the fourth impurity region 213c can be formed in the same manner. Can be simplified.

  For example, a first impurity region 203b that forms a source region or a drain region of the semiconductor film 203 is provided with a p-type conductivity type, a second impurity region 203c is provided with an n-type conductivity type, and the source or The third impurity region 213b for forming the drain is provided with an n-type conductivity type, and the fourth impurity region 213c for forming the LDD region is provided with an n-type conductivity type having a lower concentration than the third impurity region 213b. it can. Further, the second impurity region 203c and the fourth impurity region 213c can be provided at the same concentration. Needless to say, the second impurity region 203c and the third impurity region 213b can be provided at the same concentration. Note that in the case where the first impurity region 203b formed in the semiconductor film 203 is provided with n-type conductivity, the conductivity type may be reversed.

  The conductive film 207 for forming the source or drain electrode includes the first impurity region 203b and the semiconductor film 213 that form the source or drain region of the semiconductor film 203 through the openings formed in the insulating films 206a and 206b. A third impurity region 213b which forms a source region or a drain region is provided so as to be electrically connected. In addition, as illustrated in FIG. 4, the first impurity region 203 b and the third impurity region 213 b may be electrically connected through a conductive film 207 to form a CMOS circuit.

Next, an example of a method for manufacturing the semiconductor device illustrated in FIG. 4 will be described with reference to the drawings. 5 shows a top view of FIG. 6, FIG. 6 shows a sectional view of a ₁ -b ₁ in FIG. 4 (A), and FIG. 7 shows a sectional view of a ₃ -b ₃ in FIG. 4 (A). Is shown.

  First, island-shaped semiconductor films 203 and 213 are formed over a substrate 201 with an insulating film 202 interposed therebetween, and a gate insulating film 204 and a conductive film 215 are stacked to cover the island-shaped semiconductor films 203 and 213. (FIGS. 6A and 7A). For the substrate 201, the insulating film 202, the semiconductor films 203 and 213, the gate insulating film 204, and the conductive film 215, the manufacturing method, materials, and the like described in Embodiment 1 can be applied to this embodiment. Note that here, the conductive film 215 has a stacked structure of a first conductive film 215a and a second conductive film 215b.

Note that a low-concentration impurity element may be introduced in advance in order to control a threshold value or the like in the semiconductor films 203 and 213. In this case, the impurity element is also introduced into a region to be a channel formation region later in the semiconductor films 203 and 213. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. For example, boron (B) as an impurity element can be introduced in advance over the entire surface of the semiconductor films 203 and 213 so as to be contained at a concentration of 5 × 10 ^{15 to} 5 × 10 ¹⁷ / cm ³ . Needless to say, impurity elements having different concentrations may be introduced into the semiconductor film 203 and the semiconductor film 213, or impurity elements having different conductivity types may be introduced.

  Next, the conductive film 215 (here, a stacked structure of the first conductive film 215a and the second conductive film 215b) is selectively etched, so that the conductive film 205 (here, the conductive film) functions as a gate electrode. 205A and a conductive film 205b) (FIG. 5A), and then an impurity element 224 is introduced into the semiconductor films 203 and 213 using the conductive film 205 as a mask, whereby impurities are added to the semiconductor films 203 and 213. A region 223 is formed (FIGS. 5B, 6B, and 7B), in which the conductive film 205 is formed so as to cross the island-shaped semiconductor films 203 and 213, and then impurities are formed. In order to introduce the element 224, an impurity region 223 is formed in a region of the semiconductor films 203 and 213 that do not overlap with the conductive film 205.

As the impurity element 224, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, as the impurity element 224, phosphorus (P) is introduced into the semiconductor films 203 and 213 so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , thereby forming an n-type impurity region 223. To do.

  Next, after a resist 221 is selectively provided so as to cover part of the end portion of the semiconductor film 203 and the entire surface of the semiconductor film 213, the conductive film 205 formed over the resist 221 and the semiconductor film 203 As a mask, an impurity element 225 is introduced into the semiconductor film 203, whereby a channel formation region 203a, a first impurity region 203b, and a second impurity region 203c are formed in the semiconductor film 203 (FIG. 5C). 6 (C), FIG. 7 (C)). The channel formation region 203a is formed in a region where the conductive film 205 which forms a gate electrode overlaps with the semiconductor film 203, and a first impurity region 203b which functions as a source region or a drain region is formed adjacent to the channel formation region 203a. Thus, the second impurity region 203c is formed at the end of the semiconductor film 203 and adjacent to the channel formation region 203a and the first impurity region 203b. Note that here, a portion where the impurity element 225 is not introduced becomes the second impurity region 203c.

  Specifically, the second impurity region 203c is formed at both ends that overlap when the conductive film 205 crosses the semiconductor film 203, and between the second impurity regions 203c formed at both ends. The first impurity regions 203b are formed adjacent to each other. Note that the second impurity region 203c is not necessarily formed in the entire end portion of the semiconductor film 203, and is in contact with the channel formation region 203a and the first impurity region 203b as illustrated in FIG. It is also possible to provide it at a part of the end. In this case, the second impurity region 203c can be formed in a desired shape by selectively forming the resist 221 and controlling the position at which the impurity element 225 is implanted into the semiconductor film 203.

As the impurity element 225, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an impurity element having a conductivity type different from that of the impurity element 224 is used as the impurity element 225. Here, boron (B) is introduced into the semiconductor film 203 as the impurity element 225 so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , and the first impurity region 203b exhibiting p-type conductivity is formed. Form.

  Next, an insulating film 211 is formed so as to be in contact with the side surface of the conductive film 205 (see FIGS. 6D and 7D). The insulating film 211 is sometimes referred to as a sidewall. The semiconductor film functions as a mask when a high concentration n-type impurity is doped and a low concentration impurity region is formed below the insulating film 211.

  The insulating film 211 is a single layer or a stacked layer of a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or an organic material such as an organic resin, using a plasma CVD method, a sputtering method, or the like. To form. Then, the insulating film formed on the entire surface can be selectively etched by anisotropic etching mainly in the vertical direction.

  Next, after a resist 222 is selectively provided so as to cover the entire surface of the semiconductor film 203, the impurity element 226 is added to the semiconductor film 213 using the conductive film 205 and the insulating film 211 formed over the semiconductor film 213 as a mask. As a result, a channel formation region 213a, a third impurity region 213b, and a fourth impurity region 213c are formed in the semiconductor film 213 (FIGS. 5D, 6E, and 7E). . The channel formation region 213a is formed in a region where the conductive film 205 forming the gate electrode and the semiconductor film 213 overlap with each other, and functions as an LDD region in a region adjacent to the channel formation region 213a and where the insulating film 211 and the semiconductor film 213 overlap. A fourth impurity region 213c is formed, and a third impurity region 213b that functions as a source region or a drain region is formed adjacent to the fourth impurity region 213c. Note that here, a portion where the impurity element 226 is not introduced becomes the fourth impurity region 213c.

As the impurity element 226, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an impurity element having a conductivity type different from that of the impurity element 225 is used as the impurity element 226. Here, as the impurity element 226, phosphorus (P) is introduced into the semiconductor film 213 so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , and a third impurity region 213b exhibiting p-type conductivity is formed. Form.

  Note that in this embodiment, the order in which the impurity element 225 and the impurity element 226 are introduced into the semiconductor films 203 and 213 may be reversed. In this case, first, the third impurity region 213b and the fourth impurity region 213c are formed in the semiconductor film 213, and then the first impurity region 203b and the second impurity region 203c are formed in the semiconductor film 203. .

  Next, an insulating film 206a and an insulating film 206b are stacked so as to cover the conductive film 205, the semiconductor films 203 and 213, and the conductive film 207 functioning as a source electrode or a drain electrode is selected over the insulating film 206b. (FIG. 6F, FIG. 7F). The conductive film 207 is electrically connected to a first impurity region 203b that forms a source region or a drain region of the semiconductor film 203 and a third impurity region 213b that forms a source region or a drain region of the semiconductor film 213. Provide as follows. Note that in this embodiment, the conductive film 207 electrically connected to the first impurity region 203b and the conductive film 207 electrically connected to the third impurity region 213b are electrically connected. A CMOS circuit having a p-channel thin film transistor and an n-channel thin film transistor can be formed.

  For the insulating film 206a, the insulating film 206b, and the conductive film 207, the manufacturing method, materials, and the like described in Embodiment 1 can be applied to this embodiment. Here, as the insulating film 206a, silicon oxide, silicon oxynitride (SiOxNy) (x> y> 0) or silicon nitride oxide (SiNxOy) (x> y> 0) formed by a CVD method is formed, and the insulating film 206b is formed. As an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin.

  Through the above steps, a semiconductor device can be manufactured.

  By providing a semiconductor device as shown in this embodiment mode, leakage and short circuit between the gate electrode and the semiconductor film in the stepped portion can be prevented even when the gate insulating film crosses the island-shaped semiconductor film. be able to. Further, even when a fixed charge resulting from a process is formed at an end portion of the semiconductor film, it is possible to reduce the influence of characteristics on the transistor due to the channel formation region at the end portion of the semiconductor film. In the case where a p-channel thin film transistor and an n-channel thin film transistor are provided over the same substrate, an impurity region formed in one thin film transistor (for example, the fourth impurity region 213c functioning as an LDD region in this embodiment) The impurity region (e.g., the second impurity region 203c in this embodiment) formed in the other thin film transistor is provided by introducing an impurity element having the same concentration, whereby the process can be simplified.

  This embodiment can be freely combined with the above embodiment.

(Embodiment 3)
In this embodiment, a semiconductor device and a manufacturing method thereof which are different from those in the above embodiment will be described with reference to drawings.

A semiconductor device described in this embodiment is illustrated in FIGS. 8A is a top view of the semiconductor device described in this embodiment, and a cross-sectional view of a ₁ -b ₁ in FIG. 8A is shown in FIG. 8B and in a ₂ -b ₂ . A cross-sectional view is shown in FIG. 8C, and a cross-sectional view at a ₃ -b ₃ is shown in FIG. 8D.

  In the semiconductor device described in this embodiment, semiconductor films 303 and 313 provided in an island shape over a substrate 301 with an insulating film 302 interposed therebetween, and a gate insulating film 304 provided over the semiconductor films 303 and 313. A conductive film 305 for forming the gate electrode, insulating films 306 a and 306 b provided over the semiconductor films 303 and 313 so as to cover the conductive film 305, and a source electrode provided over the insulating film 306 or A conductive film 307 for forming a drain electrode (FIGS. 8A to 8D).

  A conductive film 305 forming a gate electrode is provided so as to cross the island-shaped semiconductor films 303 and 313. An insulating film 311 (also referred to as a sidewall) is provided in contact with the side surface of the conductive film 305. Note that although the case where the conductive film 305 is provided with a single-layer structure is shown here, a plurality of conductive films may be stacked as described in the above embodiment mode.

  The semiconductor film 303 provided in an island shape is a channel formation region 303a provided in a region overlapping with the conductive film 305 and a region not overlapping with the conductive film 305 and provided adjacent to the channel formation region 303a. It has a second impurity region 303c for forming an LDD region, and a first impurity region 303b and a third impurity region 303d for forming a source region or a drain region.

  The first impurity region 303b is provided adjacent to the second impurity region 303c, and the second impurity region 303c is provided between the channel formation region 303a and the first impurity region 303b. The third impurity region 303d is in the vicinity of the portion where the conductive film 305 overlaps in the end portion of the semiconductor film 303 and is adjacent to the channel formation region 303a, the first impurity region 303b, and the second impurity region 303c. It is provided to do.

  The semiconductor film 313 provided in an island shape is a channel formation region 313 a provided in a region overlapping with the conductive film 305 and a region not overlapping with the conductive film 305 and provided adjacent to the channel formation region 313 a. It has a fifth impurity region 313c for forming an LDD region, and a fourth impurity region 313b and a sixth impurity region 313d for forming a source region or a drain region.

  The fourth impurity region 313b is provided adjacent to the fifth impurity region 313c, and the fifth impurity region 313c is provided between the channel formation region 313a and the fourth impurity region 313b. The sixth impurity region 313d is in the vicinity of the portion where the conductive film 305 overlaps in the end portion of the semiconductor film 313 and is adjacent to the channel formation region 313a, the fourth impurity region 313b, and the fifth impurity region 313c. It is provided to do.

  In this embodiment, the first impurity region 303b and the second impurity region 303c formed in the semiconductor film 303 are formed so as to be impurity regions having a different conductivity type from the third impurity region 303d. The fourth impurity region 313b and the fifth impurity region 313c formed in 313 are formed to be impurity regions having a conductivity type different from that of the sixth impurity region 313d. In addition, the first impurity region 303b formed in the semiconductor film 303 is formed to be an impurity region having a different conductivity type from that of the fourth impurity region 313b formed in the semiconductor film 313.

  That is, the third impurity region 303d formed in the semiconductor film 303, the fourth impurity region 313b and the fifth impurity region 313c formed in the semiconductor film 313 have the same conductivity type. In this case, the impurity elements contained in the third impurity region 303d and the fourth impurity region 313b, or the third impurity region 303d and the fifth impurity region 313c may be formed to have the same concentration. . As a result, in the manufacturing process, the third impurity region 303d and the fourth impurity region 313b, or the third impurity region 303d and the fifth impurity region 313c can be formed in the same manner. Can be simplified.

  Further, the sixth impurity region 313d formed in the semiconductor film 313, the first impurity region 303b and the second impurity region 303c formed in the semiconductor film 303 have the same conductivity type. In this case, the sixth impurity region 313d and the first impurity region 303b, or the sixth impurity region 313d and the second impurity region 303c may be formed to have the same concentration of impurity elements. . As a result, in the manufacturing process, the sixth impurity region 313d and the first impurity region 303b, or the sixth impurity region 313d and the second impurity region 303c can be formed in the same manner. Can be simplified.

  For example, a first impurity region 303b that forms a source region or a drain region of the semiconductor film 303 and a second impurity region 303c that forms an LDD region are provided with p-type conductivity, and a third impurity region 303d is formed with an n-type conductivity. The conductivity type can be provided. In this case, a fourth impurity region 313b that forms a source region or a drain region of the semiconductor film 313 and a fifth impurity region 313c that forms an LDD region are provided with n-type conductivity, and a sixth impurity region 313d is formed as p. Provided with the conductivity type of the mold. Further, the second impurity region 303c and the sixth impurity region 313d can be provided with the same concentration, and the third impurity region 303d and the fifth impurity region 313c can be provided with the same concentration. Needless to say, the first impurity region 303b and the sixth impurity region 313d can be provided at the same concentration, and the third impurity region 303d and the fourth impurity region 313b can be provided at the same concentration.

  The conductive film 307 forming the source electrode or the drain electrode includes the first impurity region 303b and the semiconductor film 313 that form the source region or the drain region of the semiconductor film 303 through the openings formed in the insulating films 306a and 306b. A fourth impurity region 313b which forms a source region or a drain region is provided so as to be electrically connected. In addition, as illustrated in FIG. 8, the first impurity region 303 b and the fourth impurity region 313 b may be electrically connected through a conductive film 307 to form a CMOS circuit.

Next, an example of a method for manufacturing the semiconductor device illustrated in FIG. 8 will be described with reference to the drawings. 9 shows a top view of FIG. 8, FIG. 10 shows a sectional view of a ₁ -b ₁ in FIG. 8 (A), and FIG. 11 shows a sectional view of a ₃ -b ₃ in FIG. 8 (A). Is shown.

  First, island-shaped semiconductor films 303 and 313 are formed over a substrate 301 with an insulating film 302 interposed therebetween, and a conductive film is formed over the island-shaped semiconductor films 303 and 313 with a gate insulating film 304 interposed therebetween. 305 is formed (FIGS. 9A, 10A, and 11A). For the substrate 301, the insulating film 302, the semiconductor films 303 and 313, the gate insulating film 304, and the conductive film 305, the manufacturing methods, materials, and the like described in the above embodiment modes can be applied to this embodiment mode. Note that although the case where the conductive film 305 is provided with a single-layer structure is shown here, a plurality of conductive films may be stacked as described in the above embodiment mode.

  Next, a resist 321 is selectively formed over the semiconductor films 303 and 313, and an impurity element 325 is introduced into the semiconductor films 303 and 313 using the resist 321 and the conductive film 305 as a mask, whereby the semiconductor films 303 and 313 are introduced. An impurity region 331 is formed in the substrate (FIGS. 9B, 10B, and 11B). Here, the resist 321 is formed so that at least part of the end portion of the semiconductor film 303 is exposed, and the resist 321 is formed so as to cover the end portion of the semiconductor film 313.

As the impurity element 325, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into the semiconductor films 303 and 313 as the impurity element 325 so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , and an impurity region 331 indicating n-type is formed. To do.

  Next, a resist 322 is selectively formed over the semiconductor films 303 and 313, and an impurity element 326 is introduced into the semiconductor films 303 and 313 using the resist 322 and the conductive film 305 as a mask, whereby the semiconductor films 303 and 313 are formed. An impurity region 332 is formed in the region (FIGS. 9C, 10C, and 11C). Here, a resist 322 is formed so as to cover the end portion of the semiconductor film 303 so that at least a part of the end portion of the semiconductor film 313 (near the end portion of the semiconductor film 313 on the side overlapping with the conductive film 305) is exposed. A resist 322 is formed.

As the impurity element 326, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. The impurity element 326 has a conductivity type different from that of the impurity element 325. Here, boron (B) is introduced into the semiconductor films 303 and 313 as the impurity element 326 so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ , thereby forming an impurity region 331 indicating n-type. To do.

  Next, the insulating film 311 is formed so as to be in contact with the side surface of the conductive film 305, and then a resist 323 is selectively provided so as to cover part of the end portion of the semiconductor film 303 and the entire surface of the semiconductor film 313. Then, by introducing the impurity element 327 into the semiconductor film 303 using the resist 323, the conductive film 305, and the insulating film 311 as a mask, a channel formation region 303a, a first impurity region 303b, and a second impurity region are formed in the semiconductor film 303. 303c and a third impurity region 303d are formed (FIGS. 9D, 10D, and 11D). The insulating film 311 is sometimes referred to as a sidewall, and functions as a mask when a low-concentration impurity region (here, a second impurity region) is formed below the insulating film 311.

  The channel formation region 303a is formed in a region where the conductive film 305 forming the gate electrode overlaps with the semiconductor film 303, and functions as an LDD region in a region adjacent to the channel formation region 303a and where the insulating film 311 and the semiconductor film 303 overlap. A second impurity region 303c is formed, and a first impurity region 303b that functions as a source region or a drain region is formed adjacent to the second impurity region 303c. Note that here, a portion of the impurity region 332 where the impurity element 327 is not introduced becomes the third impurity region 303d.

As the impurity element 327, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an impurity element having a conductivity type different from that of the impurity element 325 is used as the impurity element 327. Here, boron (B) is introduced into the semiconductor film 303 as the impurity element 327 so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , and a first impurity region 303b exhibiting p-type conductivity is formed. Form.

  Next, a resist 324 is selectively provided so as to cover the entire surface of the semiconductor film 303 and part of an end portion of the semiconductor film 313, and then the semiconductor film is formed using the resist 324, the conductive film 305, and the insulating film 311 as a mask. By introducing the impurity element 328 into 313, a channel formation region 313a, a fourth impurity region 313b, a fifth impurity region 313c, and a sixth impurity region 313d are formed in the semiconductor film 313 (FIG. 9E). FIG. 10 (E) and FIG. 11 (E)).

  The channel formation region 313a is formed in a region where the conductive film 305 forming the gate electrode and the semiconductor film 313 overlap, and functions as an LDD region in a region adjacent to the channel formation region 313a and where the insulating film 311 and the semiconductor film 313 overlap. A fifth impurity region 313c is formed, and a fourth impurity region 313b functioning as a source region or a drain region is formed adjacent to the fifth impurity region 313c. Note that here, a portion of the impurity region 331 where the impurity element 328 is not introduced becomes the sixth impurity region 313d.

As the impurity element 328, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this embodiment, an impurity element having a conductivity type different from that of the impurity element 327 is used as the impurity element 328. Here, phosphorus (P) is introduced into the semiconductor film 313 as the impurity element 328 so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , and a fourth impurity region 313 b indicating p-type is formed. Form.

  Note that in this embodiment, the order in which the impurity element 325 and the impurity element 326 are introduced into the semiconductor films 303 and 313 may be reversed. In this case, the impurity regions 332 are formed in the semiconductor films 303 and 313 first, Thereafter, impurity regions 331 are formed in the semiconductor films 303 and 313. The order in which the impurity element 327 and the impurity element 328 are introduced into the semiconductor films 303 and 313 may be reversed. In this case, first, the fourth impurity region 313b, the fifth impurity region 313c, and the sixth impurity region 313d are formed in the semiconductor film 313, and then the first impurity region 303b and the second impurity region 313d are formed in the semiconductor film 303. An impurity region 303c and a third impurity region 303d are formed.

  Next, an insulating film 306a and an insulating film 306b are stacked so as to cover the conductive film 305, the semiconductor films 303, 313, and the like, and the conductive film 307 functioning as a source electrode or a drain electrode is selected over the insulating film 306b. (FIG. 10 (F), FIG. 11 (F)). The conductive film 307 is electrically connected to the first impurity region 303 b that forms the source region or the drain region of the semiconductor film 303 and the fourth impurity region 313 b that forms the source region or the drain region of the semiconductor film 313. Provide as follows. Note that in this embodiment, the conductive film 307 electrically connected to the first impurity region 303b and the conductive film 307 electrically connected to the fourth impurity region 313b are electrically connected. A CMOS circuit having a p-channel thin film transistor and an n-channel thin film transistor can be formed.

  For the insulating film 306a, the insulating film 306b, and the conductive film 307, any of the manufacturing methods, materials, and the like described in Embodiment 1 can be applied to this embodiment. Here, as the insulating film 306a, silicon oxide, silicon oxynitride (SiOxNy) (x> y> 0) or silicon nitride oxide (SiNxOy) (x> y> 0) formed by a CVD method is formed, and the insulating film 306b As an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy, a siloxane material such as a siloxane resin, or an oxazole resin.

  Through the above steps, a semiconductor device can be manufactured.

  Note that in this embodiment, in order to control a threshold value or the like in the semiconductor films 303 and 313, a low-concentration impurity element may be introduced before the conductive film 305 functioning as a gate electrode is formed. In this case, in the semiconductor films 303 and 313, the channel formation regions 303a and 313a also contain an impurity element. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In addition, an impurity region formed by introducing an impurity element in advance can be used as the third impurity region 303d or the sixth impurity region 313d. In this case, the step of FIG. 9B or FIG. 9C can be omitted.

  By providing a semiconductor device as shown in this embodiment mode, leakage and short circuit between the gate electrode and the semiconductor film in the stepped portion can be prevented even when the gate insulating film crosses the island-shaped semiconductor film. be able to. Further, even when a fixed charge resulting from a process is formed at an end portion of the semiconductor film, it is possible to reduce the influence of characteristics on the transistor due to the channel formation region at the end portion of the semiconductor film. In the case where a p-channel thin film transistor and an n-channel thin film transistor are provided over the same substrate, an impurity region functioning as an LDD region formed in one thin film transistor (for example, the second impurity region 303c in this embodiment, The fourth impurity region 313c) and the impurity regions formed in the other thin film transistor (for example, the sixth impurity region 313d and the third impurity region 303d in this embodiment) are provided by introducing impurity elements having the same concentration. Therefore, the process can be simplified.

  This embodiment can be freely combined with the above embodiment.

(Embodiment 4)
In this embodiment, an example of a usage pattern of a semiconductor device obtained using the manufacturing method described in the above embodiment will be described. Specifically, application examples of a semiconductor device capable of inputting and outputting data without contact will be described below with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

  First, an example of a top structure of the semiconductor device described in this embodiment will be described with reference to FIG. A semiconductor device 80 illustrated in FIG. 13 includes a thin film integrated circuit 131 provided with a plurality of elements such as thin film transistors that form a memory portion and a logic portion, and a conductive film 132 functioning as an antenna. The conductive film 132 functioning as an antenna is electrically connected to the thin film integrated circuit 131.

  In the case where a thin film transistor is provided in the thin film integrated circuit 131, the structure described in the above embodiment can be applied.

  FIGS. 13B and 13C are schematic views of the cross section of FIG. The conductive film 132 functioning as an antenna may be provided above the elements included in the memory portion and the logic portion. For example, the conductive film 132 functions as an antenna via the insulating film 130 above the structure described in the above embodiment mode. A conductive film 132 can be provided (FIG. 13B). Alternatively, the conductive film 132 functioning as an antenna can be provided over the substrate 133 and then attached to the thin film integrated circuit 131 (FIG. 13C). Here, the conductive film 136 provided over the insulating film 130 and the conductive film 132 functioning as an antenna are electrically connected through conductive particles 134 contained in an adhesive resin 135.

Note that although an example in which the conductive film 132 functioning as an antenna is provided in a coil shape and an electromagnetic induction method or an electromagnetic coupling method is applied is described in this embodiment mode, the semiconductor device of the present invention is not limited thereto, and a microwave method is used. It is also possible to apply. In the case of a microwave method, the shape of the conductive film 132 functioning as an antenna may be determined as appropriate depending on the wavelength of the electromagnetic wave used.

  For example, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in the semiconductor device 80, the wavelength of an electromagnetic wave used for signal transmission is considered. The length of the conductive layer functioning as an antenna may be set as appropriate. For example, the conductive film functioning as an antenna may be linear (for example, a dipole antenna (FIG. 14A)) or flat (for example, , A patch antenna (FIG. 14B), a ribbon shape (FIGS. 14C and 14D), etc. The shape of the conductive film 132 functioning as an antenna is not limited to a linear shape. Instead, it may be provided in a curved shape, a meandering shape, or a combination of these in consideration of the wavelength of the electromagnetic wave.

  The conductive film 132 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when the conductive film 132 that functions as an antenna is formed by using a screen printing method, a conductive paste in which conductive particles having a particle diameter of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive film, it is preferable to fire after extruding the conductive paste. For example, when fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) are used as a conductive paste material, the conductive film is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

  Next, operation of the semiconductor device described in this embodiment is described.

  The semiconductor device 80 has a function of communicating data without contact, and controls the high frequency circuit 81, the power supply circuit 82, the reset circuit 83, the clock generation circuit 84, the data demodulation circuit 85, the data modulation circuit 86, and other circuits. A control circuit 87, a memory circuit 88, and an antenna 89 are provided (FIG. 15A). The high frequency circuit 81 is a circuit that receives a signal from the antenna 89 and outputs the signal received from the data modulation circuit 86 from the antenna 89, and the power circuit 82 is a circuit that generates a power supply potential from the received signal, and a reset circuit 83. Is a circuit that generates a reset signal, a clock generation circuit 84 is a circuit that generates various clock signals based on the reception signal input from the antenna 89, and a data demodulation circuit 85 demodulates the reception signal to control the control circuit 87. The data modulation circuit 86 is a circuit that modulates the signal received from the control circuit 87. Further, as the control circuit 87, for example, a code extraction circuit 91, a code determination circuit 92, a CRC determination circuit 93, and an output unit circuit 94 are provided. The code extraction circuit 91 is a circuit that extracts a plurality of codes included in an instruction sent to the control circuit 87, and the code determination circuit 92 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 93 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

  In FIG. 15A, in addition to the control circuit 87, a high frequency circuit 81 and a power supply circuit 82 which are analog circuits are included.

  Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 89. The radio signal is sent to the power supply circuit 82 via the high frequency circuit 81, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 80. The signal sent to the data demodulation circuit 85 via the high frequency circuit 81 is demodulated (hereinafter, demodulated signal). Further, the signal and the demodulated signal that have passed through the reset circuit 83 and the clock generation circuit 84 via the high frequency circuit 81 are sent to the control circuit 87. The signal sent to the control circuit 87 is analyzed by the code extraction circuit 91, the code determination circuit 92, the CRC determination circuit 93, and the like. Then, information on the semiconductor device stored in the memory circuit 88 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 94. Further, the encoded information of the semiconductor device 80 is transmitted by the antenna 89 through the data modulation circuit 86. Note that in a plurality of circuits included in the semiconductor device 80, a low power supply potential (hereinafter referred to as VSS) is common and VSS can be GND.

  As described above, by transmitting a signal from the reader / writer to the semiconductor device 80 and receiving the signal transmitted from the semiconductor device 80 by the reader / writer, the data of the semiconductor device can be read.

  Further, the semiconductor device 80 may be of a type in which power supply voltage is supplied to each circuit by electromagnetic waves without mounting a power source (battery), or each circuit is mounted by using electromagnetic waves and a power source (battery). It is good also as a type which supplies a power supply voltage to.

  Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 15B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 15C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

  In addition to the above, the semiconductor device of the present invention has a wide range of uses, and is applicable to any product that can be used for production and management by clarifying information such as the history of an object without contact. be able to. For example, banknotes, coins, securities, certificate documents, bearer bonds, packaging containers, books, recording media, personal belongings, vehicles, foods, clothing, health supplies, daily necessities, chemicals, etc. It can be provided and used in an electronic device or the like. These examples will be described with reference to FIG.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, etc. (FIG. 16A). A certificate refers to a driver's license, a resident's card, etc. (FIG. 16B). Bearer bonds refer to stamps, gift tickets, various gift certificates, etc. (FIG. 16C). Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like (FIG. 16D). Books refer to books, books, and the like (FIG. 16E). The recording media refer to DVD software, video tapes, and the like (FIG. 16F). The vehicles refer to vehicles such as bicycles, ships, and the like (FIG. 16G). Personal belongings refer to bags, glasses, and the like (FIG. 16H). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (television receivers, thin television receivers), cellular phones, and the like.

  Forgery can be prevented by providing the semiconductor device 80 on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing semiconductor devices 80 in personal items such as packaging containers, books, recording media, personal items, foods, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems will be improved. Can do. By providing the semiconductor device 80 in vehicles, health supplies, medicines, etc., it is possible to prevent counterfeiting and theft, and in the case of medicines, it is possible to prevent mistakes in taking medicines. As a method of providing the semiconductor device 80, the semiconductor device 80 is provided by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

  In this way, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. it can. Further, forgery or theft can be prevented by providing a semiconductor device in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by embedding a semiconductor device equipped with a sensor in a living creature such as livestock, it is possible to easily manage health conditions such as body temperature as well as the year of birth, gender or type.

  Note that this embodiment can be freely combined with the above embodiment.

  In this example, electrical characteristics of transistors included in the semiconductor device described in the above embodiment are described with reference to drawings. Specifically, the result of verifying (simulating) the electrical characteristics when the transistor is operated is shown.

  As verification, regarding the current-voltage characteristics (hereinafter also referred to as “electrical characteristics”) of the transistor in the case where charges are trapped for some reason at the end of the semiconductor film, the second impurity region shown in FIG. We compared the electrical characteristics with and without. In this example, the verification was performed on the assumption that negative (negative) charges were accumulated at the end of the semiconductor film.

  First, it is assumed that negative fixed charges are accumulated at the end of the semiconductor film 103 that overlaps the conductive film 105, and the current (Id) -voltage (Vg) characteristics of the transistor according to the surface density of the accumulated fixed charges are verified. This was performed (FIGS. 19A to 19D). This is because some fixed charge is considered to be trapped in the manufacturing process at the end of the semiconductor film 103 by experiment.

Here, the edge portion of the semiconductor film 103 as a 45 ° tapered, the interface and its vicinity of the semiconductor film ends 103 assumes the accumulation of negative fixed charge Qf _e to, other than the end semiconductor film 103 It was assumed that Qf _m (1 × 10 ¹¹ / cm ² ) negative fixed charge accumulation. In addition, verification was performed by setting the channel length L of the transistor to 1 μm and the channel width W to 10 μm. In the embodiment, as the concentration of _{Qf e, (a): 1} × 10 12 / cm 2, (b): 2 × 10 12 / cm 2, (c): 3 case of a × ¹⁰ 12 / cm ² It verified about.

The verification results of the current-voltage characteristics of the transistor at this time are shown in FIGS. Note that FIG. 19C illustrates current-voltage characteristics of a p-channel transistor, and FIG. 19D illustrates current-voltage characteristics of an n-channel transistor. Note that in the case of a p-channel transistor, the first impurity region 103b for forming a source region or a drain region is p-type conductivity (concentration is 1 × 10 ²⁰ / cm ³ ), and an n-channel type transistor is used. In the case of a transistor, the first impurity region 103b is assumed to be n-type conductivity (concentration is 1 × 10 ²⁰ / cm ³ ).

In the case of a p-channel transistor, the current-voltage characteristic of the transistor changed as the concentration of the fixed charge (Qf _e ) at the end of the semiconductor film 103 increased. Further, the threshold voltage changes with a change in the concentration of Qf _e, significantly more current of the transistor - was found to affect the voltage characteristics. On the other hand, in the case of an n-channel transistor, the current-voltage characteristics of the transistor were not affected even when the concentration of the fixed charge (Qf _e ) at the end of the semiconductor film was changed.

  This is because, in a p-channel transistor, an edge transistor and a main transistor are respectively formed at the end and the center of the semiconductor film 103, and the edge transistor and the main transistor having different threshold values are connected in parallel. Thus, it is considered that the current-voltage characteristic 920 of the transistor is affected (FIG. 20A). In particular, since a negative fixed charge is accumulated at the end of the semiconductor film 103 in the p-channel transistor, the current-voltage characteristic of the entire transistor is determined by the current-voltage characteristic 922 of the edge transistor and the current-voltage characteristic 921 of the main transistor. The characteristic 920 is significantly affected, and a kink 925 is generated.

  On the other hand, in an n-channel transistor, an edge transistor and a main transistor are formed in the same manner. However, since the fixed charge accumulated at the end of the semiconductor film 103 is negative, the current-voltage characteristic 921 of the edge transistor is It is considered that the current-voltage characteristic 920 of the whole transistor was not affected by the current-voltage characteristic of the main transistor (FIG. 20B). Note that when the fixed charge formed in the semiconductor film 103 is positive, the current-voltage characteristics of the p-channel transistor and the n-channel transistor are opposite to each other.

Next, as described in the above embodiment, when the second impurity region 103 c is provided in contact with the channel formation region 103 a and the first impurity region 103 b at the end portion of the semiconductor film 103 that overlaps with the conductive film 105. The current (Id) -voltage (Vg) characteristics of the transistors were verified (FIGS. 21A to 21C). Here, the edge portion of the semiconductor film 103 as a 45 ° tapered, the interface and its vicinity of the semiconductor film ends 103 assumes the accumulation of negative fixed charge Qf _e to, other than the end semiconductor film 103 It was assumed that Qf _m (1 × 10 ¹¹ / cm ² ) negative fixed charge accumulation. In addition, the transistor channel length L is 1 μm, the channel width W is 10 μm, and the width d of the second impurity region 103c (the length of the second impurity region 103c in a direction substantially horizontal to the conductive film 105) is 1 μm. went. In the embodiment, as the concentration of _{Qf e, (a): 1} × 10 12 / cm 2, (b): 2 × 10 12 / cm 2, (c): 3 case of a × ¹⁰ 12 / cm ² It verified about.

FIG. 21C shows current-voltage characteristics of the p-channel transistor at this time. Note that here, the first impurity region 103b for forming the source region or the drain region has a p-type conductivity (1 × 10 ²⁰ / cm ³ ), and the second impurity region 103c has an n-type conductivity (1 × 10 ¹⁷ / cm ³ ).

FIG. 21C shows that there is no effect on the current-voltage characteristics of the transistor even in the case of a p-channel transistor or in the case where a negative fixed charge is trapped at the end of the semiconductor film 103. . Even when the concentration of the fixed charge (Qf _e ) at the end of the semiconductor film was increased, the current-voltage characteristics of the transistor were not affected. This is because the second impurity region 103c having a conductivity type opposite to that of the first impurity region 103b forming the source region or the drain region is provided at an end portion of the semiconductor film 103 overlapping with the conductive film 105. This is probably because the second impurity region 103c functions as a stopper for the parasitic channel formed at the end. As a result, by using the structure shown in the present invention, even when a charge is trapped due to a manufacturing process or the like at the edge of the semiconductor film, the current-voltage characteristics of the transistor are prevented from changing. I found out that I can do it.

Next, FIGS. 22A to 22C show verification results of current-voltage characteristics of the transistor when the concentration of the second impurity region 103c is changed in the structure shown in FIG. As the concentration of _{Qf e, (a): 1} × 10 12 / cm 2, (b): 2 × 10 12 / cm 2, (c): and verified with the case where a 3 × ¹⁰ 12 / cm ² It was.

22A shows a concentration of the second impurity region 103c of 1 × 10 ¹⁷ / cm ³ (n-type), and FIG. 22B shows a concentration of the second impurity region 103c of 1 × 10 ¹⁸ / cm ³ ( FIG. 22C shows the measurement result of the current-voltage characteristics of the p-channel transistor when the concentration of the second impurity region 103c is 1 × 10 ¹⁹ / cm ³ (n-type).

22A to 22C, the off-state current of the transistor increased as the concentration of the second impurity region 103c increased. This is considered to be because the off-current that flows through the second impurity region 103c flows more easily as the concentration of the second impurity region 103c is increased. Therefore, the concentration of the second impurity region 103c is preferably 1 × 10 ¹⁷ / cm ³ or more and less than 1 × 10 ¹⁸ / cm ³ .

Next, FIGS. 23A to 23D show verification results of the current-voltage characteristics of the transistor when the width d of the second impurity region 103c is changed. As the concentration of _{Qf e, (a): 1} × 10 12 / cm 2, (b): 2 × 10 12 / cm 2, (c): and verified for the case where a 3 × ¹⁰ 12 / cm ² It was.

23A shows a case where d = 0.3 μm, FIG. 23B shows a case where d = 0.5 μm, FIG. 23C shows a case where d = 1.0 μm, and FIG. 23D shows a case where d = 1.5 μm. The measurement result of the current-voltage characteristic of a transistor is shown. When the width d of the second impurity region is not sufficient, the current-voltage characteristic of the transistor increases as the fixed charge (Qf _e ) concentration at the end of the semiconductor film increases, as in the structure shown in FIG. A changing result was obtained (FIG. 23A). Further, the threshold voltage changes with a change in the concentration of Qf _e, the current of the transistor - was found to affect the voltage characteristics.

  From the above results, even when a semiconductor device including a p-channel transistor and an n-channel transistor is provided, only one transistor functions as a parasitic channel stopper, as described in the second embodiment. By providing the impurity regions to be used (for example, the second impurity region 103c (FIG. 1) and the second impurity region 203c (FIG. 4)), the characteristics of the end of the channel formation region of the semiconductor film are affected by the characteristics of the transistor. The influence can be reduced.

FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 10 shows an example of a conventional semiconductor device. FIG. 6 is a diagram showing an example of an equivalent circuit diagram of a semiconductor device of the present invention. 4A and 4B illustrate an embodiment of a semiconductor device of the invention. 4A and 4B illustrate an embodiment of a semiconductor device of the invention. 4A and 4B illustrate an embodiment of a semiconductor device of the invention. 4A and 4B illustrate an embodiment of a semiconductor device of the invention. 4A and 4B illustrate an embodiment of a semiconductor device of the invention.

Explanation of symbols

80 Semiconductor Device 81 High Frequency Circuit 82 Power Supply Circuit 83 Reset Circuit 84 Clock Generation Circuit 85 Data Demodulation Circuit 86 Data Modulation Circuit 87 Control Circuit 88 Memory Circuit 89 Antenna 91 Code Extraction Circuit 92 Code Determination Circuit 93 CRC Determination Circuit 94 Output Unit Circuit 101 Substrate 102 Insulating film 103 Semiconductor film 104 Gate insulating film 105 Conductive film 106 Insulating film 107 Conductive film 108 Resist 121 Impurity element 122 Impurity element 123 Impurity region 125 Conductive film 130 Insulating film 131 Thin film integrated circuit 132 Conductive film 133 Substrate 134 Conductive particle 135 Resin 136 Conductive film 151 Transistor 152 Transistor 201 Substrate 202 Insulating film 203 Semiconductor film 204 Gate insulating film 205 Conductive film 206 Insulating film 207 Conductive film 211 Insulating film 213 Semiconductor film 215 Conductive Film 221 resist 222 resist 223 impurity region 224 impurity element 225 impurity element 226 impurity element 301 substrate 302 insulating film 303 semiconductor film 304 gate insulating film 305 conductive film 306 insulating film 307 conductive film 311 insulating film 313 semiconductor film 321 resist 322 resist 323 resist 324 Resist 325 Impurity element 326 Impurity element 327 Impurity element 328 Impurity element 331 Impurity region 332 Impurity region 900 Characteristic 901 Substrate 902 Insulating film 903 Semiconductor film 904 Gate insulating film 905 Conductive film 907 Conductive film 920 Characteristic 921 Characteristic 922 Characteristic 103a Channel formation region 103b impurity region 103c impurity region 105a conductive film 105b conductive film 125a conductive film 125b conductive film 203a channel formation region 203b impurity region Region 203c impurity region 203d impurity region 205a conductive film 205b conductive film 206a insulating film 206b insulating film 213a channel formation region 213b impurity region 213c impurity region 213c region 215a conductive film 215b conductive film 303a channel formation region 303b impurity region 303c impurity region 303d impurity region 306a Insulating film 306b Insulating film 313a Channel forming region 313b Impurity region 313c Impurity region 313d Impurity region 3200 Reader / writer 3210 Display unit 3220 Product 3230 Semiconductor device 3240 Reader / writer 3250 Semiconductor device 3260 Product 903a Channel forming region 903b Impurity region 953b

Claims (9)

A first semiconductor film and a second semiconductor film formed in an island shape on a substrate;
A conductive film functioning as a gate electrode formed on the first semiconductor film and the second semiconductor film through a gate insulating film;
The first semiconductor film includes:
A first channel formation region provided in a region overlapping with the conductive film with the gate insulating film interposed therebetween;
A first impurity region for forming a source region or a drain region provided adjacent to the first channel formation region;
A second impurity region provided adjacent to the first channel formation region and the first impurity region;
The second semiconductor film is
A second channel formation region provided in a region overlapping with the conductive film with the gate insulating film interposed therebetween;
A third impurity region forming a source region or a drain region;
A fourth impurity region provided adjacently between the channel formation region and the third impurity region;
The first impurity region has a conductivity type different from that of the second impurity region, the third impurity region, and the fourth impurity region,
The semiconductor device, wherein the second impurity region and the fourth impurity region have impurity elements having substantially the same concentration. In claim 1 ,
A semiconductor device, wherein the first channel formation region and the second impurity region have different conductivity types. In claim 1 or claim 2 ,
The semiconductor device, wherein the second impurity region is provided adjacent to a region which is an end portion of the first semiconductor film and overlaps with the conductive film. A first semiconductor film and a second semiconductor film formed in an island shape on a substrate;
A conductive film functioning as a gate electrode formed on the first semiconductor film and the second semiconductor film across the first semiconductor film and the second semiconductor film via a gate insulating film; And
The first semiconductor film includes:
A first channel formation region provided in a region overlapping with the conductive film with the gate insulating film interposed therebetween;
A first impurity region forming a source region or a drain region;
A second impurity region forming an LDD region provided adjacently between the first channel formation region and the first impurity region;
A third impurity region provided adjacent to the first channel formation region, the first impurity region, and the second impurity region;
The second semiconductor film is
A second channel formation region provided in a region overlapping with the conductive film with the gate insulating film interposed therebetween;
A fourth impurity region forming a source region or a drain region;
A fifth impurity region forming an LDD region provided adjacently between the second channel formation region and the fourth impurity region;
A sixth impurity region provided adjacent to the second channel formation region, the fourth impurity region, and the fifth impurity region;
The first impurity region, the second impurity region, and the sixth impurity region have the same conductivity type,
The third impurity region, the fourth impurity region, and the fifth impurity region have the same conductivity type,
The semiconductor device, wherein the third impurity region and the fifth impurity region have impurity elements having substantially the same concentration. In claim 4 ,
The semiconductor device, wherein the second impurity region and the sixth impurity region have impurity elements having substantially the same concentration. In claim 4 or claim 5 ,
The third impurity region is provided adjacent to a region that is an end portion of the first semiconductor film and overlaps the conductive film,
The sixth impurity region is provided at an end portion of the second semiconductor film and adjacent to a region where the conductive film overlaps. Forming a first semiconductor film and a second semiconductor film on the substrate in an island shape;
Forming a conductive film functioning as a gate electrode through a gate insulating film so as to cross the first semiconductor film and the second semiconductor film;
A first impurity element is introduced into the first semiconductor film and the second semiconductor film using the conductive film as a mask;
Forming a first resist so as to cover an end of the first semiconductor film and the second semiconductor film;
By introducing a second impurity element having a conductivity type different from that of the first impurity element into the first semiconductor film using the first resist and the conductive film as a mask, Forming a first channel formation region in a region overlapping with the conductive film, and forming a first impurity region having the same conductivity type as the second impurity element so as to be adjacent to the first channel formation region; Forming a second impurity region having the same conductivity type as the first impurity element so as to be adjacent to the first channel formation region and the first impurity region;
Forming an insulating film in contact with the side surface of the conductive film;
Forming a second resist so as to cover the first semiconductor film;
By introducing a third impurity element having a conductivity type different from that of the second impurity element into the second semiconductor film using the conductive film and the insulating film as a mask, the conductivity of the second semiconductor film is increased. Forming a second channel formation region in a region overlapping with the film; and a fourth impurity having the same conductivity type as the first impurity element in a region adjacent to the second channel formation region and overlapping the insulating film A method for manufacturing a semiconductor device is characterized in that a region is formed, and a third impurity region having the same conductivity type as the third impurity element is formed adjacent to the fourth impurity region. In claim 7 ,
A method for manufacturing a semiconductor device, wherein the second impurity region and the fourth impurity region are formed so as to contain impurity elements having substantially the same concentration. In claim 7 or claim 8 ,
The method for manufacturing a semiconductor device, wherein the second impurity region is formed adjacent to a region which is an end portion of the first semiconductor film and overlaps with the conductive film.

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