JP5135583B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine, and more particularly to a gaming machine that performs a predetermined process after executing a predetermined number of interrupt processes in a main routine.

  In a conventional gaming machine such as a pachinko machine, in a normal game, when a game ball enters the start opening provided in the game board, a big hit lottery is performed as to whether or not to shift to a special game, and the liquid crystal display A so-called variable display game is performed in which three symbols (identification information) in a variable display means such as a device start changing, change in a predetermined pattern, and then stop sequentially. Furthermore, in the conventional pachinko machine, when the big hit lottery is won, the symbols are stopped in a predetermined combination and the game shifts to a special game. In a special game, a round game in which a special winning opening is opened for a long time is repeated a plurality of times (for example, 15 times), and a lot of prize balls are paid out.

  In these gaming machines, a predetermined process (main routine) that is started when the power is turned on, and a game ball that has passed through each winning opening such as a random number update process for updating a random number related to the big win lottery or a start opening, etc. An interrupt routine that is executed in response to an interrupt condition that occurs every predetermined time to execute a switch input process to be detected is executed, and a game is executed by executing a predetermined process after prohibiting the occurrence of this timer interrupt A gaming machine is provided (Patent Document 1).

Also, for example, in a gaming machine that performs predetermined processing once for every three interrupt routine executions, according to the control of a conventional gaming machine, an interrupt that counts the number of interrupts every three interrupt routine executions The count counter was cleared. Therefore, in these gaming machines, when it is determined whether or not to perform a predetermined process, the interrupt counter is “3” (that is, a gaming machine that executes an interruption routine at 2 ms is predetermined every 6 ms. In other words, the execution of the predetermined process is maintained once every 6 ms.
JP 2007-50109 A

  However, in the above gaming machine, for example, when determining whether or not to perform a predetermined process depending on the processing status, even if the interrupt counter indicates “4” or more, the interrupt counter is cleared. Resulting in. After that, the timing at which the predetermined processing with the interrupt counter value “3” is executed deviates from the predetermined timing. Therefore, it is possible to guarantee the number of times the predetermined processing is performed per predetermined time. It will disappear. For example, according to the example of FIG. 21, the number of executions of the predetermined process executed every 6 ms is less than “1”.

  For this reason, in such a gaming machine, there is no guarantee that a predetermined process is executed once per fixed time in a long-time operation, and there is room for improvement in the accuracy of game control.

  An object of the present invention is to provide a highly reliable gaming machine that can guarantee the accuracy of game control even in a long-time operation in order to eliminate the above disadvantages.

  (1) Game control means for controlling the progress of the game and storage means for storing data based on the game, the game control means is a routine for controlling the progress of the game, and is predetermined after the start of power supply. After performing the power-on process, a main routine that repeatedly executes a predetermined first process, and an interrupt routine that is executed when triggered by an interrupt condition that occurs every predetermined time during the execution of the main routine In the interrupt processing, the number of times the interrupt routine is executed is counted and stored as a count value in the storage means, and in the first processing, the storage means An interrupt count determination process for determining whether or not the stored count value is equal to or greater than a predetermined determination value, and is executed in the main routine, and the count value is predetermined in the interrupt count determination process When it is determined that the value is equal to or greater than the determination value, the storage unit is triggered by the execution of the second process and the second process that performs the process of moving to the first process after performing the predetermined process. A gaming machine comprising: subtracting the same value as a determination value from a stored count value, and performing an interrupt count subtraction process for storing the value after the subtraction as a count value in the storage means.

  According to the invention of (1), when it is determined in the interrupt count determination process that the count value (for example, the value of the interrupt count counter) is greater than or equal to a predetermined determination value (for example, “3”) After performing the above process, the second process for shifting to the first process is performed, and triggered by the execution of the second process, the count value (for example, the number of interrupts) stored in the storage means (for example, the main RAM) Subtraction of the same value as the determination value (for example, “3”) is performed from the counter value), and interrupt count subtraction processing for storing the value after subtraction as a count value in a storage unit (for example, main RAM) is performed. Thus, for example, when the count value (for example, the value of the interrupt count counter) is “4”, the count value (for example, the interrupt count counter of the interrupt count counter) is subtracted from the determination value (for example, “3”). When the value) becomes “1” and the interrupt routine is executed twice more, the second process is executed. As described above, the second process is always executed once every fixed time, so that the accuracy of the game control can be ensured even in a long-time operation, and a highly reliable gaming machine can be provided. it can.

  (2) In the gaming machine of (1), it is provided with a timing means for managing the progress of the game, and the game control means executes a timer update process for updating the timing means in the second process. A featured gaming machine.

  According to the invention of (2), in addition to the invention of (1), in the second process that is always executed once every fixed time, a timer update process for updating the clock means (for example, timer) is executed. Is done. For this reason, even in a long-time operation, the timekeeping means is updated once per fixed time, so that time management can be performed almost accurately. In this way, the accuracy of game control can be ensured even during long-time operation, and a highly reliable gaming machine can be provided.

  (3) In the gaming machine of (1) or (2), an effect unit that performs a predetermined effect according to the progress of the game, an effect control circuit that executes an effect control process for controlling the effect unit, A main control circuit including the game control means for executing a main routine and executing a command transmission process for transmitting an effect command capable of specifying an effect time to the effect control circuit according to the progress of the game. In the effect control process of the control circuit, the effect time management process for independently managing the effect time corresponding to the effect command is performed according to the effect command transmitted from the main control circuit, and the effect time of the effect time management process is A process of controlling the effect means is executed based on management, and the command transmission process of the game control means is executed in the second process. Tricks machine.

  According to the invention of (3), in addition to the invention of (1) or (2), in the second process that is always executed once per fixed time, the main control circuit changes to the effect control circuit (sub-control circuit). ) Executes a command transmission process of transmitting an effect command that can specify the effect time. Further, the production control circuit uniquely manages the production time corresponding to the production command according to the production command, and controls production means (for example, a liquid crystal display device and a speaker) based on the management of the production time. . For this reason, even in a long-time operation, an effect command can be transmitted once per fixed time. Therefore, the timing of the process of the main control circuit and the process of the effect control circuit coincide with each other. Since the operation is synchronized with the processing in the circuit, there is no contradiction in the operation, so that the control load can be reduced and the accuracy of the operation can be ensured. In this way, the accuracy of game control can be ensured even during long-time operation, and a highly reliable gaming machine can be provided.

  According to the present invention, the accuracy of game control can be ensured even during long-time operation, and a highly reliable gaming machine can be provided.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the embodiments described below, a case where the present invention is applied to a first type pachinko gaming machine (also referred to as “digital pachi”) is shown as a preferred embodiment for a gaming machine according to the present invention.

[Composition of gaming machine]
First, an overview of the gaming machine will be described with reference to FIGS. FIG. 1 is a perspective view showing an overview of a pachinko gaming machine 10 according to the present embodiment. FIG. 2 is an exploded perspective view showing an overview of the pachinko gaming machine 10 according to the present embodiment. FIG. 3 is a front view showing an overview of the lamp unit 53 of the pachinko gaming machine 10 in the present embodiment. FIG. 4 is a front view showing an overview of the pachinko gaming machine 10 in the present embodiment.

  As shown in FIGS. 1 to 4, the pachinko gaming machine 10 includes an outer frame 12 having an opening 12 a formed on the front surface, and a main body frame 11 pivotally attached to the outer frame 12. It is comprised from the various components attached to the main body frame 11 so that the opening 12a of the outer frame 12 may be faced, and the door pivotally attached to the front of the main body frame 11 so that opening and closing is possible. As shown in FIG. 1, this door is for closing the opening 12a from the front, and a game is normally performed in the closed state. Further, an upper plate 20, a lower plate 22, a firing handle 26, and the like are disposed on the front surface of the main body frame 11.

  The main body frame 11 is provided with a liquid crystal display device 32, a game board 14, and the like. In addition, description is abbreviate | omitted in order to make an understanding easy about various components (not shown) other than the game board 14, the spacer 31, and the liquid crystal display device 32. FIG.

  The game board 14 is entirely formed of a plate-shaped resin (a member having permeability) having permeability. Examples of the transparent member include various materials such as acrylic resin, polycarbonate resin, and methacrylic resin. In addition, the game board 14 has a game area 15 on the front side thereof in which the launched game ball can roll. The game area 15 is an area surrounded by a guide rail 30 (specifically, an outer rail 30a shown in FIG. 4 to be described later) where a game ball, which is an example of a game medium, can roll. A plurality of game nails 13 are driven into the game area 15 of the game board 14.

  The liquid crystal display device 32 is disposed behind (on the back side of) the game board 14. In other words, the liquid crystal display device 32 is disposed behind the transparent member of the game board 14. The liquid crystal display device 32 has a display area 32a that enables display of an image relating to a game. The display area 32a is disposed so as to overlap all or part of the game board 14 from the back side. In other words, the display area 32a is disposed behind the game board 14 so as to overlap at least all or part of the game area 15 in the game board 14. Specifically, the liquid crystal display device 32 is disposed behind the game board 14 so that the display area 32 a overlaps all or part of the game area 15 and all or part of the game area outer area 16. . In the liquid crystal display device 32, various images such as an effect image for effect and an ornament image for decoration are displayed in the display area 32a. In particular, in the display area 32a of the liquid crystal display device 32, after transitioning to the jackpot gaming state (special gaming state), an effect image for rendering is displayed during execution of the special game.

  Thus, in the present embodiment, by providing the effect display means such as the liquid crystal display device 32 behind the game board 14, for example, an area in which game members such as a planted area of the game nail 13, an accessory, and a decorative member are provided. And the degree of freedom of layout can be further increased.

  The spacer 31 is disposed behind (on the back side of) the game board 14, and forms a space serving as a flow path for game balls in front of (on the front side of) the liquid crystal display device 32. The spacer 31 is made of a permeable material. In the present embodiment, the spacer is formed of a material having permeability, but the present invention is not limited to this, and for example, a part of the spacer may be formed of a material having permeability. Moreover, you may form with the material which does not have permeability | transmittance.

  The door 17 is provided with a protective plate 19 having transparency. The protective plate 19 is disposed so as to face the front surface of the game board 14 with the door 17 closed.

  The firing handle 26 is provided so as to be rotatable with respect to the main body frame 11. A firing solenoid (not shown) as a driving device is provided on the back side of the firing handle 26. Further, a touch sensor (not shown) is provided on the peripheral edge of the firing handle 26. When the touch sensor is touched by the player, it is detected that the firing handle 26 is gripped by the player. When the firing handle 26 is gripped by the player and is rotated in the clockwise direction, power is supplied to the firing solenoid according to the rotational angle, and the game ball stored in the upper plate 20 is played. It is fired sequentially on the board 14 and the game proceeds.

  A lamp unit 53 is provided on the lower left side of the game board 14. As shown in FIG. 3, the lamp unit 53 includes a special symbol display 35, a normal symbol display 33, special symbol hold lamps 34a to 34d, normal symbol hold lamps 50a to 50d, and round number indicators 51a to 51d. Is provided.

  The special symbol display 35 is composed of a plurality of 7-segment LEDs. The 7-segment LED is repeatedly turned on and off in a predetermined manner when the predetermined special symbol variation display start condition is satisfied. When a special symbol (for example, a numerical symbol such as “21”, “50”, or “64”) is stopped and displayed as the special symbol, the jackpot gaming state that is advantageous to the player from the normal gaming state The gaming state shifts to (special gaming state). When the jackpot gaming state is reached, as will be described later, the shutter 40 (see FIG. 4) is controlled to the open state, and the gaming ball can be received in the big prize opening 39 (see FIG. 4). On the other hand, when a symbol other than a specific symbol (for example, a symbol symbol such as “-”) is stopped and displayed as a special symbol, the normal gaming state is maintained. As described above, a game in which a special symbol is variably displayed and then stopped and the game state is shifted or maintained according to the result is referred to as a “special symbol game”.

  Below the special symbol indicator 35, a normal symbol indicator 33 is provided. The normal symbol display 33 is composed of two display lamps, and these display lamps are alternately lit and extinguished so as to be variably displayed as normal symbols.

  Below the normal symbol display 33, special symbol holding lamps 34a to 34d are provided. The special symbol hold lamps 34a to 34d display the number of executions of the special symbol variable display held by turning on or off (so-called “hold number”, “hold number related to special symbols”). For example, when the execution of the special symbol fluctuation display is held once, the special symbol hold lamp 34a is turned on.

  Below the normal symbol display 33, normal symbol holding lamps 50a to 50d are provided. The normal symbol hold lamps 50a to 50d display the number of executions of fluctuation display of the normal symbols that are held by turning on or off (so-called “hold number”, “hold number related to normal symbols”). Similar to the special symbol, when the execution of the fluctuation display of the normal symbol is held once, the normal symbol holding lamp 50a is turned on.

  On the left side of the special symbol display 35, round number displays 51a to 51d are provided. The round number indicators 51a to 51d display the maximum number of rounds during execution of the special game. The round number indicators 51a to 51d are composed of four LEDs, and there are two patterns of lighting and extinguishing for each LED, so at least 16 patterns can be displayed (2 4th power pattern). ). The round number display 51 may be composed of a plurality of 7-segment LEDs, a liquid crystal display unit, a transmissive liquid crystal display unit, and the like.

  In addition, in the display area 32a of the liquid crystal display device 32 disposed behind the game board 14 (back side), an effect image related to the special symbol displayed on the special symbol display 35 is displayed.

  For example, during the variable display of the special symbol displayed on the special symbol display 35, an effect identification symbol (for example, “0” to “9” consisting of numerals and symbols) is displayed in the display area 32 a of the liquid crystal display device 32. The numbers up to “” are displayed in a variable manner. In addition, the special symbol that has been variably displayed on the special symbol display 35 is stopped and displayed, and the identification information for presentation is also stopped and displayed in the display area 32 a of the liquid crystal display device 32.

  In addition, when a special symbol is stopped and displayed as a special symbol on the special symbol display 35, an effect image that allows the player to grasp that it is a big hit is displayed in the display area 32a of the liquid crystal display device 32. Specifically, when a special symbol is stopped and displayed as a special symbol on the special symbol display 35, the combination of the identification information for presentation displayed in the display area 32a of the liquid crystal display device 32 is a specific display mode. (For example, the display is stopped in a state where any one of “1” to “9” is arranged in each of the plurality of symbol rows), and is also pleased with a character image such as “Big hit! The character image is displayed in the display area 32 a of the liquid crystal display device 32.

  An overview of the pachinko gaming machine 10 will be further described with reference to FIG. As shown in FIG. 4, on the gaming board 14 of the pachinko gaming machine 10, two guide rails 30 (30a and 30b), a stage 55, passing gates 54a and 54b, a stage 57, a starting port 25, a shutter 40, a large Game members such as a winning opening 39 and general winning openings 56a, 56b, 56c, 56d are provided. Further, a speaker 46 is provided on the upper portion of the door 17.

  A stage 55 is provided in the upper part of the game board 14, and a stage 57 is provided in the approximate center of the game board 14.

  The two guide rails 30 provided on the left side of the game board 14 are composed of an outer rail 30a that partitions (defines) the game area 15 and an inner rail 30b that is disposed inside the outer rail 30a. . The launched game ball is guided by a guide rail 30 provided on the game board 14 and moves to the upper part of the game board 14, and a plurality of game nails (see FIG. 2) and the game board 14 are provided. Due to the collision with the stage 55 or the like, it flows down toward the lower side of the game board 14 while changing its traveling direction.

  A ball entrance 24 is formed at the left end of the game area 15. When a game ball wins the ball entrance 24, it is guided behind the stage 57 via the warp path 47 behind the game board 14. The game ball guided behind the stage 57 is discharged to the front side of the game board 14 from a discharge port (not shown) surrounded by the stage 57 and flows down to the game board 14.

  A winning area is provided in the start opening 25 described above. This winning area includes a start winning ball sensor 116 (see FIG. 5). When a game medium such as a game ball is detected by the start winning ball sensor 116, it is determined that the game ball has won. When the game ball wins, the special symbol display by the special symbol display 35 is started. Also, if a game ball wins during the special symbol variation display, the special symbol variation display based on the winning of the game ball to the start port 25 is executed until the special symbol during the variation display is stopped and displayed ( Start) is put on hold. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started. Note that an upper limit is set for the number of times the execution of the special symbol variable display is suspended. For example, the special symbol variable display is suspended up to four times.

  In addition, as another condition (start of variable display of a predetermined special symbol), the special symbol is stopped and displayed. In other words, every time a predetermined special symbol variable display start condition is satisfied, the special symbol variable display is started.

  Passage gates 54 a and 54 b are provided on both the left and right sides of the approximate center of the game board 14. The passing gates 54a and 54b are provided with passing ball sensors 114 and 115 (see FIG. 5) described later. The passing ball sensors 114 and 115 detect that the game ball has passed through the passing gates 54a and 54b. When the passing ball sensors 114 and 115 detect the passage of the game ball, the normal symbol display is started on the normal symbol display 33, and after a predetermined time has elapsed, the normal symbol change display is stopped. .

  When the normal symbol is stopped and displayed with a predetermined symbol, the blade members (so-called normal electric accessories) provided on the left and right sides of the start port 25 are changed from the closed state to the open state, and the game ball is placed in the start port 25. Becomes easier to enter. In addition, when a predetermined time has elapsed after the blade member is opened, the blade member is closed to make it difficult for the game ball to enter the start opening 25. As described above, a game in which a normal symbol is displayed in a variable manner and then stopped and the open / closed state of the blade member varies depending on the result is referred to as a “normal symbol game”.

  Similarly to the special symbol variation display, when a game ball passes through the passing gates 54a and 54b during the normal symbol variation display, the passing gate is displayed until the normal symbol in the variation display is stopped and displayed. The execution (start) of the normal symbol variation display based on the passing of the game ball to 54a and 54b is suspended. After that, when the normal symbol that has been variably displayed is stopped and displayed, the variably displayed normal symbol that has been suspended is started.

  The big prize opening 39 is provided with a shutter 40 that can be opened and closed on the front side (front side). The shutter 40 is driven so that a special symbol is stopped and displayed on the special symbol indicator 35 as a special symbol and the game state is shifted to the jackpot gaming state so that the game ball can be easily received. As a result, the special winning opening 39 is in an open state (first state) where the game ball can be easily received.

  On the other hand, the special winning opening 39 provided on the back side (rear) of the shutter 40 has an area (not shown) having a count sensor 104 (see FIG. 5), and a predetermined number of game balls (for example, 10) or the shutter 40 is driven to the open state until a predetermined time (for example, 30 seconds) elapses. When a condition for winning a predetermined number of game balls in the grand prize opening 39 or elapse of a predetermined time is satisfied in the open state, the shutter 40 is driven so as to be in a closed state in which it is difficult to accept the game balls. . As a result, the special winning opening 39 is in a closed state in which it is difficult to accept a game ball (second state). It should be noted that from the open state (first state) in which the grand prize opening 39 is easy to accept game balls to the closed state (second state) in which the grand prize opening 39 is difficult to accept game balls. This game is called a round game. Accordingly, the shutter 40 is opened during the round game and is closed between the round games. A round game is counted as the number of rounds such as “1” round and “2” round. For example, the first round game may be referred to as the first round and the second round as the second round.

  Subsequently, the shutter 40 driven from the open state to the closed state (second state) is driven to the open state again after a predetermined interval time has elapsed. That is, when a predetermined time elapses after the shutter 40 is closed, it is possible to continue to the next round game. A game from the first round game until the end of the (final) round game that cannot continue to the next round game is called a special game.

  During execution of the special game, the number of rounds from the first round to the last round game (maximum number of continuous rounds) varies depending on the special symbols that are stopped and displayed. For example, in the present embodiment, when the number symbol stopped and displayed on the special symbol display 35 is “64”, the maximum number of continuous rounds is 15 and the number symbol stopped and displayed on the special symbol display 35 is In the case of “21”, the maximum number of continuous rounds is 15 rounds, and when the number symbol stopped and displayed on the special symbol display 35 is “50”, the maximum number of continuous rounds is two. The maximum number of continuous rounds is not limited to 2 rounds or 15 rounds. For example, the maximum number of continuous rounds is selected from “1” to “15” rounds by lottery by a round number lottery means (main control circuit 60 including the main CPU 66 (see FIG. 5)). Also good.

  In addition, when game balls win or pass through predetermined areas in the general winning ports 56a to 56d and the big winning port 39, the number of game balls set in advance according to the type of each winning port is the upper plate. 20 or lower tray 22 is paid out.

  When it is determined that a winning is made at the start opening 25 described above, a predetermined number of game balls are paid out to the upper plate 20 or the lower plate 22 according to the type of each winning port.

  In the present embodiment, the liquid crystal display device has been described as an example of the production means, but the present invention is not limited to this. The production means is an image production means such as a plasma display, a rear projection display, a CRT display, a light emission production means such as a lamp, a sound production means such as a speaker, or a movable production means such as a movable accessory. Also good.

[Electric configuration of gaming machine]
A control circuit of the pachinko gaming machine 10 in the present embodiment will be described with reference to FIG. FIG. 5 is a block diagram showing a control circuit of the pachinko gaming machine 10 in the present embodiment.

  As shown in FIG. 5, the main control circuit 60 as game control means includes a main CPU 66 as a control means, a main ROM (read only memory) 68, and a main RAM (read / write memory) 70 as an example of storage means. ing. The main control circuit 60 controls the progress of the game.

  The main CPU 66 includes a register and a reset terminal 66a. The main CPU 66 is connected to a main ROM 68, a main RAM 70, and the like, and has a function of executing various processes according to a program stored in the main ROM 68. Further, when the reset terminal 66a of the main CPU 66 receives a reset signal, the system is reset. Thus, the main CPU 66 is an example of game control means for controlling the progress of the game.

  In the main ROM 68, a program for controlling the operation of the pachinko gaming machine 10 by the main CPU 66 is stored, and in addition, various tables referred to when making a big hit determination by random number lottery are also stored. .

  The main RAM 70 has a function of storing various flags and variable values as a temporary storage area of the main CPU 66. Specific examples of data stored in the main RAM 70 include the following.

  The main RAM 70 has a control status flag, a jackpot determination random number counter, an initial value random number counter, a jackpot symbol determination random number counter, a reach random number counter, a production condition selection random number counter, a big prize opening number counter, and a big prize winning prize. Counter, waiting time timer, winning prize opening time timer, data indicating the number of reserved balls regarding special symbols, data indicating the number of reserved balls regarding normal symbols, command data for supplying commands to the sub-control circuit 200 described later, various Variables are positioned.

  The control state flag indicates the control state of the special symbol game. The jackpot determining random number counter is for determining the jackpot of a special symbol. The initial value random number counter is a counter for preventing an illegal act using a sensory device or the like by changing a period in which the value indicated by the jackpot determination random number counter becomes a predetermined value (for example, a value that is a big hit). The jackpot symbol determination random number counter is for determining a special symbol to be stopped when a special symbol jackpot is determined. The reach random number counter is used to determine whether or not to execute the reach pattern. The production condition selection random number counter is for determining a production variation pattern. These counters are stored and updated so that the main CPU 66 sequentially increases “1”, and various functions of the main CPU 66 are executed by extracting random numbers from the counters at a predetermined timing. In the present embodiment, such a random number counter is provided, and the main CPU 66 stores and updates the random number counter so as to increase “1” according to a program. You may comprise so that an apparatus like a generator may be provided.

  The waiting time timer is for synchronizing processing executed in the main control circuit 60 and the sub control circuit 200. The special prize opening time timer is for measuring the time for driving the shutter 40 and opening the special prize opening 39. Note that the timer in this embodiment is stored and updated in the main RAM 70 so as to be subtracted by the predetermined cycle at a predetermined cycle. However, the present invention is not limited to this, and the CPU itself may include a timer. .

  The big prize opening number-of-times counter indicates the number of times the big prize opening is opened (so-called round number) in the big hit gaming state. The grand prize winning prize counter indicates the number of game balls that have won the big winning prize during one round and passed through the count sensor 104. Furthermore, the data indicating the number of reserved balls related to the special symbol, when the game ball wins the start opening 25, but when the special symbol variable display cannot be executed, the start of the special symbol game is held, but is held. Indicates the number of suspensions of the special symbol game. Furthermore, the data indicating the number of reserved balls related to the normal symbol holds the start of the normal symbol game when the game ball passes through the passing gates 54a and 54b but the normal symbol variation display cannot be executed. It shows the number of times the normal symbol game is held. Thus, the main RAM 70 is an example of a storage unit that stores data based on games.

  The main control circuit 60 supplies commands to a clock pulse generation circuit 62 that generates a clock pulse of a predetermined frequency, an initial reset circuit 64 that generates a reset signal when the power is turned on, and a sub control circuit 200 described later. For this purpose, a serial communication IC 72 is provided. The clock pulse generation circuit 62, the initial reset circuit 64, and the serial communication IC 72 are connected to the main CPU 66. The clock pulse generation circuit 62 generates a clock pulse every predetermined cycle (for example, 2 milliseconds) in order to execute a system timer interrupt process to be described later.

  The initial reset circuit 64 includes a watchdog timer, and transmits a reset signal to the reset terminal 66a of the main CPU 66 when the watchdog timer detects the passage of a predetermined time. The initial reset circuit 64 clears the watchdog timer by receiving a predetermined control signal from the main CPU 66.

  The serial communication IC 72 is connected to the main CPU 66, the sub control circuit 200, and the payout / launch control circuit 126, and includes a sub control communication buffer 72a and a payout / fire control circuit buffer 72b.

  Various devices are connected to the main control circuit 60. For example, as shown in FIG. 5, the count sensor 104, the general winning ball sensors 106, 108, 110, 112, the passing ball sensors 114, 115, A start winning ball sensor 116, an ordinary electric accessory solenoid 118, a large winning opening solenoid 120, and a backup clear switch 124 are connected.

  The count sensor 104 is provided in a predetermined area in the special winning opening 39. The count sensor 104 supplies a predetermined detection signal to the main control circuit 60 when the game ball passes through the general area at the special winning opening 39.

  The general winning ball sensors 106, 108, 110, and 112 are provided in the general winning ports 56a to 56d, respectively. The general winning ball sensors 106, 108, 110, and 112 supply a predetermined detection signal to the main control circuit 60 when the game balls pass through the general winning ports 56 a to 56 d.

  The passing ball sensors 114 and 115 are provided at the passing gates 54a and 54b, respectively. The passing ball sensors 114 and 115 supply a predetermined detection signal to the main control circuit 60 when the game balls pass through the passing gates 54a and 54b, respectively.

  The start winning ball sensor 116 is provided at the start port 25. The start winning ball sensor 116 supplies a predetermined detection signal to the main control circuit 60 when a game ball passes through the start port 25.

  The ordinary electric accessory solenoid 118 is connected to a blade member provided in the start port 25 via a link member (not shown), and the blade member is in an open state or in accordance with a drive signal supplied from the main CPU 66. Closed.

  The big prize opening solenoid 120 is connected to the shutter 40 shown in FIG. 4, and drives the shutter 40 in accordance with a drive signal supplied from the main CPU 66 to make the big prize opening 39 open or closed.

  The backup clear switch 124 is built in the pachinko gaming machine 10 and has a function of clearing backup data in the event of a power interruption or the like in accordance with the operation of the game hall manager. For example, the data in the main RAM 70 is initialized by operating at power-on.

  The main control circuit 60 is connected to a payout / launch control circuit 126. The payout / launch control circuit 126 is connected to a payout device 128 that pays out game balls, a launch device 130 that fires game balls, and a card unit 150.

  The payout / launch control circuit 126 receives a prize ball control command supplied from the main control circuit 60 and a lending ball control signal supplied from the card unit 150, and transmits a predetermined signal to the payout device 128. The payout device 128 is controlled to pay out the game ball. Further, the payout / launch control circuit 126 performs a control of launching a game ball by supplying a launch signal to the launch device 130.

  In addition, the launching device 130 includes a device for launching a game ball such as the launching solenoid and the touch sensor described above. When the firing handle 26 is gripped by the player and is rotated in the clockwise direction, electric power is supplied to the firing solenoid according to the rotational angle, and the game ball stored in the upper plate 20 is launched. The game board 14 is sequentially fired by the solenoid.

  Further, a lamp 74 is connected to the main control circuit 60. The main control circuit 60 supplies a lamp (LED) control signal to the lamp 74. The lamp 74 includes incandescent bulbs, LEDs, and the like. Specifically, the special symbol holding lamps 34a to 34d, the normal symbol holding lamps 50a to 50d, the special symbol indicator 35 (7 segment LED), and the normal symbol indicator 33. (Display lamp).

  On the other hand, the sub-control circuit 200 is connected to the serial communication IC 72. The sub-control circuit 200 performs display control in the liquid crystal display device 32, control related to sound generated from the speaker 46, control of the lamp 132, and the like according to various commands supplied from the main control circuit 60. Note that the lamp 132 includes an incandescent lamp, an LED, or the like, specifically, a decorative lamp (not shown) that displays light and dark on the game board 14.

  In the present embodiment, the command is supplied from the main control circuit 60 to the sub control circuit 200 and the signal cannot be supplied from the sub control circuit 200 to the main control circuit 60. The present invention is not limited to this, and there is no problem even if it is configured such that a signal can be transmitted from the sub control circuit 200 to the main control circuit 60.

  The sub control circuit 200 which is an effect control means performs control related to the sound generated from the sub CPU 206, the program ROM 208, the work RAM 210, the display control circuit 250 as display control means for performing display control in the liquid crystal display device 32, and the speaker 46. A voice control circuit 230 is provided, and a drive circuit 240 is provided that performs control related to the lamp and the movable accessory. The sub-control circuit 200 executes an effect according to the progress of the game in accordance with a command from the main control circuit 60.

  A program ROM 208, a work RAM 210, and the like are connected to the sub CPU 206. The sub CPU 206 has a function of executing various processes according to the program stored in the program ROM 208. In particular, the sub CPU 206 controls the sub control circuit 200 in accordance with various commands supplied from the main control circuit 60. The sub CPU 206 functions as various means described later.

  The program ROM 208 stores a program for controlling the game effects of the pachinko gaming machine 10 by the sub CPU 206 and various tables.

  The program ROM 208 stores a plurality of types of effect patterns. This effect pattern relates to the progress of the effect display that is executed in association with the variable symbol display. In addition, the program ROM 208 stores effect patterns during execution of a plurality of types of special games. The effect pattern during execution of the special game relates to the progress of the effect display executed in relation to the round game in the special game.

  In the present embodiment, the main control circuit 60 uses the main ROM 68 and the sub control circuit 200 uses the program ROM 208 as storage means for storing programs, tables, etc., but the present invention is not limited to this. As long as it is a storage medium readable by a computer equipped with a storage medium such as a hard disk device, a CD-ROM and a DVD-ROM, and a ROM cartridge, a program, a table, and the like are recorded. May be. Of course, the main ROM 68 may be used as an alternative to the program ROM 208. Even if these programs are not recorded in advance, they may be downloaded after the power is turned on and recorded in the main RAM 70 in the main control circuit 60, the work RAM 210 in the sub control circuit 200, and the like. . Furthermore, each program may be recorded on a separate storage medium.

  The work RAM 210 has a function of storing various flags and variable values as a temporary storage area of the sub CPU 206. For example, various variables such as a timer variable for controlling the reach effect time and an effect display selection random number counter for selecting an effect pattern are positioned.

  In this embodiment, the main RAM 70 is used as the temporary storage area of the main CPU 66 and the work RAM 210 is used as the temporary storage area of the sub CPU 206. However, the present invention is not limited to this, and any readable / writable storage medium may be used.

  The drive circuit 240 includes a drive circuit 242 and a decoration data ROM 244 and is connected to the sub CPU 206. The light emission of the lamp 132 is controlled via the drive circuit.

  The display control circuit 250 includes an image data processor (hereinafter referred to as VDP) 212, an image data ROM 216 that stores various image data, a D / A converter 218 that converts image data as an image signal, and a reset signal when the power is turned on. The initial reset circuit 220 is generated.

  The VDP 212 described above is connected to the sub CPU 206, the image data ROM 216, the D / A converter 218, and the initial reset circuit 220.

  The VDP 212 includes a so-called sprite circuit, a screen circuit, a pallet circuit, and the like, and is a device that can perform various processes for causing the liquid crystal display device 32 to display an image. That is, the VDP 212 performs display control for the liquid crystal display device 32. Further, the VDP 212 includes a storage medium (for example, a video RAM) as a buffer for displaying an image on the display area 32 a of the liquid crystal display device 32. By storing the image data in a predetermined storage area of the storage medium, an image is displayed on the display area 32a of the liquid crystal display device 32 at a predetermined timing.

  Various image data such as background image data and effect image data are separately stored in the image data ROM 216. Of course, related image data indicating a related image is also stored.

  The VDP 212 reads various image data such as background image data and effect image data from the image data ROM 216 in response to an image display command supplied from the sub CPU 206, and generates image data to be displayed on the liquid crystal display device 32. The VDP 212 superimposes the generated image data in order from the image data located at the rear, stores the image data in a buffer, and supplies the data to the D / A converter 218 at a predetermined timing. The D / A converter 218 converts the image data as an image signal and supplies the image signal to the liquid crystal display device 32, thereby causing the liquid crystal display device 32 to display an image.

  The audio control circuit 230 includes a sound source IC 232 that controls audio, an audio data ROM 234 that stores various audio data, and an amplifier 236 (hereinafter referred to as AMP) for amplifying audio signals.

  The sound source IC 232 is connected to the sub CPU 206, the initial reset circuit 220, the audio data ROM 234, and the AMP 236. The sound source IC 232 controls sound generated from the speaker 46.

[Main processing]
The main process will be described below with reference to FIGS.

  In step S602, watch dog timer initial setting processing is performed. In this processing, the main CPU 66 performs processing for initial setting of the watchdog timer. If this process ends, the process moves to a step S604.

  In step S604, chip select initial setting processing is performed. In this processing, the main CPU 66 performs processing for initial setting of chip select. If this process ends, the process moves to a step S606.

  In step S606, the clear data (H01) is set in the watchdog output data. In this process, the main CPU 66 performs a process of setting clear data (H01) in the watchdog output data. If this process ends, the process moves to a step S608.

  In step S608, processing for setting a wait timer (500 ms) is performed. In this process, the main CPU 66 performs a process of setting a wait timer (500 ms) in the main RAM 70. If this process ends, the process moves to a step S610.

  In step S610, processing for inverting the watchdog output data is performed. In this process, the main CPU 66 performs a process of inverting the watchdog output data. If this process ends, the process moves to a step S612.

  In step S612, a process for outputting watchdog output data is performed. In this processing, the main CPU 66 performs processing for outputting watchdog output data to the initial reset circuit 64. If this process ends, the process moves to a step S614.

  In step S614, the main CPU 66 determines whether 500 ms has elapsed. If 500 ms has elapsed, the process proceeds to step S616, and if 500 ms has not elapsed, the process proceeds to step S610.

  In step S616, the main CPU 66 determines whether or not the output level of the power interruption detection signal is H (high). If the output level of the power interruption detection signal is H (high), step S618 is performed. If the output level of the power interruption detection signal is not H, step S616 is executed again. By the way, in this embodiment, a power supply board (not shown) for generating various power supply voltages and driving the pachinko gaming machine 10 is provided, and this power supply board has a predetermined power supply generated on the power supply board. A power supply monitoring circuit is provided that monitors the voltage (33V) and outputs a power interruption detection signal that changes the output voltage depending on whether or not the power supply voltage falls below a predetermined threshold (about 28V). The power interruption detection signal has an output level of H (high) in a normal operation state, but when the drop of the power supply voltage is detected, the output level becomes L (low). The main CPU 66 monitors the input state of the power failure detection signal. When the output level of the power failure detection signal detects a fall from H to L, the main CPU 66 interrupts the process being executed and performs a power failure process described later. Run.

  In step S618, processing for permitting RAM access is performed. In this process, the main CPU 66 performs a process for permitting access to the main RAM 70. If this process ends, the process moves to a step S620.

  In step S620, the main CPU 66 determines whether there is an input of the backup clear switch. If there is an input from the backup clear switch, the process proceeds to step S702. If there is no input from the backup clear switch, the process proceeds to step S622.

  In step S622, the main CPU 66 determines whether or not there is a power interruption detection flag. If there is a power interruption detection flag, the process proceeds to step S624. If there is no power interruption detection flag, the process proceeds to step S702.

  In step S624, work area damage check processing is performed. In this process, the main CPU 66 performs a process of checking whether or not the work area is damaged by checking whether or not the data in the work area of the main RAM 70 is the same as before the power is turned off. . More specifically, the main CPU 66 generates check data based on the work area data, compares it with the check data generated in the power-off process, and determines that there is no damage if they match. When this process ends, the process moves to a step S626.

  In step S626, the main CPU 66 determines whether the work area is damaged. If the work area is damaged, the process proceeds to step S702. If there is no work area damage, the process proceeds to step S628.

  In step S628, processing for returning the stack pointer is performed. In this process, the main CPU 66 performs a process for returning the stack pointer. If this process ends, the process moves to a step S630.

  In step S630, a switch input buffer clear process is performed. In this process, the main CPU 66 performs a process of clearing the switch input buffer. If this process ends, the process moves to a step S632.

  In step S632, a CTC operation setting process is performed. In this process, the main CPU 66 performs a process of setting an operation of a CTC (Counter Timer Circuit). If this process ends, the process moves to a step S634.

  In step S634, an SIO operation setting process is performed. In this processing, the main CPU 66 performs processing for setting SIO (serial input / output) operation. When this process ends, the process moves to a step S636.

  In step S636, an LED output port refresh process is performed. In this process, the main CPU 66 performs a process of refreshing the LED output port for outputting a signal to the lamp 74. If this process ends, the process moves to a step S640.

  In step S640, a power interruption return command transmission process is performed. In this process, the main CPU 66 performs a process of transmitting a power interruption return command. When this process ends, the process moves to a step S642.

  In step S642, the main CPU 66 determines whether or not the interrupt flag is in a prohibited state. The main CPU 66 moves the process to step S646 when the interrupt flag is in the prohibited state, and moves the process to step S644 when the interrupt flag is not in the prohibited state.

  In step S644, an interrupt permission process is performed. In this process, the main CPU 66 performs a process for permitting a timer interrupt process (see FIG. 8). When this process ends, the process moves to a step S646.

  In step S646, a process for restoring the registers in the stack area is performed. More specifically, in this process, the main CPU 66 restores, for example, a register (program counter) indicating a program address that was being executed when the power was turned off. By returning the program counter, it is possible to return to the process before power-off. When this process ends, the program address before the execution of the power-off process described later is restored.

  In step S702, a process for initializing the stack pointer is performed. In this processing, the main CPU 66 performs processing for initializing the stack pointer. If this process ends, the process moves to a step S704.

  In step S704, processing for setting the start address of the work area is performed. In this process, the main CPU 66 performs a process of setting the start address of the work area of the main RAM 70 in the register. If this process ends, the process moves to a step S706.

  In step S706, clear data is set. In this processing, the main CPU 66 performs processing for setting clear data. If this process ends, the process moves to a step S708.

  In step S708, the main CPU 66 determines whether the data at the set address has been cleared. If the data at the set address is cleared, the process proceeds to step S710. If not cleared, the process proceeds to step S702.

  In step S710, processing for setting the next address after the cleared address is performed. In this processing, the main CPU 66 performs processing for setting the next address after the cleared address. If this process ends, the process moves to a step S712.

  In step S712, the main CPU 66 determines whether it is the work area final address. If it is the work area final address, the main CPU 66 moves the process to step S714, and if it is not the work area final address, the main CPU 66 moves the process to step S706. As described above, the recording contents of the main RAM 70 are initialized by executing the processing from step S704 to step S712.

  In step S714, data relating to special symbols is initialized. In this processing, the main CPU 66 performs processing for initializing data relating to special symbols. If this process ends, the process moves to a step S716.

  In step S716, a CTC operation setting process is performed. In this process, the main CPU 66 performs a process for setting a CTC operation. When this process ends, the process moves to a step S718.

  In step S718, an SIO operation setting process is performed. In this process, the main CPU 66 performs a process for setting an SIO operation. If this process ends, the process moves to a step S720.

  In step S720, an LED output port refresh process is performed. In this process, the main CPU 66 performs a process of refreshing the LED output port. If this process ends, the process moves to a step S724.

  In step S724, initialization command transmission processing is performed. In this process, the main CPU 66 performs a process of transmitting an initialization command. When this process ends, the process moves to a step S726.

  In step S726, an interrupt permission process is performed. In this process, the main CPU 66 performs a process for permitting the execution of the timer interrupt process (see FIG. 8). If this process ends, the process moves to a step S728.

  In step S728, an interrupt prohibition process is performed. In this process, the main CPU 66 performs a process for prohibiting the interrupt process. That is, the interrupt signal from the clock pulse generation circuit is masked, and in this state, execution of the timer interrupt process based on the input of the interrupt signal is awaited. If this process ends, the process moves to a step S730.

  In step S730, initial value random number update processing is performed. In this process, the main CPU 66 performs a process of updating the initial value random number counter. When this process ends, the process moves to a step S732.

  In step S732, an interrupt permission process is performed. In this process, the main CPU 66 performs a process for permitting the interrupt process. If this process ends, the process moves to a step S734.

  In step S734, the main CPU 66 determines whether or not the system timer monitoring timer value is 3 or more. In this process, the main CPU 66 refers to the system timer monitoring timer value stored in the main RAM 70. If the system timer monitoring timer value is 3 or more, the main CPU 66 moves the process to step S736, and the system timer monitoring timer value is If it is less than 3, the process proceeds to step S728. As described above, step S734 executed by the main CPU 66 is an example of an interrupt number determination process for determining whether or not the count value stored in the storage means is equal to or greater than a predetermined determination value in the first process. is there.

  In step S736, a process of subtracting 3 from the value of the system timer is performed. In this process, the main CPU 66 performs a process of subtracting 3 from the system timer monitoring timer stored in the main RAM 70. If this process ends, the process moves to a step S738. In this embodiment, the value of the system timer monitoring timer is subtracted by 3. However, the present invention is not limited to this. For example, the determination value used for determining the value of the system timer in step S734 and the like Any value may be used as long as the same value is subtracted. In this way, in step S736 executed by the main CPU 66, the execution of the second process triggers the subtraction of the same value as the determination value from the count value stored in the storage means, and the value after subtraction is used as the count value. It is an example of the interruption frequency subtraction process memorize | stored in a memory | storage means.

  In step S738, timer update processing is performed. In this process, the main CPU 66 performs a timer update process stored in a predetermined area of the main RAM 70. The timer update process will be described later. If this process ends, the process moves to a step S740. The main CPU 66 manages the progress of the game based on the timer value updated by this process. Thus, the main RAM 70 is an example of a time measuring unit that manages the progress of the game. As described above, the main CPU 66 is an example of game control means for executing timer update processing for updating the clock means in the second processing.

  In step S740, a special symbol control process is performed. As will be described in detail later, in this process, the main CPU 66 stores the jackpot determination random number value and the jackpot symbol determination random number value extracted according to the detection signal from the start winning ball sensor 116, and is stored in the main ROM 68. The jackpot winning table is referred to, whether or not the jackpot lottery is won is determined, and the determination result is stored in the main RAM 70. In the present embodiment, the high probability state is a so-called probability variation state, and is a state in which the probability of winning the big hit lottery is improved from the low probability state. If this process ends, the process moves to a step S742.

  In step S742, normal symbol control processing is performed. In this process, the main CPU 66 performs a normal symbol control process. In this process, the main CPU 66 refers to the normal symbol winning table stored in the main ROM 68 based on the random number value extracted according to the detection signals from the passing ball sensors 114 and 115, and determines whether the normal symbol lottery is won. It is determined whether or not, and the result of determination is stored in the main RAM 70. If the normal symbol lottery is won, the blade member of the start port 25 (see FIG. 4) is in an open state for a predetermined period, so that the game ball is easy to enter. If this process ends, the process moves to a step S744.

  In step S744, a symbol display device control process is performed. In this process, the main CPU 66 determines the special symbol display 35 and the normal symbol display 33 according to the result of the special symbol control process stored in the main RAM 70 in step S740 and step S742 and the result of the normal symbol control process. Then, processing for updating and storing data for driving the round number display 51 in the main RAM 70 is performed. In addition, based on the updated data, a drive signal is output to each LED in the port output process of step S750. When this process ends, the process moves to a step S746.

  In step S746, game information data generation processing is performed. In this process, the main CPU 66 performs a process of generating game information data for outputting a signal to the base computer or the hall computer and storing it in the main RAM 70. When this process ends, the process moves to a step S748.

  In step S748, symbol reservation number data generation processing is performed. In this process, the main CPU 66 detects detection signals from the start winning ball sensor 116 and the passing ball sensors 114 and 115 detected in the switch input process (FIG. 8, step S810) in the system timer interrupt process to be described later, To drive the special symbol holding lamps 34a to 34d and the normal symbol holding lamps 50a to 50d based on the update result of the holding number data stored in the main RAM 70 that is updated in accordance with the execution of the variable display of the symbols and the normal symbols. The control signal is stored in the main RAM 70. If this process ends, the process moves to a step S750.

  In step S750, port output processing is performed. In this process, the main CPU 66 performs a process of outputting a control signal stored in the main RAM 70 to each port in the above steps. Specifically, an LED power source (common signal) for turning on the LED and a solenoid power source for driving the solenoid are supplied to the lamp 74. If this process ends, the process moves to a step S752.

  In step S752, a winning mouth associated command control process is performed. In this process, the main CPU 66 performs a process of controlling a winning mouth associated command. The winning opening related command control processing will be described later. If this process ends, the process moves to a step S754.

  In step S754, a storage / game state command control process is performed. Memory / game state command control processing is performed. In this process, the main CPU 66 determines whether a certain change flag or a short-time state flag is set in a predetermined area of the main RAM 70, and determines that a certain change flag or a short-time state flag is set. Processing for generating a command and transmitting it to the sub-control circuit 200 is performed. The storage / game state command control process will be described later. When this process ends, the process moves to a step S756. In the present embodiment, the short time state is a state in which the fluctuation display time of the normal symbol and the special symbol is shorter than that in the normal game, and many special symbols are fluctuated in a short time while the decrease in possession is suppressed. However, the present invention is not limited to this. For example, the winning probability of the normal symbol lottery may be higher than the normal state.

  In step S756, command output control processing is performed. In this processing, the main CPU 66 performs processing for controlling command output. The command output control process will be described later. If this process ends, the process moves to a step S758. As described above, step S756 executed by the main CPU 66 is an example of command transmission processing of the game control means executed in the second processing.

  In step S758, a payout process is performed. In this process, the main CPU 66 checks whether or not a game ball has won a prize winning port 39, a starting port 25, and general winning ports 56a to 56d, and if there is a winning, a payout request command corresponding to each. Is sent to the payout control CPU of the payout / firing control circuit 126. The payout process will be described later. If this process ends, the process moves to a step S728. As described above, the main processing (step S602 to step S758) executed by the main CPU 66 is a routine for controlling the progress of the game. After the power supply is started and the predetermined power-on processing is performed, the main processing is performed. It is an example of a main routine that repeatedly executes the first process. As described above, steps S736 to S758 of the main process executed by the main CPU 66 are executed in the main routine, and the count value is determined to be greater than or equal to a predetermined determination value in the interrupt count determination process. In addition, it is an example of a second process for performing a process of shifting to the first process after performing a predetermined process. In addition, in this way, the main control circuit 60 executes a main routine and game control means for executing a command transmission process for transmitting an effect command that can specify an effect time to the effect control circuit according to the progress of the game. It is an example of a main control circuit provided.

[Timer interrupt processing]
Even when the main CPU 66 is executing the main process, the main CPU 66 may interrupt the main process and execute the system timer interrupt process. The following system timer interrupt process is executed in response to a clock pulse generated from the clock pulse generation circuit 62 every predetermined period (for example, 2 milliseconds). The timer interrupt process will be described below with reference to FIG.

  In step S802, a register saving process is performed. In this process, the main CPU 66 performs a process for saving the register. If this process ends, the process moves to a step S804.

  In step S804, the system timer monitoring timer value is incremented by one. In this process, the main CPU 66 performs a process of adding 1 to the value of the system timer monitoring timer stored in the main RAM 70. The system timer monitoring timer is a monitoring timer for executing a predetermined process (such as a special symbol control process) on the condition that the timer interrupt process is started a predetermined number of times (three times). If this process ends, the process moves to a step S806. As described above, step S804 executed by the main CPU 66 is an example of the interrupt count process that is executed in the interrupt routine, counts the number of times the interrupt routine is executed, and stores it as a count value in the storage means. .

  In step S806, a process of setting clear data (01H) to watchdog output data is performed. In this process, the main CPU 66 sets clear data (01H) in the watchdog output data. Further, the main CPU 66 transmits a control signal based on the watchdog output data to the initial reset circuit 64. The initial reset circuit 64 clears the watchdog timer based on the received control signal.

  In the watchdog timer provided in the initial reset circuit 64, when a predetermined time (3100 ms in the present embodiment) determined by the capacitance of the capacitor connected to the initial reset circuit 64 elapses after being cleared, the initial reset circuit. A system reset signal is output from 64 to the main CPU 66. When the system reset signal from the initial reset circuit 64 is input to the reset terminal 66a, the main CPU 66 enters a system reset state. If this process ends, the process moves to a step S808.

  In step S808, random number update processing is performed. In this process, the main CPU 66 performs a process of updating the random number. For example, the main CPU 66 updates random numbers such as a jackpot determination random number counter, a jackpot symbol determination random number counter, and a normal symbol determination random number counter. Note that the jackpot determination random number counter and the jackpot symbol determination random number counter are not fair if the update timing of the counter value is indefinite. Therefore, a fixed timing every 2 ms to ensure this. I am trying to update with. If this process ends, the process moves to a step S810.

  In step S810, switch input processing is performed. In this process, the main CPU 66 performs a process for determining whether or not there is an input to the switch. For example, the main CPU 66 receives the general winnings provided in the count sensor 104 (see FIG. 5) provided in the big winning opening 39 (see FIG. 4) and the general winning openings 56a, 56b, 56c, 56d (see FIG. 4). The ball sensors 106, 108, 110, 112 (see FIG. 5), the passing ball sensors 114, 115 (see FIG. 5) provided in the passage gates 54a, 54b (see FIG. 4), and the start port 25 (see FIG. 4). ) To receive a detection signal from the start winning ball sensor 116 (see FIG. 5), it is determined whether each switch has detected a game ball. When the main CPU 66 determines that it has been detected, the main CPU 66 updates the start opening prize detection check counter, the large winning opening prize ball counter, the general winning opening prize ball counter, the starting opening prize ball counter, and the like.

  In the switch input process, the input state of each switch is detected as described above, and in order to prevent erroneous detection due to chattering, the game ball passes when two consecutive inputs are detected. It is determined. As for the detection timing of this input state, if the interval is long, there is a possibility that it cannot be detected correctly when a plurality of game balls pass in a short time. If this process ends, the process moves to a step S812.

  In step S812, a register restoration process is performed. In this process, the main CPU 66 performs a process for returning the register to return to the process before the interrupt process. When this process is finished, this subroutine is finished. As described above, the timer interrupt process (steps S802 to S812) executed by the main CPU 66 is an example of an interrupt routine that is executed with an interrupt condition generated every predetermined time as a trigger during execution of the main routine. is there.

  In the present embodiment, an example of processing has been described. However, the present invention is not limited to this, and processing related to command transmission is performed after a predetermined number of times of system timer interruption processing. As long as it is executed in the timer interrupt process, other processes in the main process (for example, special symbol control process) may be executed in the system timer interrupt process.

[Power-off processing]
With reference to FIG. 9, the power-off process executed when the main CPU 66 detects the fall of the power-off detection signal from H to L will be described below.

  In step S902, register (AF) saving processing is performed. In this processing, the main CPU 66 performs processing for saving registers. When this process ends, the process moves to a step S904.

  In step S904, the main CPU 66 determines whether the power interruption detection signal is L or not. If the power interruption detection signal is L (low), the process proceeds to step S908. If the power interruption detection signal is not L, the process proceeds to step S906. In this process, it is possible to determine whether or not the fall of the power interruption detection signal is due to chattering by detecting the state of the power interruption detection signal.

  In step S906, a register restoration process is performed. In this process, the main CPU 66 performs a process for restoring the register. When this process ends, the process returns to the process before the interruption of this process.

  In step S908, register saving processing is performed. In this processing, the main CPU 66 performs processing for saving registers. When this process ends, the process moves to a step S910.

  In step S910, a process of reflecting the interrupt state on the interrupt flag is performed. In this process, the main CPU 66 performs a process of reflecting the interrupt state on the interrupt flag. If this process ends, the process moves to a step S912.

  In step S912, processing for saving the stack pointer is performed. In this processing, the main CPU 66 performs processing for saving the stack pointer. If this process ends, the process moves to a step S914.

  In step S914, work area damage check data generation processing is performed. In this process, the main CPU 66 performs a work area damage check data generation process. If this process ends, the process moves to a step S916.

  In step S916, a process for setting a power interruption detection flag is performed. In this processing, the main CPU 66 performs processing for setting a power interruption detection flag. If this process ends, the process moves to a step S918.

  In step S918, RAM access prohibition processing is performed. In this processing, the main CPU 66 performs processing for prohibiting RAM access. When this process is finished, this subroutine is finished.

[Special symbol control processing]
The subroutine executed in step S740 in FIG. 7 will be described with reference to FIG. In FIG. 10, the numerical values drawn from step S72 to step S81 indicate control state flags corresponding to those steps, and one step corresponding to the numerical value is determined according to the numerical value of the control state flag. Will be executed and the special symbol game will proceed.

  First, as shown in FIG. 10, a process for loading a control state flag is executed (step S71). In this process, the main CPU 66 reads the control state flag. If this process ends, the process moves to a step S72.

  Note that in steps S72 to S81, which will be described later, the main CPU 66 determines whether to execute various processes in each step based on the value of the control state flag, as will be described later. This control state flag indicates the game state of the special symbol game, and enables one of the processes from step S72 to step S81 to be executed. In addition, the main CPU 66 executes processing in each step at a predetermined timing determined in accordance with a waiting time timer set for each step. Before reaching the predetermined timing, the process ends without executing the process in each step, and another subroutine is executed. Of course, timer interrupt processing (see FIG. 8) is also executed at a predetermined cycle.

  In step S72, a special symbol memory check process is executed. Details will be described later with reference to FIG. If this process ends, the process moves to a step S73.

  In step S73, a special symbol variation time management process is executed. In this process, the main CPU 66 sets the value (02) indicating the special symbol display time management to the control state flag when the control state flag is the value (01) indicating the special symbol variation time management. In addition to setting, a symbol stop command is set as effect control command data to be described later, and a waiting time after determination (for example, 1 second) is set in the waiting time timer. That is, it is set so that the process of step S74 is executed after the waiting time after determination has elapsed. Further, the symbol stop command set as described above is output as a command in a command output control process described later in FIG. If this process ends, the process moves to a step S74.

  In step S74, a special symbol display time management process is executed. In this process, the main CPU 66 determines whether or not it is a big hit when the control state flag is a value (02) indicating special symbol display time management and the waiting time after determination has elapsed. The main CPU 66 sets a value (03) indicating the jackpot start interval management in the control state flag in the case of a jackpot, sets a jackpot start command as effect control command data to be described later, and sets a time corresponding to the jackpot start interval. (For example, 10 seconds) is set in the waiting time timer. That is, after the time corresponding to the jackpot start interval elapses, the setting of step S75 is performed. The jackpot start command set as described above is output as a command in a command output control process described later in FIG. On the other hand, the main CPU 66 sets a value (07) indicating the end of the special symbol game when it is not a big hit. That is, it is set to execute the process of step S81. If this process ends, the process moves to a step S75.

  In step S75, a jackpot start interval management process is executed. In this processing, the main CPU 66 has a value (03) indicating that the control status flag indicates the jackpot start interval management, and when the time corresponding to the jackpot start interval has elapsed, the main winning prize port 39 read from the main ROM 68 is displayed. Is stored in the main RAM 70. Then, in the process of step S750 in FIG. 7, the main CPU 66 reads data for opening the big prize opening 39 stored in the main RAM 70, and sends a signal indicating that the big prize opening 39 is opened to the big prize opening solenoid. 120. As described above, the main CPU 66 and the like perform opening / closing control of the special winning opening 39. That is, one round game in which a predetermined advantageous gaming state (a gaming state from the open state where the big winning opening 39 easily accepts the game ball to the closed state where the big winning opening 39 hardly accepts the game ball) is provided a plurality of times. A special game that may be repeated is executed.

  Further, the main CPU 66 sets a value (04) indicating that the big prize opening is being opened in the control state flag, and sets the upper opening limit time (for example, 30 seconds) in the big prize opening time timer. That is, it is set to execute the process of step S78. Further, the main CPU 66 starts measuring the execution time of the special game using the special game execution time timer in the main RAM 70. Further, the main CPU 66 sets a special winning opening opening command (for example, A201) indicating “Round 1” in the main RAM 70 as effect control command data. The special winning opening release command set in this way is transmitted as a command in a command output control process described later in FIG. If this process ends, the process moves to a step S77.

  In step S77, a waiting time management process before reopening the big winning opening is executed. In this process, the main CPU 66 sets the special prize opening number counter when the control status flag is a value (05) indicating the waiting time management before the big prize opening reopening and the time corresponding to the interval between rounds has elapsed. The memory is updated so that “1” is increased. The main CPU 66 sets a value (04) indicating that the special winning opening is open in the control state flag. The main CPU 66 sets an opening upper limit time (for example, 30 seconds) in the big prize opening time timer. That is, it is set to execute the process of step S78. Further, the main CPU 66 refers to the special winning opening opening number counter and produces a corresponding special opening opening command (for example, A208 corresponding to “round 8” if the special winning opening release number counter is 8). It is set in the main RAM 70 as control command data. The special winning opening release command set in this way is transmitted as a command in a command output control process described later in FIG. As a result, the sub-control circuit 200 displays a round game corresponding to the round to be executed. If this process ends, the process moves to a step S78.

  In step S78, a special winning opening opening process is executed. In this process, when the control status flag is a value (04) indicating that the big prize opening is being opened, the main CPU 66 has passed the condition that the big prize opening prize counter is “10” or more, and the opening upper limit time ( It is determined whether or not any of the conditions that the big prize opening time timer is “0” is satisfied. The main CPU 66 updates a variable positioned in the main RAM 70 in order to close the special winning opening 39 when any of the conditions is satisfied. Then, it is determined whether or not a condition that the special winning opening opening number counter is equal to or greater than the maximum winning opening opening number (the final round) is satisfied. When this condition is satisfied, the main CPU 66 sets a value (06) indicating the jackpot end interval in the control state flag, and produces a jackpot end command (for example, a promiscuous jackpot A300, a normal jackpot A301, etc.), which will be described later. Set as data, and set the time corresponding to the jackpot end interval in the waiting time timer. That is, after the time corresponding to the jackpot end interval elapses, the setting of step S80 is performed. The jackpot end command set as described above is transmitted in a command output control process described later with reference to FIG. On the other hand, when this condition is not satisfied, the main CPU 66 sets a value (05) indicating the waiting time management before reopening the big winning opening to the control state flag. Further, the main CPU 66 sets a time corresponding to the interval between rounds in the waiting time timer. In other words, after the time corresponding to the interval between rounds has elapsed, the setting of step S77 is performed. Further, the main CPU 66 sets an inter-round interval display command (for example, A100) in the main RAM 70 as effect control command data. The inter-round interval display command set in this way is transmitted in a command output control process to be described later with reference to FIG. If this process ends, the process moves to a step S80.

  In step S80, jackpot end interval processing is executed. In this process, the main CPU 66 sets the value (07) indicating the end of the special symbol game to the control state when the control state flag is a value (06) indicating the jackpot end interval and the time corresponding to the jackpot end interval has elapsed. Set to flag. That is, it is set to execute the process of step S81. Further, the main CPU 66 sets a probability change flag in a predetermined area of the main RAM 70 when the probability change state is entered. Further, when the main CPU 66 enters the time reduction state, the main CPU 66 sets a time reduction state flag in a predetermined area of the main RAM 70 and sets 100 as the number of time reductions. Also, the main CPU 66 sets a gaming state command (for example, a high probability state (probability big hit time) B001, a low probability state (normal big hit time) B002, etc.) in the main RAM 70 as gaming state command data. The gaming state command set in this way is transmitted in a storage / gaming state command control process which will be described later with reference to FIG. As a result, the sub control circuit 200 can recognize the gaming state. If this process ends, the process moves to a step S81. In the present embodiment, 100 is set as the number of time reductions, but the present invention is not limited to this, and for example, the number of time reductions may be other time reductions such as 150, 200, and 300. In addition, when the special symbol display time management process in step S74 determines that the number of time reductions is not a big hit, the time reduction state flag is cleared when the time reduction state is "1". The game state command (for example, low probability state B000) is set in the main RAM 70 as game state command data.

  In step S81, a special symbol game end process is executed. In this process, when the control state flag is a value (07) indicating the end of the special symbol game, the main CPU 66 stores data indicating the number of reserved balls related to the special symbol (starting storage information) to be decreased by “1”. Update. Then, the main CPU 66 updates the special symbol storage area in order to perform the next fluctuation display. The main CPU 66 sets a value (00) indicating a special symbol storage check. That is, it is set to execute the process of step S72. When this process is finished, this subroutine is finished.

  As described above, the special symbol game is executed by setting the control state flag. Specifically, as shown in FIG. 10, the main CPU 66 sets the control status flag to “00”, “01”, “02”, and “ By setting “08” in order, the processing of step S72, step S73, step S74, and step S81 shown in FIG. 10 is executed at a predetermined timing. Further, the main CPU 66 sets the control state flag in the order of “00”, “01”, “02”, “03” when the result of the big hit determination is a big hit when it is not the big hit gaming state, The processing of step S72, step S73, step S74, and step S75 shown in FIG. 10 is executed at a predetermined timing, and control to the big hit gaming state is executed. Furthermore, the main CPU 66 sets the control state flag in the order of “04” and “05” when the control to the big hit gaming state is executed, thereby performing the processing of steps S78 and S77 shown in FIG. Is executed at a predetermined timing, and a special game is executed. If the special game (bonus game state) end condition (special game end condition, jackpot game end condition) is satisfied, “04”, “05”, “06”, “07” should be set in order. Thus, the processing from step S78 to step S81 shown in FIG. 10 is executed at a predetermined timing, and the special game is ended. In the present embodiment, the special game end condition is that the round game of the maximum number of continuous rounds (in the present embodiment, “2” round or “15” round) ends.

[Special symbol memory check processing]
The subroutine executed in step S72 in FIG. 10 will be described with reference to FIG.

  First, as shown in FIG. 11, the main CPU 66 determines whether or not the control state flag is a value (00) indicating a special symbol storage check (step S101). If it is determined that the control state flag is a value indicating a special symbol memory check, the process proceeds to step S102. If it is determined that the control state flag is not a value indicating a special symbol memory check, this subroutine is terminated. To do.

  In step S102, the main CPU 66 determines whether or not the number of reserved symbols related to the special symbol is “0”. If it is determined that the data indicating the number of reserved balls regarding the special symbol is “0”, the process proceeds to step S103, and if it is determined that the data indicating the number of reserved balls is not “0”, the process proceeds to step S104. Move processing.

  In step S103, a demonstration display process is executed. In this process, the main CPU 66 outputs a demonstration display command (for example, D000 at the low probability, D001 at the high probability, D002 at the low probability, D002 at the low probability) in order to cause the sub control circuit 200 to perform the demonstration display. Is set in the main RAM 70. The demo display command set in this way is output as a command output control process to be described later with reference to FIG. As a result, the display of the demonstration screen is executed in the sub control circuit 200. When this process is finished, this subroutine is finished.

  In step S104, a process of setting a value (01) indicating special symbol variation time management as a control state flag is executed. In this process, the main CPU 66 stores a value indicating special symbol variation time management in the control state flag. If this process ends, the process moves to a step S105.

  In step S105, a jackpot determination process is executed. In this process, the main CPU 66 reads the jackpot determination table corresponding to the current gaming state (low probability, high probability (probability change)), and reads the jackpot determination random number value extracted at the start winning. The jackpot determination value assigned to the determined jackpot determination table is compared, and it is determined whether or not the jackpot gaming state is advantageous to the player based on whether or not they match.

  In step S106, a symbol determination process is executed. In this process, if the determination result in step S105 is a big win, the main CPU 66 extracts the jackpot symbol random number extracted at the time of starting winning, and based on the jackpot symbol random value, the special symbol indicator 35 A special symbol (specific symbol) to be stopped and displayed is determined, and data indicating the special symbol is stored in a predetermined area of the main RAM 70. On the other hand, if the determination result in step S105 is lost, the special symbol to be stopped and displayed on the special symbol display 35 is determined as a symbol other than the specific symbol, and data indicating the special symbol is stored in a predetermined area of the main RAM 70. .

  Further, the main CPU 66 sets a stop symbol designation command (for example, 81xx (lower data changes depending on the stop symbol)) corresponding to the determined special symbol in the main RAM 70 as effect control command data. The stop symbol designation command set in this way is transmitted in a command output control process described later in FIG. If this process ends, the process moves to a step S109.

  In step S109, a variation pattern determination process is executed. In this process, the main CPU 66 extracts a rendering condition selection random value. The main CPU 66 selects a variation pattern to be executed from a variation pattern table stored in the main ROM 68 based on the special symbol determined in step S106.

  Then, the main CPU 66 sets a variation pattern designation command (for example, 82xx (subordinate data changes according to the variation pattern)) corresponding to the selected variation pattern in the main RAM 70 as effect control command data. The variation pattern designation command set in this way is transmitted in a command output control process to be described later with reference to FIG. If this process ends, the process moves to a step S110.

  In step S110, a process of setting the variation time corresponding to the selected variation pattern in the waiting time timer is executed. In this process, the main CPU 66 reads the fluctuation time corresponding to the fluctuation pattern selected by the process of step S109 from the table, and stores a value indicating the fluctuation time in the waiting time timer. Then, a process of clearing the storage area in which the jackpot determination random number value used for the current variation display is stored is executed (step S111). When this process is finished, this subroutine is finished.

[Winning mouth related command control processing]
The winning opening related command control process will be described below with reference to FIG.

  In step S1002, a count switch abnormal winning counter loading process is performed. In this processing, the main CPU 66 performs processing for loading the count switch abnormal winning counter. More specifically, the main CPU 66 loads a count switch abnormal winning counter value that is incremented by the detection value of the count switch when the attacker is not opened (when the big winning opening 39 is in the second state). When this process ends, the process moves to a step S1004.

  In step S1004, the main CPU 66 determines whether or not the counter value is greater than zero. If the main CPU 66 determines that the count switch abnormal winning counter value is greater than 0, the process proceeds to step S1006. If the main CPU 66 does not determine that the count switch abnormal winning counter value is greater than 0, the process proceeds to step S1012. Move.

  In step S1006, a process of decrementing the count switch abnormal winning counter value by -1 is performed. In this process, the main CPU 66 performs a process of decrementing the value of the count switch abnormal winning counter. If this process ends, the process moves to a step S1008.

  In step S1008, counter abnormal winning command data load (D000) processing is performed. In this processing, the main CPU 66 performs processing for loading the counter abnormal winning command data (D000) and setting it in the command output data storage area. If this process ends, the process moves to a step S1010.

  In step S1010, one command transmission processing is performed. In this processing, the main CPU 66 performs processing for sending one command. One command transmission processing will be described later. If this process ends, the process moves to a step S1012.

  In step S1012, a start opening winning detection check counter loading process is performed. In this process, the main CPU 66 performs a process of loading the start opening winning detection check counter. More specifically, the main CPU 66 loads a start opening prize detection check counter that is incremented every time the start winning ball sensor 116 is detected (see step S810 in FIG. 8). If this process ends, the process moves to a step S1014.

  In step S1014, the main CPU 66 determines whether or not the counter value is greater than zero. If it is determined that the start opening prize detection check counter value is greater than 0, the process proceeds to step S1016. If it is not determined that the start opening prize detection check counter value is greater than 0, this subroutine ends.

  In step S1016, a process of decrementing the value of the start opening prize detection check counter by -1 is performed. In this process, the main CPU 66 performs a process of decrementing the value of the start opening winning detection check counter by -1. If this process ends, the process moves to a step S1018.

  In step S1018, a start winning command data load (D100) process is performed. In this process, the main CPU 66 performs a process of loading the start winning command data (D100) and setting it in the command output data storage area. If this process ends, the process moves to a step S1020.

  In step S1020, one command transmission processing is performed. In this processing, the main CPU 66 performs processing for sending one command. One command transmission processing will be described later. When this process is finished, this subroutine is finished.

[Memory / Game state command control processing]
The storage / game state command control process will be described below with reference to FIG.

  In step S1102, gaming state command data load processing is performed. In this process, the main CPU 66 loads gaming state command data (B000 = low probability state B001 = high probability state B002 = low probability time short state) related to the gaming state when the gaming state changes and sets it in the command output data storage area. Process. If this process ends, the process moves to a step S1104.

  In step S1104, the main CPU 66 determines whether or not a gaming state command is set in the command output data storage area. When the gaming state command is set in step S1102, the main CPU 66 proceeds to step S1106, and when the gaming state command is not set, the main CPU 66 proceeds to step S1108.

  In step S1106, one command transmission processing is performed. In this processing, the main CPU 66 performs processing for sending one command. One command transmission processing will be described later. If this process ends, the process moves to a step S1108.

  In step S1108, special symbol storage display command data load processing is performed. In this process, the main CPU 66 performs a process of loading special symbol memory display command data that accompanies a change in the reserved ball data relating to the special symbol. More specifically, the main CPU 66 loads E000 as special symbol storage display command data when the number of reserved balls has changed from 1 to 0. The main CPU 66 loads E001 as the special symbol memory display command data when the number of held balls is changed from two to zero. The main CPU 66 loads E002 as the special symbol memory display command data when the number of held balls changes from three to one. The main CPU 66 loads E003 as the special symbol memory display command data when the number of held balls has changed from four to two. The main CPU 66 loads E004 as the special symbol memory display command data when the number of held balls has changed from three to four. When these command data are loaded, they are set in the command output data storage area. If this process ends, the process moves to a step S1110.

  In step S1110, the main CPU 66 determines whether or not a special memory display command has been set in the command output data storage area. If the special memory display command is set, the process proceeds to step S1112. If the special memory display command is not set, this subroutine is terminated.

  In step S1112, one command transmission processing is performed. In this processing, the main CPU 66 performs processing for sending one command. One command transmission processing will be described later. When this process is finished, this subroutine is finished.

[Command output control processing]
The command output control process will be described below with reference to FIG.

  In step S1202, effect control command data loading processing is performed. In this process, the main CPU 66 performs a process of loading the effect control command data set based on the result of the special symbol control process (see FIGS. 10 and 11) and setting it in the command output data storage area. More specifically, the main CPU 66 sets the following command data in the command output data storage area as the game progresses. The main CPU 66 sets D000 at the low probability, D001 at the high probability, D002 at the low probability, and D002 at the low probability short time at the start of the demonstration display (step S103 in FIG. 11). Further, the main CPU 66 transmits a variation pattern designation command at the start of special symbol variation (step S109 in FIG. 11), and further transmits a stop symbol designation command in the next main processing. At this time, the main CPU 66 stores the command output data as 82xx as the variation pattern designation command (lower data changes according to the variation pattern) and 81xx as the stop symbol designation command (lower data changes according to the stop symbol). Set to area. The main CPU 66 sets 8000 in the command output data storage area as a symbol stop command when the special symbol fluctuation is stopped (step S73 in FIG. 10). The main CPU 66 sets A000 in the command output data storage area as a jackpot start command when the jackpot starts (step S74 in FIG. 10). The main CPU 66 sets A2xx (subordinate data changes according to the round) in the command output data storage area as a command for opening the big prize opening at the start of opening the big prize opening (steps S75 and S77 in FIG. 10). When starting the interval between rounds (step S78 in FIG. 10), the main CPU 66 sets A100 as the interval display command between rounds in the command output data storage area. At the end of the jackpot (step S78 in FIG. 10), the main CPU 66 sets A300 (probable variation jackpot) and A301 (normal jackpot) as the jackpot end commands in the command output data storage area. If this process ends, the process moves to a step S1204.

  In step S1204, the main CPU 66 determines whether or not an effect control command has been set. If the effect control command is set, the process proceeds to step S1206. If the effect control command is not set, this subroutine is terminated.

  In step S1206, one command transmission processing is performed. In this processing, the main CPU 66 performs processing for sending one command. One command transmission processing will be described later. When this process is finished, this subroutine is finished.

[1 command transmission processing]
With reference to FIG. 15, the following describes the one-command transmission process executed in steps S1010 and S1020 in FIG. 12, S1106 and S1112 in FIG. 13, and step S1206 in FIG.

  In step S1302, processing for setting the upper byte of the command set in the command output data storage area is performed. In this process, the main CPU 66 performs a process of setting the upper byte of the command set in the command output data storage area in the sub-control communication buffer 72a of the serial communication IC 72. If this process ends, the process moves to a step S1304.

  In step S1304, command 1 byte transmission processing is performed. In this process, the main CPU 66 performs a process of sending a command byte. The command 1 byte transmission process will be described later. If this process ends, the process moves to a step S1306.

  In step S1306, processing for setting the lower byte of the command set in the command output data storage area is performed. In this process, the main CPU 66 performs a process of setting the lower byte of the command set in the command output data storage area in the sub-control communication buffer 72a of the serial communication IC 72. If this process ends, the process moves to a step S1308.

  In step S1308, command 1 byte transmission processing is performed. In this process, the main CPU 66 performs a process of sending a command byte. The command 1 byte transmission process will be described later. If this process ends, the process moves to a step S1310.

  In step S1310, the clear data is set in the command output data storage area. In this process, the main CPU 66 performs a process of setting clear data in the command output data storage area. When this process is finished, this subroutine is finished.

[Command 1 byte transmission processing]
The command 1-byte transmission process executed in steps S1304 and S1310 in FIG. 15 will be described below with reference to FIG.

  In step S1402, a process of setting 60 to the loop counter is performed. In this process, the main CPU 66 performs a process of setting 60 to the value of the loop counter stored in the main RAM 70. If this process ends, the process moves to a step S1404. In this embodiment, in order to make the period slightly longer than 300 μs, 60 is set as the value of the loop counter. However, the present invention is not limited to this, and is set when communication failure occurs. Any count can be used that prevents transmission of the command.

  In step S1404, SIO status port (output buffer) check processing is performed. In this process, the main CPU 66 performs a process of checking the SIO status port (output buffer). In this embodiment, the 1-byte command transmission time is about 298.9 μs. Until the command transmission is completed, the data exists in the output buffer (sub control communication buffer 72a) of the serial communication IC 72. As long as data exists, transmission of command data of the next byte is kept waiting. When this process ends, the process moves to a step S1406.

  In step S1406, the main CPU 66 determines whether or not the output buffer (sub control communication buffer 72a) of the serial communication IC 72 is 1. If the output buffer is 1, the process proceeds to step S1408. If the output buffer is not 1, the process proceeds to step S1412.

  In step S1408, a process of decrementing the loop counter value by -1 is performed. In this process, the main CPU 66 performs a process of decrementing the value of the loop counter by -1. If this process ends, the process moves to a step S1410.

  In step S1410, the main CPU 66 determines whether or not the value of the loop counter is zero. If the value of the loop counter is 0, it is determined that the communication is defective, and command transmission is not performed. This subroutine is terminated. If the loop counter is not 0, the process proceeds to step S1404.

  In step S1412, a process of outputting the set command to the serial communication IC is performed. In this process, the main CPU 66 performs a process of outputting the set command to the serial communication IC 72. When this process is finished, this subroutine is finished.

[Payout process]
The payout process will be described below with reference to FIGS. 17 and 18.

  In step S1502, a special winning opening prize ball counter loading process is performed. In this process, the main CPU 66 performs a process of loading the big prize winning ball counter. If this process ends, the process moves to a step S1504.

  In step S1504, the main CPU 66 determines whether the counter value is greater than zero. If it is determined that the big prize mouth ball counter value is greater than 0 (if there is a win), the process proceeds to step S1514. The process moves to S1506.

  In step S1506, a general winning opening prize ball counter loading process is performed. In this process, the main CPU 66 performs a process of loading the general winning opening prize ball counter. If this process ends, the process moves to a step S1508.

  In step S1508, the main CPU 66 determines whether the counter value is greater than zero. If it is determined that the general winning mouth prize ball counter value is greater than 0 (when there is a winning prize), the process proceeds to step S1516. The process moves to S1510.

  In step S1510, start opening prize ball counter loading processing is performed. In this process, the main CPU 66 performs a process of loading the start opening prize counter. If this process ends, the process moves to a step S1512.

  In step S1512, the main CPU 66 determines whether or not the counter value is greater than zero. If it is determined that the starting opening prize ball counter value is greater than 0 (there is a win), the process proceeds to step S1518. If it is not determined that the starting opening prize ball counter value is greater than 0, this subroutine is executed. finish.

  In step S1514, processing for setting a prize ball command (8F) is performed. In this process, the main CPU 66 performs a process of setting a prize ball command (8F) indicating 15 prize balls. When this process ends, the process moves to a step S1602 (see FIG. 18).

  In step S1516, processing for setting a prize ball command (8A) is performed. In this process, the main CPU 66 performs a process of setting a prize ball command (8A) indicating 10 prize balls. If this process ends, the process moves to a step S1602.

  In step S1518, processing for setting a prize ball command (83) is performed. In this process, the main CPU 66 performs a process of setting a prize ball command (83) indicating prize balls for three balls. If this process ends, the process moves to a step S1602.

  In step S1602, SIO status port (output buffer) check processing is performed. In this process, the main CPU 66 performs a process of checking the SIO status port (the output buffer of the serial communication IC 72). If this process ends, the process moves to a step S1604.

  In step S1604, the main CPU 66 determines whether or not the output buffer is 1. If it is determined that the output buffer (payout / launch control circuit buffer 72b) of the serial communication IC 72 is 1, this subroutine is terminated. If it is determined that the output buffer is not 1, the process proceeds to step S1606. Move.

  In step S1606, the loaded prize ball counter value is decremented by one. In this process, the main CPU 66 performs a process of decrementing the loaded prize ball counter value by -1. If this process ends, the process moves to a step S1608.

  In step S1608, processing for outputting the set prize ball command to the serial communication IC is performed. In this process, the main CPU 66 performs a process of outputting the set prize ball command to the serial communication IC 72. When this process is finished, this subroutine is finished.

[Sub control main processing]
The sub control main process will be described with reference to FIG.

  In step S1710, initialization processing is performed. In this process, the sub CPU 206 reads the activation program from the program ROM 208 and initializes and sets a flag stored in the work RAM 210 in response to power-on. If this process ends, the process moves to a step S1720.

  In step S1720, random number update processing is performed. In this process, the sub CPU 206 performs a process of updating the random number stored in the work RAM 210. If this process ends, the process moves to a step S1730.

  In step S1730, command analysis control processing is performed. In this processing, the sub CPU 206 performs processing for analyzing commands received from the main control circuit 60 and stored in the reception buffer of the work RAM 210. If this process ends, the process moves to a step S1740.

  In step S1740, display control processing is performed. In this processing, the sub CPU 206 transmits data for display on the liquid crystal display device 32 to the display control circuit 250. The display control circuit 250 transmits data for display to the display control circuit 250. In the display control circuit 250, the VDP 212 reads various image data such as background image data and effect image data from the image data ROM 216 based on data for displaying the effect image from the sub CPU 206, and superimposes them. The image is displayed on the display area 32 a of the liquid crystal display device 32. If this process ends, the process moves to a step S1750. Thus, the liquid crystal display device 32 is an example of an effect unit that performs a predetermined effect according to the progress of the game.

  In step S1750, sound control processing is performed. In this process, the sub CPU 206 transmits data for outputting sound to the sound control circuit 230. The sound control circuit 230 reads various sound data such as music data, sound effect data, and voice data from the sound data ROM 234 based on the data for outputting the sound from the sub CPU 206, superimposes the sound, and uses the AMP 236. Amplified and output from the speaker 46. If this process ends, the process moves to a step S1760. Thus, the speaker 46 is an example of an effect unit that performs a predetermined effect according to the progress of the game.

  In step S1760, lamp control processing is performed. In this process, the sub CPU 206 transmits data for lighting the lamp to the drive circuit 240. The drive circuit 240 reads various lighting pattern data from the decoration data ROM 244 based on the data for lighting the lamp from the sub CPU 206 and lights the lamp 132. If this process ends, the process moves to a step S1720. The various effects in steps S1740 to S1760 are managed by the timer stored in the work RAM 210. As described above, the lamp 132 is an example of an effect unit that performs a predetermined effect according to the progress of the game. As described above, the sub control circuit 200 is an example of an effect control circuit that executes effect control processing for controlling the effect means. As described above, steps S1740 to S1760 executed by the sub CPU 206 are an example of a process for controlling the production means based on the management of the production time by the production time management process.

[Timer interrupt processing]
Further, the sub CPU 206 may interrupt the sub control main process and execute the timer interrupt process even when the sub control main process is being executed. The sub CPU 206 generates a clock pulse every predetermined period, and executes the following timer interrupt process in response to this. The timer interrupt process will be described with reference to FIG.

  In step S2010, a process for saving each register is performed. In this processing, the sub CPU 206 performs processing for saving values used in the program being executed stored in each register (storage area) of the work RAM 210. If this process ends, the process moves to a step S2020.

  In step S2020, timer update processing is performed. In this process, the sub CPU 206 performs a process of updating the timer value stored in the work RAM 210. If this process ends, the process moves to a step S2030. As described above, step S2020 executed by the sub CPU 206 is an example of an effect time management process that uniquely manages the effect time corresponding to the effect command in accordance with the effect command transmitted from the main control circuit.

  In step S2030, command reception processing is performed. In this processing, the sub CPU 206 performs processing for storing the command transmitted from the main control circuit 60 in the reception buffer. If this process ends, the process moves to a step S2040.

  In step S2040, processing for restoring each register is performed. In this processing, the sub CPU 206 performs processing for returning the value saved in step S2010 to each register. When this process is finished, this subroutine is finished.

[Comparison with conventional control]
The control of the present invention and conventional gaming machine will be described in comparison with FIG. FIG. 21A is a time chart showing control performed in a conventional gaming machine. FIG. 21B is a time chart showing the control in the present embodiment. In both FIG. 21 (A) and FIG. 21 (B), the number written above indicates the interrupt counter value (system timer monitoring timer value), and the upward arrow indicates the determination timing of the interrupt count. Yes.

  In the present embodiment, the initial value random number update process (step S730) for updating the initial value random number counter after performing the power recovery process in the main process (FIGS. 6 and 7), and a system timer described later. A process of determining the monitoring timer value (step S734) and (these correspond to the first process) are looped.

  As shown in FIG. 21 (A) and FIG. 21 (B), the interrupt timer detects the passage of 2 ms during the execution of the main process (first process) in both the conventional control and the control of this embodiment. In this case, timer interrupt processing (see FIG. 8) is executed on condition that the interrupt is not prohibited (mask state). In the mask state, a timer interrupt process is executed when the mask is released.

  In the timer interrupt process, the system timer monitoring timer (step S804) is incremented, and the jackpot determination random number counter value, the jackpot symbol determination random number counter value, and the regular symbol determination random number that need to be operated every 2 ms. A random number update process (step S808) for updating the counter value and a switch input process (step S810) for detecting a game ball that has passed through each winning opening or gate are executed.

  Note that the timer interrupt process must be ensured to be executed every 2 ms, and if there are too many processes in the timer interrupt process, the above interrupt generation condition is satisfied during the execution of the timer interrupt process. As a result, there is a possibility that a situation such as multiple interrupts or interruptions may be caused. Therefore, in the timer interruption process, it is preferable that the number of processes is as small as possible. For this reason, processing that does not require execution security every 2 ms, although there is a need for time management, is executed during the second processing described later. Thereby, the control of the game can be given a certain amount of time, and the accuracy of time management is ensured.

  Further, as shown in FIGS. 21A and 21B, in the conventional control and the control of this embodiment, the system timer monitoring timer value is determined in the determination of the system timer monitoring timer value (step S734). If it is “3” or more, that is, since the timer interrupt process is performed every 2 ms, it is determined whether or not 6 ms has elapsed.

  When the system timer monitoring timer value indicates “3” or more, it is determined that 6 ms has elapsed, and each process (step S736 to step S758 second process) described in FIG. 7 is executed, Thereafter, the first process is executed.

  In the second process, first, a process of subtracting “3” from the system timer monitoring timer value is performed (step S736). As shown in FIG. 21 (A), in the conventional control, the system timer monitoring timer value is cleared. However, if the system timer monitoring timer value indicates “4” or more after being cleared, The execution of the second process every 6 ms cannot be secured.

  As described above, when the system timer monitoring timer value is cleared, even if it takes 8 ms from the previous second processing to the current processing, the next execution of the second processing is performed after 6 ms has elapsed. Therefore, the number of executions of the second process per 6 ms does not satisfy “1”, and the accuracy of the progress of the game is not ensured.

  Further, in the pachinko gaming machine, the main control circuit 60 and the sub control circuit 200 perform interrupt processing (see, for example, FIGS. 8 and 20). Further, in the pachinko gaming machine, the movement of data from the main control circuit 60 to the sub control circuit 200 moves only in one direction from the main control circuit 60 to the sub control circuit 200. For this reason, in the conventional control, there is a possibility that the processing timing of the main control circuit 60 and the sub control circuit 200 may be shifted, and when the gaming machine is executed for a long period of time, this processing timing shift is accumulated. Therefore, there is a possibility that the progress of the game will be abnormal.

  On the other hand, in the present embodiment, as shown in FIG. 21B, the system timer monitoring timer value is “4” or more because the system timer monitoring timer value is subtracted by “3”. In this case, even if it took 8 ms from the previous second process to the current process at that time, the next second process is executed after 4 ms. When viewed over a time span, the execution of the second process once per 6 ms is ensured, so that the accuracy of the progress of the game can be ensured.

[Another embodiment]
Since the interrupt processing executed every 2 ms is within 2 ms and it is necessary to perform the main processing, it must be assembled with a considerable time margin. A part of the subroutine in the process 2 may be executed by the interrupt process. The command output control process and the game information data generation process for outputting the test signal are preferably performed in the second process.

  As described above, according to the present embodiment, it is determined in the interrupt count determination process that the count value (for example, the value of the interrupt count counter) is greater than or equal to a predetermined determination value (for example, “3”). In this case, after the predetermined process is performed, the second process for shifting to the first process is performed, and the count value stored in the storage unit (for example, the main RAM 70) is triggered by the execution of the second process. Subtraction of the same value as the determination value (for example, “3”) from the value of the interrupt counter (for example, the value of the interrupt number counter), and the interrupt number subtraction process for storing the value after the subtraction as a count value in the storage means (for example, the main RAM 70) And do. Thus, for example, when the count value (for example, the value of the interrupt count counter) is “4”, the count value (for example, the interrupt count counter of the interrupt count counter) is subtracted from the determination value (for example, “3”). When the value) becomes “1” and the interrupt routine is executed twice more, the second process is executed. As described above, the second process is always executed once every fixed time, so that the accuracy of the game control can be ensured even in a long-time operation, and a highly reliable gaming machine can be provided. it can.

  Further, according to the present embodiment, in the second process that is always executed once per fixed time, the timer update process for updating the clock means (for example, timer) is executed. For this reason, even in a long-time operation, the timekeeping means is updated once per fixed time, so that time management can be performed almost accurately. In this way, the accuracy of game control can be ensured even during long-time operation, and a highly reliable gaming machine can be provided.

  Further, according to the present embodiment, in the second process that is always executed once per fixed time, an effect command that can specify the effect time from the main control circuit 60 to the effect control circuit (sub control circuit 200) is provided. Executes the command transmission process to be transmitted. Further, the effect control circuit (sub control circuit 200) independently manages the effect time corresponding to the effect command in accordance with the effect command, and effect means (for example, the liquid crystal display device 32) is managed based on the effect time management. And the speaker 46) are controlled. For this reason, even in a long-time operation, an effect command can be transmitted once per fixed time. Therefore, the processing timing of the main control circuit 60 and the effect control circuit (sub control circuit 200) coincide with each other. Since the process in the control circuit 60 and the process in the effect control circuit (sub-control circuit 200) are synchronized, there is no contradiction in the operation, so that the control load is reduced and the accuracy of the operation can be ensured. In this way, the accuracy of game control can be ensured even during long-time operation, and a highly reliable gaming machine can be provided.

  Although the embodiments of the present invention have been described above, they are merely illustrative examples and do not particularly limit the present invention. That is, the present invention mainly comprises a game control means for controlling the progress of a game and a storage means for storing data based on the game, wherein the game control means is a routine for controlling the progress of the game, After a predetermined power-on process is performed after power supply starts, a main routine that repeatedly executes a predetermined first process and an interrupt condition that occurs every predetermined time during the execution of the main routine are triggered. An interrupt routine executed as the interrupt routine, the interrupt routine counting process executed in the interrupt routine, counting the number of times the interrupt routine has been executed, and storing it in the storage means as a count value, and the first process The interrupt count determination process for determining whether or not the count value stored in the storage means is greater than or equal to a predetermined determination value, and the interrupt count determination process executed in the main routine. When it is determined that the count value is equal to or greater than the predetermined determination value, the second process for performing the process of shifting to the first process after performing the predetermined process and the execution of the second process are performed. As a trigger, a game is performed in which a determination value is subtracted from a count value stored in the storage means, and an interrupt count subtraction process is performed in which the value after the subtraction is stored in the storage means as a count value. Although it is a machine, the specific configuration of the game control means, the storage means, etc. can be changed as appropriate.

  It should be noted that the effects described in the embodiments of the present invention only list the most preferable effects resulting from the present invention, and the effects of the present invention are limited to those described in the embodiments of the present invention. is not.

1 is a perspective view showing an overview of a pachinko gaming machine according to an embodiment of the present invention. It is a disassembled perspective view which shows the general view of the pachinko game machine in one Embodiment of this invention. It is a front view which shows the lamp unit of the pachinko game machine in one Embodiment of this invention. 1 is a front view showing an overview of a game board of a pachinko gaming machine according to an embodiment of the present invention. It is a block diagram which shows the main control circuit and sub control circuit which are comprised in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is a flowchart which shows the control processing performed in the pachinko game machine of one Embodiment of this invention. It is explanatory drawing which shows the subject of the control performed with the conventional game machine.

Explanation of symbols

10 Pachinko machine 32 Liquid crystal display device 60 Main control circuit 66 Main CPU
70 Main RAM
200 Sub-control circuit

Claims (3)

Game control means for controlling the progress of the game;
Storage means for storing data based on the game,
The game control means includes
A routine for controlling the progress of the game, and after performing a predetermined power-on process after the start of power supply, a main routine for repeatedly executing a predetermined first process;
An interrupt routine that is executed in response to an interrupt condition that occurs every predetermined time during the execution of the main routine;
An interrupt count process that is executed in the interrupt routine, counts the number of times the interrupt routine is executed, and stores it as a count value in the storage means;
In the first process, an interrupt number determination process for determining whether or not the count value stored in the storage means is equal to or greater than a predetermined determination value;
A process that is executed in the main routine and performs a process of shifting to the first process after performing a predetermined process when it is determined in the interrupt number determination process that the count value is greater than or equal to a predetermined determination value. 2 processing,
With the execution of the second process as an opportunity, a subtraction of the same value as the determination value from the count value stored in the storage means, and an interrupt count subtraction process for storing the value after subtraction in the storage means as the count value; A gaming machine characterized by In the gaming machine according to claim 1,
It has timekeeping means to manage the progress of the game,
The gaming machine is characterized in that, in the second process, a timer update process for updating the timing unit is executed. In the gaming machine according to claim 1 or 2,
Production means for performing a predetermined production according to the progress of the game,
An effect control circuit for executing an effect control process for controlling the effect means;
A main control circuit including the game control means for executing a main routine and executing a command transmission process for transmitting an effect command capable of specifying an effect time to the effect control circuit according to the progress of the game;
In the production control process of the production control circuit,
In addition to performing the production time management process for independently managing the production time corresponding to the production command according to the production command transmitted from the main control circuit,
Based on the management of the production time by the production time management process, execute the process of controlling the production means,
The gaming machine, wherein the command transmission process of the game control means is executed in the second process.

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