JP5134797B2 - GaN-based semiconductor device, manufacturing method thereof, and GaN-based semiconductor device - Google Patents

Description

  The present invention relates to a GaN-based semiconductor element used for a semiconductor amplifying element such as a power transistor capable of obtaining a large current, a manufacturing method thereof, and a GaN-based semiconductor device.

  MOS FETs and HEMTs (High Electron Mobility Transistors) that use GaN-based III-V compound semiconductors such as GaN and AlGaN for the channel layer are more operating than MOS FETs and HEMTs that use Si, GaAs, etc. The device has been attracting attention as a device capable of high temperature operation and large current operation with a high withstand voltage and a small on-resistance.

For example, as shown in FIG. 10, the GaN-based semiconductor element has a GaN buffer layer 52, an undoped GaN layer 53, an n ⁺ -type GaN drain layer 54, and an n ⁻ -type GaN layer 5 on a semi-insulating sapphire substrate 51. The p-type GaN channel layer 56 is laminated, and an n-type GaN source layer 57 having a striped ridge shape is formed on the p-type GaN channel layer 56. A source electrode 60 is formed over the entire surface of the ridge shape of the n-type GaN source layer 57 and a part of the surface of the p-type GaN channel layer 56.

On the other hand, the gate electrode 59 is formed on the insulating film 58 laminated on the surface of the p-type GaN channel layer 56, and the drain electrode 61 is formed on the exposed surface of the mesa-etched n ⁺ -type GaN drain layer 54.
JP 2004-260140 A

  However, the conventional GaN-based semiconductor device has the following problems. In the method for manufacturing the GaN-based semiconductor device shown in FIG. 10, after the GaN buffer layer 52 to the n-type GaN source layer 57 are stacked on the sapphire substrate 51, the n-type GaN source layer 57 is formed into a ridge shape by mesa etching. Although it is processed, GaN-based semiconductors are hard and difficult to remove by wet etching, so dry etching by plasma irradiation or the like is usually used.

  When the ridge portion of the n-type GaN source layer 57 is produced by this dry etching, all of the n-type GaN source layer 57 other than the ridge portion must be removed by dry etching, and the p-type GaN channel layer 56 The exposed surface (XXX portion shown in the figure) was damaged.

  As described above, when the surface of the p-type GaN channel layer 56 is damaged, the junction region between the p-type GaN channel layer 56 and the source electrode 60 becomes a Schottky contact, and the contact resistance with the source electrode 60 increases. The current cannot flow through the element. When the damage is applied, the interface state density of the p-type GaN channel layer 56 is increased, and therefore, when a positive voltage is applied to the gate electrode 59, the n-channel is not immediately inverted. Therefore, it takes time to become an inversion distribution, and there is a problem that the on-resistance becomes high and the device cannot be operated at a high speed.

  On the other hand, since GaN has a lattice constant different from that of a growth substrate such as a sapphire substrate, dislocations (lattice defects) extending in the vertical direction from the substrate exist in the GaN-based semiconductor layer grown on the growth substrate. Yes. When this lattice defect increases, it becomes difficult to diffuse the dopant and control it to p-type and n-type. As described above, in the case of an electronic device, the lattice defect has a great influence in terms of pressure resistance and the like, and lowering the dislocation density is important in terms of improving device characteristics.

  The present invention was devised to solve the above-described problem, and can reduce the contact resistance of the channel layer, reduce the on-resistance, and reduce the dislocation density of lattice defects. An object is to provide an element, a manufacturing method thereof, and a GaN-based semiconductor device.

In order to achieve the above object, a GaN-based semiconductor device of the present invention is a GaN-based semiconductor device comprising a channel layer made of a GaN-based semiconductor, and a source layer and a drain layer arranged with the channel layer interposed therebetween. the source layer has a ridge portion formed by the selective growth, the source electrode over the adjacent two ridges sandwiched by the channel layer surface to the two ridge surfaces are formed by the selective growth The main feature is that the selective growth mask used is left on the surface of the channel layer, and a gate electrode is provided on the selective growth mask.

The GaN-based semiconductor device of the present invention is a GaN-based semiconductor element including a channel layer made of a GaN-based semiconductor, and a source layer and a drain layer disposed so as to sandwich the channel layer, and the source layer is selected A source electrode is formed from a channel layer surface sandwiched between two adjacent ridge portions to a surface of the two ridge portions having a ridge portion formed by growth, and used for the selective growth. A main feature is that a GaN-based semiconductor element is provided in which a mask is left on the surface of the channel layer and a gate electrode is provided on the selective growth mask .

The method for manufacturing a GaN-based semiconductor device according to the present invention is a method for manufacturing a GaN-based semiconductor device comprising a channel layer made of a GaN-based semiconductor, and a source layer and a drain layer arranged with the channel layer interposed therebetween. A first step of stacking a selective growth mask on the channel layer; a second step of removing a part of the selective growth mask to form an opening; and a source layer grown on the opening. A third step of forming a ridge portion with the selective growth mask interposed therebetween, a fourth step of removing the selective growth mask by wet etching, and a source electrode on the surface of the channel layer after the removal of the selective growth mask. And a fifth step of forming the part .

  According to the present invention, since the source layer is formed by selective growth and the mask used for selective growth is removed by wet etching, the channel layer surface is formed so that part of the source electrode is in contact with the channel layer. No damage is left on the layer, the contact resistance of the channel layer can be reduced, and the on-resistance can also be reduced. Since the source layer is formed by selective growth, the dislocation density of lattice defects to the source layer can be reduced.

  In addition, the entire selective growth mask is not peeled and removed, but a part is left and the gate electrode is formed thereon, so that it is not necessary to separately stack an insulating film for the gate electrode.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional structure of a GaN-based semiconductor device of the present invention, FIG. 2 is a top view of the GaN-based semiconductor device of FIG. 1 as viewed from above, and the AA cross-section of FIG. It corresponds to. The GaN-based semiconductor element of the present invention uses a III-V group GaN-based semiconductor which is a hexagonal compound semiconductor, and the III-V group GaN-based semiconductor is a quaternary mixed crystal Al _x Ga _y In _z. N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). Although FIG. 1 shows an example of an NPN structure, the present invention can also be applied to a PNP structure.

A GaN buffer layer 2, an undoped GaN layer 3, an n ⁺ -type GaN drain layer 4, an n ⁻ -type GaN layer 5, and a p-type GaN-based channel layer 6 are stacked on the sapphire substrate 1. An n-type GaN source layer 8 having a ridge shape is formed thereon. The n-type GaN source layer 8 has a ridge portion A, a ridge portion B, and two ridge portions. From the top surface to the side surface of the ridge portion A and ridge portion B, the p-type between the ridge portions A and B is further provided. A source electrode 10 is formed over the surface of the GaN-based channel layer 6. A selective growth mask 7 made of an insulating material is formed so as to sandwich the ridge portions A and B, and a gate electrode 9 is formed on the selective growth mask 7.

In addition, a drain electrode 12 is formed in the exposed n ⁺ -type GaN drain layer 4 inside the groove formed by mesa etching, and a p-type GaN-based channel layer is formed so that leakage does not occur by the drain electrode 12. An insulating film 11 is provided from 6 to part of the side surfaces of the n ⁻ -type GaN layer 5 and the n ⁺ -type GaN drain layer 4. As will be described later, the n-type GaN source layer 8 is formed by selective growth, and the selective growth mask 7 used at that time is used as an insulating film for the gate electrode 9.

For the selective growth mask 7, a transparent insulator such as SiO ₂ , Si ₃ N ₄ , ZrO ₂ , Al ₂ O ₃ or the like is used. As the p-type GaN-based channel layer 6, a p-type GaN layer, or a p-type GaN layer stacked on a p-type AlGaN layer is used. Si is used for the n-type dopant, and Mg is used for the p-type dopant.

The n ⁺ -type GaN drain layer 4 is doped with impurity Si so that the carrier concentration becomes 1 × 10 ¹⁸ cm ⁻³ , for example, in order to make an ohmic contact with the drain electrode 12, and the n ⁻ -type GaN layer Reference numeral 5 denotes an intermediate layer provided to lower the energy barrier at the junction interface between the n-type layer and the p-type layer to facilitate current flow, and is doped with impurity Si so as to be 1 × 10 ¹⁷ cm ^−3. Has been. The p-type GaN-based channel layer 6 needs to have a high carrier concentration so that the device is not turned on when no voltage is applied to the gate electrode. For example, the carrier concentration is 4 × 10 ¹⁶ to 1 × 10 ^18. Impurity Mg is doped so as to be cm ⁻³ .

  A multilayer metal film made of TaSi / Au or the like is used for the source electrode 10 and the drain electrode 12, and a multilayer metal film made of Ni / Au or the like is used for the gate electrode.

  By the way, since the growth substrate such as a sapphire substrate and GaN have different lattice constants, the GaN-based semiconductor layer grown on the growth substrate has dislocations (lattice defects) extending vertically from the substrate. Yes. As a method for reducing such dislocations, selective lateral growth (ELO: Epitaxial Lateral Overgrowth) is well known. In the present invention, the selective growth is used.

  By covering the p-type GaN channel layer 6 with a selective growth mask 7 such as a dielectric mask, growth first occurs from the opening of the selective growth mask 7 (selective growth), and then on the selective growth mask 7. In addition, the growth of the growth layer causes crystal growth in the lateral direction.

  Therefore, the selective growth mask 7 requires an opening for crystal growth, and the shape of the n-type GaN source layer 8 formed by selective growth differs depending on the shape of the mask. A pattern example of this selective growth mask is shown in FIG. In FIG. 9, the shaded area represents a selective growth mask.

  In FIG. 9A, the central mask portion 7b is patterned in a stripe shape, and stripe-shaped openings 7a are provided in parallel on both sides thereof. When crystal growth is performed from the opening 7a, the formed epitaxial layer has a shape having two striped ridges.

  FIG. 9B shows a pattern in which openings 7a are provided concentrically around a circular central mask portion 7b. When crystal growth is performed from the opening 7a, the formed epitaxial layer has a shape having a ridge portion connected in a donut shape.

  FIG. 9C shows a pattern in which openings 7a are provided concentrically around a square central mask portion 7b. Therefore, the opening 7a is also a square. When crystal growth is performed from the opening 7a, the formed epitaxial layer has a shape having a ridge portion connected in a square shape.

  FIG. 9D shows a pattern in which openings 7a are provided concentrically around the hexagonal central mask portion 7b. Therefore, the opening 7a is also hexagonal. When crystal growth is performed from the opening 7a, the formed epitaxial layer has a shape having a ridge portion connected in a hexagonal shape.

  In the embodiment of FIG. 1, the circular pattern of FIG. 9B is used as the selective growth mask shape, and the overall shape of the mask is also patterned into a circular shape. As shown in FIG. 2, the n-type GaN source layer 8 is formed into a circular shape by using a selective growth mask in which the entire shape of the selective growth mask 7 is circular and the opening 7a and the central mask portion 7b are formed concentrically. The source electrode 10 and the gate electrode 9 which are formed in a shape and then stacked are also provided in a circular shape.

Next, a method for manufacturing the GaN-based semiconductor device shown in FIGS. As a manufacturing method, an MOCVD method (metal organic chemical vapor deposition method) is mainly used. First, the sapphire substrate 1 is transferred into the MOCVD apparatus, and the GaN buffer layer 2 is grown on the sapphire substrate 1 at a low temperature of 600 to 700 ° C. as shown in FIG. Thereafter, the substrate temperature is raised to 1000 ° C. or higher, and the undoped GaN layer 3, n ⁺ -type GaN drain layer 4, n ⁻ -type GaN layer 5, and p-type GaN-based channel layer 6 are epitaxially grown on the GaN buffer layer 2 in this order. The p-type GaN-based channel layer 6 may be a p-type GaN layer or a multilayer structure in which a p-type GaN layer is stacked on a p-type AlGaN layer.

For example, when a GaN layer is formed, trimethylgallium (TMGa), which is a Ga atom source gas, and ammonia (NH ₃ ), which is a nitrogen atom source gas, are used together with hydrogen or nitrogen as a carrier gas. In the case of n-type GaN, silane (SiH ₄ ) or the like as an n-type dopant gas, and in the case of p-type GaN, CP ₂ Mg (cyclopentadiethyl magnesium) or the like as a p-type dopant gas is used. Add to the reaction gas. When fabricating the AlGaN layer, TMGa, added trimethylaluminum (TMA) in NH _3.

  In this way, by supplying the reaction gas corresponding to the components of each semiconductor layer, the dopant gas for making the n-type and p-type, the crystal is grown in order by changing to the optimum growth temperature, thereby having a predetermined composition. A semiconductor layer of a predetermined conductivity type was formed to a required thickness. The doping concentration of impurities was controlled by the flow rate of each source gas.

Next, the laminated wafer as shown in FIG. 3 is taken out from the MOCVD apparatus, and a selective growth mask 7 is laminated on the p-type GaN channel layer 6 by CVD, plasma CVD, sputtering, etc. After the resist is patterned into a predetermined shape on the top, as shown in FIG. 4, the entire shape of the selective growth mask 7 is formed by, for example, wet etching using BHF or dry etching using CF _4. Etching is performed to form the opening 7a, and then the resist is removed by, for example, a method using acetone or methanol or an O ₂ ashing method.

  Here, in order to obtain the shape of the resist shown in FIG. 2, a resist pattern having a circular shape as shown in FIG. 9B is used. The crystal growth is started again in the MOCVD apparatus, and the n-type GaN source layer 8 is formed by selective growth in which crystal growth is performed from the opening 7a of the selective growth mask 7, as shown in FIG. The n-type GaN source layer 8 has a structure having a ridge shape on the left and right with the center selective growth mask 7b as the center. More specifically, the central selective growth mask 7b is formed in a ring shape so as to surround the periphery of the mask 7b.

  Thereafter, as shown in FIG. 6, the selective growth mask 7 present between the left and right ridges is removed by wet etching using a hydrofluoric acid (HF) solution or the like. A portion surrounded by a broken line in FIG. 2 corresponds to a region where the selective growth mask has been removed.

  Next, as shown in FIG. 7, the source electrode 10 is deposited on the surface of the p-type GaN-based channel layer 6 from which the left and right ridge side surfaces of the n-type GaN source layer 8 and the selective growth mask have been removed by vapor deposition, sputtering, or the like. Form across. Also, as shown in FIG. 8, a gate electrode 9 is formed on the remaining selective growth mask 7 by vapor deposition, sputtering, or the like.

  The source electrode 10 is formed across the inner side surface of the ridge portion connected in a donut shape in the n-type GaN source layer 8, a part of the top surface of the ridge portion, and the region where the selective growth mask is removed. As shown in FIG. 2, the source electrode 10, the n-type GaN source layer 8, the gate electrode 9, the selective growth mask 7 and the like are formed concentrically when viewed from above.

Next, by performing mesa etching to form a groove portion from the p-type GaN-based channel layer 6 toward ^{the n +} -type GaN drain layer 4, to expose the ^{n +} -type GaN drain layer 4, an insulating film 11 such as SiO ₂ Laminated in a groove formed by mesa etching by CVD, plasma CVD, sputtering, etc., leaving a part of the exposed surface of the n ⁺ -type GaN drain layer 4 and a part of the side surface, covered with a resist, etched, and insulating film 11 is removed (portion not covered with the resist), and the drain electrode 12 is formed by vapor deposition, sputtering, or the like in the region where the insulating film 11 is removed. In this way, the GaN-based semiconductor device shown in FIGS.

  As described above, by forming the ridge portion of the source layer by selective growth, the selective growth mask existing in the center sandwiched between the ridge portions is removed and removed by wet etching with an acidic solution. Since the channel layer under the growth mask can be prevented from being damaged and the junction region between the source electrode and the channel layer can be in ohmic contact, the contact resistance of the source layer can be reduced. In addition, when the channel layer is not damaged, the interface state density is reduced. Therefore, when a voltage is applied to the gate electrode, the channel layer is immediately inverted to the n-channel or p-channel, and the inversion distribution speed increases. The element can be operated at high speed because the on-resistance is lowered. Furthermore, the dislocation density of lattice defects to the source layer can be reduced by selective growth.

By the way, the vertical GaN-based semiconductor element of FIGS. 1 and 2 is used particularly as a power device for high power. FIGS. 1 and 2 show the structure of one element. A large number of devices are fabricated in the wafer, wiring is performed to connect a plurality of source electrodes in series or in parallel, and a plurality of gate electrodes and a plurality of drain electrodes are also connected in series or in parallel to each other. It is also possible to make one GaN-based semiconductor device.

It is a figure which shows the cross-section of the GaN-type semiconductor element of this invention. It is the figure which looked at the GaN-type semiconductor element of FIG. 1 from the upper surface. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows one manufacturing process of the manufacturing method of the GaN-type semiconductor element in this invention. It is a figure which shows the example of a pattern of the mask for selective growth. It is a figure which shows the cross-section of the conventional GaN-type semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 GaN buffer layer 3 Undoped GaN layer 4 n ⁺ type GaN drain layer 5 n ⁻ type GaN layer 6 p type GaN channel layer 7 mask for selective growth 8 n type GaN source layer 9 gate electrode 10 source electrode 11 insulation film

Claims (9)

A GaN-based semiconductor element comprising a channel layer made of a GaN-based semiconductor, and a source layer and a drain layer arranged with the channel layer interposed therebetween,
The source layer has a ridge portion formed by selective growth, and a source electrode is formed from the surface of the channel layer sandwiched between two adjacent ridge portions to the surface of the two ridge portions , and is used for the selective growth. The selected selective growth mask is left on the surface of the channel layer, and a gate electrode is provided on the selective growth mask . The GaN-based semiconductor device according to claim 1, wherein each of the two ridge portions has a stripe shape . 2. The GaN-based semiconductor device according to claim 1, wherein the two ridge portions are continuous, and the continuous shape is a donut shape or a polygonal shape. 4. The GaN-based semiconductor device according to claim 1, wherein the selective growth mask is made of a transparent insulator. 5. A GaN-based semiconductor device comprising the GaN-based semiconductor element according to claim 1. A method of manufacturing a GaN-based semiconductor element comprising a channel layer made of a GaN-based semiconductor, and a source layer and a drain layer arranged with the channel layer interposed therebetween,
A first step of stacking a selective growth mask on the channel layer;
A second step of removing part of the selective growth mask and forming an opening;
A third step of growing a source layer in the opening and forming a ridge portion with the selective growth mask interposed therebetween;
A fourth step of removing the selective growth mask by wet etching;
And a fifth step of forming a part of the source electrode on the surface of the channel layer after removing the selective growth mask . 7. The GaN-based semiconductor device according to claim 6, wherein the selective growth mask formed in the second step has an annular opening formed so as to surround the periphery of the central selective growth mask. Method. 8. The method for manufacturing a GaN-based semiconductor device according to claim 7, wherein the selective growth mask has a circular shape or a polygonal shape. 9. The GaN system according to claim 6, wherein the removal of the selective growth mask in the fourth step is to remove only the selective growth mask sandwiched between the ridge portions. 10. A method for manufacturing a semiconductor device.

Images