JP5132097B2 - Display device - Google Patents

Description

  The present invention relates to a semiconductor device including a transistor and a driving method thereof. In particular, the present invention relates to a semiconductor device including a pixel including a thin film transistor (hereinafter also referred to as “TFT”) and a driving method thereof.

  In recent years, thin displays (also referred to as flat panel displays) using electroluminescent characteristics of liquid crystals and elements that emit light by electroluminescence have attracted attention, and the market is expected to expand. As a thin display, a so-called active matrix display in which pixels are formed by TFTs formed on a glass substrate is regarded as important. In particular, a TFT in which a channel portion is formed of a polycrystalline silicon film has a higher field effect mobility than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. Therefore, the pixel can be controlled by a driver circuit formed using a TFT over the same substrate on which the pixel is formed. A display in which a pixel and a functional circuit are integrally formed on a glass substrate by using a TFT is expected to have many advantages such as a reduction in the number of components, an improvement in yield due to a simplified manufacturing process, and an improvement in productivity.

  An active matrix display (hereinafter also referred to as “EL display”) that combines an electroluminescent element (hereinafter also referred to as “EL element” in this specification) and a TFT can be reduced in thickness and weight. It is attracting attention as the next generation display. As for this display, development of a large display exceeding 40 inches from a small one having a size of 1 to 2 inches is under consideration.

The light emission luminance of the EL element is proportional to the current value flowing through the EL element. For this reason, in an EL display using an EL element as a display medium, gradation can be expressed by current. As a gradation expression method, a gate and a source of a driving TFT operating in a saturated state in a configuration in which an EL element and a TFT (hereinafter also referred to as “driving TFT”) are connected in series between two power supply lines. A method is known in which the voltage between the two is changed and the value of the current flowing in the EL element is controlled (see, for example, Patent Document 1). There is also known a driving method in which the current value is constant and the time during which the current flows in the EL element is controlled to express gradation (see, for example, Patent Document 2).
JP 2003-271095 A JP 2002-514320 A

  However, in the conventional pixel configuration, when the potential of the signal line changes every time a video signal is applied from a wiring (hereinafter also referred to as a “signal line”) that outputs a video signal to the gate of the driving TFT (driving transistor), There is a problem that power consumption increases because charging and discharging are performed by the parasitic capacitance of the line.

  The present invention has been made in view of such problems, and an object thereof is to reduce the power consumption of a semiconductor device using TFTs.

  The present invention is a semiconductor device including a pixel to which a video signal is input, a gate signal line for selecting the pixel to which the video signal is input, and a source signal line for inputting the video signal to the pixel. This semiconductor device is inserted in series with a source signal line, and is turned on when a pixel is not selected by a gate signal line, and is controlled to be turned off when a pixel is selected. have.

  According to one aspect of the present invention, a plurality of pixels arranged in a row direction and a column direction to which a video signal is input, and a plurality of gate signals that are wirings extending in the row direction and select input of the video signal to the plurality of pixels The semiconductor device includes a line and a plurality of source signal lines that extend in the column direction and input video signals to a plurality of pixels. A row corresponding to each of the plurality of pixels and inserted in series in the plurality of source lines and not selected by the plurality of gate signal lines is turned on, and a row selected by the plurality of gate signal lines is turned off. A plurality of switches to be controlled.

  In one embodiment of the present invention, a pixel to which a video signal is input, a gate signal line that selects input of the video signal to the pixel, a source signal line that inputs a video signal to the pixel, and a source signal line are inserted in series. A semiconductor device including a first transistor which is controlled to be turned on when a pixel is not selected by a gate signal line and turned off when a pixel is selected. The pixel includes a light-emitting element, and a light-emission control circuit that controls light emission and non-light-emission states of the light-emitting element according to a video signal, one of a source and a drain connected to the first transistor, and the other is a light emission control circuit And a second transistor to be connected.

  According to one aspect of the present invention, a plurality of pixels arranged in a row direction and a column direction to which a video signal is input, and a plurality of gate signals that are wirings extending in the row direction and select input of the video signal to the plurality of pixels The semiconductor device includes a line and a plurality of source signal lines that extend in the column direction and input video signals to a plurality of pixels. A row corresponding to each of the plurality of pixels, inserted in series with the plurality of source signal lines, and not selected by the plurality of gate signal lines is turned on, and a row selected by the plurality of gate signal lines is turned off. And a plurality of first transistors controlled in this manner. The pixel includes a light-emitting element, a light-emission control circuit that controls light emission and non-light-emission states of the light-emitting element according to a video signal, one of a source and a drain is connected to the first transistor, and the other is a light emission control circuit And a second transistor connected to.

  According to one embodiment of the present invention, a pixel to which a video signal is input, a first gate signal line that selects input of the video signal to the pixel, and a second gate having a potential inverted from the first gate signal line A semiconductor device including a signal line, a source signal line that inputs a video signal to a pixel, and a first transistor that is inserted in series with the source signal line and to which the potential of the second gate signal line is applied to the gate. is there. The pixel includes a light-emitting element, a light-emission control circuit that controls light emission and non-light-emission states of the light-emitting element according to a video signal, one of the source and the drain is connected to the first transistor, and the other is connected to the light emission control circuit The first gate signal line and the second transistor connected to the gate are included.

  According to one embodiment of the present invention, a pixel to which a video signal is input, a first gate signal line that selects input of the video signal to the pixel, a source signal line that inputs a video signal to the pixel, and a source signal line in series And a second gate signal line connected to the gate of the first transistor. The pixel includes a light emitting element, and a light emission control circuit that controls the light emitting and non-light emitting states of the light emitting element according to a video signal, one of the source and the drain is connected to the source signal line, and the other is connected to the light emitting control circuit. , And a second transistor connected to the gate, each of the first gate signal line and the second gate signal line being connected to the first gate signal line. Is turned on, the first transistor in the row selected by the second gate signal line is turned off, and the second transistor connected to the first gate signal line is turned off. And a potential for turning on the first transistors in the row selected by the gate signal line.

  The switch shown in the present invention can be used in various forms, and examples thereof include an electrical switch and a mechanical switch. In other words, any device can be used as long as it can control the flow of current, and it is not limited to a specific device, and various devices can be used. For example, it may be a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), a thyristor, or a logic circuit that combines them. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. Further, when the transistor operated as a switch operates at a source terminal potential close to a low potential power source (Vss, GND, 0 V, etc.), the N-channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to the side power supply (Vdd or the like), it is desirable to use a P-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch.

  A CMOS switch may be used by using both an N channel type and a P channel type. When a CMOS switch is used, a current can flow when either the P-channel switch or the N-channel switch is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. In addition, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

  Note that in the case where a transistor is used as a switch, the transistor has an input terminal (one of a source terminal or a drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal for controlling conduction (a gate terminal). Yes. On the other hand, when a diode is used as a switch, it may not have a terminal for controlling conduction. Therefore, the wiring for controlling the terminals can be reduced.

  In the present invention, the term “connected” includes the case of being electrically connected, the case of being functionally connected, and the case of being directly connected. Therefore, the configuration disclosed by the present invention includes other than the predetermined connection relationship. For example, one or more elements (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, or the like) that can be electrically connected may be arranged between a certain portion. In addition, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (a DA conversion circuit, an AD conversion circuit, a gamma correction circuit, etc.) or a potential level conversion circuit ( Power supply circuits such as booster circuits and step-down circuits, level shifter circuits that change the potential level of H and L signals, etc., voltage sources, current sources, switching circuits, and amplifier circuits (op amps, differential amplifier circuits, source follower circuits, and buffer circuits) Etc.), or a signal generation circuit, a memory circuit, a control circuit, etc.) may be disposed between them. Alternatively, they may be arranged directly connected without interposing other elements or other circuits therebetween.

  In the case of including only the case of being connected without interposing elements or circuits, it is described as being directly connected. In addition, when it is described as being electrically connected, when it is electrically connected (that is, when connected with another element in between) and when it is functionally connected (That is, connected with another circuit in between) and directly connected (that is, connected without another element or circuit in between). .

  Various forms can be used for the display element, the display device, the light-emitting element, and the light-emitting device. For example, as a display element arranged in a pixel, an EL element (organic EL element, inorganic EL element or EL element including organic and inorganic substances), electron-emitting element, liquid crystal element, electronic ink, grating light valve (GLV), plasma display (PDP), a digital micromirror device (DMD), a piezoelectric ceramic element, a carbon nanotube, or the like can be used as a display medium whose contrast is changed by an electromagnetic action. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). A display device using the element includes a liquid crystal display, a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, and a display device using electronic ink includes electronic paper.

  In the present invention, various types of transistors can be used as the transistor. Thus, there is no limitation on the type of applicable transistor. Therefore, for example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon can be used. As a result, they can be manufactured even at a low manufacturing temperature, can be manufactured at low cost, can be manufactured on a large substrate, can be manufactured on a transparent substrate, and light can be transmitted through a transistor. Alternatively, a MOS transistor, a junction transistor, a bipolar transistor, or the like formed using a semiconductor substrate or an SOI substrate can be used. Accordingly, a transistor with little variation can be manufactured, a transistor with high current supply capability can be manufactured, a transistor with a small size can be manufactured, and a circuit with low power consumption can be configured. In addition, a transistor including a compound semiconductor such as ZnO, a-InGaZnO, SiGe, or GaAs, or a thin film transistor obtained by thinning them can be used. Accordingly, the transistor can be manufactured even at a low manufacturing temperature, can be manufactured at room temperature, or a transistor can be directly formed on a substrate having low heat resistance, such as a plastic substrate or a film substrate. In addition, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, can manufacture in a state with a low degree of vacuum, or can manufacture with a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. In addition, a transistor including an organic semiconductor or a carbon nanotube, or another transistor can be used. Thus, a transistor can be formed over a substrate that can be bent. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. In addition, various types of substrates on which the transistor is arranged can be used, and the substrate is not limited to a specific type. Therefore, for example, it can be disposed on a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stainless steel substrate, a stainless steel foil substrate, or the like. Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be moved to another substrate and placed on another substrate. By using these substrates, it is possible to form a transistor with good characteristics, to form a transistor with low power consumption, to make the device hard to break, or to have heat resistance.

  The structure of the transistor can take various forms. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is used, the channel regions are connected in series, so that a plurality of transistors are connected in series. The multi-gate structure reduces the off current, improves the breakdown voltage of the transistor to improve reliability, and even when the drain-source voltage changes when operating in the saturation region. The inter-current does not change so much, and flat characteristics can be achieved. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By adopting a structure in which gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased, and a depletion layer can be easily formed to improve the S value. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained.

  A structure in which a gate electrode is disposed above a channel, a structure in which a gate electrode is disposed below a channel, a normal staggered structure, an inverted staggered structure, or a channel The region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. In addition, a source electrode or a drain electrode may overlap with the channel (or a part thereof). By using a structure in which a source electrode or a drain electrode overlaps with a channel (or part of it), it is possible to prevent electric charges from being accumulated in part of the channel and unstable operation. There may also be an LDD region. By providing an LDD region, the off-current can be reduced, the breakdown voltage of the transistor can be improved to improve reliability, or the drain-source voltage can be changed even when the drain-source voltage changes when operating in the saturation region. The current does not change so much, and a flat characteristic can be obtained.

  Various types of transistors can be used in the present invention and can be formed over various substrates. Therefore, the entire circuit may be formed on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, or may be formed on an SOI substrate. Alternatively, it may be formed on any substrate. Since all the circuits are formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with circuit parts can be reduced to improve the reliability. Alternatively, a part of the circuit may be formed on a certain substrate, and another part of the circuit may be formed on another substrate. That is, all of the circuits may not be formed on the same substrate. For example, part of a circuit is formed using a transistor over a glass substrate, another part of the circuit is formed over a single crystal substrate, and the IC chip is connected with COG (Chip On Glass) to form a glass. You may arrange | position on a board | substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board. As described above, since a part of the circuit is formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with the circuit parts can be reduced to improve the reliability. In addition, since the power consumption increases in a portion where the drive voltage is high or a portion where the drive frequency is high, an improvement in power consumption can be prevented if such a portion is not formed on the same substrate.

  In the present invention, one pixel represents one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels. Note that the color elements are not limited to three colors, and more than that may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, RGB may be obtained by adding one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like. Further, for example, a similar color may be added for at least one of RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have slightly different absorption wavelengths. By using such a color element, it is possible to perform display closer to the real thing or to reduce power consumption. As another example, in the case where brightness is controlled using a plurality of areas for one color element, one area corresponds to one pixel. Therefore, as an example, when performing area gradation, there are a plurality of areas for controlling the brightness for each color element, and the gradation is expressed as a whole. One portion is defined as one pixel. Therefore, in that case, one color element is composed of a plurality of pixels. In that case, the size of the region contributing to the display may be different depending on the pixel. Further, in a plurality of brightness control areas for one color element, that is, in a plurality of pixels constituting one color element, a signal supplied to each is slightly different to widen the viewing angle. You may do it.

  When describing as one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered as one pixel. In the case of describing one pixel (for one color), it is assumed that when there are a plurality of pixels for one color element, they are collectively considered as one pixel.

  In the present invention, the pixels include a case where the pixels are arranged (arranged) in a matrix. Here, the arrangement (arrangement) of pixels in a matrix includes a case where pixels are arranged side by side in a vertical direction or a horizontal direction or a case where they are arranged on a jagged line. Therefore, for example, when full color display is performed with three color elements (for example, RGB), the case where stripes are arranged and the case where dots of three color elements are arranged in a so-called delta are also included. Furthermore, the case where a Bayer is arranged is also included. Further, the size of the display area may be different for each dot of the color element. Thereby, power consumption can be reduced and the lifetime of the display element can be extended.

  A transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and the drain region, the channel region, and the source region. A current can be passed through. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in the present invention, a region functioning as a source and a drain may not be called a source or a drain. In that case, as an example, there are cases where they are referred to as a first terminal and a second terminal, respectively.

  Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, the emitter and the collector may be referred to as a first terminal and a second terminal.

  Note that a gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line). A gate electrode refers to a conductive film which overlaps with a semiconductor that forms a channel region, an LDD (Lightly Doped Drain) region, and the like with a gate insulating film interposed therebetween. The gate wiring refers to wiring for connecting between the gate electrodes of each pixel or connecting the gate electrode to another wiring.

  However, there is a portion that functions as a gate electrode and also functions as a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region that overlaps with an extended gate wiring, the region functions as a gate wiring, but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring.

  A region formed of the same material as the gate electrode and connected to the gate electrode may also be called a gate electrode. Similarly, a region formed of the same material as the gate wiring and connected to the gate wiring may be called a gate wiring. In a strict sense, such a region may not overlap with the channel region or may not have a function of being connected to another gate electrode. However, there is a region that is formed of the same material as the gate electrode and the gate wiring and connected to the gate electrode and the gate wiring because of a manufacturing margin. Therefore, such a region may also be called a gate electrode or a gate wiring.

For example, in a multi-gate transistor, the gate electrode of one transistor and the gate electrode of another transistor are often connected by a conductive film formed using the same material as the gate electrode. Such a region is a region for connecting the gate electrode and the gate electrode, and may be referred to as a gate wiring. However, a multi-gate transistor can be regarded as a single transistor, and thus the gate electrode You can call it. That is, what is formed of the same material as the gate electrode and the gate wiring and is connected to the gate electrode and the gate wiring may be called a gate electrode and a gate wiring.
For example, a portion of the conductive film where the gate electrode and the gate wiring are connected may be called a gate electrode or a gate wiring.

  The gate terminal refers to a part of a gate electrode region or a region electrically connected to the gate electrode.

  A source refers to the whole or part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, or the like). The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a little P-type impurity or N-type impurity, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode may be referred to as a source electrode including the source region. The source wiring is a wiring for connecting between the source electrodes of each pixel or connecting the source electrode and another wiring.

  However, there is a portion that functions as a source electrode and also functions as a source wiring. Such a region may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when there is a source region that overlaps with an extended source wiring, the region functions as a source wiring, but also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring.

  A region formed of the same material as the source electrode and connected to the source electrode, or a portion connecting the source electrode and the source electrode may also be referred to as a source electrode. A portion overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may be called a source wiring. In a strict sense, such a region may not have a function of connecting to another source electrode. However, there is a region formed of the same material as the source electrode and the source wiring and connected to the source electrode and the source wiring because of a manufacturing margin. Therefore, such a region may also be called a source electrode or a source wiring.

  Further, for example, a conductive film in a portion where the source electrode and the source wiring are connected to each other may be referred to as a source electrode or a source wiring.

  The source terminal refers to a part of a source region, a source electrode, or a region electrically connected to the source electrode. The drain is the same as the source.

In the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). In addition, any device that can function by utilizing semiconductor characteristics may be used. A display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including display elements such as a liquid crystal element and an EL element and peripheral drive circuits for driving these pixels are formed over the same substrate may be used. Further, it may include a peripheral drive circuit, so-called chip on glass (COG), which is disposed on the substrate by wire bonding or bumps. Furthermore, a device to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (an IC, a resistor, a capacitor, an inductor, a transistor, or the like) may also be included. Furthermore, an optical sheet such as a polarizing plate or a retardation plate may be included. Furthermore, a backlight (which may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, or a light source (such as an LED or a cold cathode tube)) may be included.
A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

  In the present invention, the description “on top” or “on top”, such as “formed on a certain object” or “formed on top”, It is not limited to touching directly on top. This includes cases where they are not in direct contact, that is, cases where another object is sandwiched between them. Therefore, for example, when “layer B is formed on layer A (or on layer A)”, when layer B is formed in direct contact with layer A, In which another layer (for example, layer C or layer D) is formed in direct contact with layer B and layer B is formed in direct contact therewith. The same applies to the description “above” and is not limited to being in direct contact with a certain object, and includes a case in which another object is sandwiched therebetween. Therefore, for example, when “the layer B is formed above the layer A”, the layer B is formed in direct contact with the layer A, and another layer is formed in direct contact with the layer A. (For example, the layer C or the layer D) is formed, and the layer B is formed in direct contact therewith. The same applies to the case of “under” or “under” and includes the case of direct contact and the case of no contact.

  In this specification, the “source signal line” refers to a wiring connected to the output of the source driver as means for transmitting a video signal for controlling the operation of the pixel from the source driver.

  In this specification, a “gate signal line” is a wiring connected to an output of a gate driver as means for transmitting a scanning signal for controlling selection / non-selection of writing of a video signal to a pixel from the gate driver. It points to that.

  According to the present invention, the video signal is written from the source signal line to the pixel selected by the gate signal line, the switching element of the pixel not selected by the gate signal line is turned on, and the pixel selected by the gate signal line is switched. By turning off the element, the influence of the parasitic capacitance of the source signal line can be suppressed. That is, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. Thus, an increase in power consumption due to charging / discharging of the source signal line can be reduced, and power consumption can be reduced.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

(First embodiment)
A first structure of a semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 1, a plurality of pixels 103 are arranged in the row direction and the column direction. The source driver 101 includes a circuit that outputs a video signal in accordance with an input control signal. The source driver 101 inputs a video signal via the source signal line 107 to the pixel 103 selected for writing. The gate driver 102 includes a circuit that scans the gate signal line 108 in accordance with a control signal input to the gate driver 102 and selects a pixel into which a video signal is written. The pixel 103 includes a light emitting unit 104 and a switch 105 and a switch 106 that are turned on or off by a gate signal line 108. The two switches operate so that the switch 106 is turned off when the switch 105 is on, and the switch 106 is turned on when the switch 105 is off. Note that the light emitting unit 104 includes a light emitting element and a circuit for controlling the light emitting element.

  An operation in the case of writing a video signal to the pixel 103 from the source driver 101 via the source signal line 107 in the semiconductor device having this structure will be described. In this case, in the pixel 103 to which the video signal is input, the switch 105 is turned off and the switch 106 is turned on. Then, a video signal is input from the source driver 101 to the light emitting unit 104 via the source signal line 107.

  Next, an operation when a video signal is not written to the pixel 103 will be described. In this case, in the pixel 103 to which no video signal is written, the switch 105 is turned on and the switch 106 is turned off. Therefore, no video signal is written from the source driver 101 to the light emitting unit 104 via the source signal line 107.

  The video signal output from the source driver 101 can be similarly applied regardless of whether it is a voltage signal or a current signal. Further, there is no limitation on the internal configuration of the pixel as long as a video signal is input to the pixel. For example, a circuit that corrects the threshold voltage of the driving transistor, a circuit that determines whether or not the light emitting element emits light for sharpening an image, and an erasing transistor for turning off the driving transistor used for time-division gradation There may be. Further, a signal line for controlling these may be added. Further, a power supply line for precharging a voltage to the pixel, which is used when a video signal is input to the pixel with a current, may be added. Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the switch 105 of the pixel 103 to which the video signal is written, the influence of the parasitic capacitance of the source signal line 107 seen from the output of the source driver 101 affects only the pixel 103 to which the video signal is written. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 107 can be suppressed.

  In addition, the influence of the parasitic capacitance of the source signal line 107 as viewed from the output of the source driver 101 affects only the pixel 103 to which the video signal is written, so that the video signal writing time is shortened. This is a great advantage when the pixel 103 is operated as a current input type.

  As described above, according to the present embodiment, the parasitic capacitance that affects the charging / discharging of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. . As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Second Embodiment)
A second configuration of the semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 2, the plurality of pixels 203 are arranged in the row direction and the column direction. The source driver 201 is a circuit that outputs a video signal in accordance with an input control signal, and inputs the video signal to the pixel 203 selected for writing via the source signal line 207. The gate driver 202 scans the gate signal line 209 that outputs the inverted potential of the gate signal line 208 via the gate signal line 208 and the inverter 210 in accordance with the control signal input to the gate driver 202, and writes a video signal. Select a pixel.

  The pixel 203 is turned on or off by a light emitting unit 204 including a light emitting element and a circuit for controlling the light emitting element, a switch 206 that is turned on or off by a gate signal line 208, and a gate signal line 209. The switch 205 is included. When the switch 205 is on, the switch 206 is turned off, and when the switch 205 is off, the switch 206 is turned on.

  An operation when a video signal is written to the pixel 203 from the source driver 201 via the source signal line 207 will be described. In this case, in the pixel 203 to which the video signal is written, the switch 205 is turned off and the switch 206 is turned on. Then, a video signal is written from the source driver 201 to the light emitting unit 204 via the source signal line 207.

  Next, an operation when a video signal is not written to the pixel 203 will be described. In this case, in the pixel 203 to which no video signal is written, the switch 205 is turned on and the switch 206 is turned off. Therefore, a video signal is not written from the source driver 201 to the light emitting unit 204 via the source signal line 207.

  In this embodiment, by controlling the switches 205 and 206 with inverted signals, even if the characteristics of the switch 205 and the switch 206 are the same, when the switch 205 is on, the switch 206 is off and the switch 205 is off. In this case, the switch 206 can be turned on.

  The connection relationship between the gate signal line 208 and the gate signal line 209 and the switch 205 and the switch 206 may be reversed. That is, on / off of the switch 205 may be controlled by the gate signal line 208, and on / off of the switch 206 may be controlled by the gate signal line 209.

  The video signal output from the source driver 201 can be similarly applied regardless of whether it is a voltage signal or a current signal. Further, there is no limitation on the internal configuration of the pixel as long as a video signal is input to the pixel. For example, a circuit that corrects the threshold voltage of the driving transistor, a circuit that determines whether or not the light emitting element emits light for sharpening an image, and an erasing transistor for turning off the driving transistor used for time-division gradation There may be. Further, a signal line for controlling these may be added. Further, a power supply line for precharging a voltage may be added to a pixel used when a video signal is input to the pixel with a current. Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the switch 205 of the pixel 203 for writing the video signal, the influence of the parasitic capacitance of the source signal line 207 as seen from the output of the source driver 201 affects only the pixel 203 for writing the video signal. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 207 can be suppressed.

  In addition, since the influence of the parasitic capacitance of the source signal line 207 as viewed from the output of the source driver 201 affects only the pixel 203 to which the video signal is written, the video signal writing time is shortened. This is a great advantage when the pixel 203 is operated as a current input type.

  As described above, according to the present embodiment, the parasitic capacitance that affects the charging / discharging of the source signal line affects only the source signal line from the output of the source driver to the pixel that is selected to be written to the pixel. Disappear. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Third embodiment)
A third configuration of the semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 3, the plurality of pixels 303 are arranged in the row direction and the column direction. The source driver 301 is a circuit that outputs a video signal in accordance with an input control signal, and inputs the video signal to the pixel 303 selected for writing via the source signal line 307. The gate driver 302 scans the gate signal line 308 in accordance with the control signal input to the gate driver 302, and selects a pixel into which a video signal is written.

  The pixel 303 includes a light emitting unit 304 including a light emitting element and a circuit for controlling the light emitting element, a TFT 305, and a TFT 306. The TFT 305 is inserted in series with the source signal line 307, and one of the source and drain of the TFT 306 is connected to the TFT 305, and the other of the source and drain is connected to the light emitting unit 304. The gates of the TFTs 305 and 306 are connected to the gate signal line 308, and the on or off of the TFT is selected by the gate signal line 308. In FIG. 3, since the TFT 305 is a P-channel TFT and the TFT 306 is an N-channel TFT, the TFT 306 is turned off when the TFT 305 is on, and the TFT 306 is turned on when the TFT 305 is off. Further, when the gate signal line 308 selects the pixel 303, the TFT 305 is turned off and the TFT 306 is turned on.

  The TFTs 305 and 306 need only have different polarities. For example, when the TFT 305 is an N-channel type, the TFT 306 may be a P-channel type. In the case where the TFT 305 is a P-channel type, the TFT 306 may be an N-channel type.

  An operation when a video signal is written to the pixel 303 from the source driver 301 via the source signal line 307 will be described. In this case, in the pixel 303 into which the video signal is written, the TFT 305 is turned off and the TFT 306 is turned on. Then, a video signal is written from the source driver 301 to the light emitting unit 304 via the source signal line 307.

  An operation when a video signal is not written to the pixel 303 will be described. In this case, in the pixel 303 to which no video signal is written, the TFT 305 is turned on and the TFT 306 is turned off. Therefore, a video signal is not written from the source driver 301 to the light emitting unit 304 via the source signal line 307.

  The video signal output from the source driver in the present embodiment may be output as voltage or current. The pixel configuration may be any pixel configuration that inputs a video signal to the pixel. For example, a circuit for correcting the threshold voltage of the driving transistor, a circuit for determining the presence or absence of light emission of a light emitting element for sharpening an image, and an erasing transistor for turning off a driving transistor used for time division gradation There may be. In addition, a signal line for controlling these may be added, or a power supply line for precharging a voltage may be added to a pixel used when a video signal is input to the pixel with a current. .

  Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the TFT 305 of the pixel 303 to which the video signal is written, the influence of the parasitic capacitance of the source signal line 307 as viewed from the output of the source driver 301 affects only the pixel 303 to which the video signal is written. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 307 can be suppressed.

  In addition, the influence of the parasitic capacitance of the source signal line 307 as viewed from the output of the source driver 301 affects only the pixel 303 into which the video signal is written, so that the video signal writing time is shortened. This is a great advantage when the pixel 303 is operated in a current input type.

  As described above, according to the present embodiment, the parasitic capacitance that affects the charging / discharging of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. . As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Fourth embodiment)
A fourth structure of the semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 4, the plurality of pixels 403 are arranged in the row direction and the column direction. The source driver 401 is a circuit that outputs a video signal in accordance with an input control signal, and inputs the video signal to the pixel 403 selected for writing via the source signal line 407. The gate driver 402 scans the gate signal line 408 in accordance with the control signal input to the gate driver 402, and selects a pixel into which a video signal is written.

  The pixel 403 includes a light emitting unit 404 including a light emitting element and a circuit for controlling the light emitting element, a TFT 405, and a TFT 406. The TFT 405 is inserted in series with the source signal line 407, and one of the source and drain of the TFT 406 is connected to the TFT 405, and the other of the source and drain is connected to the light emitting unit 404. The gates of the TFTs 405 and 406 are connected to the gate signal line 408, and ON or OFF is selected by the gate signal line 408. Since the TFT 405 is an N-channel TFT and the TFT 406 is a P-channel TFT, the TFT 406 is turned off when the TFT 405 is on, and the TFT 406 is turned on when the TFT 405 is off. Further, when the gate signal line 408 selects the pixel 403, the TFT 405 is turned off and the TFT 406 is turned on.

  The TFTs 405 and 406 may have different polarities. For example, the TFT 405 may be a P-channel type and the TFT 406 may be an N-channel type.

  An operation in the case where a video signal is written to the pixel 403 from the source driver 401 via the source signal line 407 will be described. In this case, in the pixel 403 to which the video signal is written, the TFT 405 is turned off and the TFT 406 is turned on. Then, a video signal is written from the source driver 401 to the light emitting unit 404 via the source signal line 407.

  An operation when the video signal is not written to the pixel 403 will be described. In this case, in the pixel 403 to which no video signal is written, the TFT 405 is turned on and the TFT 406 is turned off. Therefore, a video signal is not written from the source driver 401 to the light emitting unit 404 via the source signal line 407.

  The video signal output from the source driver in the present embodiment may be output as voltage or current. The pixel configuration may be any pixel configuration that inputs a video signal to the pixel. For example, a circuit for correcting the threshold voltage of the driving transistor, a circuit for determining the presence or absence of light emission of a light emitting element for sharpening an image, and an erasing transistor for turning off a driving transistor used for time division gradation There may be. In addition, a signal line for controlling these may be added, or a power supply line for precharging a voltage may be added to a pixel used when a video signal is input to the pixel with a current. .

  Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the TFT 405 of the pixel 403 for writing the video signal, the influence of the parasitic capacitance of the source signal line 407 as viewed from the output of the source driver 401 affects only the pixel 403 for writing the video signal. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 407 can be suppressed.

  In addition, since the influence of the parasitic capacitance of the source signal line 407 as viewed from the output of the source driver 401 affects only the pixel 403 to which the video signal is written, the video signal writing time is shortened. This is a great advantage when the pixel 403 is operated as a current input type.

(Fifth embodiment)
A fifth configuration of the semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 5, the plurality of pixels 503 are arranged in the row direction and the column direction. The source driver 501 is a circuit that outputs a video signal in accordance with an input control signal, and inputs the video signal to the pixel 503 selected for writing via the source signal line 507. The gate driver 502 scans the gate signal line 509 that outputs the inverted potential of the gate signal line 508 via the gate signal line 508 and the inverter 510 in accordance with the control signal input to the gate driver 502, and writes a video signal. Select a pixel.

  The pixel 503 includes a light emitting element, a light emitting unit 504 including a circuit for controlling the light emitting element, a TFT 505, and a TFT 506. The TFT 505 is inserted in series with the source signal line 507, and one of the source and drain of the TFT 506 is connected to the TFT 505, and the other of the source and drain is connected to the light emitting unit 504. The gate of the TFT 505 is connected to the gate signal line 509, the gate of the TFT 506 is connected to the gate signal line 508, the TFT 505 is turned on or off by the gate signal line 509, and the TFT 506 is turned on or off by the gate signal line 508. Selected. Since the TFT 505 and the TFT 506 are N-channel type, the TFT 506 is turned off when the TFT 505 is on, and the TFT 506 is turned on when the TFT 505 is off.

  The TFTs 505 and 506 only need to have the same polarity. For example, the TFT 505 and the TFT 506 may be a P-channel type.

  An operation in the case where a video signal is written to the pixel 503 from the source driver 501 through the source signal line 507 will be described. In this case, in the pixel 503 into which the video signal is written, the TFT 505 is turned off and the TFT 506 is turned on. Then, a video signal is written from the source driver 501 to the light emitting unit 504 through the source signal line 507.

  An operation when a video signal is not written to the pixel 503 is described. In this case, in the pixel 503 to which no video signal is written, the TFT 505 is on and the TFT 506 is off. Therefore, a video signal is not written from the source driver 501 to the light emitting unit 504 through the source signal line 507.

  The video signal output from the source driver in the present embodiment may be output as voltage or current. The pixel configuration may be any pixel configuration that inputs a video signal to the pixel. For example, a circuit for correcting the threshold voltage of the driving transistor, a circuit for determining the presence or absence of light emission of a light emitting element for sharpening an image, and an erasing transistor for turning off a driving transistor used for time division gradation There may be. Further, a signal line for controlling these may be added. A power supply line for precharging a voltage may be added to a pixel used when a video signal is input to the pixel with a current.

  Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the TFT 505 of the pixel 503 for writing the video signal, the influence of the parasitic capacitance of the source signal line 507 as viewed from the output of the source driver 501 affects only the pixel 503 for writing the video signal. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 507 can be suppressed.

  Further, the influence of the parasitic capacitance of the source signal line 507 viewed from the output of the source driver 501 affects only the pixel 503 to which the video signal is written, so that the video signal writing time is shortened. This is a great advantage when the pixel 503 is operated as a current input type.

  As described above, according to the present embodiment, the parasitic capacitance that affects the charging / discharging of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. . As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Sixth embodiment)
A sixth configuration of the semiconductor device according to the present invention will be described with reference to FIG.

  In FIG. 6, a plurality of pixels 603 are arranged in the row direction and the column direction. The source driver 601 is a circuit that outputs a video signal in accordance with an input control signal, and inputs the video signal to the pixel 603 selected for writing via the source signal line 607. The gate driver 602 scans the gate signal line 609 that outputs the inverted potential of the gate signal line 608 through the gate signal line 608 and the inverter 610 in accordance with the control signal input to the gate driver 602, and writes a video signal. Select a pixel.

  The pixel 603 includes a light emitting unit 604 including a light emitting element and a circuit for controlling the light emitting element, a TFT 605, and a TFT 606. The TFT 605 is inserted in series with the source signal line 607, and one of the source and drain of the TFT 606 is connected to the TFT 605, and the other of the source and drain is connected to the light emitting unit 604. The gate of the TFT 605 is connected to the gate signal line 609, the gate of the TFT 606 is connected to the gate signal line 608, the TFT 605 is turned on or off by the gate signal line 609, and the TFT 606 is turned on or off by the gate signal line 608 Is done. Since the TFT 605 and the TFT 606 are p-channel transistors, the TFT 606 is turned off when the TFT 605 is on, and the TFT 606 is turned on when the TFT 605 is off.

  The TFTs 605 and 606 only need to have the same polarity. For example, the TFTs 605 and 606 may be N-channel type.

  An operation in the case where a video signal is written to the pixel 603 from the source driver 601 through the source signal line 607 will be described. In this case, in the pixel 603 to which the video signal is written, the TFT 605 is turned off and the TFT 606 is turned on. Then, a video signal is written from the source driver 601 to the light emitting unit 604 via the source signal line 607.

  An operation when the video signal is not written to the pixel 603 will be described. In this case, in the pixel 603 to which no video signal is written, the TFT 605 is turned on and the TFT 606 is turned off. Therefore, a video signal is not written from the source driver 601 to the light emitting unit 604 via the source signal line 607.

  The video signal output from the source driver in the present embodiment may be output as voltage or current. The pixel configuration may be any pixel configuration that inputs a video signal to the pixel. For example, a circuit for correcting the threshold voltage of the driving transistor, a circuit for determining the presence or absence of light emission of a light emitting element for sharpening an image, and an erasing transistor for turning off a driving transistor used for time division gradation There may be. In addition, a signal line for controlling these may be added, or a power supply line for precharging a voltage may be added to a pixel used when a video signal is input to the pixel with a current. .

  The configuration of the light emitting unit described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the sixth embodiment is not particularly limited. Further, as already described, the video signal output from the source driver may be output as a voltage or may be output as a current. In any case, any pixel may be used as long as it operates by inputting a video signal.

  Further, a power supply line and a signal line may be added as necessary. The power supply line may supply voltage or current. The signal line may be controlled by voltage or current.

  In this embodiment, by turning off the TFT 605 of the pixel 603 for writing the video signal, the influence of the parasitic capacitance of the source signal line 607 as viewed from the output of the source driver 601 affects only the pixel 603 for writing the video signal. Therefore, an increase in power consumption due to charging / discharging of the parasitic capacitance of the source signal line 607 can be suppressed.

  In addition, since the influence of the parasitic capacitance of the source signal line 607 as viewed from the output of the source driver 601 affects only the pixel 603 to which the video signal is written, the time for writing the video signal to the pixel 603 is shortened. This is a great advantage when the pixel 603 is operated as a current input type.

  As described above, according to the present embodiment, the parasitic capacitance that affects the charging / discharging of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. . As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Seventh embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 7, a TFT 701 is a P-channel transistor, and a capacitor 702 is a capacitor having a pair of electrodes. The light-emitting element 703 is a light-emitting element having a pair of electrodes, and the counter electrode 704 is the other electrode of the light-emitting element 703. The power supply line 705 is a power supply line for supplying power to one electrode of the light emitting element 703 via the TFT 701, and the signal input line 706 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 703 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 703.

  The power supply line 705 is connected to one of the source and drain of the TFT 701, the other of the source and drain of the TFT 701 is connected to one electrode of the light emitting element 703, and the gate of the TFT 701 is connected to the signal input line 706 and the capacitor 702. One electrode is connected, and the other electrode of the capacitor 702 is connected to the power supply line 705.

  The power supply line 705 is set to a potential higher than that of the counter electrode 704, and the signal input line 706 inputs a video signal to the light emitting unit for writing.

  Next, an operation for writing a video signal will be described. The video signal is input from the signal input line 706, and the video signal is held in the capacitor 702. Then, the value of the current flowing through the light-emitting element 703 and the light emission luminance are determined by the relationship between the potential held in the capacitor 702, the potential of the power supply line 705, and one potential of the light-emitting element 703. That is, the value of the current flowing through the light emitting element 703 and the light emission luminance are determined by the potential between the source and the gate of the TFT 701 and the potential between the source and the drain. Further, in the case of time gradation driving in which gradation (luminance) is expressed by light emission time, the TFT 701 may be operated as a switch, and on / off of the TFT 701 may be controlled by a video signal to express gradation (luminance). .

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Eighth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 8, a TFT 801 is an N-channel transistor, and a capacitor 802 is a capacitor having a pair of electrodes. The light-emitting element 803 is a light-emitting element having a pair of electrodes, and the counter electrode 804 is the other electrode of the light-emitting element 803. A power supply line 805 is a power supply line for supplying power to one electrode of the light emitting element 803 via the TFT 801, and a signal input line 806 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 803 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 803.

  The power supply line 805 is connected to one of the source and drain of the TFT 801, the other of the source and drain of the TFT 801 is connected to one electrode of the light emitting element 803, and the gate of the TFT 801 is one of the signal input line 806 and the capacitor 802. The other electrode of the capacitor 802 is connected to the power supply line 805.

  The power supply line 805 is set to a potential higher than that of the counter electrode 804, and the signal input line 806 inputs a video signal to the light emitting unit that performs writing.

  An operation for writing a video signal will be described. The video signal is input from the signal input line 806, and the video signal is held in the capacitor 802. Then, the value of the current flowing through the light-emitting element 803 and the light emission luminance are determined by the relationship between the potential held in the capacitor 802, the potential of the power supply line 805, and one potential of the light-emitting element 803. That is, the value of the current flowing through the light emitting element 803 and the light emission luminance are determined by the potential between the source and the gate of the TFT 801 and the potential between the source and the drain. Further, in the case of time gradation driving in which the light emission gradation is expressed by the light emission time, the light emission gradation may be expressed by operating the TFT 801 as a switch and controlling on / off of the TFT 801 by a video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Ninth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 9, a TFT 901 is a P-channel transistor, and a switch 902 is a switch whose ON or OFF is controlled by a gate signal line 907. The capacitor 903 is a capacitor having a pair of electrodes, the light emitting element 904 is a light emitting element having a pair of electrodes, and the counter electrode 905 is an electrode of the light emitting element 904. A power supply line 906 is a power supply line for supplying power to one electrode of the light emitting element 904 via the TFT 901, and a signal input line 908 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 904 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 904.

  The power supply line 906 is connected to one of the source and drain of the TFT 901, and the other of the source and drain of the TFT 901 is connected to one electrode of the light emitting element 904. The gate of the TFT 901 is connected to the signal input line 908, one electrode of the capacitor 903 and one terminal of the switch 902, and the other electrode of the capacitor 903 is connected to the power supply line 906. The TFT 901 is controlled to be turned on and off by a gate signal line 907.

  The power supply line 906 is set to a potential higher than that of the counter electrode 905, and the signal input line 908 inputs a video signal to the light emitting unit for writing.

  As an example, a description will be given of driving when light emission gradation is expressed using time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 908, the video signal is set to a binary potential of H level and L level, and the video signal is held in the capacitor 903. At this time, since the TFT 901 operates as a switch, on / off of the TFT 901 is controlled by a potential held in the capacitor 903. That is, the light emission time of the light emitting element 904 is controlled. At this time, the switch 902 is turned off.

  The erase period shown above will be described. The TFT 901 can be turned off by turning on the switch 902, holding the potential of the power supply line 906 in the capacitor 903, and setting the potential difference between the gate and source of the TFT 901 to be near 0V. That is, the light emitting element 904 can be made to emit no light regardless of the video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Tenth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 10, a TFT 1001 is an N-channel transistor, and a switch 1002 is a switch whose ON or OFF is controlled by a gate signal line 1007. The capacitor 1003 is a capacitor having a pair of electrodes, the light-emitting element 1004 is a light-emitting element having a pair of electrodes, and the counter electrode 1005 is an electrode of the light-emitting element 1004. A power supply line 1006 is a power supply line for supplying power to one electrode of the light emitting element 1004 via the TFT 1001, and a gate signal line 1007 is a gate signal line for selecting whether or not video signal writing is possible. A line 1008 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1004 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1004.

  The power supply line 1006 is connected to one of the source and the drain of the TFT 1001, and the other of the source and the drain of the TFT 1001 is connected to one electrode of the light emitting element 1004. The gate of the TFT 1001 is connected to the signal input line 1008, one electrode of the capacitor 1003 and one terminal of the switch 1002, and the other electrode of the capacitor 1003 is connected to the power supply line 1006. The TFT 1001 is controlled to be turned on and off by a gate signal line 1007.

  The power supply line 1006 is set to a potential lower than that of the counter electrode 1005, and the signal input line 1008 inputs a video signal to the light emitting unit that performs writing.

  As an example, a description will be given of driving when light emission gradation is expressed using time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 1008, the video signal is set to a binary potential of H level and L level, and the video signal is held in the capacitor 1003. At this time, since the TFT 1001 operates as a switch, on / off of the TFT 1001 is controlled by a potential held in the capacitor 1003. That is, the light emission time of the light emitting element 1004 is controlled. At this time, the switch 1002 is turned off.

  The erase period shown above will be described. The TFT 1001 can be turned off by turning on the switch 1002, holding the potential of the power supply line 1006 in the capacitor 1003, and setting the potential difference between the gate and the source of the TFT 1001 to around 0V. That is, the light emitting element 1004 can be made to emit no light regardless of the video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Eleventh embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 11, a TFT 1101 is a P-channel transistor, and a diode 1102 is a diode having an input as a gate signal line 1107 and an output as a gate of the TFT 1101. The capacitor 1103 is a capacitor having a pair of electrodes, the light-emitting element 1104 is a light-emitting element having a pair of electrodes, and the counter electrode 1105 is the other electrode of the light-emitting element 1104. A power supply line 1106 is a power supply line for supplying power to one electrode of the light emitting element 1104 via the TFT 1101, and a gate signal line 1107 is a gate signal line for selecting whether or not writing of a video signal is possible. A line 1108 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1104 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1104.

  The power supply line 1106 is connected to one of a source and a drain of the TFT 1101, and the other of the source and the drain of the TFT 1101 is connected to one electrode of the light emitting element 1104. The gate of the TFT 1101 is connected to the signal input line 1108, one electrode of the capacitor 1103 and the output of the diode 1102, and the other electrode of the capacitor 1103 is connected to the power supply line 1106. The input of the diode 1102 is connected to the gate signal line 1107.

  The power supply line 1106 is set to a potential higher than that of the counter electrode 1105, and the signal input line 1108 inputs a video signal to the light emitting unit for writing.

  As an example, a description will be given of driving when light emission gradation is expressed using time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 1108, the video signal is set to a binary potential of H level and L level, and the video signal is held in the capacitor 1103. At this time, since the TFT 1101 operates as a switch, on / off of the TFT 1101 is controlled by a potential held in the capacitor 1103. That is, the light emission time of the light emitting element 1104 is controlled. At this time, since the gate signal line 1107 is set to a potential lower than the potential held in the capacitor 1103, the potential of the video signal is not affected.

  The erase period shown above will be described. The potential of the gate signal line 1107 is set to a potential at which the TFT 1101 is turned off. By setting the potential of the gate signal line 1107 to be equal to or higher than the potential of the power supply line 1106 or the power supply line 1106, the potential of the gate signal line 1107 is held in the capacitor 1103. Accordingly, the potential difference between the gate and the source of the TFT 1101 can be set to 0 V or higher, so that the TFT 1101 can be turned off. That is, the light-emitting element 1104 can be made to emit no light regardless of the video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Twelfth embodiment)
A configuration example of a light emitting unit that can be applied in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 12, a TFT 1201 is an N-channel transistor, and a diode 1202 is a diode having an input as a gate of the TFT 1201 and an output as a gate signal line 1207. The capacitor 1203 is a capacitor having a pair of electrodes, the light-emitting element 1204 is a light-emitting element having a pair of electrodes, and the counter electrode 1205 is the other electrode of the light-emitting element 1204. A power supply line 1206 is a power supply line for supplying power to one electrode of the light emitting element 1204 via the TFT 1201, and a gate signal line 1207 is a gate signal line for selecting whether or not writing of a video signal is possible. A line 1208 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1204 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1204.

  The power supply line 1206 is connected to one of a source and a drain of the TFT 1201, and the other of the source and the drain of the TFT 1201 is connected to one electrode of the light emitting element 1204. The gate of the TFT 1201 is connected to the signal input line 1208, one electrode of the capacitor 1203 and the input of the diode 1202, and the other electrode of the capacitor 1203 is connected to the power supply line 1206. The output of the diode 1202 is connected to the gate signal line 1207.

  The power supply line 1206 is set to a potential lower than that of the counter electrode 1205, and the signal input line 1208 inputs a video signal to the light emitting unit for writing.

  As an example, a description will be given of driving when light emission gradation is expressed using time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 1208, the video signal is set to a binary potential of H level and L level, and the video signal is held in the capacitor 1203. At this time, since the TFT 1201 operates as a switch, on / off of the TFT 1201 is controlled by a potential held in the capacitor 1203. That is, the light emission time of the light emitting element 1204 is controlled. At this time, since the gate signal line 1207 is set to a potential higher than the potential held in the capacitor 1203, the potential of the video signal is not affected.

  The erase period shown above will be described. The potential of the gate signal line 1207 is set to a potential at which the TFT 1201 is turned off. By setting the potential of the gate signal line 1207 to be equal to or lower than the potential of the power supply line 1206 or the potential of the power supply line 1206, the potential of the gate signal line 1207 is held in the capacitor 1203. Accordingly, the potential difference between the gate and the source of the TFT 1201 can be set to 0 V or less, so that the TFT 1201 can be turned off. That is, the light-emitting element 1204 can be made to emit no light regardless of the video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(13th Embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 13, TFTs 1301 and 1302 are P-channel transistors, and a capacitor 1303 and a capacitor 1304 are capacitors having a pair of electrodes. The light emitting element 1305 and the light emitting element 1306 are light emitting elements having a pair of electrodes, and the counter electrode 1307 is an electrode of the light emitting element 1305 and the light emitting element 1306. A power supply line 1308 is a power supply line that supplies power to the light emitting element 1305 via the TFT 1301 and supplies power to the light emitting element 1306 via the TFT 1302. A signal input line 1309 and a signal input line 1310 are signal lines for inputting a video signal to the light emitting unit. The light-emitting unit includes light-emitting elements 1305 and 1306 and a light-emission control circuit that controls light emission and non-light-emission of the light-emitting elements 1305 and 1306.

  The power supply line 1308 is connected to one of the source and drain of the TFT 1301 and one of the source and drain of the TFT 1302. The other of the source and drain of the TFT 1301 is connected to one electrode of the light emitting element 1305, and the other of the source and drain of the TFT 1302 is connected to one electrode of the light emitting element 1306. The gate of the TFT 1301 is connected to the signal input line 1310 and one electrode of the capacitor 1303. The gate of the TFT 1302 is connected to the signal input line 1309 and one electrode of the capacitor 1304. The other electrode of the capacitor 1303 and the other electrode of the capacitor 1304 are connected to the power supply line 1308.

  The power supply line 1308 is set to a higher potential than the counter electrode 1307, and the signal input lines 1309 and 1310 input video signals to the light emitting unit for writing.

  As an example, a description will be given of driving when light emission gradation is expressed using area gradation driving and time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 1309 and the signal input line 1310, the video signal is set to a binary potential of H level and L level, and the video signal input from the signal input line 1309 is held in the capacitor 1304, A video signal input from the input line 1310 is held in the capacitor 1303. At this time, since the TFTs 1301 and 1302 operate as switches, on / off of the TFT 1301 is controlled by the potential held in the capacitor 1303, and on / off of the TFT 1302 is controlled by the potential held in the capacitor 1304. That is, the light emission time of the light emitting element 1305 and the light emitting element 1306 is controlled.

  The erase period shown above will be described. In the erasing period, an L-level potential is held in the capacitor 1303 and the capacitor 1304 by a video signal input from the signal input line, whereby the potential difference between the gate and the source of the TFT 1301 and the TFT 1302 is about 0 V or higher. By setting the following, the TFT 1301 and the TFT 1302 can be turned off. That is, the light-emitting elements 1305 and 1306 can be made to emit no light.

  In addition, as described in the ninth embodiment, by holding the potential of the power supply line 1308 in the capacitor 1303 and the capacitor 1304, the light-emitting element 1305 and the light-emitting element 1306 can be made to emit no light. Further, as described in the eleventh embodiment, a diode is provided, the gate signal line is used as the input, the gates of the TFT 1301 and TFT 1302 are used as the output, and the potential of the gate signal line is set to the potential that turns off the TFT 1301 and TFT 1302 during the erasing period. The light emitting element 1305 and the light emitting element 1306 can be made non-light emitting.

  In this embodiment, each pixel includes a light emitting element 1305 and a light emitting element 1306 having two different light emitting areas. Therefore, when the light emission luminance of the light emitting element 1305 and the light emitting element 1306 is controlled separately, a light emission gradation higher than the light emission gradation that can be expressed by the signal input line 1309 and the signal input line 1310 can be expressed.

  Further, in the present embodiment, the configuration in the case where area gradation driving is performed using two light emitting elements is shown, but the present invention is not limited to this, and there may be a plurality of light emitting elements. Any one is acceptable. In that case, the gradation that can be expressed increases, so that the gradation can be expressed clearly.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Fourteenth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 14, TFTs 1401 and 1402 are N-channel transistors, and the capacitor element 1403 and the capacitor element 1404 are capacitor elements having a pair of electrodes. The light emitting element 1405 and the light emitting element 1406 are light emitting elements having a pair of electrodes, and the counter electrode 1407 is an electrode of the light emitting element 1405 and the light emitting element 1406. A power supply line 1408 is a power supply line that supplies power to the light emitting element 1405 via the TFT 1401 and supplies power to the light emitting element 1406 via the TFT 1402. A signal input line 1409 and a signal input line 1410 are signal lines for inputting a video signal to the light emitting unit. The light emitting unit includes light emitting elements 1405 and 1406 and a light emission control circuit that controls light emission and non-light emission of the light emitting elements 1405 and 1406.

  The power supply line 1408 is connected to one of the source and drain of the TFT 1401 and one of the source and drain of the TFT 1402. The other of the source and drain of the TFT 1401 is connected to one electrode of the light emitting element 1405. The other of the source and the drain of the TFT 1402 is connected to one electrode of the light emitting element 1406. The gate of the TFT 1401 is connected to the signal input line 1410 and one electrode of the capacitor 1403. The gate of the TFT 1402 is connected to the signal input line 1409 and one electrode of the capacitor 1404. The other electrode of the capacitor 1403 and the other electrode of the capacitor 1404 are connected to the power supply line 1408.

  The power supply line 1408 is set to a potential lower than that of the counter electrode 1407, and the signal input lines 1409 and 1410 input a video signal to the light emitting unit for writing.

  As an example, a description will be given of driving when light emission gradation is expressed using area gradation driving and time gradation driving. In the present embodiment, a driving method in which driving is performed in a writing period and an erasing period will be described. However, the present invention is not limited to this, and the light emission luminance may be changed by changing the potential of the video signal, or the current may be input as a video signal.

  The writing period shown above will be described. The video signal is input from the signal input line 1409 and the signal input line 1410, the video signal is set to a binary potential of H level (high potential) and L level (low potential), and the video signal input from the signal input line 1409 is A video signal held in the capacitor 1404 and input from the signal input line 1410 is held in the capacitor 1403. At this time, since the TFTs 1401 and 1402 operate as switches, on / off of the TFT 1401 is controlled by a potential held in the capacitor 1403, and on / off of the TFT 1402 is controlled by a potential held in the capacitor 1404. That is, the light emission time of the light emitting element 1405 and the light emitting element 1406 is controlled.

  The erase period shown above will be described. In the erasing period, the potential difference between the gate and the source of the TFT 1401 and the TFT 1402 is set to about 0 V or higher by holding the L-level potential in the capacitor 1403 and the capacitor 1404 by the video signal input from the signal input line. By setting the following, the TFT 1401 and the TFT 1402 can be turned off. That is, the light-emitting elements 1405 and 1406 can be made to emit no light.

  As described in the ninth embodiment, the light-emitting element 1405 and the light-emitting element 1406 can be made to emit no light by holding the potential of the power supply line 1408 in the capacitor 1403 and the capacitor 1404. As described in the eleventh embodiment, a diode is provided, the gate signal line is used as the input, the gates of the TFT 1401 and TFT 1402 are used as the output, and the potential of the gate signal line is set to the potential that turns off the TFT 1401 and TFT 1402 during the erasing period. The element 1405 and the light-emitting element 1406 can be made non-light-emitting.

  In this embodiment, each pixel has a light emitting element 1405 and a light emitting element 1406 having two different light emitting areas. Therefore, when the light emission luminances of the light emitting element 1405 and the light emitting element 1406 are controlled separately, a light emission gradation higher than the light emission gradation that can be expressed by the signal input line 1409 and the signal input line 1410 can be expressed.

  In this embodiment, the configuration in the case of performing area gradation driving using two light emitting elements is shown, but the present invention is not limited to this. Since the number of gradations that can be expressed according to the number of light-emitting elements increases, the gradation can be expressed clearly.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Fifteenth embodiment)
A structural example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 15, a TFT 1501 is a P-channel transistor, and a switch 1502 and a switch 1503 are switches that are turned on or off by a gate signal line 1511. A switch 1504 is a switch that is turned on or off by a gate signal line 1512. A capacitor 1505 and a capacitor 1506 are capacitors each having a pair of electrodes. The light-emitting element 1507 is a light-emitting element having a pair of electrodes, the counter electrode 1508 is one electrode of the light-emitting element 1507, and the power supply line 1509 supplies power to one electrode of the light-emitting element 1507 through the switch 1504 and the TFT 1501. It is a power line. The power supply line 1510 is a power supply line for supplying a reference potential, and the gate signal line 1511 is a signal line for controlling the switch 1502 and the switch 1503. The gate signal line 1512 is a signal line for controlling the switch 1504, and the signal input line 1513 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1507 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1507.

  The power supply line 1509 is connected to one terminal of the switch 1504 and one electrode of the capacitor 1506. The other terminal of the switch 1504 is connected to one of the source and drain of the TFT 1501 and one terminal of the switch 1502. The other of the source and drain of the TFT 1501 is connected to one electrode of the light emitting element 1507. The gate of the TFT 1501 is connected to one electrode of the capacitor 1505 and one terminal of the switch 1503. The other terminal of the switch 1503 is connected to the power supply line 1510. The other terminal of the switch 1502 is connected to the other electrode of the capacitor 1506, the other electrode of the capacitor 1505, and the signal input line 1513. The switch 1502 and the switch 1503 are controlled to be turned on / off by the gate signal line 1511, and the switch 1504 is controlled to be turned on / off by the gate signal line 1512.

  The power supply line 1509 is set to a potential higher than that of the counter electrode 1508, the power supply line 1510 is set to an arbitrary constant potential, and the signal input line 1513 inputs a video signal to the light emitting unit for writing. The video signal is input as a voltage.

  Since the driving method of this embodiment is divided into a threshold voltage acquisition period, a video signal writing period, and a light emission period, the operation in each period is described below.

  The operation of this embodiment during the threshold voltage acquisition period will be described. First, a video signal is not input from the signal input line 1513, the switch 1502 and the switch 1503 are turned on, and the switch 1504 is turned off. Here, one electrode of the capacitor 1505 becomes the potential of the power supply line 1510, and the other electrode of the capacitor 1505 and the other electrode of the capacitor 1506 have the potential of the sum of the potential of the power supply line 1510 and the threshold voltage of the TFT 1501. Become.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 1513, the switch 1502 and the switch 1503 are turned off, and the switch 1504 is turned off. Here, the other electrode of the capacitor 1505 becomes a potential input from the signal input line 1513, and one electrode of the capacitor 1505 subtracts the threshold voltage of the TFT 1501 from the sum of the potential of the power supply line 1510 and the potential of the video signal. Potential.

  The operation of the present embodiment during the light emission period will be described. First, since no video signal is input from the signal input line 1513, the switch 1502 and the switch 1503 are turned off, and the switch 1504 is turned on, the potential of one electrode of the capacitor 1505 is held. Here, one electrode of the capacitor 1505 has a potential obtained by subtracting the threshold voltage of the TFT 1501 from the sum of the potential of the power supply line 1510 and the potential of the video signal. When a current corresponding to the potential between the light source and the source flows through the light emitting element 1507, the light emitting element 1507 can emit light.

  The gradation expression is performed by controlling the current flowing through the light emitting element 1507 by determining the potential between the gate and the source of the TFT 1501 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Sixteenth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 16, a TFT 1601 is a P-channel TFT, a switch 1602 is a switch whose on / off is controlled by a gate signal line 1610, and a switch 1603 is a switch whose on / off is controlled by a gate signal line 1609. It is. The capacitor 1604 and the capacitor 1605 are capacitors having a pair of electrodes, the light-emitting element 1606 is a light-emitting element having a pair of electrodes, and the counter electrode 1607 is one electrode of the light-emitting element 1606. A power supply line 1608 is a power supply line that supplies power to one electrode of the light emitting element 1606 via the TFT 1601 and the switch 1602. A gate signal line 1609 is a signal line for controlling the switch 1603, a gate signal line 1610 is a signal line for controlling the switch 1602, and a signal input line 1611 is a signal for inputting a video signal to the light emitting unit. Is a line. The light emitting unit includes a light emitting element 1606 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1606.

  The power supply line 1608 is connected to one of a source and a drain of the TFT 1601 and one electrode of the capacitor 1604. The other of the source and the drain of the TFT 1601 is connected to one terminal of the switch 1602 and one terminal of the switch 1603. The gate of the TFT 1601 is connected to the other electrode of the capacitor 1604, one electrode of the capacitor 1605, and the other terminal of the switch 1603. The other terminal of the switch 1602 is connected to one electrode of the light emitting element 1606. The other electrode of the capacitor 1605 is connected to the signal input line 1611. The switch 1602 is controlled to be turned on / off by the gate signal line 1610, and the switch 1603 is controlled to be turned on / off by the gate signal line 1609.

  The power supply line 1608 is set to a potential higher than that of the counter electrode 1607, and the signal input line 1611 inputs a video signal to the light emitting unit for writing. The video signal is input as a voltage.

  Since the driving method of this embodiment is divided into a threshold voltage acquisition period, a video signal writing period, and a light emission period, the operation in each period is described below.

  The operation of this embodiment during the threshold voltage acquisition period will be described. First, a video signal is not input from the signal input line 1611, and the switch 1602 and the switch 1603 are turned off. Here, the other electrode of the capacitor 1604 and the one electrode of the capacitor 1605 have a potential obtained by subtracting the threshold voltage of the TFT 1601 from the potential of the power supply line 1608.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 1611, the switch 1602 is turned off, and the switch 1603 is turned on. Here, the other electrode of the capacitor 1605 becomes the potential of the input video signal, and the other electrode of the capacitor 1604 and one electrode of the capacitor 1605 are calculated from the sum of the potential of the power supply line 1608 and the potential of the video signal. This is a potential obtained by subtracting the threshold voltage of the TFT 1601.

  The operation of the present embodiment during the light emission period will be described. First, since a video signal is not input from the signal input line 1611 and the switch 1602 and the switch 1603 are off, the potential of the other electrode of the capacitor 1604 and the one electrode of the capacitor 1605 is held. . Here, the other electrode of the capacitor 1604 and the one electrode of the capacitor 1605 have a potential obtained by subtracting the threshold voltage of the TFT 1601 from the sum of the potential of the power supply line 1608 and the potential of the video signal. Therefore, the light-emitting element 1606 can emit light when a current corresponding to the potential between the gate and the source corrected for variation in the threshold voltage of the TFT 1601 flows to the light-emitting element 1606.

  The gradation expression is performed by controlling the current flowing through the light emitting element 1606 by determining the potential between the gate and the source of the TFT 1601 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Seventeenth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 17, a TFT 1701 is a P-channel transistor, a switch 1702 is a switch whose on / off is controlled by a gate signal line 1708, and a switch 1703 is a switch whose on / off is controlled by a gate signal line 1709. is there. The capacitor 1704 is a capacitor having a pair of electrodes, the light-emitting element 1705 is a light-emitting element having a pair of electrodes, and the counter electrode 1706 is an electrode of the light-emitting element 1705. A power supply line 1707 is a power supply line for supplying power to one electrode of the light emitting element 1705 via the switch 1702 and the TFT 1701. A gate signal line 1708 is a signal line for controlling the switch 1702, a gate signal line 1709 is a signal line for controlling the switch 1703, and a signal input line 1710 is a signal for inputting a video signal to the light emitting unit. Is a line. The light emitting unit includes a light emitting element 1705 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1705.

  The power supply line 1707 is connected to one terminal of the switch 1702. The other terminal of the switch 1702 is connected to one of the source and drain of the TFT 1701, one electrode of the capacitor 1704, and the signal input line 1710. The other of the source and drain of the TFT 1701 is connected to one electrode of the light emitting element 1705 and one terminal of the switch 1703. The gate of the TFT 1701 is connected to the other electrode of the capacitor 1704 and the other terminal of the switch 1703. The switch 1702 is controlled to be turned on / off by a gate signal line 1708, and the switch 1703 is controlled to be turned on / off by a gate signal line 1709.

  The power supply line 1707 is set to a potential higher than that of the counter electrode 1706, and the signal input line 1710 inputs a video signal to the light emitting unit for writing. Also, the video signal is input as a current.

  Since the driving method of this embodiment is divided into the video signal writing period and the light emission period, the operation in each period is described below.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 1710, the switch 1702 is turned off, and the switch 1703 is turned on. Here, the capacitor 1704 holds a potential corresponding to the input video signal. Further, since the video signal is input as a current, the current flowing through the light-emitting element 1705 is not affected by the variation in the threshold voltage of the TFT 1701.

  The operation of the present embodiment during the light emission period will be described. First, a video signal is not input from the signal input line 1710, the switch 1702 is turned on, and the switch 1703 is turned off. Here, since the potential of the power supply line 1707 is applied to one electrode of the capacitor 1704 and one of the source and drain of the TFT 1701, the potential of the other electrode of the capacitor 1704 is held. Here, since the other electrode of the capacitor 1704 holds the potential written in the video signal writing period, a current corresponding to the potential between the gate and the source in which the variation of the threshold voltage of the TFT 1701 is corrected is a light emitting element. By flowing to 1705, the light emitting element 1705 can emit light.

  The gradation expression is performed by controlling the current flowing through the light emitting element 1705 by determining the potential between the gate and the source of the TFT 1701 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Eighteenth embodiment)
A configuration example of a light emitting unit that can be applied in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 18, a TFT 1801 is a P-channel transistor, a switch 1802 is a switch that is turned on or off by a gate signal line 1809, and a switch 1803 is a switch that is turned on or off by a gate signal line 1808. It is. The capacitor 1804 is a capacitor having a pair of electrodes, the light-emitting element 1805 is a light-emitting element having a pair of electrodes, and the counter electrode 1806 is the other electrode of the light-emitting element 1805. A power supply line 1807 is a power supply line that supplies power to one electrode of the light emitting element 1805 via the TFT 1801 and the switch 1802. A gate signal line 1808 is a signal line for controlling the switch 1803, a gate signal line 1809 is a signal line for controlling the switch 1802, and a signal input line 1810 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1805 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1805.

  The power supply line 1807 is connected to one of the source and drain of the TFT 1801 and one electrode of the capacitor 1804. The other of the source and the drain of the TFT 1801 is connected to one terminal of the switch 1802, one terminal of the switch 1803, and the signal input line 1810. The other terminal of the switch 1802 is connected to one electrode of the light emitting element 1805. The gate of the TFT 1801 is connected to the other electrode of the capacitor 1804 and the other terminal of the switch 1803. The switch 1802 is controlled to be turned on and off by the gate signal line 1809. The switch 1803 is controlled to be turned on and off by the gate signal line 1808.

  The power supply line 1807 is set to a higher potential than the counter electrode 1806, and the signal input line 1810 inputs a video signal to the light-emitting unit that performs writing. Also, the video signal is input as a current.

  Since the driving method of this embodiment is divided into the video signal writing period and the light emission period, the operation in each period is described below.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 1810, the switch 1802 is turned off, and the switch 1803 is turned on. Here, the capacitor 1804 holds a potential corresponding to the input video signal. Further, since the video signal is input as a current, the current flowing through the light-emitting element 1805 is not affected by variations in the threshold voltage of the TFT 1801.

  The operation of the present embodiment during the light emission period will be described. First, a video signal is not input from the signal input line 1810, the switch 1802 is turned on, and the switch 1803 is turned off. Here, the potential of the power supply line 1807 is applied to one electrode of the capacitor 1804 and one of the source and the drain of the TFT 1801, and thus the potential of the other electrode of the capacitor 1804 is held. Here, since the other electrode of the capacitor 1804 holds the potential written in the video signal writing period, a current corresponding to the potential between the gate and the source in which variation in the threshold voltage of the TFT 1801 is corrected is a light emitting element. By flowing through 1805, the light emitting element 1805 can emit light.

  The gradation expression is performed by controlling the current flowing through the light emitting element 1805 by determining the potential between the gate and the source of the TFT 1801 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Nineteenth embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 19, a TFT 1901 is a P-channel transistor, a switch 1902 is a switch whose on / off is controlled by a gate signal line 1908, and a switch 1903 is a switch whose on / off is controlled by a gate signal line 1909. It is. The capacitor 1904 is a capacitor having a pair of electrodes, the light-emitting element 1905 is a light-emitting element having a pair of electrodes, and the counter electrode 1906 is the other electrode of the light-emitting element 1905. A power supply line 1907 is a power supply line for supplying power to one electrode of the light emitting element 1905 via the TFT 1901 and the switch 1903. A gate signal line 1908 is a signal line for controlling the switch 1902, a gate signal line 1909 is a signal line for controlling the switch 1903, and a signal input line 1910 is a signal line for inputting a video signal to the light emitting unit. The light emitting unit includes a light emitting element 1905 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 1905.

  The power supply line 1907 is connected to one of the source and drain of the TFT 1901. The other of the source and the drain of the TFT 1901 is connected to one terminal of the switch 1903 and one terminal of the switch 1902. The other terminal of the switch 1903 is connected to one electrode of the light emitting element 1905. The gate of the TFT 1901 is connected to the other terminal of the switch 1902 and one electrode of the capacitor 1904. The other electrode of the capacitor 1904 is connected to the signal input line 1910. The switch 1902 is controlled to be turned on and off by the gate signal line 1908. The switch 1903 is controlled to be turned on and off by the gate signal line 1909.

  The power supply line 1907 is set to a potential higher than that of the counter electrode 1906, and the signal input line 1910 inputs a video signal to the light emitting unit that performs writing. The video signal is input as a voltage.

  Since the driving method of this embodiment is divided into a threshold voltage acquisition period, a video signal writing period, and a light emission period, the operation in each period is described below.

  The operation of this embodiment during the threshold voltage acquisition period and the video signal writing period will be described. First, a video signal is input from the signal input line 1910, the switch 1902 is turned on, and the switch 1903 is turned off. Here, one electrode of the capacitor 1904 has a potential obtained by subtracting the threshold voltage of the TFT 1901 from the potential of the power supply line 1907. The other electrode of the capacitor 1904 becomes a potential of the video signal.

  The operation of the present embodiment during the light emission period will be described. First, a triangular wave is input from the signal input line 1910, the switch 1902 is turned off, and the switch 1903 is turned on. Here, one electrode of the capacitor 1904 has a difference between a potential obtained by subtracting a threshold voltage of the TFT 1901 from a potential of the power supply line 1907 and a potential of the signal input line 1910; therefore, input is performed during the threshold voltage acquisition period and the video signal writing period. The light emission time varies depending on the potential of the video signal.

  The gradation expression is performed by controlling the current flowing through the light emitting element 1905 by determining the potential between the gate and the source of the TFT 1901 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(20th embodiment)
A configuration example of a light emitting unit that can be applied in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 20, TFTs 2001 and 2002 are P-channel transistors, and a switch 2003 is a switch that is turned on or off by a gate signal line 2008. The capacitor element 2004 is a capacitor element having a pair of electrodes, the light emitting element 2005 is a light emitting element having a pair of electrodes, and the counter electrode 2006 is the other electrode of the light emitting element 2005. A power supply line 2007 is a power supply line for supplying power to one electrode of the light emitting element 2005 via the TFT 2001, a gate signal line 2008 is a signal line for controlling the switch 2003, and a signal input line 2009 inputs a video signal. Signal line. The light emitting unit includes a light emitting element 2005 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 2005.

  The power supply line 2007 is connected to one of the source and drain of the TFT 2001, one of the source and drain of the TFT 2002, and one electrode of the capacitor 2004. The other of the source and drain of the TFT 2001 is connected to one electrode of the light emitting element 2005. The other of the source and the drain of the TFT 2002 is connected to one terminal of the switch 2003 and the signal input line 2009. The gate of the TFT 2001 is connected to the gate of the TFT 2002, the other electrode of the capacitor 2004, and the other terminal of the switch 2003. The switch 2003 is controlled to be turned on and off by the gate signal line 2008.

  The power supply line 2007 is set to a potential higher than that of the counter electrode 2006, and the signal input line 2009 inputs a video signal to the light emitting unit for writing. Also, the video signal is input as a current.

  Since the driving method of this embodiment is divided into the video signal writing period and the light emission period, the operation in each period is described below.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 2009, and the switch 2003 is turned on. Here, the capacitor element 2004 holds a potential corresponding to the input video signal. In addition, since the video signal is input as a current, the current flowing through the light emitting element 2005 is not affected by the variation in the threshold voltage of the TFT 2002.

  The operation of the present embodiment during the light emission period will be described. First, since no video signal is input from the signal input line 2009 and the switch 2003 is off, the potential of the other electrode of the capacitor 2004 is held. Here, since the other electrode of the capacitor 2004 holds the potential written in the video signal writing period, variation in the threshold voltage of the TFT 2002 is corrected. In addition, one of the gate of TFT 2001, the gate of TFT 2002, and the source and drain of the TFT 2002 is common, and if the threshold voltage of TFT 2001 and TFT 2002 is the same, the difference between the threshold voltage of TFT 2001 is corrected between the gate and the source. The light emitting element 2005 can emit light when a current corresponding to the potential of the current flows to the light emitting element 2005.

  The gradation expression is performed by controlling the current flowing through the light-emitting element 2005 by determining the potential between the gate and the source of the TFT 2001 and the TFT 2002 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(21st Embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 21, a TFT 2101 is an N-channel transistor, and a switch 2102 is a switch whose gate signal line 2107 is controlled to be turned on or off. The capacitor 2103 is a capacitor having a pair of electrodes, the light emitting element 2104 is a light emitting element having a pair of electrodes, and the counter electrode 2105 is a counter electrode which is an electrode of the light emitting element 2104. The power supply line 2106 is a power supply line for supplying power to one electrode of the light emitting element 2104 via the TFT 2101, the gate signal line 2107 is a signal line for controlling the switch 2102, and the signal input line 2108 is connected to the light emitting unit. It is a signal line for inputting a video signal. The light emitting unit includes a light emitting element 2104 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 2104.

  The power supply line 2106 is connected to one of the source and the drain of the TFT 2101 and one terminal of the switch 2102. The other of the source and the drain of the TFT 2101 is connected to one electrode of the light emitting element 2104, one electrode of the capacitor 2103, and the signal input line 2108. The gate of the TFT 2101 is connected to the other terminal of the switch 2102 and the other electrode of the capacitor 2103, and the switch 2102 is controlled to be turned on and off by the gate signal line 2107.

  The power supply line 2106 is set to a potential lower than that of the counter electrode 2105, and the signal input line 2108 inputs a video signal to the light emitting unit that performs writing. Also, the video signal is input as a current.

  Since the driving method of this embodiment is divided into the video signal writing period and the light emission period, the operation in each period is described below.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 2108, and the switch 2102 is turned on. Here, the capacitor 2103 holds a potential corresponding to the input video signal. Further, since the video signal is input as a current, the current flowing through the light-emitting element 2104 is not affected by variations in the threshold voltage of the TFT 2101.

  The operation of the present embodiment during the light emission period will be described. First, since no video signal is input from the signal input line 2108 and the switch 2102 is off, the potential of the other electrode of the capacitor 2103 is held. Here, since the other electrode of the capacitor 2103 has a potential held in the video signal writing period, a current corresponding to the potential between the gate and the source in which the variation in threshold voltage of the TFT 2101 is corrected is supplied to the light emitting element 2104. The light emitting element 2104 can emit light by flowing.

  The gradation expression is performed by controlling the current flowing through the light emitting element 2104 by determining the potential between the gate and the source of the TFT 2101 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(Twenty-second embodiment)
A configuration example of a light emitting unit that can be applied in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 22, a TFT 2201 is an N-channel transistor, and a switch 2202 is a switch whose gate signal line 2207 is controlled to be turned on or off. The capacitor 2203 is a capacitor having a pair of electrodes, the light emitting element 2204 is a light emitting element having a pair of electrodes, and the counter electrode 2205 is a counter electrode which is an electrode of the light emitting element 2204. A power supply line 2206 is a power supply line for supplying power to one electrode of the light emitting element 2204 via the TFT 2201, a gate signal line 2207 is a signal line for controlling the switch 2202, and a signal input line 2208 is connected to the light emitting unit. It is a signal line for inputting a video signal. The light-emitting unit includes a light-emitting element 2204 and a light-emission control circuit that controls light emission and non-light emission of the light-emitting element 2204.

  The power supply line 2206 is connected to one of the source and drain of the TFT 2201 and one terminal of the switch 2202. The other of the source and the drain of the TFT 2201 is connected to one electrode of the light emitting element 2204 and one electrode of the capacitor 2203. The gate of the TFT 2201 is connected to the other terminal of the switch 2202, the other electrode of the capacitor 2203, and the signal input line 2208. The switch 2202 is controlled to be turned on and off by the gate signal line 2207.

  The power supply line 2206 is set to a potential lower than that of the counter electrode 2205, and the signal input line 2208 inputs a video signal to the light emitting unit for writing. The video signal is input as a voltage.

  Since the driving method of this embodiment is divided into a threshold voltage acquisition period, a video signal writing period, and a light emission period, the operation in each period is described below.

  The operation of this embodiment during the threshold voltage acquisition period will be described. First, the switch 2202 is turned on with no video signal being sent from the signal input line 2208. Here, the threshold voltage of the TFT 2201 is held between the other electrode of the capacitor 2203 and the other electrode of the light emitting element 2204.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 2208, and the switch 2202 is off. Here, the other electrode of the capacitor 2203 has a potential obtained by subtracting the threshold voltage of the TFT 2201 from the potential of the video signal.

  The operation of the present embodiment during the light emission period will be described. First, since no video signal is input from the signal input line 2208 and the switch 2202 is off, the potential of the other electrode of the capacitor 2203 is held. Here, since the potential of the other electrode of the capacitor 2203 is a potential obtained by subtracting the threshold voltage of the TFT 2201 from the sum of the potential of the counter electrode 2205 and the potential of the video signal, the gate and the source corrected for variations in the threshold voltage of the TFT 2201 A current according to the current flows through the light emitting element 2204, whereby the light emitting element 2204 can emit light.

  The gradation expression is performed by controlling the current flowing through the light emitting element 2204 by determining the potential between the gate and the source of the TFT 2201 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(23rd embodiment)
A configuration example of a light emitting unit applicable in the first to sixth embodiments will be described with reference to FIG.

  In FIG. 23, TFTs 2301 and 2302 are N-channel transistors, and a switch 2303 is a switch whose gate signal line 2308 is controlled to be turned on or off. The capacitor 2304 is a capacitor having a pair of electrodes, the light emitting element 2305 is a light emitting element having a pair of electrodes, and the counter electrode 2306 is the other electrode of the light emitting element 2305. A power supply line 2307 is a power supply line for supplying power to one electrode of the light emitting element 2305 via the TFT 2301, a gate signal line 2308 is a signal line for controlling the switch 2303, and a signal input line 2309 inputs a video signal. Signal line. The light emitting unit includes a light emitting element 2305 and a light emission control circuit that controls light emission and non-light emission of the light emitting element 2305.

  The power supply line 2307 is connected to one of the source and drain of the TFT 2301. The other of the source and drain of the TFT 2301 is connected to one electrode of the light emitting element 2305 and the other of the source and drain of the TFT 2302. The gate of the TFT 2301 is connected to the gate of the TFT 2302, one electrode of the capacitor 2304, the signal input line 2309, and one terminal of the switch 2303. One of the source and drain of the TFT 2302 is connected to the other terminal of the switch 2303. The switch 2303 is controlled to be turned on and off by the gate signal line 2308.

  The power supply line 2307 is set to a potential higher than that of the counter electrode 2306, and the signal input line 2309 inputs a video signal to the light emitting unit that performs writing. Also, the video signal is input as a current.

  Since the driving method of this embodiment is divided into the video signal writing period and the light emission period, the operation in each period is described below.

  The operation of this embodiment during the video signal writing period will be described. First, a video signal is input from the signal input line 2309, and the switch 2303 is turned on. Here, the capacitor 2304 holds a potential corresponding to the input video signal. In addition, since the video signal is input as a current, the current flowing through the light emitting element 2304 is not affected by variations in the threshold voltage of the TFT 2302.

  The operation during the light emission period will be described. First, since no video signal is input from the signal input line 2309 and the switch 2303 is off, the potential of the other electrode of the capacitor 2304 is held. Here, since the other electrode of the capacitor 2304 holds the potential written in the video signal writing period, variation in the threshold voltage of the TFT 2302 is corrected. Further, one of the gate of the TFT 2301, the gate, the source and the drain of the TFT 2302 is common, and if the threshold voltages of the TFT 2301 and the TFT 2302 are the same, the difference between the threshold voltage of the TFT 2301 and the gate and the source corrected. The light emitting element 2305 can emit light when a current corresponding to the potential of the current flows to the light emitting element 2305.

  The gradation expression is performed by controlling the current flowing through the light emitting element 2305 by determining the potential between the gate and the source of the TFT 2301 in accordance with the input video signal.

  The light emitting unit according to this embodiment includes a light emitting unit 104 shown in FIG. 1, a light emitting unit 204 shown in FIG. 2, a light emitting unit 304 shown in FIG. 3, a light emitting unit 404 shown in FIG. 4, a light emitting unit 504 shown in FIG. It can be applied as the light emitting unit 604 shown in FIG. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

(24th Embodiment)
In the present invention, as described in the first to sixth embodiments, a source signal line is provided with a switch or a TFT functioning as a switch. Therefore, the configuration of the pixel can be similarly applied as long as a video signal is supplied through the source signal line in addition to the pixels described in the seventh to 23rd embodiments. Further, the present invention can be applied to a liquid crystal display or the like that outputs voltage and current having amplitude from a source signal line.

  The switches provided in the source signal lines use n-channel transistors or p-channel transistors in the third to sixth embodiments, but may be analog switches.

  Although an example using a transistor as an example of a switching element has been shown, the present invention is not limited to this. The switching element may be an electrical switch or a mechanical switch as long as it can control the flow of current. As the switching element, a diode may be used, or a logic circuit combining a diode and a transistor may be used.

  In the present invention, there is no limitation on the type of transistor that can be used as a switching element, and a TFT, a semiconductor substrate, or an SOI substrate using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon is used. A formed MOS transistor can be applied. In addition, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, and other transistors can be used. There is no limitation on the type of the substrate over which the transistor is formed, and a single crystal substrate, an SOI substrate, a quartz substrate, a glass substrate, a resin substrate, or the like can be used freely.

  Since the transistor operates as a simple switching element, the polarity (conductivity type) is not particularly limited, and may be either an N-type transistor or a P-type transistor. However, in the case where it is desirable that the off-state current is small, it is desirable to use a transistor having characteristics with a small off-state current. As a transistor with low off-state current, there is a transistor in which a region to which an impurity element imparting a conductivity type is added at a low concentration (referred to as an LDD region) is provided between a channel formation region and a source or drain region.

  In the case where the transistor operates in a state in which the potential of the source of the transistor is close to a low-potential-side power supply, the transistor is preferably N-type. On the other hand, when the transistor operates in a state where the source potential is close to the high-potential side power supply, the transistor is preferably P-type. With such a structure, the absolute value of the voltage between the gate and the source of the transistor can be increased, so that the transistor can be easily operated as a switch. Note that a CMOS switching element may be formed using both an N-type transistor and a P-type transistor.

  In the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth actual child form, and the sixth embodiment, the circuit configuration in the block diagram is the text. Any circuit configuration is possible as long as the driving described above can be performed.

  In this embodiment, an example of a structure of a light emitting unit including a transistor and a light emitting element will be described. The structure of this embodiment can be applied to the light emitting unit shown in FIGS.

  7 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  8 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  9 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  10 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  11 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  12 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  The signal input line 1309 or the signal input line 1310 in FIG. 13 includes the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. This corresponds to the source signal line 507 and the source signal line 607 in FIG.

  The signal input line 1409 or the signal input line 1410 in FIG. 14 includes the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. This corresponds to the source signal line 507 and the source signal line 607 in FIG.

  15 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  16 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  17 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  18 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  19 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  20, the signal input line 2009 includes the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  21 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  22 includes a source signal line 107 in FIG. 1, a source signal line 207 in FIG. 2, a source signal line 307 in FIG. 3, a source signal line 407 in FIG. 4, a source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  23 are the source signal line 107 in FIG. 1, the source signal line 207 in FIG. 2, the source signal line 307 in FIG. 3, the source signal line 407 in FIG. 4, the source signal line 507 in FIG. This corresponds to the source signal line 607 in FIG.

  The other wirings shown in FIGS. 7 to 23 are not shown in FIGS.

  In FIG. 24A, as the substrate 2400, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic may be used. The surface of the substrate 2400 may be planarized by polishing such as a CMP method.

  As the base film 2401, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used. The base film 2401 can prevent alkali metal such as Na or alkaline earth metal contained in the substrate 2400 from diffusing into the semiconductor layer 2402 and adversely affecting the characteristics of the TFT 2410. In FIG. 24, the base film 2401 has a single-layer structure, but it may be formed of two or more layers. Note that the base film 2401 is not necessarily provided when the diffusion of impurities such as a quartz substrate is not a problem.

  As the semiconductor layer 2402 and the semiconductor layer 2412, a patterned crystalline semiconductor film or amorphous semiconductor film can be used. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film. As a crystallization method, a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like can be used. The semiconductor layer 2402 includes a channel formation region and a pair of impurity regions to which an impurity element imparting a conductivity type is added. Note that an impurity region to which an impurity element is added at a low concentration may be provided between the channel formation region and the pair of impurity regions. The semiconductor layer 2412 can have a structure in which an impurity element imparting a conductivity type is added to the whole.

  As the first insulating film 2403, silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used, and a single layer or a plurality of films can be stacked.

  Note that a film containing hydrogen may be used as the first insulating film 2403 and the semiconductor layer 2402 may be hydrogenated.

  As the gate electrode 2404 and the electrode 2414, a single layer or a stacked structure formed using one kind of element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy or a compound containing a plurality of such elements is used. it can.

  The TFT 2410 includes a semiconductor layer 2402 and a gate electrode 2404, and a first insulating film 2403 between the semiconductor layer 2402 and the gate electrode 2404. In FIG. 24, only the TFT 2410 connected to the first electrode 2407 of the light-emitting element 2415 is shown as a TFT constituting the pixel; however, a structure having a plurality of TFTs may be used. In this embodiment, the TFT 2410 is shown as a top gate type transistor. However, a bottom gate type transistor having a gate electrode below the semiconductor layer may be used, or a dual gate electrode having a gate electrode above and below the semiconductor layer. It may be a gate type transistor.

  The capacitor 2411 includes a first insulating film 2403 as a dielectric, and a semiconductor layer 2412 and an electrode 2414 facing each other with the first insulating film 2403 interposed therebetween as a pair of electrodes. In FIG. 24, as a capacitor element, one of a pair of electrodes is a semiconductor layer 2412 formed at the same time as the semiconductor layer 2402 of the TFT 2410, and the other electrode is an electrode 2414 formed at the same time as the gate electrode 2404 of the TFT 2410. Although an example is shown, the present invention is not limited to this configuration.

  As the second insulating film 2405, a single layer or a stacked layer of an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, polyamide, BCB (benzoic acid) is used. A film such as cyclobutene), acrylic or positive photosensitive organic resin, or negative photosensitive organic resin can be used.

  For the second insulating film 2405, a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O) can be used. As a substituent of this material, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

Note that the surface of the second insulating film 2405 may be nitrided by treatment with high-density plasma. The high density plasma is generated by using a high frequency microwave, for example 2.45 GHz. Note that the high-density plasma has an electron density of 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and an electron temperature of 0.2 eV to 2.0 eV (more preferably 0.5 eV to 1. 5 eV or less) is used. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects than conventional plasma treatment. In the high-density plasma treatment, the substrate 2400 is set to a temperature of 350 ° C. to 450 ° C. In the apparatus for generating high-density plasma, the distance from the antenna that generates microwaves to the substrate 2400 is set to 20 nm to 80 mm (preferably 20 nm to 60 mm).

In an atmosphere of nitrogen and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or a nitrogen atmosphere such as nitrogen and hydrogen and a rare gas atmosphere, or NH ₃ and a rare gas atmosphere High density plasma treatment is performed to nitride the surface of the second insulating film 2405. Nitrogen and elements of He, Ne, Ar, Kr, and Xe are mixed in the surface of the second insulating film 2405 formed by nitriding treatment with high-density plasma. For example, a silicon oxide film or a silicon oxynitride film is used as the second insulating film 2405, and the surface of the film is processed with high-density plasma to form a silicon nitride film. Hydrogen contained in the silicon nitride film formed in this manner may be used to hydrogenate the semiconductor layer 2402 of the TFT 2410. Note that the hydrogenation treatment may be combined with the hydrogenation treatment using hydrogen in the first insulating film 2403 described above.

  Note that a second insulating film 2405 may be formed by further forming an insulating film over the nitride film formed by the high-density plasma treatment.

  As the electrode 2406, a single layer or a laminated structure made of one kind of element selected from Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements is used. it can.

  One or both of the first electrode 2407 and the second electrode 2417 can be a transparent electrode. As the transparent electrode, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like can be used. Needless to say, indium tin oxide (ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can also be used.

  The light emitting layer is preferably formed using a plurality of layers having different functions, such as a hole injecting and transporting layer, a light emitting layer, and an electron injecting and transporting layer.

  The hole injecting and transporting layer is preferably formed of a composite material including a hole transporting organic compound material and an inorganic compound material that exhibits an electron accepting property with respect to the organic compound material. By adopting such a configuration, many hole carriers are generated in an organic compound that has essentially no intrinsic carrier, and extremely excellent hole injecting and transporting properties can be obtained. Due to this effect, the drive voltage can be made lower than in the prior art. In addition, since the hole injecting and transporting layer can be thickened without causing an increase in driving voltage, a short circuit of the light emitting element due to dust or the like can be suppressed.

  As a hole-transporting organic compound material, 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 1,3,5- Tris [N, N-di (m-tolyl) amino] benzene (abbreviation: m-MTDAB), N, N′-diphenyl-N, N′-bis (3-methylphenyl) -1,1′-biphenyl- 4,4′-diamine (abbreviation: TPD), 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), and the like, but are not limited thereto. There is no.

  Examples of the inorganic compound material that exhibits electron acceptability include titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, and zinc oxide. Vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are particularly preferable because they can be vacuum-deposited and are easy to handle.

The electron injecting and transporting layer is formed using an organic compound material having an electron transporting property. Specific examples include tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), and the like, but are not limited thereto. .

The light-emitting layer is composed of 9,10-di (2-naphthyl) anthracene (abbreviation: DNA), 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4,4 ′. -Bis (2,2-diphenylvinyl) biphenyl (abbreviation: DPVBi), coumarin 30, coumarin 6, coumarin 545, coumarin 545T, perylene, rubrene, periflanthene, 2,5,8,11-tetra (tert-butyl) perylene (Abbreviation: TBP), 9,10-diphenylanthracene (abbreviation: DPA), 5,12-diphenyltetracene, 4- (dicyanomethylene) -2-methyl- [p- (dimethylamino) styryl] -4H-pyran ( Abbreviations: DCM1), 4- (dicyanomethylene) -2-methyl-6- [2- (julolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCM2), 4- (dicyanomethylene) -2,6-bis [p- (dimethylamino) styryl] -4H-pyran (abbreviation: BisDCM), and the like. In addition, bis [2- (4 ′, 6′-difluorophenyl) pyridinato-N, C ^{2 ′} ] iridium (picolinate) (abbreviation: FIrpic), bis {2- [3 ′, 5′-bis (trifluoromethyl) ) Phenyl] pyridinato-N, C ^{2 ′} } iridium (picolinate) (abbreviation: Ir (CF ₃ ppy) ₂ (pic)), tris (2-phenylpyridinato-N, C ^{2 ′} ) iridium (abbreviation: Ir (Ppy) ₃ ), bis (2-phenylpyridinato-N, C ^{2 ′} ) iridium (acetylacetonate) (abbreviation: Ir (ppy) ₂ (acac)), bis [2- (2′-thienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) _{(abbreviation: Ir (thp) 2 (acac} )), bis (2-phenylquinolinato--N, C ^2') iridium (Asechirua Tonato) _{(abbreviation: Ir (pq) 2 (acac} )), bis [2- (2'-benzothienyl) pyridinato -N, C ^{3 ']} iridium (acetylacetonate) (abbreviation: Ir _(btp) 2 (acac A compound capable of emitting phosphorescence such as)) can also be used.

  In addition, examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

An inorganic material can be used as a base material for forming the light emitting layer. As the inorganic material, a sulfide, oxide, or nitride of a metal material such as zinc, cadmium, or gallium is preferably used. For example, as sulfides, zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), barium sulfide (BaS) or the like can be used. As the oxide, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used, such as calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). Ternary mixed crystals such as ₂ S ₄ ).

  As an impurity element, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (as a light emitting center utilizing inner-shell electronic transition of a metal ion) Metal elements such as Tm), europium (Eu), cerium (Ce), and praseodymium (Pr) can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

  In addition, a light-emitting material including a first impurity element and a second impurity element can be used as a light-emission center using donor-acceptor recombination. As the first impurity element, for example, a metal element such as copper (Cu), silver (Ag), gold (Au), platinum (Pt), silicon (Si), or the like can be used. Examples of the second impurity element include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium. (Tl) or the like can be used.

  The luminescent material is a solid phase reaction, that is, a base material and an impurity element are weighed, mixed in a mortar, heated in an electric furnace, and reacted to cause the base material to contain the impurity element. For example, the base material, the first impurity element or the compound containing the first impurity element, and the second impurity element or the compound containing the second impurity element are weighed and mixed in a mortar, Heat and fire. The firing temperature is preferably 700 to 1500 ° C. This is because the solid reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

In addition, as an impurity element in the case of using a solid phase reaction, a compound composed of a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. Examples of the compound composed of the first impurity element and the second impurity element include copper fluoride (CuF ₂ ), copper chloride (CuCl), copper iodide (CuI), copper bromide (CuBr), and nitride Copper (Cu ₃ N), copper phosphide (Cu ₃ P), silver fluoride (CuF), silver chloride (CuCl), silver iodide (CuI), silver bromide (CuBr), gold chloride (AuCl ₃ ), Gold bromide (AuBr ₃ ), platinum chloride (PtCl ₂ ), or the like can be used. Alternatively, a light emitting material containing a third impurity element may be used instead of the second impurity element.

  Examples of the third impurity element include lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), nitrogen (N), phosphorus (P), arsenic (As), and antimony. (Sb), bismuth (Bi), or the like can be used. The concentration of these impurity elements may be 0.01 to 10 mol%, preferably 0.1 to 5 mol%, based on the base material.

  As a light-emitting material having high electrical conductivity, a light-emitting material in which the above-described material is used as a base material and a light-emitting material containing the first impurity element, the second impurity element, and the third impurity element is added. Can be used. The concentration of these impurity elements may be 0.01 to 10 mol%, preferably 0.1 to 5 mol% with respect to the base material.

  Examples of the compound composed of the second impurity element and the third impurity element include lithium fluoride (LiF), lithium chloride (LiCl), lithium iodide (LiI), copper bromide (LiBr), and sodium chloride. Alkali halides such as (NaCl), boron nitride (BN), aluminum nitride (AlN), aluminum antimony (AlSb), gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs) Indium antimony (InSb) or the like can be used.

  A light-emitting layer using the above-described material as a base material and using the above-described light-emitting material including the first impurity element, the second impurity element, and the third impurity element requires hot electrons accelerated by a high electric field. Without emitting light. That is, since it is not necessary to apply a high voltage to the light emitting element, a light emitting element that can operate with a low driving voltage can be obtained. In addition, since light can be emitted with a low driving voltage, a light-emitting element with reduced power consumption can be obtained. Further, an element that becomes another light emission center may be included.

  Alternatively, the above-described material can be used as a base material, and a light-emitting material including a light-emitting center using the second impurity element, the third impurity element, and the above-described inner-shell electron transition of a metal ion can be used. In this case, the metal ion serving as the emission center is preferably 0.05 to 5 atomic% with respect to the base material. Moreover, it is preferable that the density | concentration of a 2nd impurity element is 0.05-5 atomic% with respect to a base material. Moreover, it is preferable that the density | concentration of a 3rd impurity element is 0.05-5 atomic% with respect to a base material. The light emitting material having such a structure can emit light at a low voltage. Accordingly, a light-emitting element that can emit light at a low driving voltage can be obtained, and thus a light-emitting element with reduced power consumption can be obtained. Further, an element that becomes another light emission center may be included. By using such a light emitting material, luminance deterioration of the light emitting element can be suppressed. Further, the transistor can be driven at a low voltage.

  In any case, the layer structure of the light-emitting layer can be changed, and instead of having a specific hole or electron injecting and transporting layer or light-emitting layer, the light-emitting layer has an electrode layer exclusively for this purpose, or has a light-emitting property. Such a modification that the material is dispersed and provided can be tolerated as long as the object as the light emitting element can be achieved.

The other of the first electrode 2407 and the second electrode 2417 may be formed using a material that does not transmit light. For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, alloys containing these (Mg: Ag, Al: Li, Mg: In, etc.), and compounds thereof (CaF ₂ ) In addition, rare earth metals such as Yb and Er can be used.

  The third insulating film 2408 can be formed using a material similar to that of the second insulating film 2405. The third insulating film 2408 is formed around the first electrode 2407 so as to cover the end portion of the first electrode 2407 and has a function of separating the light emitting layer 2409 in adjacent pixels.

  The light emitting layer 2409 includes one or more layers. When composed of a plurality of layers, these layers can be classified into a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like from the viewpoint of carrier transport characteristics. Note that the boundaries between the layers are not necessarily clear, and there are cases where the materials constituting the layers are partially mixed and the interface is unclear. For each layer, an organic material or an inorganic material can be used. As the organic material, any of a high molecular weight material, a medium molecular weight material, and a low molecular weight material can be used.

  The light-emitting element 2415 includes a light-emitting layer 2409 and a first electrode 2407 and a second electrode 2417 that overlap with each other with the light-emitting layer 2409 interposed therebetween. One of the first electrode 2407 and the second electrode 2417 corresponds to an anode, and the other corresponds to a cathode. When a voltage greater than the threshold voltage is applied between the anode and the cathode with a forward bias, the light emitting element 2415 emits light by current flowing from the anode to the cathode.

  Next, the structure of FIG. 24B will be described. Note that the same portions as those in FIG. 24A are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 24B illustrates a structure in which the insulating film 2418 is provided between the second insulating film 2405 and the third insulating film 2408 in FIG. The electrode 2406 and the first electrode 2407 are connected to each other through an electrode 2416 in a contact hole provided in the insulating film 2418.

  The insulating film 2418 can have a structure similar to that of the second insulating film 2405. The electrode 2416 can have a structure similar to that of the electrode 2406.

  This embodiment shows an example of the structure of the light emitting unit shown in FIGS. In other words, the light-emitting unit illustrated in FIGS. 7 to 23 can be formed using the TFT 2410, the capacitor 2411, and the light-emitting element 2415 which are illustrated in FIGS. The light emitting unit includes the light emitting unit 104 shown in FIG. 1, the light emitting unit 204 shown in FIG. 2, the light emitting unit 304 shown in FIG. 3, the light emitting unit 404 shown in FIG. 4, the light emitting unit 504 shown in FIG. The unit 604 can be applied. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

  In this embodiment, a case where hydrogenated amorphous silicon (a-Si: H) is used for a semiconductor layer of a transistor will be described. FIG. 28 shows the case of a top gate transistor, and FIGS. 29 and 30 show the case of a bottom gate transistor.

  FIG. 28A shows a cross section of a top-gate transistor using hydrogenated amorphous silicon as a semiconductor layer. As shown in the figure, a base film 2802 is formed on a substrate 2801. Further, a pixel electrode 2803 is formed over the base film 2802. A first electrode 2804 made of the same material is formed in the same layer as the pixel electrode 2803.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 2802, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

  In addition, a wiring 2805 and a wiring 2806 are formed over the base film 2802, and an end portion of the pixel electrode 2803 is covered with the wiring 2805. Over the wiring 2805 and the wiring 2806, an N-type semiconductor layer 2807 and an N-type semiconductor layer 2808 having an N-type conductivity are formed. A semiconductor layer 2809 is formed between the wiring 2805 and the wiring 2806 and over the base film 2802. A part of the semiconductor layer 2809 is extended over the N-type semiconductor layer 2807 and the N-type semiconductor layer 2808. Note that this semiconductor layer is formed of an amorphous semiconductor film such as hydrogenated amorphous silicon (a-Si: H), microcrystalline silicon (μc-Si: H), or the like. In addition, a gate insulating film 2810 is formed over the semiconductor layer 2809. An insulating film 2811 made of the same material and in the same layer as the gate insulating film 2810 is also formed over the first electrode 2804. Note that as the gate insulating film 2810, a silicon oxide film, a silicon nitride film, or the like is used.

  A gate electrode 2812 is formed over the gate insulating film 2810. A second electrode 2813 made of the same material and in the same layer as the gate electrode 2812 is formed over the first electrode 2804 with an insulating film 2811 interposed therebetween. A capacitor element 2819 in which an insulating film 2811 is sandwiched between the first electrode 2804 and the second electrode 2813 is formed. Further, an interlayer insulating film 2814 is formed so as to cover an end portion of the pixel electrode 2803, the driving transistor 2818, and the capacitor 2819.

  A region 2815 containing an organic compound and a counter electrode 2816 are formed over the interlayer insulating film 2814 and the pixel electrode 2803 located in the opening, and the pixel electrode 2803 and the counter electrode 2816 sandwich the layer 2815 containing the organic compound Then, a light emitting element 2817 is formed.

  Alternatively, the first electrode 2804 illustrated in FIG. 28A may be formed using the first electrode 2820 as illustrated in FIG. The first electrode 2820 is formed of the same material in the same layer as the wirings 2805 and 2806.

  FIG. 29 shows a partial cross section of a panel of a semiconductor device using a bottom-gate transistor using hydrogenated amorphous silicon as a semiconductor layer.

  A gate electrode 2903 is formed over the substrate 2901. A first electrode 2904 made of the same material is formed in the same layer as the gate electrode 2903. As a material for the gate electrode 2903, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

  A gate insulating film 2905 is formed so as to cover the gate electrode 2903 and the first electrode 2904. As the gate insulating film 2905, a silicon oxide film, a silicon nitride film, or the like is used.

  A semiconductor layer 2906 is formed over the gate insulating film 2905. In addition, a semiconductor layer 2907 made of the same material is formed in the same layer as the semiconductor layer 2906. As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used.

  An N-type semiconductor layer 2908 and an N-type semiconductor layer 2909 having N-type conductivity are formed over the semiconductor layer 2906, and an N-type semiconductor layer 2910 is formed over the semiconductor layer 2907.

  A wiring 2911 and a wiring 2912 are formed on the N-type semiconductor layer 2908 and the N-type semiconductor layer 2909, respectively, and a conductive layer 2913 made of the same material as the wiring 2911 and the wiring 2912 is formed on the N-type semiconductor layer 2910. ing.

  A second electrode including the semiconductor layer 2907, the N-type semiconductor layer 2910, and the conductive layer 2913 is formed. Note that a capacitor 2920 having a structure in which the gate insulating film 2905 is sandwiched between the second electrode and the first electrode 2904 is formed.

  One end of the wiring 2911 extends, and a pixel electrode 2914 is formed in contact with the upper part of the extended wiring 2911.

  An insulating layer 2915 is formed so as to cover the end portion of the pixel electrode 2914, the driving transistor 2919, and the capacitor 2920.

  A layer 2916 containing an organic compound and a counter electrode 2917 are formed over the pixel electrode 2914 and the insulating layer 2915, and a light-emitting element 2918 is formed in a region where the layer 2916 containing an organic compound is sandwiched between the pixel electrode 2914 and the counter electrode 2917. Has been.

  The semiconductor layer 2907 and the N-type semiconductor layer 2910 which are part of the second electrode of the capacitor may not be provided. That is, the second electrode may be a conductive layer 2913 and a capacitor having a structure in which the gate insulating film is sandwiched between the first electrode 2904 and the conductive layer 2913 may be used.

  Note that in FIG. 29A, by forming the pixel electrode 2914 before forming the wiring 2911, the second electrode made of the same material in the same layer as the pixel electrode 2914 as shown in FIG. A capacitor 2920 having a structure in which the gate insulating film 2905 is sandwiched between 2921 and the first electrode 2904 can be formed.

  Note that although an inverted staggered channel-etched transistor is shown in FIG. 29, a channel-protective transistor may of course be used. The case of a transistor with a channel protective structure will be described with reference to FIGS.

  A transistor with a channel protection structure shown in FIG. 30A has an insulating layer 3001 serving as an etching mask over a region where a channel of the semiconductor layer 2906 of the drive transistor 2919 with a channel etch structure shown in FIG. Are different from each other, and other common parts use common reference numerals.

  Similarly, in the channel protection type transistor shown in FIG. 30B, an etching mask is formed on the region where the channel of the semiconductor layer 2906 of the channel etching structure driving transistor 2919 shown in FIG. 29B is formed. The difference is that an insulating layer 3001 is provided, and the other common parts are denoted by common reference numerals.

  By using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, manufacturing cost can be reduced. For example, an amorphous semiconductor film can be used by using the pixel structure shown in FIGS.

  Note that the structure of the transistor to which the pixel structure of the present invention can be applied and the structure of the capacitor are not limited to those described above, and transistors having various structures and structures of capacitors can be used. .

FIG. 28 shows the case of a top gate transistor, and FIGS. 29 and 30 show the case of a bottom gate transistor. This embodiment shows an example of the structure of the light emitting unit shown in FIGS. That is, the light emission shown in FIGS. 7 to 23 using the driving transistor 2818, the capacitor 2819, and the light emitting element 2817 shown in FIG. 28 or the driving transistor 2919, the capacitor 2920, and the light emitting element 2918 shown in FIGS. Units can be configured. The light emitting unit includes the light emitting unit 104 shown in FIG. 1, the light emitting unit 204 shown in FIG. 2, the light emitting unit 304 shown in FIG. 3, the light emitting unit 404 shown in FIG. 4, the light emitting unit 504 shown in FIG. The unit 604 can be applied. As a result, the parasitic capacitance that affects the charge / discharge of the source signal line affects only the source signal line from the output of the source driver to the pixel for which writing to the pixel is selected. As a result, an increase in power consumption due to charging / discharging of the source signal line can be reduced and power consumption can be reduced.

  In this embodiment, as a method for manufacturing a transistor or the like that can be applied to Embodiments 1 and 2, a method for manufacturing a semiconductor device using plasma treatment will be described.

  FIG. 31 is a diagram illustrating a structure example of a semiconductor device including a transistor. Note that in FIG. 31, FIG. 31B corresponds to a cross-sectional view taken along line ab in FIG. 31A, and FIG. 31C corresponds to a cross-sectional view taken along line cd in FIG. To do.

  31 includes semiconductor films 4603a and 4603b provided over a substrate 4601 with an insulating film 4602 interposed therebetween, and a gate electrode 4605 provided over the semiconductor films 4603a and 4603b with a gate insulating film 4604 interposed therebetween. Have. In addition, insulating films 4606 and 4607 provided so as to cover the gate electrode and conductive films 4608 that are electrically connected to the source region or the drain region of the semiconductor films 4603a and 4603b and provided over the insulating film 4607 are provided. ing. Note that FIG. 31 shows the case where an N-channel transistor 4610a using part of the semiconductor film 4603a as a channel region and a P-channel transistor 4610b using part of the semiconductor film 4603b as a channel region are shown. However, it is not limited to this configuration. For example, in FIG. 31, the LDD region is not provided in the N-channel transistor 4610a and the LDD region is not provided in the P-channel transistor 4610b. However, the structure may be provided in both, or may not be provided in both. Is possible.

  Note that in this embodiment, at least one of the substrate 4601, the insulating film 4602, the semiconductor films 4603a and 4603b, the gate insulating film 4604, the insulating film 4606, and the insulating film 4607 is oxidized or nitrided by plasma treatment. The semiconductor device shown in FIG. 31 is manufactured by oxidizing or nitriding the semiconductor film or the insulating film. In this manner, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and characteristics and the like of the semiconductor device can be improved.

  In this embodiment, a method of manufacturing a semiconductor device by performing plasma treatment on the semiconductor films 4603a and 4603b or the gate insulating film 4604 in FIG. 31 and oxidizing or nitriding the semiconductor films 4603a and 4603b or the gate insulating film 4604 will be described. This will be described with reference to the drawings. Note that in the following description, FIGS. 32A1 to 32D1 correspond to cross-sectional views taken along line ab in FIG. 32A2 to 32D2 correspond to cross-sectional views taken along line cd in FIG. The same applies to FIGS. 33 to 37.

  First, the case where an island-shaped semiconductor film provided over a substrate is provided with an end portion of the island-shaped semiconductor film having a shape close to a right angle is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 32A1 and 32A2). The island-shaped semiconductor films 4603a and 4603b are formed using a material containing silicon (Si) as a main component (for example, Si _x ) by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 4602 formed in advance on a substrate 4601. An amorphous semiconductor film is formed using Ge _1-x or the like. Then, the amorphous semiconductor film can be crystallized and the semiconductor film can be selectively etched. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed. Note that in FIGS. 32A1 and 32A2, the end portions of the island-shaped semiconductor films 4603a and 4603b are provided in a shape close to a right angle (θ = 85 to 100 °).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 4603a and 4603b, whereby oxide or nitride films 4621a and 4621b (hereinafter also referred to as insulating films 4621a and 4621b) are formed on the surfaces of the semiconductor films 4603a and 4603b, respectively. ) Is formed (FIGS. 32B1 and 32B2). For example, when Si is used for the semiconductor films 4603a and 4603b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 4621a and 4621b. Alternatively, the semiconductor films 4603a and 4603b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. Note that in the case where the semiconductor film is oxidized by plasma treatment, in an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen Plasma treatment is performed in an atmosphere of hydrogen (H ₂ ) and a rare gas or in a rare gas atmosphere of dinitrogen monoxide. On the other hand, in the case where a semiconductor film is nitrided by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen Plasma treatment is performed in a hydrogen and rare gas atmosphere or a NH ₃ and rare gas atmosphere. As the rare gas, for example, Ar can be used. Moreover, you may use the gas which mixed Ar and Kr. Therefore, the insulating films 4621a and 4621b include a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. When Ar is used, the insulating films 4621a and 4621b are used. Contains Ar.

In the plasma treatment, the plasma electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less in the gas atmosphere, and the plasma electron temperature is 0.5 eV or more and 1.5 eV or less. To do. Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor films 4603a and 4603b) formed over the substrate 4601 is low, damage to the object to be processed is prevented. Can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide or a nitride film formed by oxidizing or nitriding an object to be processed using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like can be formed. In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation treatment can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  Next, a gate insulating film 4604 is formed so as to cover the insulating films 4621a and 4621b (FIGS. 32C1 and 32C2). The gate insulating film 4604 is formed using a sputtering method, an LPCVD method, a plasma CVD method, or the like using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy). A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used. For example, in the case where Si is used as the semiconductor films 4603a and 4603b and silicon oxide is formed as the insulating films 4621a and 4621b on the surfaces of the semiconductor films 4603a and 4603b by oxidizing the Si by plasma treatment, the insulating films 4621a and 4621b Silicon oxide (SiOx) is formed thereon as a gate insulating film. In FIGS. 32B1 and 32B2, the insulating films 4621a and 4621b formed by oxidizing or nitriding the semiconductor films 4603a and 4603b by plasma treatment have sufficient thickness. The films 4621a and 4621b can also be used as gate insulating films.

  Next, a gate electrode 4605 and the like are formed over the gate insulating film 4604, so that a semiconductor device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 32 (D1), (D2)).

  In this manner, before the gate insulating film 4604 is provided over the semiconductor films 4603a and 4603b, the surface of the semiconductor films 4603a and 4603b is oxidized or nitrided by plasma treatment, so that the gate insulation in the end portions 4651a and 4651b of the channel region is obtained. A short-circuit between the gate electrode and the semiconductor film due to the coating failure of the film 4604 can be prevented. When the side end portion of the island-shaped semiconductor film is substantially vertical (θ = 85 to 100 °), there is a problem that the side end portion cannot be covered well when the gate insulating film is formed. However, by previously oxidizing or nitriding the surface of the semiconductor film by using plasma treatment, it becomes possible to prevent a defective coating of the gate insulating film at the side end portion of the semiconductor film.

  In FIGS. 32C1 and 32C2, the gate insulating film 4604 may be oxidized or nitrided by performing plasma treatment after the gate insulating film 4604 is formed. In this case, plasma treatment is performed on the gate insulating film 4604 (FIGS. 33A1 and 33A2) formed so as to cover the semiconductor films 4603a and 4603b, and the gate insulating film 4604 is oxidized or nitrided to thereby provide gate insulation. An oxide film or a nitride film (hereinafter also referred to as an insulating film 4623) is formed on the surface of the film 4604 (FIGS. 33B1 and 33B2). The conditions for the plasma treatment can be the same as those in FIGS. 32B1 and 32B2. The insulating film 4623 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4623 contains Ar.

  In FIGS. 33B1 and 33B, the gate insulating film 4604 may be oxidized by once performing plasma treatment in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. . In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed over the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 4605. Is done. After that, by forming the gate electrode 4605 and the like over the insulating film 4623, a semiconductor device including the N-channel transistor 4610a and the P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 33 (C1), (C2)). In this manner, by performing plasma treatment on the gate insulating film, the surface of the gate insulating film is oxidized or nitrided, whereby the surface of the gate insulating film can be modified and a dense film can be formed. An insulating film obtained by performing plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that the characteristics of the transistor can be improved.

  Note that FIG. 33 shows the case where the surfaces of the semiconductor films 4603a and 4603b are oxidized or nitrided by performing plasma treatment on the semiconductor films 4603a and 4603b in advance, but the semiconductor films 4603a and 4603b are subjected to plasma treatment. Alternatively, a method in which plasma treatment is performed after the gate insulating film 4604 is formed may be used. In this manner, by performing plasma treatment before forming the gate electrode, the semiconductor film exposed due to the poor coverage of the gate insulating film can be oxidized or nitrided, so that the occurrence of the defect can be prevented. That is, it is possible to prevent a short-circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film.

  In this manner, even when the end portion of the island-shaped semiconductor film is provided in a shape close to a right angle, plasma treatment is performed on the semiconductor film or the gate insulating film to oxidize or nitride the semiconductor film or the gate insulating film. As a result, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

  Next, in the island-shaped semiconductor film provided over the substrate, the case where the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °) is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 34A1 and 34A2). The island-shaped semiconductor films 4603a and 4603b are formed using a material containing silicon (Si) as a main component (for example, Si _x ) by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 4602 formed in advance on a substrate 4601. An amorphous semiconductor film is formed using Ge _1-x or the like and crystallized. The amorphous semiconductor film is crystallized by a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. 34A1 and 34A2, the end portion of the island-shaped semiconductor film is etched into a tapered shape (θ = 30 to 85 °).

  Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b (FIGS. 34B1 and 34B2). The gate insulating film 4604 is formed using a sputtering method, an LPCVD method, a plasma CVD method, or the like using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy). A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used.

  Next, plasma treatment is performed to oxidize or nitride the gate insulating film 4604, whereby an oxide film or a nitride film (hereinafter also referred to as an insulating film 4624) is formed on the surface of the gate insulating film 4604 (FIG. 34C1). ), (C2)). The plasma treatment conditions can be the same as described above. For example, when silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is used for the gate insulating film 4604, plasma treatment is performed in an oxygen atmosphere to oxidize the gate insulating film 4604. As the insulating film, a dense film with fewer defects such as pinholes can be formed on the surface of the gate insulating film than a gate insulating film formed by a CVD method, a sputtering method, or the like. On the other hand, by performing plasma treatment in a nitrogen atmosphere and nitriding the gate insulating film 4604, silicon nitride oxide (SiNxOy) (x> y) can be provided as the insulating film 4624 on the surface of the gate insulating film 4604. Alternatively, the gate insulating film 4604 may be oxidized by performing plasma treatment once in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. The insulating film 4624 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4624 contains Ar.

  Next, a gate electrode 4605 and the like are formed over the gate insulating film 4604, so that a semiconductor device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 34 (D1), (D2)).

  In this manner, by performing plasma treatment on the gate insulating film, an insulating film made of an oxide film or a nitride film can be provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified. An insulating film oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by a CVD method or a sputtering method, so that transistor characteristics can be improved. it can. In addition, by forming the end portion of the semiconductor film in a tapered shape, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end portion of the semiconductor film can be suppressed. By performing plasma treatment after the formation, a short circuit between the gate electrode and the semiconductor film can be further prevented.

  Next, a method for manufacturing a semiconductor device which is different from that in FIG. 34 is described with reference to drawings. Specifically, a case where plasma treatment is selectively performed on an end portion of a semiconductor film having a tapered shape is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 35A1 and 35A2). The island-shaped semiconductor films 4603a and 4603b are formed using a material containing silicon (Si) as a main component (for example, Si _x ) by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over an insulating film 4602 formed in advance on a substrate 4601. In this case, an amorphous semiconductor film formed using Ge _1-x or the like is crystallized. The resists 4625a and 4625b are used for etching the semiconductor film into an island shape. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed.

  Next, before removing the resists 4625a and 4625b used for etching the semiconductor film, plasma treatment is performed to selectively oxidize or nitride the end portions of the island-shaped semiconductor films 4603a and 4603b. An oxide film or a nitride film (hereinafter also referred to as an insulating film 4626) is formed on end portions of the films 4603a and 4603b, respectively (FIGS. 35B1 and 35B2). The plasma treatment is performed under the conditions described above. The insulating film 4626 contains a rare gas used for plasma treatment.

  Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b (FIGS. 35C1 and 35C2). The gate insulating film 4604 can be provided in a manner similar to the above.

  Next, a gate electrode 4605 and the like are formed over the gate insulating film 4604, so that a semiconductor device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 35 (D1), (D2)).

  In the case where the end portions of the semiconductor films 4603a and 4603b are provided in a tapered shape, the end portions 4652a and 4602b of the channel region formed in part of the semiconductor films 4603a and 4603b are also tapered and the thickness of the semiconductor film or the gate insulating film Since the film thickness changes as compared with the central portion, the characteristics of the transistor may be affected. Therefore, here, by selectively oxidizing or nitriding an end portion of the channel region by plasma treatment and forming an insulating film in the semiconductor film which is the end portion of the channel region, a transistor caused by the end portion of the channel region The influence on can be reduced.

  Note that FIG. 35 shows an example in which oxidation or nitridation is performed by plasma treatment only on the end portions of the semiconductor films 4603a and 4603b. However, as shown in FIGS. 34C1 and C2, the gate insulation is performed. The insulating film 4624 may be formed by oxidizing or nitriding the film 4604 by plasma treatment (FIGS. 37A1 and 37A2).

  Next, a method for manufacturing a semiconductor device different from the above is described with reference to drawings. Specifically, a case where plasma treatment is performed on a semiconductor film having a tapered shape is described.

  First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 in the same manner as described above (FIGS. 36A1 and 36A2).

  Next, plasma treatment is performed to oxidize or nitride the semiconductor films 4603a and 4603b, whereby oxide films or nitride films (hereinafter also referred to as insulating films 4627a and 4627b) are formed on the surfaces of the semiconductor films 4603a and 4603b, respectively. (FIG. 36 (B1), (B2)). The plasma treatment can be similarly performed under the above-described conditions. For example, when Si is used for the semiconductor films 4603a and 4603b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 4627a and 4627b. Alternatively, the semiconductor films 4603a and 4603b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in contact with the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x > Y) is formed. Therefore, the insulating films 4627a and 4627b contain a rare gas used for plasma treatment. Note that the end portions of the semiconductor films 4603a and 4603b are simultaneously oxidized or nitrided by performing the plasma treatment.

  Next, a gate insulating film 4604 is formed so as to cover the insulating films 4627a and 4627b (FIGS. 36C1 and 36C2). The gate insulating film 4604 is formed using a sputtering method, an LPCVD method, a plasma CVD method, or the like using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy). A single-layer structure of an insulating film containing oxygen or nitrogen such as (x> y) or a stacked structure thereof can be used. For example, when silicon is formed as the insulating films 4627a and 4627b on the surfaces of the semiconductor films 4603a and 4603b by oxidizing Si as the semiconductor films 4603a and 4603b by plasma treatment, a gate is formed over the insulating films 4627a and 4627b. Silicon oxide (SiOx) is formed as an insulating film.

  Next, a gate electrode 4605 and the like are formed over the gate insulating film 4604, so that a semiconductor device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 36 (D1), (D2)).

  When the end portion of the semiconductor film is provided in a tapered shape, the end portion of the channel region formed in a part of the semiconductor film also has a tapered shape, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, as a result, the end portion of the channel region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

  Note that although FIG. 36 shows an example in which oxidation or nitridation is performed by plasma treatment only on the semiconductor films 4603a and 4603b, of course, the gate insulating film 4604 is formed on the gate insulating film 4604 as shown in FIGS. The insulating film 4624 can also be formed by performing plasma treatment to be oxidized or nitrided (FIGS. 37B1 and 37B2). In this case, after the gate insulating film 4604 is oxidized by performing plasma treatment once in an oxygen atmosphere, it may be nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed over the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 4605. Is done.

  In this embodiment, the semiconductor films 4603a and 4603b or the gate insulating film 4604 in FIG. 31 are subjected to plasma treatment, and the semiconductor films 4603a and 4603b or the gate insulating film 4604 are oxidized or nitrided. The layer used for oxidation or nitridation is not limited to this. For example, plasma treatment may be performed on the substrate 4601 or the insulating film 4602, or plasma treatment may be performed on the insulating film 4607.

  Note that the contents described in this embodiment can be freely combined with the contents described in Embodiment 1 or Embodiment 2.

  In this embodiment, a halftone method will be described as a method for manufacturing a transistor or the like which can be applied to Embodiments 1 and 2.

  FIG. 38 illustrates a cross-sectional structure of a semiconductor device including a transistor, a capacitor, and a resistor. FIG. 38 shows an N-channel transistor 5401, an N-channel transistor 5402, a capacitor 5404, a resistor 5405, and a P-channel transistor 5403. Each transistor and the capacitor each include a semiconductor layer 5505 and an insulating layer 5508, and each transistor further includes a gate electrode 5509. The gate electrode 5509 is formed with a stacked structure of a first conductive layer 5503 and a second conductive layer 5502. FIGS. 39A to 39E are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 38, and can be referred to together.

  In FIG. 38, an N-channel transistor 5401 is also called a low concentration drain (LDD) structure, and an impurity region 5507 doped at a lower concentration than the impurity concentration of the impurity region 5506 forming the source and drain regions is a semiconductor layer 5505. Is formed. In the case of forming the N-channel transistor 5401, phosphorus or the like is added to the impurity region 5506 and the impurity region 5507 as an impurity imparting N-type conductivity. The LDD region is formed as a means for suppressing hot electron degradation and the short channel effect.

  As shown in FIG. 39A, in the gate electrode 5509 of the N-channel transistor 5401, the first conductive layer 5503 is formed so as to spread on both sides of the second conductive layer 5502. In this case, the first conductive layer 5503 is formed thinner than the second conductive layer 5502. The first conductive layer 5503 is formed to have a thickness that allows passage of ion species accelerated by an electric field of 10 to 100 kV. The impurity region 5507 is formed so as to overlap with the first conductive layer 5503 of the gate electrode 5509. That is, an LDD region overlapping with the gate electrode 5509 is formed. In this structure, an impurity region 5507 is formed in a self-aligned manner in the gate electrode 5509 by adding an impurity of one conductivity type through the first conductive layer 5503 using the second conductive layer 5502 as a mask. That is, the LDD region overlapping with the gate electrode is formed in a self-aligning manner.

  In FIG. 38, an N-channel transistor 5402 has an impurity region 5507 doped in a lower concentration than the impurity concentration of the impurity region 5506 in one side of the impurity region 5506 in the semiconductor layer 5505. As shown in FIG. 39B, in the gate electrode 5509 of the N-channel transistor 5402, the first conductive layer 5503 is formed so as to spread on one side of the second conductive layer 5502. In this case as well, an LDD region can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 5503 using the second conductive layer 5502 as a mask.

  A transistor having an LDD on one side of the impurity region 5506 may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 38, the capacitor 5404 is formed by sandwiching an insulating layer 5508 between a first conductive layer 5503 and a semiconductor layer 5505. A semiconductor layer 5505 for forming the capacitor 5404 includes an impurity region 5510 and an impurity region 5511. The impurity region 5511 is formed in the semiconductor layer 5505 so as to overlap only with the first conductive layer 5503. Further, the impurity region 5510 is in contact with the wiring 5504. Since the impurity region 5511 can be doped with one conductivity type impurity through the first conductive layer 5503, the impurity concentration in the impurity region 5510 and the impurity region 5511 can be the same or can be different. It is. In any case, since the semiconductor layer 5505 functions as an electrode in the capacitor 5404, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 39C, the first conductive layer 5503 can function sufficiently as an electrode by using the second conductive layer 5502 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 5503 and the second conductive layer 5502 are combined, the capacitor 5404 can be formed in a self-aligning manner.

  In FIG. 38, the resistance element 5405 is formed of a first conductive layer 5503. Since the first conductive layer 5503 is formed to a thickness of about 30 nm to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small. A top view of the resistor 5405 is shown in FIG.

  In FIG. 38, a P-channel transistor 5403 includes an impurity region 5512 in a semiconductor layer 5505. The impurity region 5512 forms a source and drain region in contact with the wiring 5504. The gate electrode 5509 has a structure in which the first conductive layer 5503 and the second conductive layer 5502 overlap each other. The P-channel transistor 5403 is a single drain transistor without an LDD region. In the case where the P-channel transistor 5403 is formed, boron or the like is added to the impurity region 5512 as an impurity imparting P-type conductivity. On the other hand, when phosphorus is added to the impurity region 5512, an N-channel transistor having a single drain structure can be obtained. A top view of the P-channel transistor 5403 is shown in FIG.

One or both of the semiconductor layer 5505 and the gate insulating layer 5508 are excited by microwaves, have an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻³ . Oxidation or nitridation may be performed by some high density plasma treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, or the like) or a nitriding atmosphere (N ₂ , NH _3, or the like), whereby the interface between the semiconductor layer 5505 and the gate insulating layer 5508 The defect level of can be reduced. By performing this treatment on the gate insulating layer 5508, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 5508. In the case where the driving voltage of the transistor is 3 V or more, a gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 5505 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 5508 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 5404. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 nm to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 38 and 39, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit below the resolution limit in a photomask or reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 39A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  38 and 39, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same patterning process using a photomask or reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  Note that the contents described in this embodiment can be freely combined with the contents described in Embodiments 1 to 3.

  In this embodiment, an example of a mask pattern in manufacturing a transistor or the like that can be applied to Embodiments 1 and 2 will be described with reference to FIGS.

  The semiconductor layers 5610 and 5611 shown in FIG. 40A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In this case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that defined as the semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 5610 and 5611 having specific shapes including the source and drain regions of the transistor and the channel formation region are formed. The semiconductor layers 5610 and 5611 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layers 5610 and 5611 shown in FIG. 40A includes a mask pattern 5630 shown in FIG. This mask pattern 5630 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, a mask pattern 5630 shown in FIG. 40B is manufactured as a light shielding portion. Mask pattern 5630 has a shape in which polygonal apex A is cut away. In addition, the bent portion B has a shape that is bent over a plurality of steps so that the corner portion does not become a right angle.

  The shape of the mask pattern 5630 illustrated in FIG. 40B is reflected in the semiconductor layers 5610 and 5611 illustrated in FIG. 40A by a photolithography process. In that case, a shape similar to the mask pattern 5630 may be transferred, but the top portion A and the bent portion B of the mask pattern 5630 may be transferred to be further rounded. That is, rounded portions with a smoother pattern shape than the mask pattern 5630 can be formed in the semiconductor layers 5610 and 5611.

  Over the semiconductor layers 5610 and 5611, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 41A, gate wirings 5712, 5713, and 5714 are formed so as to partially overlap the semiconductor layer. The gate wiring 5712 is formed corresponding to the semiconductor layer 5610. The gate wiring 5713 is formed corresponding to the semiconductor layers 5610 and 5611. The gate wiring 5714 is formed corresponding to the semiconductor layers 5610 and 5611. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 5731 shown in FIG. This mask pattern 5731 is formed so that the outside and inside of the corner portion are not bent at an acute angle. That is, the corner portion is not bent at a right angle by cutting out the top portion outside the corner portion and filling the inside.

The shape of the mask pattern 5731 illustrated in FIG. 41B is reflected in the gate wirings 5712, 5713, and 5714 illustrated in FIG. In that case, a shape similar to the mask pattern 5731 may be transferred, or the corner of the mask pattern 5731 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 5731 may be provided. If there is a sharp portion in the wiring pattern, an electric field concentrates on the dry etching, and abnormal discharge occurs and fine powder is generated. In this case, it is possible to eliminate such a defect by rounding the corners of the wiring pattern. Further, in the cleaning process, the wiring pattern with smooth corners also has an advantage that fine powder does not stay in the bent portion and can be washed cleanly.

  The interlayer insulating layer is a layer formed next to the gate wirings 5712, 5713, and 5714. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material using polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 5712, 5713, and 5714. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities such as exogenous metal ions and moisture that are not good for the transistor.

  Openings are formed in predetermined positions in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 42A, wirings 5815 to 5820 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 5815 to 5820 includes a mask pattern 5832 shown in FIG. Even in this case, by providing roundness at the corners of the wiring, as described above, generation of fine powder due to abnormal discharge during dry etching and residual fine powder in the cleaning process can be prevented.

  In FIG. 42A, N-channel transistors 5821 to 5824 and P-channel transistors 5825 and 5826 are formed. The N-channel transistor 5823 and the P-channel transistor 5825, and the N-channel transistor 5824 and the P-channel transistor 5826 constitute inverters 5827 and 5828. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  Note that the contents described in this embodiment mode can be freely combined with the contents described in the first to fourth embodiments.

  In this embodiment, a structure in which a substrate over which a pixel is formed is sealed will be described with reference to FIG. FIG. 25A is a top view of a panel formed by sealing a substrate on which pixels are formed. FIGS. 25B and 25C are cross-sectional views of FIGS. It is sectional drawing in A '. FIG. 25B and FIG. 25C are examples in which sealing is performed by different methods.

  25A to 25C, a pixel portion 2502 including a plurality of pixels is provided over a substrate 2501, a sealant 2506 is provided so as to surround the pixel portion 2502, and a sealant 2507 is attached. ing. As for the structure of the pixel, the best mode for carrying out the invention described above or the configuration shown in Embodiment 1 can be used.

  In the display panel in FIG. 25B, the sealant 2507 in FIG. 25A corresponds to the counter substrate 2521. A transparent counter substrate 2521 is attached using the sealant 2506 as an adhesive layer, and a sealed space 2522 is formed by the substrate 2501, the counter substrate 2521, and the sealant 2506. The counter substrate 2521 is provided with a color filter 2520 and a protective film 2523 for protecting the color filter. Light emitted from the light emitting elements arranged in the pixel portion 2502 is emitted to the outside through the color filter 2520. The sealed space 2522 is filled with an inert resin or liquid. Note that as the resin filled in the sealed space 2522, a light-transmitting resin in which a hygroscopic material is dispersed may be used. Alternatively, the sealing material 2506 and the material filled in the sealed space 2522 may be the same material, and the counter substrate 2521 may be bonded and the pixel portion 2502 may be sealed at the same time.

  In the display panel illustrated in FIG. 25C, the sealant 2507 in FIG. 25A corresponds to the sealant 2524. A sealant 2524 is attached using the sealant 2506 as an adhesive layer, and a sealed space 2508 is formed by the substrate 2501, the sealant 2506, and the sealant 2524. The sealant 2524 is provided with a hygroscopic agent 2509 in the recess in advance, and plays a role of adsorbing moisture, oxygen, and the like in the sealed space 2508 to maintain a clean atmosphere and suppressing deterioration of the light emitting element. This recess is covered with a fine mesh-like cover material 2510. The cover material 2510 allows air and moisture to pass through, but does not allow the moisture absorbent 2509 to pass. Note that the sealed space 2508 may be filled with a rare gas such as nitrogen or argon, and may be filled with a resin or a liquid if inactive.

  An input terminal portion 2511 for transmitting a signal to the pixel portion 2502 and the like is provided over the substrate 2501, and a signal such as a video signal is transmitted to the input terminal portion 2511 through an FPC 2512 (flexible printed circuit). . In the input terminal portion 2511, a wiring formed over the substrate 2501 and a wiring provided in the FPC 2512 are electrically connected using a resin in which a conductor is dispersed (anisotropic conductive resin: ACF). .

  A driver circuit that inputs a signal to the pixel portion 2502 may be formed over the substrate 2501 over which the pixel portion 2502 is formed. A driver circuit for inputting a signal to the pixel portion 2502 may be formed using an IC chip and connected to the substrate 2501 by COG (Chip On Glass), or the IC chip may be connected using a TAB (Tape Auto Bonding) or a printed circuit board. You may arrange | position on the board | substrate 2501. FIG.

  The present embodiment can be implemented by freely combining the first to sixth embodiments and the first to fifth embodiments.

  The present invention can be applied to a display module in which a circuit for inputting a signal to the panel is mounted on the panel.

  FIG. 26 shows a display module in which a panel 2600 and a circuit board 2604 are combined. FIG. 26 shows an example in which a controller 2605, a signal dividing circuit 2606, and the like are formed on a circuit board 2604. The circuit formed over the circuit board 2604 is not limited to this. Any circuit may be formed as long as the circuit generates a signal for controlling the panel.

  Signals output from these circuits formed on the circuit board 2604 are input to the panel 2600 through connection wirings 2607.

  The panel 2600 includes a pixel portion 2601, a source driver 2602, and a gate driver 2603. The configuration of the panel 2600 can be the same as the configuration shown in the first embodiment, the second embodiment, or the like. FIG. 26 illustrates an example in which the source driver 2602 and the gate driver 2603 are formed over the same substrate as the substrate over which the pixel portion 2601 is formed. However, the display module of the present invention is not limited to this. Only the gate driver 2603 may be formed over the same substrate as the substrate over which the pixel portion 2601 is formed, and the source driver 2602 may be formed over the circuit substrate. Both the source driver and the gate driver may be formed on the circuit board.

  By incorporating such a display module, display portions of various electronic devices can be formed.

  The present embodiment can be implemented by freely combining the first to sixth embodiments and the first to seventh embodiments.

  The present invention can be applied to various electronic devices. Electronic devices include cameras (video cameras, digital cameras, etc.), projectors, head-mounted displays (goggles type displays), navigation systems, car stereos, personal computers, game devices, portable information terminals (mobile computers, mobile phones or electronic books) Etc.), and an image reproduction apparatus (specifically, an apparatus equipped with a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image). An example of the electronic device is illustrated in FIG.

  FIG. 27A illustrates a personal computer, which includes a main body 2711, a housing 2712, a display portion 2713, a keyboard 2714, an external connection port 2715, a pointing mouse 2716, and the like. The present invention is applied to the display portion 2713. By using the present invention, power consumption of the display portion can be reduced.

  FIG. 27B shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2721, a housing 2722, a first display portion 2723, a second display portion 2724, and a recording medium reading Part 2725 (DVD or the like), operation keys 2726, speaker part 2727, and the like. The first display portion 2723 mainly displays image information, and the second display portion 2724 mainly displays character information. The present invention is applied to the first display portion 2723 and the second display portion 2724. By using the present invention, power consumption of the display portion can be reduced.

  FIG. 27C illustrates a cellular phone, which includes a main body 2731, an audio output portion 2732, an audio input portion 2733, a display portion 2734, operation switches 2735, an antenna 2736, and the like. The present invention is applied to the display portion 2734. By using the present invention, power consumption of the display portion can be reduced.

  FIG. 27D shows a camera, which includes a main body 2741, a display portion 2742, a housing 2743, an external connection port 2744, a remote control receiving portion 2745, an image receiving portion 2746, a battery 2747, an audio input portion 2748, operation keys 2749, and the like. The present invention is applied to the display portion 2742. By using the present invention, power consumption of the display portion can be reduced.

  This embodiment can be implemented by freely combining the first to sixth embodiments and the first to seventh embodiments.

The figure which shows 1st Embodiment. The figure which shows 2nd Embodiment. The figure which shows 3rd Embodiment. The figure which shows 4th Embodiment. The figure which shows 5th Embodiment. The figure which shows 6th Embodiment. The figure which shows 7th Embodiment. The figure which shows 8th Embodiment. The figure which shows 9th Embodiment. The figure which shows 10th Embodiment. The figure which shows 11th Embodiment. The figure which shows 12th Embodiment. The figure which shows 13th Embodiment. The figure which shows 14th Embodiment. The figure which shows 15th Embodiment. The figure which shows 16th Embodiment. The figure which shows 17th Embodiment. The figure which shows 18th Embodiment. The figure which shows 19th Embodiment. The figure which shows 20th Embodiment. The figure which shows 21st Embodiment. The figure which shows 22nd Embodiment. The figure which shows 23rd Embodiment. FIG. 3 is a diagram illustrating Example 1; FIG. 6 shows a sixth embodiment. FIG. 9 shows a seventh embodiment. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. FIG. 6 shows a fifth embodiment. FIG. 6 shows a fifth embodiment. FIG. 6 shows a fifth embodiment.

Explanation of symbols

101 source driver 102 gate driver 103 pixel 104 light emitting unit 105 switch 106 switch 107 source signal line 108 gate signal line 201 source driver 202 gate driver 203 pixel 204 light emitting unit 205 switch 206 switch 207 source signal line 208 gate signal line 209 gate signal line 210 Inverter 301 Source driver 302 Gate driver 303 Pixel 304 Light emitting unit 305 TFT
306 TFT
307 Source signal line 308 Gate signal line 401 Source driver 402 Gate driver 403 Pixel 404 Light emitting unit 405 TFT
406 TFT
407 Source signal line 408 Gate signal line 501 Source driver 502 Gate driver 503 Pixel 504 Light emitting unit 505 TFT
506 TFT
507 Source signal line 508 Gate signal line 509 Gate signal line 510 Inverter 601 Source driver 602 Gate driver 603 Pixel 604 Light emitting unit 605 TFT
606 TFT
607 Source signal line 608 Gate signal line 608 Gate signal line 609 Gate signal line 610 Inverter 701 TFT
702 Capacitance element 703 Light emitting element 704 Counter electrode 705 Power supply line 706 Signal input line 801 TFT
802 Capacitance element 803 Light emitting element 804 Counter electrode 805 Power supply line 806 Signal input line 901 TFT
902 Switch 903 Capacitance element 904 Light emitting element 905 Counter electrode 906 Power supply line 907 Gate signal line 908 Signal input line 1001 TFT
1002 Switch 1003 Capacitance element 1004 Light emitting element 1005 Counter electrode 1006 Power supply line 1007 Gate signal line 1008 Signal input line 1101 TFT
1102 Diode 1103 Capacitor element 1104 Light emitting element 1105 Counter electrode 1106 Power supply line 1107 Gate signal line 1108 Signal input line 1201 TFT
1202 Diode 1203 Capacitance element 1204 Light emitting element 1205 Counter electrode 1206 Power line 1207 Gate signal line 1208 Signal input line 1301 TFT
1302 TFT
1303 Capacitor element 1304 Capacitor element 1305 Light emitting element 1306 Light emitting element 1307 Counter electrode 1308 Power supply line 1309 Signal input line 1310 Signal input line 1401 TFT
1402 TFT
1403 Capacitor element 1404 Capacitor element 1405 Light emitting element 1406 Light emitting element 1407 Counter electrode 1408 Power line 1409 Signal input line 1410 Signal input line 1501 TFT
1502 Switch 1503 Switch 1504 Switch 1505 Capacitor element 1506 Capacitor element 1507 Light emitting element 1508 Counter electrode 1509 Power line 1510 Power line 1511 Gate signal line 1512 Gate signal line 1513 Signal input line 1601 TFT
1602 Switch 1603 Switch 1604 Capacitor element 1605 Capacitor element 1606 Light emitting element 1607 Counter electrode 1608 Power supply line 1609 Gate signal line 1610 Gate signal line 1611 Signal input line 1701 TFT
1702 Switch 1703 Switch 1704 Capacitance element 1705 Light emitting element 1706 Counter electrode 1707 Power supply line 1708 Gate signal line 1709 Gate signal line 1710 Signal input line 1801 TFT
1802 Switch 1803 Switch 1804 Capacitance element 1805 Light emitting element 1806 Counter electrode 1807 Power line 1808 Gate signal line 1809 Gate signal line 1810 Signal input line 1901 TFT
1902 Switch 1903 Switch 1904 Capacitor 1905 Light emitting element 1906 Counter electrode 1907 Power line 1908 Gate signal line 1909 Gate signal line 1910 Signal input line 2001 TFT
2002 TFT
2003 switch 2004 capacitor element 2005 light emitting element 2006 counter electrode 2007 power supply line 2008 gate signal line 2009 signal input line 2101 TFT
2102 Switch 2103 Capacitor element 2104 Light emitting element 2105 Counter electrode 2106 Power supply line 2107 Gate signal line 2108 Signal input line 2201 TFT
2202 Switch 2203 Capacitor element 2204 Light emitting element 2205 Counter electrode 2206 Power supply line 2207 Gate signal line 2208 Signal input line 2301 TFT
2302 TFT
2303 Switch 2304 Capacitor element 2305 Light emitting element 2306 Counter electrode 2307 Power line 2308 Gate signal line 2309 Signal input line 2400 Substrate 2401 Underlayer 2402 Semiconductor layer 2403 Insulating film 2404 Gate electrode 2405 Insulating film 2406 First electrode 2407 First electrode 2408 Insulating film 2409 Light emitting layer 2410 TFT
2411 Capacitor element 2412 Semiconductor layer 2414 Electrode 2415 Light emitting element 2416 Second electrode 2417 Second electrode 2418 Insulating film 2501 Substrate 2502 Pixel portion 2506 Seal material 2507 Seal material 2508 Sealed space 2509 Hygroscopic agent 2510 Cover material 2511 Input terminal portion 2512 FPC
2520 Color filter 2521 Counter substrate 2522 Sealed space 2523 Protective film 2524 Sealing material 2600 Panel 2601 Pixel portion 2602 Source driver 2603 Gate driver 2604 Circuit board 2605 Controller 2606 Signal dividing circuit 2607 Connection wiring 2801 Substrate 2802 Base film 2803 Pixel electrode 2804 First Electrode 2805 Wiring 2806 Wiring 2807 N-type semiconductor layer 2808 N-type semiconductor layer 2809 Semiconductor layer 2810 Gate insulating film 2811 Insulating film 2812 Gate electrode 2813 Second electrode 2814 Interlayer insulating film 2815 Layer 2816 containing an organic compound Counter electrode 2817 Light-emitting element 2818 Driving transistor 2819 Capacitance element 2820 First electrode 2901 Substrate 2903 Gate electrode 2904 First electrode 2905 Gate insulating film 2 906 Semiconductor layer 2907 Semiconductor layer 2908 N-type semiconductor layer 2909 N-type semiconductor layer 2910 N-type semiconductor layer 2911 Wiring 2912 Wiring 2913 Conductive layer 2914 Pixel electrode 2915 Insulating layer 2916 Layer containing an organic compound 2917 Counter electrode 2918 Light-emitting element 2919 Drive transistor 2920 Capacitor element 2921 Second electrode 3001 Insulating layer 4601 Substrate 4602 Insulating film 4603a Semiconductor film 4603b Semiconductor film 4604 Gate insulating film 4605 Gate electrode 4606 Insulating film 4607 Insulating film 4608 Conductive film 4610a N-channel transistor 4610b P-channel transistor 4621a Insulating film 4621b Insulating film 4623 Insulating film 4624 Insulating film 4625a Resist 4625b Resist 4626 Insulating film 4627a Insulating film 4627b Insulating film 4 651a End of channel region 4651b End of channel region 4651a End of channel region 4651b End of channel region 5401 N-channel transistor 5402 N-channel transistor 5403 P-channel transistor 5404 Capacitance element 5405 Resistance element 5502 Conductive layer 5503 Conduction Layer 5504 wiring 5505 semiconductor layer 5506 impurity region 5507 impurity region 5508 insulating layer 5509 gate electrode 5510 impurity region 5511 impurity region 5512 impurity region 5610 semiconductor layer 5611 semiconductor layer 5630 mask pattern 5712 gate wiring 5713 gate wiring 5714 gate wiring 5731 mask pattern 5815 wiring 5816 Wiring 5817 Wiring 5818 Wiring 5819 Wiring 5820 Wiring 5821 N-channel type transistor DISTAR 5823 N-channel transistor 5824 N-channel transistor 5825 P-channel transistor 5826 P-channel transistor 5827 Inverter 5828 Inverter 5832 Mask pattern

Claims (1)

A first pixel and a second pixel;
Each of the first pixel and the second pixel includes a first switch, a second switch, a third switch, a fourth switch, a transistor, and a light emitting element.
In each of the first pixel and the second pixel,
One terminal of the first switch is electrically connected to one terminal of the second switch;
One of a source and a drain of the transistor is electrically connected to a power supply line,
The other of the source and the drain of the transistor is electrically connected to the other terminal of the second switch;
One terminal of the third switch is electrically connected to the gate of the transistor;
The other terminal of the third switch is electrically connected to the other of the source and the drain of the transistor;
One terminal of the fourth switch is electrically connected to the other of the source and the drain of the transistor;
The other terminal of the fourth switch is electrically connected to the light emitting element,
One terminal of the first switch of the first pixel is electrically connected to a source driver;
One terminal of the first switch included in the second pixel is electrically connected to the other terminal of the first switch included in the first pixel.

Images