JP2009192745A - Electrooptical device, driving method of the electrooptical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To significantly improve the display characteristics of a non-selected pixel, by minimizing influence on the non-selected pixel, of fluctuation in data line potential caused by writing on selected pixelw. <P>SOLUTION: An electrooptical device (liquid crystal display, or the like) includes: n (n is an integer of one or more) lines of main data lines (MDL); m (m is an integer of 1 or larger) lines of sub-data lines (SDLn) which are provided corresponding to a k-th (1≤k≤n) main data line (MDLn) in the n lines of main data lines; m pieces of first switches (SW1), provided between the k-th main data lines and each of the m lines of sub-data lines, which switch electrical connection/non-connection between the k-th main data line and each of the m lines of sub-data lines; and i (i is an integer of 1 or larger) pieces of pixel circuits which are connected to each of m lines of sub-data lines. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device (for example, a liquid crystal display device or an organic EL display device), a driving method of the electro-optical device, an electronic apparatus, and the like.

  In a liquid crystal display device, as a factor that fluctuates the holding voltage (display voltage) of each pixel, feedthrough due to a parasitic capacitance between the gate and drain of a MOS transistor as a transfer switch provided in each pixel is known. An example of a countermeasure for feedthrough is described in Patent Document 1.

  Further, Patent Document 2 describes a configuration in which data lines are hierarchized in a DRAM (dynamic RAM).

Further, in an IC using a silicon substrate, a configuration for absorbing charges generated by alpha rays (that is, a configuration in which a hydrogen diffusion layer formed by ion implantation is used as a manufacturing process) is described in Patent Document 3. Has been.
JP 2002-341313 A JP-A-5-54634 Japanese Patent Laid-Open No. 9-129843

  For example, in a liquid crystal display device, when it is intended to realize a higher-definition image display, a new problem to be solved arises in addition to the above feedthrough. Hereinafter, a new problem that has been clarified by the inventors of the present invention before the present invention will be described. In the following description, reference is made to FIG. FIG. 9A to FIG. 9D are diagrams for explaining a new problem that has been clarified before the present invention.

(1) Problem 1 (Fluctuation in potential of data line causes fluctuation in scanning line potential of non-selected pixel)
A plurality of pixel circuits are connected on the data line. Each pixel circuit is provided with a MOS transistor as a transfer gate, and a parasitic capacitance exists between the gate and source (or drain) of the MOS transistor. Therefore, when the potential of the data line fluctuates for writing to the selected pixel, the fluctuation of the data line potential is caused by the parasitic capacitance between the gate and source (drain) of the MOS transistor of the non-selected pixel. The scanning line potential in the non-selected state is changed by the ring. As a result, the leakage current of the unselected MOS transistor is increased. The leak current of the pixel transistor causes a potential change such as a decrease or an increase in holding voltage, and affects display characteristics.

  This will be specifically described with reference to FIG. FIG. 9A shows the first and second pixels (PIX (A) and PIX (B)). Each pixel is provided with NMOS transistors (pixel transistors) M100a and M100b as transfer gates.

  In FIG. 9A, GLa and GLb are scanning lines, DL is a data line, and VDL is a voltage (data line voltage) of an image signal supplied to each pixel via the data line DL. Cgd (s) is a gate-drain parasitic capacitance, Cgs (d) is a gate-source parasitic capacitance, I (LE) is a leakage current, and I (WR) is a write current. LC is a liquid crystal element (liquid crystal capacitor), Cst is a storage capacitor, VCOM is a reference voltage applied to one end of the storage capacitor Cst, and LCOM is a lower pixel of the liquid crystal element (liquid crystal capacitor) A reference voltage applied to the electrode (eg, LCOM is set equal to VCOM).

  When image data is written to the second pixel PIX (B), the voltage change of the data line DL is scanned via the capacitance Cgd (s) parasitic on the NMOS transistor M100a in the first pixel PIX (A). Is transmitted to the line GLa. Therefore, the potential of the unselected scanning line GLa (that is, the gate potential of the NMOS transistor M100a) varies. Due to this gate potential fluctuation, the amount of leakage current I (LE) varies. Therefore, the voltage (display voltage) held in the holding capacitor Cst in the first pixel PIX (A) varies due to the leakage current I (LE), and affects the image display.

  (2) Problem 2 (Leakage current fluctuation due to change in voltage between source and drain of NMOS transistor)

  Since the potential written through the data line is arbitrarily determined for each pixel, the voltage applied between the source and drain of the NMOS transistor (transfer gate) configuring the non-selected pixel has various voltage values for each pixel. The amount of leakage current of the transistor varies from pixel to pixel depending on various source-drain voltage conditions. For example, even if there are multiple pixels holding the same voltage, if the voltage of the data line of each pixel changes with time, the voltage between the source and drain of the NMOS transistor in each pixel will change with time. It changes variously. Therefore, the result is that the amount of leakage current differs for each pixel. This affects display characteristics. When the problems 1 and 2 occur simultaneously, the display characteristics change.

  Here, reference is made to FIG. In FIG. 9B, GLa to GLd are scanning lines, DL1 and DL2 are data lines, A1 to D2 are pixels, PIX (g1) is a first pixel group, and PIX (g2) Is the second pixel group, and PIX (g3) is the third pixel group. For example, it is assumed that the scanning line GLa is selected and the voltage V1 is written in the first pixel group PIX (g1) (that is, the pixel A1 and the pixel A2). Next, the scanning lines GLb to GLd are sequentially selected, and for example, the voltage V2 (> V1) is written to the second pixel group PIX (g2) (that is, the pixels B1 to D1). For example, it is assumed that the voltage V0 (<V1) is written in the third pixel group PIX (g3) (that is, the pixel B2 to the pixel D2). In this case, the holding voltages of the two pixels (pixel A1 and pixel A2) included in the first pixel group PIX (g1) are different voltages. That is, the potential held in the pixels A1 and A2 is V1 (A2)> V1 (A1). Since the same voltage V1 is written, the holding voltage of the pixel A1 and the pixel A2 should be the same, but the holding voltage of each of the pixel A1 and the pixel A2 is affected by the fluctuation of the potential of the data line. The voltage value will be different.

(3) Problem 3 (Measures against α-ray (light) irradiation in the display device)
In display devices (for example, liquid crystal display devices and organic EL display devices), there is currently no particular countermeasure against α-ray (light) irradiation. However, when aiming at higher-definition image display, it is preferable to take measures against α-ray (light) irradiation in a display device (for example, a reflective liquid crystal (Liquid Crystal On Silicon, LCOS) panel).

This will be specifically described with reference to FIGS. 9C and 9D. FIG. 9C illustrates an example of a pixel structure. In FIG. 9C, GL is a scanning line, DL is a data line, M100 is an NMOS transistor as a pixel transistor, Cst is a holding capacitor, and LC is a liquid crystal element (liquid crystal capacitor). FIG. 9D illustrates an example of a cross-sectional structure of the NMOS transistor illustrated in FIG. In FIG. 9 (D), the above ^{P +} -type substrate 200, an ^{N +} layer 202 and 204 serving as the source and drain, are provided and ^{the P +} layer 206a and 206b for grounding the ^{P +} -type substrate 200. The surface of the P ⁺ type substrate 200 is covered with field oxide films 208a and 208b. Of the electron-hole pairs generated by α-ray (light) irradiation, holes are absorbed by the P ⁺ layers 206a and 206b for grounding the P ⁺ -type substrate 200, but the electrons become the source and drain. Move towards N ⁺ layers 202 and 204. As a result, the voltage of the N ⁺ layer 204 varies, and the retention voltage of the retention capacitor Cst varies.

  In this way, electrons and holes generated by the incidence of α-rays and light are attracted to the source (drain) of the pixel transistor (NMOS transistor), causing a change in the holding voltage of the pixel. May have an impact. Note that, as described above, in Patent Document 3, the charge generated by the α-ray is dealt with in the manufacturing process by the hydrogen diffusion layer formed by ion implantation. If α-ray countermeasures are implemented in the manufacturing process, the manufacturing process becomes complicated and the cost increases.

  The present invention has been made based on such consideration. According to some embodiments of the present invention, for example, it is possible to minimize the influence of fluctuations in the data line potential due to writing to the selected pixel on the non-selected pixel, and to significantly improve the display characteristics of the non-selected pixel. It is.

  (1) In one aspect of the electro-optical device of the present invention, n (n is an integer of 1 or more) main data lines and the k-th main data line (1 ≦ k) of the n main data lines. ≦ n), provided between m (m is an integer of 1 or more) sub-data lines, and each of the k-th main data line and the m sub-data lines, M first switches for switching electrical connection / disconnection between the k-th main data line and each of the m sub-data lines, and each of the one sub-data lines. I pixel circuits (i is an integer of 1 or more).

  In this aspect, the data lines are hierarchized. That is, at least one sub data line is provided for one main data line. At least one pixel circuit is connected to one sub data line. A first switch is provided between one main data line and sub data line. The electrical connection / non-connection between the main data line and the sub data line can be switched by turning on / off the first switch. If the first switch is turned on, the pixel voltage can be written to the selected pixel via the main data line and the sub data line. On the other hand, when all of at least one pixel connected to the sub data line is in a non-selected state, the sub data line can be electrically separated from the main data line by turning off the first switch. By this separation, even if the data line potential fluctuates due to the write voltage for the selected pixel, the potential fluctuation is not transmitted to the sub data line, and thus the non-selected pixel is not adversely affected. That is, the scanning line potential does not vary due to the parasitic capacitance of the pixel transistor. Therefore, the display characteristics of the non-selected pixel can be improved.

  (2) In another aspect of the electro-optical device of the present invention, m second switches for switching supply / non-supply of the non-selected sub data line voltage to each of the m sub data lines are provided. Each of the m first switches is turned on when a corresponding sub-data line of the m sub-data lines is in a selected state, turned off when in a non-selected state, and Each of the m second switches is turned off when the corresponding sub-data line among the m sub-data lines is selected, and turned on when the sub-data line is not selected.

  The non-selected sub data line voltage is supplied to the non-selected sub data line via the second switch. As described above, the first switch is turned on when the corresponding sub data line is in the selected state (that is, when at least one of the pixel circuits connected to the sub data line is selected), and is in the non-selected state. (That is, when all the pixel circuits connected to the sub data line are not selected). On the other hand, the second switch is turned on / off in a complementary manner (in reverse phase) with respect to the first switch. In other words, the second switch is turned on when the corresponding sub data line is in the non-selected state, and supplies the non-selected sub data line voltage (VR) to the sub data line in the non-selected state. Turns off when selected. The non-selected sub data line is electrically isolated from the main data line and is maintained at a constant voltage (VR: non-selected sub data line voltage) different from the voltage of the main data line. The amount of leakage current depends only on the voltage held in the pixel, and the influence of the potential of the main data line is eliminated. Therefore, the non-selected pixel connected to the sub data line maintains a more stable non-selected state, such as electrical noise from the selected pixel electrically connected to the main data line. Will be significantly reduced. Therefore, as compared with the conventional case, the variation in the display characteristics of the non-selected pixel is reduced, and the display quality is improved.

  (3) In another aspect of the electro-optical device according to the aspect of the invention, the non-selected sub data line voltage may be a midpoint between the maximum voltage and the minimum voltage of the image signal transmitted via the kth main data line. Is the voltage.

  By setting the non-selected sub data line voltage (VR) to a voltage corresponding to the midpoint potential ((maximum value−minimum value) / 2) of the maximum value and the minimum value of the voltage written to the pixel, The maximum leakage current can be suppressed as compared with the conventional case. For example, the maximum value of the voltage written to the pixel is 5V, and the minimum value is 0V. Conventionally, there is a possibility that a maximum voltage of 5V is applied to the source / drain of a non-selected pixel transistor (for example, NMOS transistor) (the data line voltage is 0V or 5V, and the pixel holding voltage is 5V). Or when it is 0V). In this embodiment, since the non-selected sub data line voltage (VR) is 2.5 V, for example, the maximum value of the voltage applied between the source and drain of the pixel transistor regardless of whether the pixel holding voltage is 0 V or 5 V Is 2.5 V, which is half the maximum value of the conventional source-drain voltage. Therefore, the leakage current of the pixel transistor is also suppressed compared to the conventional case. Further, when the sub data line is changed from the non-selected state to the selected state, the sub data line is set in advance to the midpoint voltage (that is, VR) of the maximum value and the minimum value of the image signal. Regardless of the voltage, the fluctuation range (amplitude) of the voltage of the sub data line is minimized. By minimizing the amplitude of the sub data line, the mutual influence between the plurality of pixels connected to the sub data line (that is, the potential fluctuation of the sub data line due to the write voltage of the selected pixel is not selected) It is also possible to obtain an effect that the transmission is performed via the parasitic capacitance of the pixel transistor of the pixel in the state and the holding voltage of the pixel in the non-selected state is reduced).

  (4) In another aspect of the electro-optical device according to the aspect of the invention, the potential polarity of the image signal is periodically switched based on a predetermined potential, and the non-selected sub data line voltage is positive when the image signal is positive. In some cases, the voltage is a midpoint voltage between the maximum voltage and the minimum voltage of the positive image signal transmitted via the kth main data line, and the image signal is negative. This is the midpoint voltage between the maximum voltage and the minimum voltage of the negative image signal transmitted through the k main data lines.

  As a result, even when the voltage polarity of the image signal transmitted via the main data line is periodically inverted (that is, when the pixel is AC driven), the same operation and effect as the above (3) can be obtained. Can do.

  (5) In another aspect of the electro-optical device according to the aspect of the invention, the potential polarity of the image signal is periodically switched based on a predetermined potential, and the non-selected sub data line voltage is positive when the image signal is positive. The maximum voltage transmitted through the kth main data line in some cases and the minimum voltage transmitted through the kth main data line when the image signal is negative. The voltage at the point.

  In this aspect, the unselected sub data line voltage (VR) is always a constant value and does not need to be changed. Therefore, even when the voltage polarity of the image signal transmitted via the main data line is periodically inverted (that is, when the pixel is AC-driven), the non-selected sub data line voltage (VR) depends on the voltage polarity. ) Need not be inverted, and thus the burden on the driver circuit of the display device is reduced.

  (6) In another aspect of the electro-optical device of the present invention, each of the i pixel circuits includes a transfer provided between a pixel electrode, each of the m sub-data lines, and the pixel electrode. And the non-selected sub data line voltage is set to a voltage equal to or higher than a maximum voltage transmitted via the kth main data line when the transfer switch is configured by an NMOS transistor, When the transfer switch is composed of a PMOS transistor, the voltage is set to a voltage equal to or lower than the minimum voltage transmitted via the kth main data line.

  In this aspect, carriers (charges) generated when high-energy radiation such as light or α rays is incident on a silicon substrate, for example, are moved to the sub-data line side (for example, the source side of the pixel transistor constituting the transfer switch). Can be collected and absorbed. Therefore, for example, the drain potential fluctuation of the pixel transistor constituting the transfer switch is suppressed. In other words, the amount of charge stored in the storage capacitor by recombining the charge stored in the storage capacitor of the pixel with the charge of the polarity attracted to the storage capacitor among the carriers generated by irradiation with α rays and the like. This reduces the problem of reducing. Therefore, fluctuations in the holding voltage of the pixel can be suppressed electrically. Since there is no change in the manufacturing process, there is no concern that the manufacturing process becomes complicated or the manufacturing cost increases.

  (7) In another aspect of the electro-optical device of the present invention, m second for switching supply / non-supply of the first non-selected sub data line voltage to each of the m sub data lines. And m number of third switches for switching supply / non-supply of the second non-selected sub-data line voltage to each of the m sub-data lines. Each of the first switches is turned on when a corresponding sub-data line of the m sub-data lines is in a selected state, and is turned off when the sub-data line is in a non-selected state, and the m second switches And each of the third switches is turned off when the corresponding sub-data line of the m sub-data lines is in a selected state, and the corresponding sub-data line of the m sub-data lines When is not selected, first, the third switch is turned on. The second non-selected sub-data line voltage is supplied to a corresponding sub-data line among the m sub-data lines, and then the third switch is turned off and the second switch is turned on. The first unselected sub data line voltage is supplied to a corresponding sub data line among the m sub data lines.

  In general, a large number of non-selected sub-data lines are connected to a supply node (or supply line) of a non-selected sub-data line voltage (VR). Therefore, when one sub data line changes from the selected state to the non-selected state, the non-selected sub data line voltage (VR) supply node is applied to the sub data line immediately after being electrically separated from the main data line. Is connected, a charge / discharge current flows along with the connection. The charge / discharge current may be a factor (noise factor) that fluctuates the potential of many other non-selected sub-data lines connected to the supply node of the non-selected sub-data line voltage (VR). In this case, the display characteristics of the non-selected pixel are affected. Therefore, in this aspect, two types of voltages (for example, a first non-selected sub data line voltage VRB and a second non-selected sub data line voltage VRA) are prepared as non-selected sub data line voltages. The two types of unselected sub-data line voltages (VRB and VRA) are preferably separated from each other electrically (preferably also physically). However, the voltage values of VRB and VRA are basically the same (however, for example, a slight difference can be provided). When one sub data line changes from the selected state to the non-selected state, the third switch is turned on, and first, the second non-selected sub data line voltage VRA is supplied to the sub data line. As a result, the potential of the sub data line converges to the second unselected sub data line voltage VRA (or becomes a voltage close to VRA). At this time, the charge / discharge current flows and the VRA potential fluctuates. However, since VRA is electrically (preferably further physically separated) from VRB, the VRA potential fluctuation affects the VRB potential. Don't give. Therefore, there is no influence on many non-selected pixels connected to the VRB. After the potential of the sub data line approaches VRA (ideally after it matches VRA), the third switch is turned off to disconnect VRA from the sub data line, and then the second switch is turned on. , VRB is supplied to the sub data line. Since the sub-data line has the same voltage as VRB or a voltage in the vicinity of VRB, the amount of charge / discharge current is reduced, and therefore there is almost no effect on a large number of non-selected pixels. Therefore, the display characteristics of the non-selected pixel can be further improved.

  (8) In another aspect of the electro-optical device of the present invention, the first switch is a mechanical switch.

  For example, by using a mechanical switch (eg, a switch manufactured using MEMS (Mechanical Electrical Microsystem) technology) as the first switch, more complete electrical isolation is realized and leakage current is increased. Can be further reduced. Therefore, it is possible to further reduce the influence of fluctuations in the sub data line potential on the display characteristics of the pixels. A similar effect can be obtained by using a mechanical switch as the above-described second switch (or third switch).

  (9) In one aspect of the driving method of the electro-optical device of the present invention, n (n is an integer of 1 or more) main data lines and the k-th main data line (n of the n main data lines) 1 (k ≦ n) provided between m sub-data lines (m is an integer of 1 or more) and each of the k-th main data line and the m sub-data lines. M first switches for switching electrical connection / disconnection between the k-th main data line and each of the m sub-data lines, and the one sub-data line. M pixel circuits for switching supply / non-supply of unselected sub data line voltages to i pixel circuits (i is an integer of 1 or more) connected to each of the m sub data lines. A method of driving an electro-optical device including a second switch, wherein the m sub-data lines When the xth (1 ≦ x ≦ m) sub-data line is selected, the x-th first switch corresponding to the x-th sub-data line among the m first switches is selected. The image signal is turned on to at least one of the i pixel circuits connected to the xth sub data line via the kth main data line and the xth subdata line. And when the x-th (1 ≦ x ≦ m) sub-data line of the m sub-data lines is not selected, the x-th of the m first switches The xth first switch corresponding to a sub data line is turned off, thereby electrically separating the kth main data line and the xth subdata line, and the xth The x-th second switch corresponding to the sub data line is turned on to Supplying-option sub data line voltage to the sub-data lines of the first x.

  In the driving method of the electro-optical device according to this aspect, the data lines are hierarchized, and when a pixel is selected, the pixel voltage is written to the selected pixel via the main data line and the corresponding sub data line. On the other hand, when all of at least one pixel connected to the sub data line is in the non-selected state, the sub data line is electrically separated from the main data line by turning off the first switch. By this separation, even if the data line potential fluctuates due to the write voltage for the selected pixel, the potential fluctuation is not transmitted to the sub data line, and thus the non-selected pixel is not adversely affected. In other words, the above-described problem 1 is solved without the fluctuation of the scanning line potential caused by the parasitic capacitance of the pixel transistor. Therefore, the display characteristics of the non-selected pixel can be improved. Further, the non-selected sub data line voltage (VR) is supplied to the non-selected sub data line (that is, the sub data line electrically disconnected from the main data line) via the second switch. To do. That is, the non-selected sub data line is electrically separated from the main data line and is maintained at a constant voltage (VR: non-selected sub data line voltage) different from the voltage of the main data line. The amount of leakage current of the transistor depends only on the voltage held in the pixel, and the influence of the potential of the sub data line is eliminated. Therefore, the non-selected pixel connected to the sub data line maintains a more stable non-selected state, such as electrical noise from the selected pixel electrically connected to the main data line. Will be significantly reduced. Therefore, as compared with the conventional case, the variation in the display characteristics of the non-selected pixel is reduced, and the display quality is improved.

(10) An electronic apparatus of the present invention is equipped with the above electro-optical device.
In the electro-optical device of the present invention, display characteristics are improved by hierarchizing data lines, and high-quality display is possible. Accordingly, the display performance of an electronic device (for example, a mobile phone terminal equipped with a liquid crystal display panel) equipped with the electro-optical device is also improved.

  As described above, according to some embodiments of the present invention, for example, the influence of fluctuations in the data line potential caused by writing to the selected pixel on the non-selected pixel is minimized, and the display characteristics of the non-selected pixel are significantly improved. It becomes possible to make it.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
In the following description, a liquid crystal display device will be described as an example of an electro-optical device. However, the invention is not limited to this, and the electro-optical device may be an organic EL display device or other display devices.

(Configuration and operation of the main part of a liquid crystal display device with a hierarchical data line structure)
FIGS. 1A to 1C are diagrams for explaining a configuration of a main part of a liquid crystal display device having a hierarchical data line structure and a voltage applied to a sub data line. In FIG. 1A, the sub data line is in a non-selected state, and in FIG. 1B, the sub data line is in a selected state.

  In FIG. 1A and FIG. 1B, one sub data line SDLn is provided corresponding to one main data line MDLn among a plurality of data lines. That is, the data lines are distinguished from main data lines and sub data lines. That is, the data lines are hierarchized. It is also possible to connect (correspond to) a plurality of sub data lines to one main data line MDLn. For example, at least one sub data line can be further provided in the horizontal direction of the sub data line SDLn in FIG. 1A (the direction in which the scanning line L10 extends). Further, it is possible to adopt a configuration in which the sub data lines are arranged around the main data line on the left and right sides (for example, so as to be line symmetric). When the sub data lines are arranged symmetrically (symmetrically) with the main data line as the center, there is an advantage that, for example, when a wiring is formed using a multilayer wiring structure, a balanced high-density arrangement is realized. .

  1A and 1B, a plurality of pixel circuits (specifically, (m + 1) pixel circuits) are connected to one main data line MDLn. Note that at least one pixel circuit (pixel) may be connected to one main data line MDLn. One pixel circuit includes a transistor (NMOS transistor: pixel transistor) M1, which forms a transfer switch, a holding capacitor Cst, and a liquid crystal element (liquid crystal capacitor) LC. Note that the configuration of the pixel circuit is not limited to this, and a circuit configuration using a flip-flop (RAM) instead of a storage capacitor can be employed as the configuration of the pixel circuit. On / off of the pixel transistor M1 in each pixel circuit is controlled by the scanning lines (GL0 to GLm). An image signal VDn (write voltage) is supplied to one end (for example, source) of the pixel transistor M1 via the main data line MDLn and the sub data line SDLn. One end of the storage capacitor Cst and one pixel electrode of the liquid crystal element are connected to the other end (drain) of the pixel transistor M1. A reference voltage VCOM is applied to the other end of the storage capacitor. A reference voltage LCOM (voltage value is the same as, for example, VCOM) is applied to the other pixel electrode (counter electrode) of the liquid crystal element.

  A first switch SW1 is provided between the main data line MDLn and the sub data line SDLn corresponding to the main data line MDLn. By switching on / off the first switch SW1, the electrical connection / disconnection between the main data line MDLn and the sub data line SDLn can be switched. The first switch SW1 is turned on when the sub data line SDLn is in a selected state (that is, when at least one pixel circuit connected to the sub data line SDLn is in a selected state), and the sub data line SDLn is turned on. It is turned off when it is in a non-selected state (that is, when all of at least one pixel circuit connected to the sub data line SDLn is not selected). ON / OFF of the first switch SW1 is controlled by a switch control signal Y.

  A second switch SW2 is provided between the sub data line SDLn and the supply node NE1 for the non-selected sub data line voltage VR. The second switch SW2 is in a non-selected state when the sub data line SDLn is in a non-selected state (that is, when all of at least one pixel circuit connected to the sub data line SDLn is not selected). It is provided for supplying unselected sub data line voltage VR to sub data line SDLn. The second switch SW2 is turned off when the sub data line SDLn is in the selected state (that is, when at least one pixel circuit connected to the sub data line SDLn is in the selected state), and the sub data line SDLn is It is turned on when it is in a non-selected state (that is, when at least one pixel circuit connected to the sub-data line SDLn is not selected). On / off of the second switch SW1 is controlled by a switch control signal / Y (a signal having a phase opposite to that of the switch control signal Y).

  As shown in FIG. 1B, when the first switch SW1 is turned on, the pixel voltage can be written to the selected pixel via the main data line MDLn and the sub data line SDLn. In FIG. 1B, a thick arrow indicates a current that flows as image data is written.

  On the other hand, in the state shown in FIG. 1A, the sub data line SDLn can be electrically separated from the main data line MDLn by turning off the first switch SW1. By this separation, a write voltage (image signal) for the selected pixel (that is, a pixel related to another sub-data line connected to the main data line MDLn: not shown in FIGS. 1A and 1B). Even if the potential of the main data line MDLn fluctuates due to VDm, the potential fluctuation is not transmitted to the sub data line SDLn, and thus the unselected pixels connected to the sub data line SDLn are not adversely affected. That is, the scanning line potential does not vary due to the parasitic capacitance of the pixel transistor M1. Therefore, the display characteristics of the non-selected pixel can be improved.

  However, if the voltage of the non-selected sub data line SDLn is indefinite, the display voltage of the pixel circuit connected to the sub data line SDLn may be affected. Therefore, in FIG. 1A, the first switch SW1 is turned off, and at the same time, the second switch SW2 is turned on to supply the non-selected sub data line voltage VR to the sub data line SDLn. That is, the non-selected sub data line SDLn is electrically isolated from the main data line and is different from the main data line MDLn in the non-selected sub data line voltage VR (a constant different from the main data line voltage). Voltage).

  As shown in FIG. 1A, the non-selected sub data line voltage VR is supplied to the non-selected sub data line SDLn via the supply node NE1, the supply line L10, and the second switch SW2. . A thick arrow in FIG. 1A indicates a current that flows along with the supply of VR. At this time, the amount of leakage current of the pixel transistor M1 connected to the non-selected sub data line SDLn depends only on the voltage held in the pixel, and the influence of the potential of the main data line is eliminated. Is done. Therefore, the non-selected pixel connected to the sub data line maintains a more stable non-selected state, such as electrical noise from the selected pixel electrically connected to the main data line. Will be significantly reduced. Therefore, as compared with the conventional case, the variation in the display characteristics of the non-selected pixel is reduced, and the display quality is improved.

  The above-described circuit configuration of the electro-optical device shown in FIGS. 1A and 1B is generalized and expressed as follows. In the following description, variables N, M, K, and I are used for convenience. That is, the electro-optical device is provided corresponding to N main data lines (N is an integer equal to or greater than 1) and the Kth main data line (1 ≦ K ≦ N) of the N main data lines. Provided between the M sub data lines (M is an integer equal to or greater than 1) and each of the Kth main data line and the M sub data lines, and the Kth main data line and the M sub data lines. M first switches for switching electrical connection / disconnection with each of the sub data lines, and I (I is an integer of 1 or more) connected to each of the M sub data lines A pixel circuit. The electro-optical device has M second switches for switching supply / non-supply of the non-selected sub data line voltage to each of the M sub data lines, and the M first data Each of the switches is turned on when a corresponding sub-data line of the M sub-data lines is in a selected state, is turned off when the sub-data line is in a non-selected state, and each of the M second switches is Turns off when the corresponding sub-data line of the M sub-data lines is selected, and turns on when the sub-data line is not selected.

(Consideration on unselected sub-data line voltage VR)
Next, the voltage level of the unselected sub data line voltage VR will be considered with reference to FIG.

(Discussion 1)
In FIG. 1C, + V and −V indicate voltages applied to the liquid crystal element LC in the positive field and the negative field. Data “1” is written to the pixel during the period from time t1 to time t2. Data “0” is written into the pixel during the period from time t2 to time t3. As apparent from FIG. 1C, the write voltage corresponding to the data “1” is + V (in the case of the positive field) and −V (in the case of the negative field), and the write voltage corresponding to the data “0” is VCOM. The voltage polarity of the applied voltage to the liquid crystal is inverted every frame (or subfield), for example, to prevent the burn-in of the liquid crystal. That is, the liquid crystal element LC is periodically AC driven. A period during which a positive voltage is applied to the liquid crystal with reference to the reference voltage VCOM is a positive field, and a period during which a negative voltage is applied to the liquid crystal with respect to VCOM is a negative field.

Here, the case of the positive field is considered. In FIG. 1C, the non-selected sub data line voltage VR is set to the midpoint potential of the maximum voltage + V and the minimum voltage VCOM of the positive image signal. That is, the following formula (1) is established.
VR = (+ V−VCOM) / 2 + VCOM (1)

  By setting the non-selected sub data line voltage VR to a voltage corresponding to the voltage of the midpoint between the maximum value and the minimum value ((maximum voltage−minimum voltage) / 2), the maximum leakage current from the pixel transistor is set. The value can be suppressed compared to the conventional case. For example, the maximum value of the voltage written to the pixel is 5V, and the minimum value is 0V. Conventionally, there is a possibility that a maximum voltage of 5V is applied to the source / drain of the non-selected pixel transistor (NMOS transistor M1) (the data line voltage is 0V or 5V, and the pixel holding voltage is 5V or When 0V). On the other hand, when the non-selected sub data line voltage VR is set as shown in FIG. 1C, the non-selected sub data line voltage (VR) is, for example, 2.5V. In any case of 5V, the maximum value of the voltage applied between the source and drain of the pixel transistor M1 is 2.5V, which is half of the conventional maximum value of the source-drain voltage. Therefore, the leakage current of the pixel transistor is also suppressed compared to the conventional case.

  Further, when the sub data line SDLn is changed from the non-selected state to the selected state, the sub data line SDLn is set to a voltage at the midpoint (intermediate) of the maximum value and the minimum value of the image signal in advance. Regardless of the voltage VDn, the fluctuation range (amplitude) of the voltage of the sub data line SDLn is minimized. By minimizing the amplitude of the sub data line SDLn, the mutual influence between a plurality of pixels connected to the sub data line SDLn (that is, the potential fluctuation of the sub data line due to the write voltage of the pixel in the selected state is There is also an effect that the transmission is performed via the parasitic capacitance of the pixel transistor M1 of the pixel in the non-selected state and the holding voltage of the pixel in the non-selected state fluctuates).

For the negative field, the following equation (2) is established. As a result, the same effect as in the positive field can be obtained.
VR = (− V−VCOM) / 2 + VCOM (2)

(Discussion 2)
Here, measures against alpha ray (light) irradiation are considered. In this embodiment, when the pixel transistor M1 functioning as a transfer switch is an NMOS transistor, the non-selected sub data line voltage VR is set to a voltage equal to or higher than the maximum voltage transmitted via the main data line MDLn. When the pixel transistor M1 functioning as a PMOS transistor is configured, the voltage is set to a voltage equal to or lower than the minimum voltage transmitted via the main data line MDLn.

Reference is now made to FIG. 2A and 2B are diagrams for explaining an example in which the non-selected sub data line voltage is used as a voltage for absorbing carriers generated by irradiation with alpha rays (light). In FIG. 2A, the pixel transistor M1 is an NMOS transistor. In FIG. 2A, a P-type substrate 100 is provided with N ⁺ layers 102 and 104 serving as a source and a drain. Reference numeral 106 is a gate electrode made of polysilicon. The non-selected sub data line voltage VR is applied to the N ⁺ layer 102 serving as the source via the sub data line SDLn.

  The unselected sub data line voltage VR is set to a voltage equal to or higher than the maximum voltage transmitted via the main data line MDL. That is, as shown in FIG. 2B, the non-selected sub data line voltage VR (NMOS) when the pixel transistor M1 is an NMOS transistor passes through the main data line MDL regardless of the positive field / negative field. Is set to a voltage + V1 equal to or higher than the maximum voltage + V transmitted.

As shown in FIG. 2A, among the electron-hole pairs generated by irradiation with α rays (light), holes are absorbed by the ground potential (tap potential) of the P-type substrate 100, but electrons are Attempts to move toward both N ⁺ layers 102 and 104, which will be the source and drain. However, since the non-selected sub data line voltage VR (voltage higher than the maximum write voltage) is applied to the source N ⁺ layer 102 via the sub data line SDLn, electrons are transferred to the N ⁺ layer 102. Move towards and be absorbed. Therefore, the fluctuation of the voltage of the N ⁺ layer 104 is suppressed, and the fluctuation of the holding voltage of the holding capacitor Cst is minimized.

In this way, electrons generated by the incidence of α rays or light are attracted to the source layer N ⁺ layer 102 of the pixel transistor (NMOS transistor) and disappear, so that fluctuations in the holding voltage of the pixel are suppressed. In other words, the amount of charge stored in the storage capacitor by recombining the charge stored in the storage capacitor of the pixel with the charge of the polarity attracted to the storage capacitor among the carriers generated by irradiation with α rays and the like. This reduces the problem of reducing. Therefore, fluctuations in the holding voltage of the pixel can be suppressed electrically. Since there is no change in the manufacturing process, there is no concern that the manufacturing process becomes complicated or the manufacturing cost increases.

When the pixel transistor M1 functioning as a transfer switch is configured with a PMOS transistor, the non-selected sub data line voltage VR is set to a voltage equal to or lower than the minimum voltage transmitted via the main data line MDLn. That is, as shown in FIG. 2B, the non-selected sub data line voltage VR (PMOS) when the pixel transistor M1 is a PMOS transistor passes through the main data line MDL regardless of the positive field / negative field. Is set to a voltage −V1 which is equal to or lower than the minimum voltage −V transmitted. In this case, the holes generated by the incidence of α rays and light are attracted to the source layer N ⁺ layer 102 of the pixel transistor (PMOS transistor) and disappear, so that the variation in the holding voltage of the pixel is suppressed. In other words, the amount of charge stored in the storage capacitor by recombining the charge stored in the storage capacitor of the pixel with the charge of the polarity attracted to the storage capacitor among the carriers generated by irradiation with α rays and the like. This reduces the problem of reducing. Therefore, fluctuations in the holding voltage of the pixel can be suppressed electrically. Since there is no change in the manufacturing process, there is no concern that the manufacturing process becomes complicated or the manufacturing cost increases.

(Discussion 3)
Further, the non-selected sub data line voltage VR can be set to VCOM. VCOM is a maximum voltage + V transmitted via the main data line MDLn when the image signal is positive and a minimum voltage transmitted via the main data line MDLn when the image signal is negative. This is the midpoint (intermediate) voltage from −V.

  In this case, the non-selected sub data line voltage VR is always a constant value and does not need to be changed according to the positive field / negative field. Therefore, the burden on the driver circuit of the liquid crystal display device is reduced. Note that the VR voltage setting described in the above considerations 1 to 3 is an example, and other voltage settings can be appropriately set.

(Second Embodiment)
In the present embodiment, an example of the entire configuration of the liquid crystal display device will be described.

(Example of configuration of liquid crystal display device)
FIG. 3 is a diagram for explaining an example of the entire configuration of the liquid crystal display device. The liquid crystal display device of FIG. 3 has a plurality of pixels PIX arranged in a matrix of n rows and n columns (n is an integer of 0 or more). In FIG. 3 and the following description, the pixel in the nth row and the nth column is PIX (n, n). In FIG. 3, main data lines MDL0 to MDLn are prepared. MDLn represents the nth column main data line. For the sub data line SDL, the notation SDL (n, 0) or SDL (n, 1) is used. The sub data line SDL is divided into two sub data lines, that is, an upper sub data line and a lower sub data line. “0” is used, and “1” is used for the upper sub-data line. That is, SDL (n, 0) represents the lower sub-data line in the nth column, and SDL (n, 1) represents the upper sub-data line in the nth column. In FIG. 3, GL (M) to GL (M-3) are drawn as scanning lines. In FIG. 3, GL (M) is the lowermost scanning line.

  The liquid crystal display device of FIG. 3 includes a scanning line driving circuit 200, a data line driving circuit 300, a plurality of pixels (PIX (n, n)) arranged two-dimensionally, and data having a hierarchical structure. Lines (having main data lines MDL0 to MDLn and sub data lines SDL (0,0) to SDL (n, 1)), a first switch circuit (lower circuit SW1a, upper circuit SW1b), a second Switch circuit (lower circuit SW2a, upper circuit SW2b). The first switch circuit (lower circuit) SW1a includes a plurality of NMOS transistors MQa that function as first switches. The first switch circuit (upper circuit) SW1b is composed of a plurality of NMOS transistors MQb that function as first switches. The second switch circuit (lower circuit) SW2a includes a plurality of NMOS transistors MRa that function as second switches. The second switch circuit (upper circuit) SW2b includes a plurality of NMOS transistors MRb that function as second switches.

  The scanning line driving circuit 200 drives each of the scanning lines GL (M) to GL (M-3), for example, line-sequentially. Further, the scanning line driving circuit 200 controls on / off of the plurality of first switches (NMOS transistors MQa) included in the first switch circuit (lower circuit) SW1a by the control signal Yp, and the second switch On / off of a plurality of second switches (NMOS transistors MRa) included in the circuit (lower circuit) SW2a is controlled by a control signal / Yp, and a plurality of second switches included in the second switch circuit (upper circuit) SW2b are controlled. The on / off of the second switch (NMOS transistor MRb) is controlled by the control signal / Yp-1, and the plurality of first switches (NMOS transistors MQb) included in the first switch circuit (upper circuit) SW1b are turned on / off. Off is controlled by the control signal Yp-1. The operation of the scanning line driving circuit 200 is controlled by a control signal YCNT.

  Image signals VID0 to VIDx are input to the data line driving circuit 300, and the image signals are supplied to at least one of the main data lines (MDL0 to MDLn). The operation of the data line driving circuit 300 is controlled by a control signal XCNT. The reference voltage VCOM is supplied to each pixel circuit via the wiring L200. The non-selected sub data line voltage VR is supplied to each of the sub data lines (SDL (0,0) to SDL (n, 1)) via the supply node NE1, the wiring L100, and the second switch circuits SW2a and SW2b. To be supplied.

  In the liquid crystal display device of FIG. 3, two sub data lines (an upper sub data line and a lower sub data line) are provided for one main data line. Next, the operation of the liquid crystal display device of FIG. 3 will be described with reference to FIG. In the following description, it is assumed that data is written in four pixels (PIX (0, 0) to PIX (3, 0)) arranged in a line in the vertical direction on the left side among the pixels shown in FIG. .

(Operation example of liquid crystal display device)
FIG. 4 is a timing chart for explaining an example of the operation of the liquid crystal display device of FIG. As shown in (1) to (4) of FIG. 4, the scanning lines GL (M−3) to GL (M) are driven line-sequentially. Further, as shown in (5) and (6) of FIG. 4, the switch control signal Yp-1 becomes H level and / Yp-1 becomes L level in the period from time t0 to t8. As a result, the sub data line SDL (0, 1) is selected. Similarly, as shown in (7) and (8) of FIG. 4, the switch control signal Yp becomes H level and / Yp becomes L level during the period from time t8 to t16. As a result, the sub data line SDL (0, 0) is selected.

  As shown in (9) of FIG. 4, write data (image data) D1, D2, D3, and D4 are supplied to the main data line MDL0. The potential of the sub data line SDL (0, 1) changes as indicated by (10) in FIG. The potential of the sub data line SDL (0, 0) changes as indicated by (11) in FIG. Each of the pixel PIX (3, 0), the pixel PIX (2, 0), the pixel PIX (1, 0), and the pixel PIX (0, 0) is shown in (12) to (15) of FIG. As described above, each of the write data (image data) D1 to D4 is written.

(Third embodiment)
FIG. 5 is a circuit diagram showing another example of a configuration of a main part of a liquid crystal display device having a hierarchical data line structure.

(Configuration of liquid crystal display device)
The circuit configuration of FIG. 5 is basically the same as the circuit configuration shown in FIG. However, in this embodiment, two types of voltages VRA (preliminary voltage) and VRB (regular voltage) are used as the unselected sub data line voltage VR. That is, the first non-selected sub data line voltage VRB and the second non-selected sub data line voltage VRA are provided, and when the sub data line is changed from the selected state to the non-selected state, first, The sub-data line voltage VRA is supplied to the non-selected sub-data line, and then the first non-selected sub-data line voltage VRB is supplied. The supply of the first sub data line voltage VRB is controlled by second switches (NMOS transistors) MB1 and MB2 constituting the switch circuit SW20. On / off of the second switches (NMOS transistors) MB1 and MB2 is controlled by switch control signals / YBp-1 and / YBp output from the scanning line driving circuit 200. The supply of the second sub data line voltage VRA is controlled by third switches (NMOS transistors) MRa and MRb constituting the switch circuit SW10. On / off of the second switches (NMOS transistors) MRa and MRb is controlled by switch control signals / Yp and / Yp−1 output from the scanning line driving circuit 200.

  In general, a large number of non-selected sub-data lines SDL are connected to a supply node (or supply line) of the non-selected sub-data line voltage VR. Therefore, when one sub data line SDL is changed from the selected state to the unselected state, the non-selected sub data line voltage VR is supplied to the sub data line SDL immediately after being electrically separated from the main data line MDL. When nodes are connected, a charge / discharge current flows along with the connection. The charge / discharge current may be a factor (noise factor) that fluctuates the potentials of many other non-selected sub-data lines SDL connected to the supply node of the non-selected sub-data line voltage VR. In this case, the display characteristics of the non-selected pixel are affected.

  Therefore, in this embodiment, two types of voltages (first unselected sub data line voltage VRB and second unselected sub data line voltage VRA) are prepared as the unselected sub data line voltage VR. The two types of unselected sub-data line voltages (VRB and VRA) are preferably separated from each other electrically (preferably also physically). However, the voltage values of VRB and VRA are basically the same (however, for example, a slight difference can be provided). When one sub data line SDL changes from the selected state to the non-selected state, the third switches MRa and MRb are turned on, and the sub data lines (SDL (0,1), SDL (0,0)) are turned on. First, the second unselected sub data line voltage VRA is supplied. As a result, the potentials of the sub data lines (SDL (0, 1), SDL (0, 0)) converge (or become close to) the second unselected sub data line voltage VRA. At this time, the charge / discharge current flows and the VRA potential fluctuates. However, since VRA is electrically (preferably further physically separated) from VRB, the VRA potential fluctuation affects the VRB potential. Don't give. Therefore, there is no influence on many non-selected pixels connected to the VRB. After the potentials of the sub-data lines (SDL (0,1), SDL (0,0)) approach VRA (ideally after matching with VRA), the third switches MRa and MRb are turned off and VRA Is disconnected from the sub data lines (SDL (0,1), SDL (0,0)), and then the second switch (MB1, MB2) is turned on to connect the VRB to the sub data lines (SDL (0,1)). ), SDL (0, 0)). Since the sub data lines (SDL (0,1), SDL (0,0)) are preliminarily charged (or discharged) by VRA and become the same voltage as VRB or a voltage in the vicinity of VRB. The amount of discharge current is reduced. Therefore, the non-selected pixels connected to the VRB supply node (NE1 in FIG. 3) or the VRB supply line (L100 in FIG. 3) are hardly affected. Therefore, the display characteristics of the non-selected pixel can be further improved.

(Example of circuit for generating VRA and VRB)
FIGS. 6A and 6B are circuit diagrams showing examples of circuits for generating the first and second unselected sub data line voltages. In the case of FIG. 6A, the first sub data line voltage VRB and the second non-selected sub data line voltage VRA are electrically separated via the switch SW3. VRA and VRB are generated by the following procedure. First, the non-selected sub data line voltage VR is applied to the terminal TP1, and the switch SW3 is turned on. Charges are accumulated in the capacitor CA and the capacitor CB, and VRA and VRB (both voltages coincide with VR) are generated. Next, the switch SW3 is turned off. As a result, VRA and VRB are electrically separated by the switch SW3.

  In the case of FIG. 6B, the first sub data line voltage VRB and the second non-selected sub data line voltage VRA are separated not only electrically but also physically. That is, VRA and VRB are generated by separate circuits that are completely separated. VRA is applied to terminal TP2. The capacitor CA functions as a stabilizing capacity. Similarly, VRB is applied to the terminal TP3. The capacitor CB functions as a stabilizing capacity. Since it is preferable that VRA and VRB have high independence, it can be said that the circuit configuration in FIG. 6B has higher reliability.

(Operation example of liquid crystal display device)
FIG. 7 is a timing chart for explaining an example of the operation of the liquid crystal display device of FIG. As shown in (1) to (4) of FIG. 7, the scanning lines GL (M−3) to GL (M) are driven line-sequentially. Further, as shown in (5) and (6) of FIG. 7, the switch control signal Yp-1 becomes the H level during the period of time t0 to t8, whereby the sub data line SDL (0, 1) is selected. Is done.

  Here, it should be noted that the switch control signal / Yp-1 becomes H level during the period from time t8 to t8 ', whereby the second non-selected data is supplied to the sub-data line SDL (0, 1). The line voltage VRA is applied. Further, as shown in (7) of FIG. 7, at time t8 ', the switch control signal / Yp-1 changes to L level, and at the same time, the switch control signal / YBp-1 changes from L level to H level. As a result, the first non-selected data line voltage VRB is applied to the sub data line SDL (0, 1).

  Similarly, as shown in (8) of FIG. 7, the switch control signal Yp becomes H level during the period from time t8 to t16, and thereby the sub data line SDL (0, 0) is selected. Further, as shown in (9) of FIG. 7, the switch control signal / Yp becomes H level during the period from time t16 to t16 ′, and thereby the second non-data line SDL (0, 0) is supplied to the second non-line. A selected data line voltage VRA is applied.

  Further, at time t16 ', the switch control signal / Yp becomes L level, and at the same time, as shown in (10) of FIG. 7, the switch control signal / YBp changes from L level to H level. As a result, the first non-selected data line voltage VRB is applied to the sub data line SDL (0, 0).

  As shown in (11) of FIG. 7, write data (image data) D1, D2, D3, and D4 are supplied to the main data line MDL0. The potential of the sub data line SDL (0, 1) changes as indicated by (10) in FIG. The potential of the sub data line SDL (0, 0) changes as indicated by (12) in FIG. VRA is applied during a period from time t8 to t8 ', and VRB is applied after time t8'. Similarly, the potential of the sub data line SDL (0, 0) changes as indicated by (13) in FIG. VRA is applied during a period from time t16 to t16 ', and VRB is applied after time t16'.

  Each of the pixel PIX (3, 0), the pixel PIX (2, 0), the pixel PIX (1, 0), and the pixel PIX (0, 0) is shown in (14) to (17) of FIG. As described above, each of the write data (image data) D1 to D4 is written.

(Fourth embodiment)
FIG. 8 is a perspective view showing an appearance of an example (mobile phone terminal) of an electronic device in which the liquid crystal display device of the present invention is mounted. In FIG. 8, the mobile phone terminal 1300 includes a liquid crystal display device (liquid crystal panel) 100, operation keys 1302, an audio output unit 1304, and an audio input unit 1306.

  As described above, in the liquid crystal display device 100 of the present invention, display characteristics are improved by hierarchizing data lines, and high-quality display is possible. Therefore, the display performance of the electronic device (that is, the mobile phone terminal) 1300 on which the liquid crystal display device 100 is mounted is also improved. The present invention is also applicable to other electronic devices. For example, the present invention can also be applied to a reflective projector and an illumination device that use a reflective liquid crystal on silicon (LCOS) panel.

  As described above, according to some embodiments of the present invention, for example, the influence of fluctuations in the data line potential caused by writing to the selected pixel on the non-selected pixel is minimized, and the display characteristics of the non-selected pixel are significantly improved. It becomes possible to make it.

  The present invention has been described above with reference to the embodiments. However, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the present invention. The present invention can be applied to various electro-optical devices (liquid crystal display devices and organic EL display devices) and various electronic devices.

1A to 1C are diagrams for explaining a configuration of a main part of a liquid crystal display device having a hierarchical data line structure and a voltage applied to a sub data line. 2A and 2B are diagrams for explaining an example in which a non-selected sub data line voltage is used as a voltage for absorbing carriers generated by irradiation with alpha rays (light). The figure for demonstrating an example of the whole structure of a liquid crystal display device FIG. 3 is a timing chart for explaining an example of the operation of the liquid crystal display device of FIG. The circuit diagram which shows the other example of a structure of the principal part of the liquid crystal display device which has a hierarchical data line structure FIGS. 6A and 6B are circuit diagrams showing examples of circuits for generating the first and second unselected sub data line voltages. FIG. 6 is a timing chart for explaining an example of the operation of the liquid crystal display device of FIG. The perspective view which shows the external appearance of an example (cellular phone terminal) of the electronic device carrying the liquid crystal display device of this invention FIG. 9A to FIG. 9D are diagrams for explaining a new problem that was clarified before the present invention.

Explanation of symbols

M1 pixel transistor, LC liquid crystal element, Cst storage capacitor,
GL0 to GLm scanning line, MDLn main data line, SDLn sub data line,
VDn write voltage (image signal), VR non-selected sub data line voltage,
NE1 VR supply node, L10 VR supply line, L20, L30 VCOM supply line VCOM Reference voltage applied to one end of the holding capacitor,
LCOM Reference voltage applied to one end of liquid crystal element

Claims (10)

n main data lines (n is an integer of 1 or more);
M sub-data lines (m is an integer of 1 or more) provided corresponding to the k-th main data line (1 ≦ k ≦ n) of the n main data lines;
Electrical connection / disconnection between the k-th main data line and each of the m sub-data lines provided between the k-th main data line and each of the m-th sub-data lines. M first switches for switching between,
I pixel circuits (i is an integer of 1 or more) connected to each of the m sub-data lines;
An electro-optical device comprising: The electro-optical device according to claim 1,
M second switches for switching supply / non-supply of the unselected sub data line voltage to each of the m sub data lines,
Each of the m first switches is turned on when a corresponding sub-data line of the m sub-data lines is in a selected state, turned off when in a non-selected state, and
Each of the m second switches is turned off when a corresponding sub-data line among the m sub-data lines is in a selected state, and turned on when the sub-data line is in a non-selected state. Optical device. The electro-optical device according to claim 2,
The electro-optical device, wherein the non-selected sub data line voltage is a midpoint voltage between a maximum voltage and a minimum voltage of an image signal transmitted via the kth main data line. The electro-optical device according to claim 2,
The potential polarity of the image signal is periodically switched based on a predetermined potential,
The unselected sub data line voltage is:
When the image signal is positive, it is a midpoint voltage between the maximum voltage and the minimum voltage of the positive image signal transmitted via the kth main data line,
When the image signal has a negative polarity, it is a midpoint voltage between the maximum voltage and the minimum voltage of the negative image signal transmitted through the kth main data line. Electro-optic device. The electro-optical device according to claim 2,
The potential polarity of the image signal is periodically switched based on a predetermined potential,
The unselected sub data line voltage is:
The maximum voltage transmitted via the kth main data line when the image signal is positive, and the maximum voltage transmitted via the kth main data line when the image signal is negative. An electro-optical device characterized in that the voltage is a midpoint voltage with respect to the minimum voltage to be generated. The electro-optical device according to claim 2,
Each of the i pixel circuits is
A pixel electrode;
A transfer switch provided between each of the m sub-data lines and the pixel electrode;
The unselected sub data line voltage is:
When the transfer switch is composed of an NMOS transistor, it is set to a voltage equal to or higher than the maximum voltage transmitted via the kth main data line,
When the transfer switch is composed of a PMOS transistor, the electro-optical device is set to a voltage equal to or lower than a minimum voltage transmitted via the kth main data line. The electro-optical device according to claim 1,
M second switches for switching supply / non-supply of the first unselected sub data line voltage to each of the m sub data lines;
M number of third switches for switching supply / non-supply of the second unselected sub-data line voltage to each of the m sub-data lines,
Each of the m first switches is turned on when a corresponding sub-data line among the m sub-data lines is selected, and is turned off when the sub-data line is not selected.
Each of the m second switches and the third switch is turned off when a corresponding sub-data line among the m sub-data lines is in a selected state,
When the corresponding sub-data line among the m sub-data lines is in a non-selected state, first, the third switch is turned on and the corresponding sub-data line among the m sub-data lines is firstly turned on. To supply the second unselected sub-data line voltage,
Next, the third switch is turned off and the second switch is turned on to supply the first unselected sub-data line voltage to the corresponding sub-data line among the m sub-data lines. An electro-optical device. The electro-optical device according to claim 1,
The electro-optical device, wherein the first switch is a mechanical switch. n (m is an integer equal to or greater than 1) main data lines and m (m ≦ m) provided corresponding to the kth main data line (1 ≦ k ≦ n) of the n main data lines. Is an integer greater than or equal to 1) and between the kth main data line and the m subdata lines, the kth main data line and the m subdata lines. M first switches for switching electrical connection / disconnection with each of the lines, and i pixels (i is an integer of 1 or more) connected to each of the one sub data line A driving method of an electro-optical device, including a circuit and m second switches for switching supply / non-supply of a non-selected sub data line voltage to each of the m sub data lines,
When the x-th (1 ≦ x ≦ m) sub-data line of the m sub-data lines is selected, it corresponds to the x-th sub-data line of the m first switches. The i-th switch connected to the x-th sub data line is turned on via the k-th main data line and the x-th sub data line. Supplying to at least one of the pixel circuits,
When the x-th (1 ≦ x ≦ m) sub-data line of the m sub-data lines is not selected, the x-th sub-data line of the m first switches The corresponding x-th first switch is turned off, whereby the k-th main data line and the x-th sub data line are electrically separated, and the x-th sub-data line is separated. A driving method for an electro-optical device, wherein the corresponding x-th second switch is turned on to supply the unselected sub-data line voltage to the x-th sub-data line.   An electronic apparatus equipped with the electro-optical device according to claim 1.

Images