JP2000231367A - Active matrix circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current by providing first, second switching elements adjacent to each other and connected to the same data signal line, controlling the first switching element with first, second selection signal lines and controlling the second switching element with second, third selection signal lines. SOLUTION: The first switching element is controlled by the first selection signal line Xn and the second selection signal line Xn+1 adjacent to the first selection signal line Xn. The second switching element adjacent to the first switching element and connected to the same data signal line Ym as the first switching element is controlled by the second selection signal line Xn+1 and the third selection signal line Xn+2 adjacent to the second selection signal line Xn+1. The first, second switching elements consist of plural thin film transistors Tr1, Tr2, and the thin film transistors Tr1, Tr2 are reverse stagger type transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an active matrix circuit. The active matrix circuit of the present invention is used for a liquid crystal display or the like.

[0002]

2. Description of the Related Art FIG. 6A is a schematic view of a conventional example of an active matrix display device. A region surrounded by a broken line in the figure is a display region, in which a single transistor (Tr) is arranged in a matrix as a switching element. Paying attention to the n-th row and the m-th column in this matrix, the wiring connected to the source of the transistor is an image (data) signal line (Y _m ), and the wiring connected to the gate electrode of the transistor is This is a gate (selection) signal line ( _Xn ).

Attention is paid here to a switching element, and the transistor switches data to drive a liquid crystal cell (LC). The auxiliary capacity (C) is
A capacitor for reinforcing the capacity of a liquid crystal cell, which is used for holding image data. The transistor is used to switch image data of a voltage applied to the liquid crystal. The biggest problem when using a transistor as a switching element is a leakage current (leakage current or OFF current) in a state where a selection pulse is not applied to a gate (non-selection state). If the leakage current is large, the charge stored in the pixel electrode and the auxiliary capacitance easily decreases, and the display characteristics deteriorate.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. In a switching element having a plurality of transistors connected in series, one end is connected to a data signal line and the other end is connected to a pixel electrode. , And control of each transistor is performed by gate signal lines independent of each other. By connecting transistors in series,
Leakage current is reduced.

[0005]

A first aspect of the present invention is that there are first and second switching elements adjacent to each other and connected to the same data signal line, and the first to third switching elements are provided.
In the case where there are three consecutive gate signal lines, the first switching element is controlled by the first and second selection signal lines, and the second switching element is
It is controlled by the second and third selection signal lines.

A second aspect of the present invention is that there are first and second switching elements adjacent to each other and connected to the same data signal line, and four first to fourth continuous gate signal lines. In some cases, the first switching element is controlled by first and second selection signal lines, and the second switching element is controlled by third and fourth selection signal lines, Signal line and third
Are applied with the same signal to the selection signal line.

[0007]

FIG. 1A is a circuit diagram showing a first concept of the present invention, and FIG. 1B is a circuit diagram showing a second concept of the present invention.
Circuit diagrams each illustrating the concept of the above. In the figure, a region surrounded by a dotted line indicates a unit pixel. That is, FIG.
In each of (A) and (B), the switching element is composed of two transistors (Tr1 and Tr2). Tr1 and Tr2 are controlled by different gate signal lines. In FIG. 1 (B), 2 pieces of gate signal lines per row (X _n and Z _n) is provided. However, as shown in FIG, gate signal line X _{n + 1} of Z _n and down one line is connected with the outside of the matrix, i.e., the same signal is applied.

In the first and second embodiments of the present invention, it is possible to provide an auxiliary capacitance (C) as shown in FIG.
However, in the conventional case, it is possible to form a capacitor between the adjacent gate signal line (X _{n + 1} ) as shown in FIG. 7, but this is not preferable in the present invention. Because, in the present invention, the gate signal line adjacent to the pixel electrode is a gate signal line for driving the pixel, the potential of the pixel electrode fluctuates (referred to as a through voltage drop) according to ON / OFF of the selection pulse. Because there is.

For this reason, in the present invention, it is preferable that the auxiliary capacitance is formed between another wiring. For example, a light-blocking layer may be formed using a conductive material, and may be held at a constant potential. Also,
As shown in FIG. 1C, an overlap may be provided between a portion (intermediate portion) between Tr1 and Tr2 and a gate signal line for controlling Tr2 to provide a capacitance. However, Tr1
It is not preferable to provide a capacitance between the gate signal line and the gate signal line for controlling the voltage. The reason will be described later. FIG. 1C is FIG.
The case where the present invention is applied to the circuit of FIG. 1A is applicable to the circuit of FIG.

As derived from the above discussion, in the first embodiment of the present invention, the pulse applied to the first signal line is the second pulse.
Has a temporal overlap with the pulse applied to the signal line of
Similarly, the pulse applied to the second signal line has a temporal overlap with the pulse applied to the third signal line. If the pulse applied to the first signal line does not overlap with the pulse applied to the second signal line in time, Tr1 and Tr2 cannot be turned on at the same time, so that the pixel electrode is charged. Can not do.

Similarly, in the second embodiment of the present invention, the pulse applied to the first signal line has a temporal overlap with the pulse applied to the second signal line, and is applied to the third signal line. The applied pulse (same as that applied to the second signal line) has a temporal overlap with the pulse applied to the fourth signal line.

FIG. 2 shows this state. In FIG.
_n represents the voltage state of the gate signal line X _n of FIG. 1 (A),
D _m represents a voltage state of the data signal line Y _m. As can be seen from Fig., V _n and _{V n + 1, V n +} 1 and V _{n + 2} of the pulses overlap each other. Then, D _m when overlapping (e.g., pixel Z _n, the _m D (Z _{n, m)} is the pixel Z _{n + 1,} the _m D (Z
_{n + 1, m} ) is written to the corresponding pixel electrode. The V n _{+ 2} and D _m, for comparison, are also shown a V _n by a dotted line.

FIG. 2A shows a case where the selection pulse is applied sequentially from the top, and FIG. 2B shows a case where the selection pulse is applied sequentially from the bottom. FIG. 2 (B)
In the case of the data signal D _m may be as shown in FIG. 2 (C). In the above description, expressions such as from top to bottom and from bottom to bottom are more general expressions. The former is that “the transistor (Tr1) connected to the data signal line is selected first. A pulse is applied (that is, Tr1 is turned on first and then turned off) ”, and the latter is a“ transistor (T
R2) is first applied with a selection pulse (ie, Tr2
Are turned on first and turned off).

As shown in FIG. 1C, when a capacitance is formed between a specific gate signal line and a specific gate signal line, a selection pulse is applied in order from the bottom (for a more general expression, see above. Note that the capacitance does not function as an auxiliary capacitance.

For example, consider the case of FIG. Focusing on the pixel Z _{n, m} , the data D (Z _{n, m} ) to be written to the pixel is, of course, in a state where Tr1 and Tr2 are simultaneously ON. Then, Tr
2 is OFF and only Tr1 remains ON, but at that time, the data changes to the next one. Of course, Tr
Since 2 is OFF, the potential of the pixel capacitor LC does not change. However, the following data is written to the auxiliary capacitance C. Therefore, the capacitance C does not become an auxiliary capacitance of the pixel capacitance LC. The same applies to the case of FIG.

In the present invention, it is impossible to continue sending the data of the pixel over the entire period in which Tr1 is in the ON state. This is because Tr1 is also involved in controlling the signal of the pixel above it.

From the above discussion, it is possible to explain the reason why it is not preferable to first form a capacitance between the gate signal line (X _n ) for controlling Tr1. In such a circuit arrangement, in order to avoid a change in the potential of the pixel electrode due to the coupling of the capacitor C and the gate signal line, Tr2 is turned off first (that is, a selection pulse is applied in order from the bottom).
is necessary. However, in this case, Tr1 is still ON after Tr2 is turned OFF, and a signal not for the pixel is written in the capacitor C. Therefore, the capacitance C is not suitable as an auxiliary capacitance. Also, Tr1 is OF
When the potential becomes F, the potential of the capacitor C drops as much as the potential of the gate signal line. In this sense, such a capacitor is not preferable.

When the selection pulse is applied in order from the top, Tr1 is turned off first, and the potential of the capacitor C at that time is the same as the potential of the pixel capacitor LC.
Even if 2 is turned off, there is no current exchange with the data signal line, so that no problem occurs.

[0019]

[Embodiment 1] This embodiment will be described with reference to FIGS. FIG. 3 shows a state in which the active matrix circuit of the present embodiment is viewed from above in the order of manufacturing steps. FIG.
FIG. 3 conceptually shows a cross section of a manufacturing process of elements, wirings, and the like constituting the circuit of this embodiment. FIG. 5 shows a circuit diagram of the active matrix circuit of this embodiment. The cross-sectional view of FIG. 4 does not correspond to the cross-section of a specific portion of FIG. 3 and is a conceptual drawing merely showing a manufacturing process of elements and wirings used in the present embodiment.

An island-shaped crystalline semiconductor film 11 is formed on a substrate 10 having an insulating surface by a known method. Further, a gate insulating film 12 is formed so as to cover it. Then, a gate signal line 13 is formed. (FIG. 3A and FIG. 4A) Then, using the gate signal line 13 as a mask, an N-type or P-type impurity is introduced into the semiconductor film 11 in a self-aligned manner to form a source 14 and a drain 15. . Further, a first interlayer insulator 16 is deposited so as to cover the gate signal line 13. (FIG. 4 (B))

Next, a contact hole leading to the source 14 is formed, and a data signal line 17 is formed. Further, a second interlayer insulator 18 is deposited to cover the data signal lines.
(FIGS. 3B and 4C) Next, a metallic light-shielding layer 19 is formed in a region to be shielded from light. (FIG. 3D) Further, a third interlayer insulator 20 is deposited so as to cover the light shielding layer 19. Then, the first to third interlayer insulators 16, 1
8 and 20 are etched to form a contact hole reaching the drain 15.

Further, a pixel electrode 21 is formed by a transparent conductive film. At this time, the pixel electrode 21 is formed so as to overlap with the light shielding layer 19, and the capacitance 22 is formed by the light shielding layer 19 and the pixel electrode 21. (FIG. 4D) Thus, a circuit as shown in FIG. 5 can be obtained.
In this embodiment, the light shielding layer 19 is used as an auxiliary capacitance of the pixel capacitance.
(In use, the capacitor 22 is maintained at a constant potential.) A capacitor 22 obtained by the pixel electrode 21 is used. (Fig. 5)

In this embodiment, as can be seen from FIG.
The length of the semiconductor film 11 is substantially determined by the distance between the gate signal lines. If the distance between the gate signal lines is large, the semiconductor film 11 is inevitably elongated, and the resistance of the circuit increases.
Therefore, it is suitable for a circuit in which the distance between the gate signal lines is narrow, that is, a circuit in which the shape of the pixel is long in the direction along the gate signal line. Conversely, if the shape of the pixel is long in the direction along the data signal line, the distance between the gate signal lines is large,
This embodiment is not appropriate.

Generally, the shape of a pixel is determined by the shape of the entire screen. What has the effect in this embodiment is
When the aspect ratio of a screen such as EDTV, HDTV or the like (width / height ratio, that is, the length of the side in the direction of the gate signal line: the length of the side in the direction of the data signal line) is a: b, >
b. Specifically, the aspect ratio is 3:
Suitable for two or more, for example, 16: 9, monochromatic (for example, a panel used for a projection type display device).

Embodiment 2 This embodiment will be described with reference to the circuit diagram shown in FIG. In this embodiment, the manufacturing steps are substantially the same as those shown in Embodiment 1, and the same reference numerals are used. However, in the circuit layout, FIG.
As shown in (1), a capacitor 22 is formed between the first transistor and the second transistor. Moreover, instead of forming a capacitance between the gate signal line as shown in FIG. 1C, a capacitance is formed between the gate signal line and the conductive film 19 for the black matrix as in the first embodiment. The capacitor thus provided can be used similarly to the auxiliary capacitor C in FIG. (FIG. 8A)

FIG. 14 shows an example of arrangement of actual wirings and the like of the circuit as described above. 14 are the same as those in the first embodiment. As shown in the figure, a semiconductor film 11 is formed widely, and a capacitor using an interlayer insulator as a dielectric is formed between the semiconductor film 11 and a conductive film (not shown) formed thereon. (FIG. 14)

Embodiment 3 This embodiment will be described with reference to a circuit diagram shown in FIG. In this embodiment, a gate signal line for controlling a first transistor (a transistor connected to a data signal line) and a gate signal line for controlling a second transistor (a transistor connected to a pixel electrode) are separated. That is, in FIG. 9A, X _2n , X
_{2n + 2} , X _{2n + 4} , _.... are the former, and X _{2n + 1} , X _{2n + 3} ,
_.... is the latter. Similarly, in FIG. 9B, X
_{2n + 1} , _{X2n + 3} , _{... Are the} former, and _X2n , _{X2n + 2} , X
_{2n + 4} , _.... is the latter. For example, in the circuit shown in FIG. 1, all gate signal lines control both the first transistor and the second transistor.

In such a circuit, the signals applied to the gate signal lines are different from those shown in FIG. 2 and control the first transistor as shown on the right side of the circuit diagram of FIG. 9B. The pulse waveform applied to the gate signal line to be applied is different from that applied to the gate signal line for controlling the second transistor. When the driving signal shown in FIG. 9B is used, in each pixel, the second transistor is turned off first.
After that, the first transistor can be turned off. The reverse operation (after turning off the first transistor,
In the case where the second transistor is turned off), part of the electric charge stored in the second transistor in the ON state moves to the pixel electrode, causing a potential change of the pixel electrode.

[Embodiment 4] This embodiment will be described with reference to FIG. This embodiment shows an actual arrangement of an active matrix circuit having the circuit diagram of FIG. The circuit manufacturing method of the present embodiment is the same as that of the first embodiment, and the reference numerals in FIG. 10A are the same as those of the first embodiment. FIG. 10A shows an arrangement of the wiring of the unit pixel, and shows a state corresponding to a step corresponding to FIG. In the present embodiment, unlike the first embodiment, the number of gate signal lines is 2 per row.
This is necessary, and the aperture ratio is reduced. . However, since the length of the semiconductor film 11 is not limited by the interval between the gate signal lines, a <b when a: b is the aspect ratio determined to be inappropriate in the first embodiment. There is no problem even if there is.

The circuit of the present embodiment (that is, the circuit shown in FIG. 1B) and the circuit of the first embodiment (that is, the circuit shown in FIG.
(A) is described with reference to FIG. FIG. 15 shows only a gate signal line and a data signal line for simplification, and does not show a semiconductor film or the like.

First, as shown in FIGS. 15A and 15B, consider a case where a pixel is horizontally long (aspect ratio 3: 1). In the case of employing this embodiment (FIG. 15A), the ratio of the wiring (gate signal line and data signal line) to the unit pixel (indicated by a dotted rectangle in the figure) is the case of Embodiment 1 (FIG. 1
5 (B)). Therefore, it is not preferable to apply this embodiment to horizontally long pixels. (FIG. 15
(A), same figure (B))

Next, the pixels are vertically long (aspect ratio 1: 3).
Consider things. When this embodiment is adopted (FIG. 1)
5 (C)), the ratio of the wiring (gate signal line and data signal line) to the unit pixel (indicated by a dotted square in the figure) is
This is not much different from the case of the first embodiment (FIG. 15D). Conversely, in the case of the first embodiment, although not shown in the figure, the resistance of the semiconductor film becomes a problem because the semiconductor film becomes long. In addition, the ratio of the semiconductor film to the unit pixel is large. Therefore, it is not preferable to apply this embodiment to horizontally long pixels. (FIG. 15 (C), FIG. 15 (D))

The above-described vertically long pixel has three pixels per unit pixel even in a normal display panel having an aspect ratio of 4: 3.
Used in a color panel having three pixels corresponding to the primary colors. That is, in such a panel, the unit picture element is substantially square, but the unit picture element is divided into three in the row direction, so that the unit pixel has an aspect ratio of 1: 3.
It will be vertically long.

Embodiment 5 This embodiment will be described with reference to FIGS. 10B and 10C. In the present embodiment, FIG.
This is a further development of the active matrix circuit having the circuit diagram of FIG. The circuit manufacturing method of the present embodiment is the same as that of the first embodiment, and the reference numerals in FIG. 10B are the same as those of the first embodiment. FIG. 10B shows an arrangement of the wiring of the unit pixel, and shows a state in a process corresponding to FIG. FIG. 10C is a circuit diagram of a unit pixel. The auxiliary capacitance is formed using a conductive black matrix film and a part of the pixel electrode as in the first embodiment.

In the present embodiment, the so-called multi-gate type transistor in which the gate signal line X _{n + 1} traverses the semiconductor film at least twice or more is used for the second switching element, so that the second switching element is further improved. Can be reduced. FIG. 10B shows FIG.
Although a multi-gate transistor is applied to the circuit shown in FIG. 1A, it is obvious that the same can be applied to the circuit (circuit arrangement) shown in FIG. 1B (or FIG. 10A). is there.

Embodiment 6 FIGS. 11 and 12 show this embodiment. The active matrix circuit of the present embodiment is shown in FIG.
FIG. 3C shows an actual arrangement of the circuit diagram shown in FIG. FIG. 11 shows a state in which the active matrix circuit of this embodiment is viewed from above in the order of the manufacturing process. FIG. 12 conceptually shows a cross section of a manufacturing process of elements, wirings, and the like constituting the circuit of this embodiment. The cross-sectional view of FIG. 12 does not correspond to the cross-section of a specific portion of FIG. 11 and is a conceptual drawing merely showing a manufacturing process of elements and wirings used in the present embodiment.

A gate signal line 13 and a gate insulating film 12 are formed over the substrate 10 having an insulating surface. Further, an island-shaped amorphous semiconductor film 11 is formed by a known method. (FIGS. 11A and 12A) Then, N-type or P-type semiconductor films 14 (source) and 15 (drain) are formed by a known semiconductor film formation method. Here, in the portion where the switching element is formed (the left side in FIG. 12), the semiconductor films 14 and 15 are formed so as to be separated by the gate signal line. Conversely, in the portion where the auxiliary capacitance 22 is formed (the right side in FIG. 12), it is formed so as to cross the gate signal line. (FIG. 11
(B) and FIG. 12 (B))

Next, by a known metal wiring forming technique,
The data signal line 17 is formed. Thus, the main part of the circuit is formed. Thereafter, a pixel electrode and a protective film are formed to complete the process. (FIG. 11 (C) and FIG. 12 (C)) In this embodiment, since the storage capacitor 22 is constituted by the gate signal line 13 and the semiconductor film 15, a plurality of interlayer insulators as in the first embodiment are formed. It has the feature that it is not necessary.

Embodiment 7 FIGS. 8B and 13 show this embodiment. The manufacturing process of the active matrix circuit of this embodiment is substantially the same as that of the sixth embodiment, and the same reference numerals are used. This embodiment relates to an example in which an auxiliary capacitor is provided between the gate signal line shown in FIG. 1C and the circuit shown in FIG. 1B as shown in the circuit diagram of FIG. Things. The actual arrangement is shown in FIG. That is, a part of the semiconductor film 11 overlaps with the gate signal line 13 (Z _n ) to form the auxiliary capacitance 22.

[0040]

As described above, the voltage drop of the liquid crystal cell can be suppressed by connecting a plurality of thin film transistors and an appropriate capacitor. The present invention is effective in applications that require higher-level image display. That is, when expressing very delicate shades of 256 gradations or more, the discharge of the liquid crystal cell is 1% during one frame.
It is necessary to keep it below. The conventional scheme (FIG. 6) was not suitable for this purpose.

The present invention is also suitable for an active matrix display device using a crystalline silicon semiconductor thin film transistor particularly suitable for displaying a matrix having a large number of rows. Generally, in a matrix having a large number of rows, an amorphous silicon semiconductor thin film transistor is not suitable for use because the selection time per row is short. However, there is a problem that a thin film transistor using a crystalline silicon semiconductor has a large OFF current. Therefore, the present invention that can reduce the OFF current can make a great contribution in this field.

Although the details of the manufacturing process have not been described in the embodiments, the present invention relates to the arrangement and design of circuits, and therefore, when various known methods for forming elements and wirings are applied to the present invention. It is clear that there is no contradiction. For example, a transistor having a so-called low-concentration drain (LDD) may have a transistor having an offset gate structure (for example, see Japanese Unexamined Patent Publication No.
114724 and 5-267667), there is no problem in practicing the present invention.

[Brief description of the drawings]

FIG. 1 shows an active matrix circuit diagram according to the present invention.

FIG. 2 shows an example of driving an active matrix circuit according to the present invention.

FIG. 3 shows a manufacturing process of the active matrix circuit element of the embodiment.

FIG. 4 shows a concept of a manufacturing process of the circuit element of the embodiment.
(Cross section)

FIG. 5 is a circuit diagram of an active matrix circuit according to an embodiment.

FIG. 6 shows a circuit diagram of a conventional active matrix circuit.

FIG. 7 shows a circuit diagram of a conventional active matrix circuit.

FIG. 8 is a circuit diagram of an active matrix circuit according to the embodiment.

FIG. 9 is a circuit diagram of an active matrix circuit according to an embodiment.

FIG. 10 shows an arrangement and a circuit diagram of an active matrix circuit according to an embodiment.

FIG. 11 shows a manufacturing process of the active matrix circuit element of the example.

FIG. 12 shows the concept of the manufacturing process of the circuit element of the example.
(Cross section)

FIG. 13 shows an arrangement of an active matrix circuit according to the embodiment.

FIG. 14 shows an arrangement of an active matrix circuit according to the embodiment.

FIG. 15 shows an arrangement of an active matrix circuit according to the embodiment.

[Explanation of symbols]

 10 substrate 11 semiconductor film 12 gate insulating film 13 gate signal line 14 source 15 drain 16 first interlayer insulation Object 17: Data signal line 18: Second interlayer insulator 19: Light shielding layer 20: Third interlayer insulator 21: Pixel electrode 22: Auxiliary capacitance

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04N 5/66 102 H01L 29/78 612C

Claims (5)

[Claims] A pixel electrode arranged in a matrix on a substrate; a selection signal line; a data signal line intersecting the selection signal line; and a switching element connected to the data signal line. In the active matrix circuit in which the switching element is connected to each of the pixel electrodes, the first switching element is controlled by a first selection signal line and a second selection signal line adjacent to the first selection signal line. The first switching element and the first switching element;
A second switching element connected to the same data signal line as the switching element is controlled by the second selection signal line and a third selection signal line adjacent to the second selection signal line; An active matrix circuit, wherein the first switching element and the second switching element include a plurality of thin film transistors, and the thin film transistors are inverted staggered transistors. 2. A display device using the active matrix circuit according to claim 1. 3. The display device according to claim 2, wherein the display device is a liquid crystal display device. 4. A projection type display device using the active matrix circuit according to claim 1. 5. An HDTV using the active matrix circuit according to claim 1.