JPH06324642A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate the need for a selector for DC conversion and to use a current amplifier which is fast and small in power consumption by connecting odd-numbered and even-numbered data lines selectively to an upper-side and a lower-side data driver. CONSTITUTION:When the ON/OFF states of respective switch elements SHx, SHx+1, SLx, and SLx+1 are controlled according to a specific combination, the output of the upper data driver DDH is supplied to an 'odd-numbered' data line Dx and the output of the lower data driver DDL is supplied to an 'even- numbered' data line Dx+1 in mode 1. In mode 2, on the other hand, the output of the upper data driver DDH is supplied to an 'even-numbered' data line Dx and the output of the lower data driver DDL is supplied to an 'odd- numbered' data line Dx+1. Namely, the outputs of the opposite-side data drivers are supplied to the same data line in the mode 1 and mode 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device, and more particularly to
The present invention relates to a liquid crystal display device of active matrix type and displaying multiple gradations.

[0002]

2. Description of the Related Art A liquid crystal display device, which is often used for a display device such as a portable personal computer, is a CRT (Cathode Radar).
y Tube) type display device has much lower power,
In order to realize battery operation for a long period of time, further power control technology is required. FIG. 4 is a block diagram of a conventional liquid crystal display device. Reference numeral 1 denotes a liquid crystal panel, and the liquid crystal panel 1 has a large number of data lines D _{1 to} D _n laid in the vertical direction of the screen [n is the total number of dots forming one scanning line; for example, a display density is 640 × 400. In case of dots, n = 640 × 3
(3 is each of R, G, and B dots)], and a large number of gate lines G _{1 to} G _m laid in the horizontal direction of the screen [m is the number of scanning lines forming one screen; for example, display density Is 640 x 40
Liquid crystal cell P _{(i , j)} (where i is the gate line number; 1 to
m and j are configured by connecting data line numbers; 1 to n). The data lines D _{1 to} D _n have odd groups D ₁ , D ₃ , D ₅ , ... And even groups D ₂ , D ₄ , D.
_6, is divided into ..., data lines of odd group on the upper side of the data driver 2H, also, the data lines of the even group is connected to the data driver 2L lower.

The gate lines G _{1 to} G _m are provided for each liquid crystal cell P _{(i, j)} and TFTs (thin not shown ₎ are provided.
TFT connected to the gate of the film transistor)
Is connected to the gate driver 4 via the gate lines G _{1 to} G _m.
In response to a predetermined ON voltage applied from sequentially turned on, the data line D ₁ to D _n and the liquid crystal cell P _{(i, j)} between and connected to the horizontal scanning line units above and below the data driver Write the display voltage from 2H, 2L.

The liquid crystal cell P _{(i, j)} displays a gray scale according to the potential difference between the display voltage and the common voltage (voltage applied to the counter electrode), but in general, the influence of parasitic capacitance derived from the TFT is displayed. In order to reduce the number of pixels or to suppress flicker, display voltages having different polarities are written to liquid crystal cells that are adjacent in the lateral direction. That is, 4 is a power supply unit that generates a plurality of reference voltages for multi-gradation display (for example, 5 kinds of voltages in 16-gradation display), and 5 is a selector that alternately switches the polarities of the reference voltages for each frame. The reference voltage VH having one polarity is applied to the upper data driver 2H through the current amplifier 6H, and the reference voltage VL having the other polarity is supplied to the current amplifier 6H.
It is given to the lower data driver 2L through L.

Here, an arbitrary frame (for example, F0 in FIG. 5)
1), the polarity of one reference voltage VH (however, with respect to the common voltage COM) is positive, and the polarity of the other reference voltage VL is negative, the positive display voltage from the upper data driver 2H. (Refer to symbol A in FIG. 5)
In addition, the lower data driver 2L outputs a negative display voltage (see symbol B in FIG. 5).

That is, the upper data driver 2H is connected to the odd-numbered groups of data lines D ₁ , D ₄ , D ₆ , ... And the lower data driver 2L is connected to the even-numbered group of data lines D _2. , D ₅ , D ₆ , ... Are connected, the display voltages of different polarities are written between adjacent cells to n liquid crystal cells forming one horizontal scanning line.

[0007]

However, in such a conventional liquid crystal display device, the polarities of the reference voltages VH and VL given to the upper data driver 2H and the lower data driver 2L are set for each frame. Since the configuration is such that the polarity is switched, the selector 5 for switching the polarity is required, the power consumption of the current amplifiers 6H and 6L is large in order to amplify the AC-converted reference voltage, and the rising and falling of the reference voltage is sharp. In order to do so, there is a problem that high-speed current amplifiers 6H and 6L must be used. [Purpose] Therefore, an object of the present invention is to provide a liquid crystal display device that does not require a selector and can use a current amplifier that is slow and consumes less power.

[0008]

In order to achieve the above object, the present invention is configured by arranging m gate lines and n data lines in an intersecting shape and connecting a liquid crystal cell at each intersection. A liquid crystal panel, an upper data driver and a lower data driver which are separately arranged on the upper end side and the lower end side of the data line and each have at least n / 2 output terminals, Between an upper switch group capable of individually connecting and disconnecting an upper end of a data line and an output terminal of the upper data driver, and between a lower end of the n data lines and an output terminal of the lower data driver. A lower switch group that can be individually connected and disconnected, and divides the n switch elements that form the upper switch group into odd-numbered groups and even-numbered groups, and Divided n switches elements constituting the switch group to the odd-numbered group and the even-numbered group, and, is characterized in that so as to control the on / off each group.

[0009]

FIG. 1 is a partial conceptual configuration diagram for explaining the operation of the present invention. In this figure, D _x represents an odd-numbered one of n data lines, and D _{x + 1}
Represents an even-numbered data line adjacent to D _x . Further, R _x and R _{x + 1} represent equivalent resistance components of the respective data lines, and C _x and C _{x + 1} represent equivalent capacitance components.

The upper ends of D _x and D _{x + 1} (the upper ends on the screen) are connected to upper data drivers DDH via switch elements SH _x and SH _{x + 1} which form a part of the upper switch group, respectively. Further, the lower end sides of D _x and D _{x + 1} are connected to the lower data driver DDL via switch elements SL _x and SL _{x + 1} that form a part of the lower switch group, respectively.

Here, each of the above switch elements SH _x , S _x
When ON / OFF of H _{x + 1} , SL _x , and SL _{x + 1} is controlled according to the combination of the following table, (hereinafter, margin) In mode 1, the output of the upper data driver DDH is given to the “odd number” data line D _x, and the output of the lower data driver DDL is given to the “even number” data line D _{x + 1} . In mode 2, the output of the upper data driver DDH is applied to the "even" data line D _x, and the output of the lower data driver DDL is applied to the "odd" data line D _{x + 1.} . That is, in mode 1 and mode 2, an output is given to the same data line from the data driver on the opposite side.

Therefore, the polarity of the reference voltage applied to the upper data driver DDV is fixed to one polarity (eg, positive polarity), and the polarity of the reference voltage applied to the lower data driver DDL is the other polarity (eg, negative polarity). Property), even if it is fixed to the liquid crystal cell adjacent in the lateral direction,
It becomes possible to write display voltages having different polarities. As a result, it is not necessary to convert the reference power source to alternating current,
The selector (see reference numeral 5 in FIG. 4) can be eliminated, and a current amplifier with low power consumption and low speed can be used.

Further, in the mode 3, since the outputs of the data drivers on both sides are simultaneously applied to both the odd-numbered data line D _x and the even-numbered data line D _{x + 1} , the voltage on the data line is It is the average voltage of the output.
Note that the average voltage is achieved without the current supply from the data driver. Therefore, from mode 1 to mode 2
If mode 3 is temporarily executed during the transition to (or from mode 2 to mode 1), the potential on the data line temporarily reaches the average voltage from the display voltage of mode 1 (or mode 2). After that, the average voltage is used as a start potential to stepwise change to the display voltage of mode 2 (or mode 1). As a result, the data driver only needs to drive a small voltage width from the average voltage to the display voltage of mode 1 or mode 2, so that power consumption can be reduced compared to the conventional example.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 are views showing an embodiment of the liquid crystal display device according to the present invention. In this embodiment, circuit elements common to the conventional example are given the same reference numerals. In FIG. 2, 1
Reference numeral 0 is a liquid crystal panel. In the liquid crystal panel 10, the liquid crystal cell P _{(i, j)} is connected to each intersection of the _m gate lines G _{1 to} G _m and the n data lines D _{1 to} D _n , as in the conventional example. However, n switch elements (preferably TFTs) S are provided at the upper and lower ends of the n data lines D _{1 to} D _n.
H _{1 to} SH _n and SL _{1 to} SL _n are connected to each other, and these switch elements are respectively connected to the upper switch group 11
The difference is that the H and lower switch groups 11L are configured.

Here, among the switch elements SH _{1 to} SH _n constituting the upper switch group 11H, those which are adjacent to each other in the horizontal direction of the screen (for example, SH ₁ and SH ₂ , SH _n-1).
And SH _n ) are individually connected to the respective output terminals (the number of output terminals is n / 2) of the upper data driver 12H,
Further, among the switch elements SL _{1 to} SL _n forming the lower switch group 11L, those adjacent to each other in the horizontal direction of the screen (for example, SL ₁ and SL 2, SL _n-1 and SL _n ) are
Each of the output terminals of the lower data driver 12L (the number of output terminals is n / 2) is individually connected.

Further, among the switch elements SH _{1 to} SH _n constituting the upper switch group 11H, those connected to odd-numbered data lines D ₁ , D ₃ , D ₅ , ..., D _n-1 (for example, The gates of SH ₁ , SH _n-1 ) are connected to the first common line 13 and are connected to the even-numbered data lines D ₂ , D ₄ , D ₆ , ..., D _n (for example, SH ₂ , SH _n ) gates are connected to the second common line 14, and odd-numbered data lines D ₁ and D ₃ among the switch elements SL _{1 to} SL _n that configure the lower switch group 11L. The gates of those connected to D ₅ , ..., D _n-1 (for example, SL ₁ , SL _n-1 ) are connected to the second common line 14, and even-numbered data lines D ₂ , D ₄ , D _6, ......, to lead to D _n of the (e.g. SL _2, SL _n) gate To each other said first common line 1
Connected to 3.

On the first common line 13, the output of the first voltage amplifier 15, that is, the output of the first transmission gate 16 which is turned on when the signal STP is at the L level (when the signal is on, the same phase as the signal SEL). Is applied, the H level given by the first pull-up resistor 17 is applied when it is off, and when the applied level is the H level, odd-numbered switch elements (for example, the upper switch group 11H) (for example, SH
₁ , SH _n−1 ) and the even-numbered switch elements (eg, SL ₂ , SL _n ) of the lower switch group 11L are turned on. In addition, the output of the second voltage amplifier 18, that is, the output of the second transmission gate 19 which is turned on when the signal STP is at the L level, is output to the second common line 14 (inverted by the inverter gate 20 when turned on). The level of the signal SEL applied thereto is set to the H level provided by the second pull-up resistor 21 when turned off. When the provided level is the H level, the even-numbered switches of the upper switch group 11H are provided. The switch elements (for example, SH ₂ , SH _n ) and the odd-numbered switch elements (for example, SL ₁ , SL _n-1 ) of the lower switch group 11L are turned on.

Reference numeral 22 is a voltage source for generating a reference voltage. From this voltage source 22, two types of voltages VH 'and VL' fixed to different polarities (that is, converted into direct current) are used.
Are taken out and supplied to the upper data driver 12H and the lower data driver 12L via the current amplifiers 23H and 23L, respectively. In such a configuration, now, the first output terminal of the upper data driver 12H; is (the output terminal corresponding to one dot th scanning line conveniently indicated at d ₁₎ VH 'considerable potential, also , The first output terminal of the lower data driver 12L (scan line 2
Consider a case where a potential corresponding to VL 'appears at the output terminal corresponding to the dot eye; indicated by reference numeral d ₂ for convenience).

In the operation waveform diagram of FIG. 3, the signal STP
In the H level period c ′, the first common line 13 and the second common line 13
Both lines 14 are pulled up to H level,
All switches of H group 11H and lower switch group 11L
Element SH₁~ SH_n, SL₁~ SL_nAre all on
Becomes Therefore, in this period c ′, the data line
D ₁, D₂And gate line G₁LCD located at the intersection of
Cell P_(1,1), P_(1,2)And d₁Voltage (= VH ')
d₂Voltage (= VL ') average voltage V_AV(V_AV= (V
H '+ VL') / 2) is written.

Next, in the L level period D of the signal STP,
The first and second transmission gates 16 and 19 are turned on,
The common line 13 of 1 has the same logic level (H
Level), and the second common line 14 has a signal SEL
The opposite logic level (L level) is given. Obey
During this period d, the even number of the upper switch group 11H
Eye switch element (eg SH₁, SH_n-1) And the bottom
Switch group 11L of even-numbered switch elements (for example,
SL₂, SL_n) Only turns on, resulting in an even
Data line D₁And gate line G₁Located at the intersection of
Liquid crystal cell P_{(1 , 1)}To d₁Voltage (= VH ') is written
And the odd-numbered data line D ₂And Gatra
In G₁Liquid crystal cell P located at the intersection of_(1,2)To d₂of
The voltage (= VL ') is written.

That is, while the signal STP changes from the H level to the L level, the write voltage of the even-numbered liquid crystal cells P _(1,1) temporarily reaches the average voltage V _AV and then V
The liquid crystal cell P rises and changes to H ′ while the even-numbered liquid crystal cells P
_After the write voltage of _{(1, 2)} temporarily reaches the average voltage V _AV , the write voltage starts to decrease to VL ′. Therefore, according to the above embodiment, the upper data driver 12
Even if the polarities of the reference voltages VH 'and VL' supplied to H and the lower data driver 12L are fixed, in other words, converted to DC, the display voltages having different polarities with respect to the liquid crystal cells adjacent in the horizontal direction. Can be written on the TFT
Since it is possible to sufficiently satisfy the design requirements of reducing the influence of parasitic capacitance derived from the above and suppressing flicker, a selector for AC conversion (see reference numeral 5 in FIG. 4).
Can be eliminated, and the low-power and low-speed current amplifiers 23H and 23L can be used.

When all the switch elements of the upper switch group 11H and the lower switch group 11L are turned on at the same time _, the write voltage of the selected liquid crystal cell P _{(i, j)} is temporarily average voltage V _AV. However, since the average voltage V _AV is achieved without receiving the current supply from the upper and lower data drivers 12H and 12L, the power consumption of the upper and lower data drivers 12H and 12L is suppressed. Therefore, it is possible to contribute to power consumption reduction of the entire liquid crystal display device.

[0023]

According to the present invention, the odd-numbered data lines and the even-numbered data lines can be selectively connected to the upper data driver and the lower data driver, respectively. It is possible to change the polarities of the write voltages of the liquid crystal cells adjacent to each other in the horizontal direction of the screen while the polarity of the reference voltage supplied to the LCD is fixed (that is, DC).

Therefore, it is possible to eliminate the need for a selector for converting to direct current, and to use a current amplifier which operates at low speed and consumes less power.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of an embodiment.

FIG. 2 is an overall configuration diagram of an embodiment.

FIG. 3 is an operation waveform diagram of one embodiment.

FIG. 4 is an overall configuration diagram of a conventional example.

FIG. 5 is an operation waveform diagram of a conventional example.

[Explanation of symbols]

D _{1 to} D _n : Data line G _{1 to} G _m : Gate line P _{(i, j)} : Liquid crystal cell SH _{1 to} SH _n , SL _{1 to} SL _n : Switch element 10: Liquid crystal panel 11H: Upper switch group 11L : Lower switch group 12H: Upper data driver 12L: Lower data driver

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Sekido 1015 Odanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Co., Ltd.

Claims (1)

[Claims] 1. A liquid crystal panel in which m gate lines and n data lines are arranged in a cross shape and a liquid crystal cell is connected to each intersection, and the liquid crystal panel is divided into an upper end side and a lower end side of the data lines. Between the upper data driver and the lower data driver each having at least n / 2 output terminals, and the upper ends of the n data lines and the output terminals of the upper data driver. An upper switch group that can be individually connected and disconnected, and a lower switch group that can be individually connected and disconnected between the lower ends of the n data lines and the output terminals of the lower data driver. , The n switch elements forming the upper switch group are divided into odd-numbered groups and even-numbered groups, and the n switch elements forming the lower switch group are odd-numbered groups. Groups and divided into even-numbered group, and a liquid crystal display device which is characterized in that so as to control the on / off each group.