JP5130835B2 - Differential amplifier circuit and current control device using the same - Google Patents

Differential amplifier circuit and current control device using the same Download PDF

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JP5130835B2
JP5130835B2 JP2007234037A JP2007234037A JP5130835B2 JP 5130835 B2 JP5130835 B2 JP 5130835B2 JP 2007234037 A JP2007234037 A JP 2007234037A JP 2007234037 A JP2007234037 A JP 2007234037A JP 5130835 B2 JP5130835 B2 JP 5130835B2
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考徳 小濱
崇智 大江
龍 斎藤
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Fuji Electric Co Ltd
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Description

この発明は、自動車電装機器をはじめとする半導体産業機器の分野などで用いられる差動増幅回路とそれを用いた電流制御装置および半導体集積回路装置に関する。特に、同相入力電圧が電源電圧付近以上の高い電圧となった場合でも正常に動作するpチャネルMOSFETで構成されたオペアンプを含む差動増幅回路とそれを用いた電流制御装置に関する。   The present invention relates to a differential amplifier circuit used in the field of semiconductor industrial equipment including automobile electrical equipment, a current control device using the same, and a semiconductor integrated circuit device. In particular, the present invention relates to a differential amplifier circuit including an operational amplifier composed of a p-channel MOSFET that operates normally even when the common-mode input voltage is higher than the vicinity of the power supply voltage, and a current control device using the same.

自動車の電動パワーステアリング装置やオートマチック車の速度変換装置などでは、モータやソレノイドなどのインダクタンス負荷に流れる電流を高精度に検出し、その信号をフィードバックして、電流を高精度に制御するための電流制御装置が使われている。
電流制御装置は主にPWM回路と差動増幅回路および電流検出器で構成され、電流検出器としては、電流を電圧に変換し、高精度な測定が可能で幅広い温度範囲で使用できて、安価であるシャント抵抗が自動車用途ではよく用いられている。
図5は、ソレノイド電流を制御する車載用の電流制御装置の要部回路図である。ここでは、同相入力電圧がVcc付近まで上昇する例として、車載用ECU(Electronic Control Unit)を構成する電流制御装置115を取り上げる。この電流制御装置115の回路は、前記したように、PWM回路102とpチャネルMOSFET(以下、PchMOSと称す)を用いたオペアンプを含む差動増幅回路104で主に構成される。ここでは同相入力電圧(Vcommon)は、シャント抵抗58の低電位側の電圧をいう。
図5の左側の回路は、スイッチングデバイス52、55(HSP、LSP)、ソレノイド57、シャント抵抗58(その抵抗値はRshunt)およびダイオード54で構成されるPWM(Pulse width moduration)回路102である。
In electric power steering devices for automobiles, speed converters for automatic vehicles, etc., current that flows through an inductance load such as a motor or solenoid is detected with high accuracy, and the current is fed back to control the current with high accuracy. A control device is used.
The current control device mainly consists of PWM circuit, differential amplifier circuit and current detector. As the current detector, current can be converted into voltage, high-precision measurement is possible, it can be used in a wide temperature range, and it is inexpensive. This shunt resistance is often used in automotive applications.
FIG. 5 is a main part circuit diagram of an in-vehicle current control device for controlling the solenoid current. Here, as an example in which the common-mode input voltage rises to near Vcc, a current control device 115 constituting an on-vehicle ECU (Electronic Control Unit) will be taken up. As described above, the circuit of the current control device 115 is mainly configured by the differential amplifier circuit 104 including an operational amplifier using the PWM circuit 102 and a p-channel MOSFET (hereinafter referred to as PchMOS). Here, the common-mode input voltage (Vcommon) is a voltage on the low potential side of the shunt resistor 58.
5 is a PWM (Pulse width modulation) circuit 102 including switching devices 52 and 55 (HSP, LSP), a solenoid 57, a shunt resistor 58 (whose resistance value is Rshunt), and a diode 54.

尚、シャント抵抗58は微小電流を電圧に変換できる電流検出器である。HSPはハイサイドのパワースイッチング素子(例えば、nチャネル型パワーMOSFET)、LSPはローサイドのパワースイッチング素子(例えば、nチャネル型パワーMOSFET)である。
図5の右側の回路は、シャント抵抗58を流れる電流Isにより発生した差動電圧(Vs=Is×Rshunt)を一定倍(例えば5倍)に増幅してマイコン59に入力するPchMOSを用いたオペアンプを含む従来の差動増幅回路104である。
差動増幅回路104では、例えば、R2=Rf=5R1=5Rsを満たす任意の抵抗を定めた構成とすることによりVsを5倍に増幅し出力電圧Voutとして出力点28から出力される。
図6は、PWM回路102の各部の動作波形を示し、同図(a)はLSP−INの電圧波形、同図(b)はVINN1の電圧波形、同図(c)はVINP1の電圧波形、同図(d)はIs×Rshuntの電圧波形、同図(e)はVoutの電圧波形である。横軸は時間であり任意スケールである。
HSP−INはスイッチングデバイス52のゲート電圧信号であり、LSP−INはスイッチングデバイス55のゲート電圧信号である。VINN1は第2入力点27の電圧でありシャント抵抗58の低電位側の電圧である。VINP1は第1入力点26の電圧でありシャント抵抗58の高電位側の電圧である。Is×Rshuntはシャント抵抗58の高電位側の電圧(VINP1)と低電位側の電圧(VINN1)の差の電圧(VINP1−VINN1)であり差動電圧Vsある。Voutは出力点28の電圧でありオペアンプ15の出力電圧である。
The shunt resistor 58 is a current detector that can convert a minute current into a voltage. HSP is a high-side power switching element (for example, n-channel power MOSFET), and LSP is a low-side power switching element (for example, n-channel power MOSFET).
The circuit on the right side of FIG. 5 is an operational amplifier using a PchMOS that amplifies the differential voltage (Vs = Is × Rshunt) generated by the current Is flowing through the shunt resistor 58 to a fixed value (for example, 5 times) and inputs it to the microcomputer 59. This is a conventional differential amplifier circuit 104 including:
In the differential amplifier circuit 104, for example, Vs is amplified five times by setting an arbitrary resistance satisfying R2 = Rf = 5R1 = 5Rs, and output from the output point 28 as the output voltage Vout.
6A and 6B show operation waveforms of each part of the PWM circuit 102. FIG. 6A shows a voltage waveform of LSP-IN, FIG. 6B shows a voltage waveform of VINN1, FIG. 6C shows a voltage waveform of VINP1, FIG. 4D is a voltage waveform of Is × Rshunt, and FIG. 4E is a voltage waveform of Vout. The horizontal axis is time and is an arbitrary scale.
HSP-IN is a gate voltage signal of the switching device 52, and LSP-IN is a gate voltage signal of the switching device 55. VINN1 is a voltage at the second input point 27 and is a voltage on the low potential side of the shunt resistor 58. VINP1 is a voltage at the first input point 26 and is a voltage on the high potential side of the shunt resistor 58. Is × Rshunt is a voltage (VINP1−VINN1) which is a difference between the voltage (VINP1) on the high potential side of the shunt resistor 58 and the voltage (VINN1) on the low potential side, and is a differential voltage Vs. Vout is the voltage at the output point 28 and the output voltage of the operational amplifier 15.

図6において、LSP−INの立ち下がり部においてVs=Is×Rshuntを5倍増幅したVout波形に誤動作が生じて、Vout波形が跳ね上がっている。
これは、VINN2が、LSP−INの立ち下がりと同時に4.3V付近まで引き上げられ、また、VINP2がさらに高く4.7V付近まで引き上げられたためである。つまり、オペアンプ15の−入力端子および+入力端子に入力される電圧(VINN2およびVINP2)がオペアンプの同相入力電圧範囲の上限値を超えたためである。
オペアンプの同相入力電圧範囲の上限値を超えるとオペアンプ15は異常動作するようになる。オペアンプ15が異常動作すると、オペアンプ15の出力点28には異常なVout波形が出力される。この異常なVout波形がマイコン59に入力されると、フィードバック信号が異常な状態となりPWM回路102のPWM制御回路56が正常動作できなくなる。そうすると、インダクタンス負荷であるソレノイド57に流す電流を高精度に制御できなくなる。
ここで使用しているオペアンプ15はPch入力型(入力信号の入るMOSFETがPchMOSということ)である。ソレノイド電流などを制御するのに用いられる、このオペアンプ15を含む差動増幅回路104では、オペアンプ15としては同相入力電圧の下限(0V)から精度良く出力する必要があるため、通常、Nch入力型オペアンプを使用することは出来ない。
In FIG. 6, a malfunction occurs in the Vout waveform obtained by amplifying Vs = Is × Rshunt five times at the falling portion of LSP-IN, and the Vout waveform jumps up.
This is because VINN2 was raised to near 4.3 V simultaneously with the fall of LSP-IN, and VINP2 was further raised to around 4.7 V. That is, the voltages (VINN2 and VINP2) input to the −input terminal and the + input terminal of the operational amplifier 15 exceed the upper limit value of the common-mode input voltage range of the operational amplifier.
When the upper limit value of the common-mode input voltage range of the operational amplifier is exceeded, the operational amplifier 15 operates abnormally. When the operational amplifier 15 operates abnormally, an abnormal Vout waveform is output to the output point 28 of the operational amplifier 15. When this abnormal Vout waveform is input to the microcomputer 59, the feedback signal becomes abnormal and the PWM control circuit 56 of the PWM circuit 102 cannot operate normally. If it does so, it will become impossible to control the electric current sent through the solenoid 57 which is an inductance load with high precision.
The operational amplifier 15 used here is a Pch input type (a MOSFET into which an input signal enters is a PchMOS). In the differential amplifier circuit 104 including the operational amplifier 15 used for controlling the solenoid current and the like, the operational amplifier 15 needs to output with high accuracy from the lower limit (0 V) of the common-mode input voltage. An operational amplifier cannot be used.

また、グランド電位から電源電圧まで出力することができるレール ツー レール(rail−to−rail)入力型は、入力電圧がNMOS・PMOS同時オンする期間でgm(相互コンダクタンス)歪が生じ、精度面で課題が大きい。
そのため、ソレノイド電流などを制御するのに用いられるオペアンプ15を含む差動増幅回路104ではPch入力型オペアンプを使用せざるを得ない。Pch入力型オペアンプを正常動作させるためには、PchMOSを飽和領域で動作させる必要があり、すなわち、オペアンプの入力電圧を電源電圧Vccに対してPchMOSのゲートしきい値電圧とオーバドライブ電圧の和(約1V)以下で使用しなければならない。
つまりオペアンプ15の−入力端子および+入力端子での入力電圧の限界値はVcc−1Vとなる。同相入力電圧(VINN2およびVINP2)は、第2入力点27および第1入力点26の電圧であるVINN1およびVINP1から抵抗4および抵抗3で負担する電圧分だけ低い値となる。
従って、VINN1、VINP1の同相入力電圧レベルの上限値は抵抗4および抵抗3の入力抵抗に依存することになる。また、電源電圧Vccが高くなると((Vcc−1V)/Vcc)の値が大きくなり、そのため、VINN1、VINP1の同相入力電圧レベルの値も大きくなる。そのため、VINN1、VINP1の同相入力電圧レベルの上限値はVccにも依存する。
In addition, the rail-to-rail input type that can output from ground potential to power supply voltage causes gm (mutual conductance) distortion during the period when the input voltage is turned on simultaneously with NMOS and PMOS. The challenges are big.
Therefore, a Pch input type operational amplifier must be used in the differential amplifier circuit 104 including the operational amplifier 15 used for controlling the solenoid current and the like. In order for the Pch input type operational amplifier to operate normally, it is necessary to operate the PchMOS in the saturation region, that is, the input voltage of the operational amplifier is the sum of the gate threshold voltage of the PchMOS and the overdrive voltage with respect to the power supply voltage Vcc ( About 1V) or less.
That is, the limit value of the input voltage at the − input terminal and the + input terminal of the operational amplifier 15 is Vcc−1V. The common-mode input voltages (VINN2 and VINP2) have a value that is lower than the voltage at the second input point 27 and the first input point 26 by the voltage borne by the resistor 4 and the resistor 3 from VINN1 and VINP1.
Therefore, the upper limit value of the common-mode input voltage level of VINN1 and VINP1 depends on the input resistances of the resistors 4 and 3. Further, when the power supply voltage Vcc increases, the value of ((Vcc-1V) / Vcc) increases, so that the values of the common-mode input voltage levels of VINN1 and VINP1 also increase. Therefore, the upper limit value of the common-mode input voltage level of VINN1 and VINP1 also depends on Vcc.

また、特許文献1には、モータのバッテリー陽極の電位を基準とする第1の基準電圧源と、グランド電位を基準とする第2の基準電圧源と、上アームスイッチング素子と下アームスイッチング素子の接続点とモータの間に設けられたシャント抵抗と、このシャント抵抗の電位に基づいて上記第1および第2の基準電圧源の一方からの電圧を出力する切り替え手段と、該切り替え手段の出力と上記シャント抵抗の両端の間の電位差をそれぞれ分圧して2つの電圧信号を生成する分圧手段と、該分圧手段によって生成された2つの電圧信号を入力し、上記シャント抵抗に流れる電流値と電流方向に基づいて所定の増幅率で増加または減少する電圧を出力する増幅手段とを有する電流検出回路が開示されている。
また、特許文献2には、直流電源と誘導負荷の間に設けられ、制御信号により回路を開閉するスイッチング手段と、スイッチング手段が回路を開放したとき誘導負荷に流れる電流を還流させるための還流ダイオードと、誘導負荷に流れる電流を検出する電流検出用抵抗器と、この電流検出用抵抗器の両端電圧を入力とする差動増幅気と、誘導負荷に流すべき電流に対応する基準電圧と差動増幅器の出力電圧の差を増幅し制御信号として出力する誤差増幅器と、スイッチング手段が回路を開放したといに、差動増幅器に入力される電圧の同相分電圧に対応した補償電圧を発生する補償電圧源とで構成される電流制御回路が開示されている。
Patent Document 1 discloses a first reference voltage source based on a potential of a battery anode of a motor, a second reference voltage source based on a ground potential, an upper arm switching element, and a lower arm switching element. A shunt resistor provided between the connection point and the motor, a switching means for outputting a voltage from one of the first and second reference voltage sources based on the potential of the shunt resistance, and an output of the switching means Voltage dividing means for dividing the potential difference between both ends of the shunt resistor to generate two voltage signals, and input of the two voltage signals generated by the voltage dividing means, and a current value flowing through the shunt resistor, There is disclosed a current detection circuit having amplification means for outputting a voltage that increases or decreases at a predetermined amplification rate based on a current direction.
Patent Document 2 discloses a switching means that is provided between a DC power supply and an inductive load, and that opens and closes a circuit by a control signal, and a free-wheeling diode for returning a current flowing through the inductive load when the switching means opens the circuit. A current detecting resistor for detecting the current flowing through the inductive load, a differential amplifier having the voltage across the current detecting resistor as an input, and a reference voltage and a differential corresponding to the current to be passed through the inductive load An error amplifier that amplifies the difference between the output voltages of the amplifier and outputs it as a control signal, and a compensation voltage that generates a compensation voltage corresponding to the in-phase voltage of the voltage input to the differential amplifier when the switching means opens the circuit A current control circuit comprising a source is disclosed.

尚、図5において、VINP1=Vcommon+Is・Rshunt、VINN1=Vcommonとしたとき、VINP1とVINN1の電圧レベルを差動増幅器に入力される同相入力電圧レベルと称する。
また、VINP2=(R2/R1+R2)・(Vcommon+Is・Rshunt)、VINN2=((1/(Rf+Rs))・(Vf・Vcommon+Rs・Vout)=((Rf/(Rf+Rs))・Vcommonとしたとき、VINP2とVINN2の電圧範囲をオペアンプの+入力端子、−入力端子直近に入力される同相入力範囲と称する。
特開2006−64596号公報 特許第3330022号公報
In FIG. 5, when VINP1 = Vcommon + Is · Rshunt and VINN1 = Vcommon, the voltage levels of VINP1 and VINN1 are referred to as common-mode input voltage levels input to the differential amplifier.
When VINP2 = (R2 / R1 + R2) · (Vcommon + Is · Rshunt), VINN2 = ((1 / (Rf + Rs)) · (Vf · Vcommon + Rs · Vout) = ((Rf / (Rf + Rs)) · Vcommon) And the voltage range of VINN2 is referred to as an in-phase input range that is input in the immediate vicinity of the + input terminal and the −input terminal of the operational amplifier.
JP 2006-64596 A Japanese Patent No. 3330022

図7は、従来の差動増幅回路での同相入力電圧レベルの上限値の電源電圧依存性を示す図である。c列の○印は差動電圧増幅率が5倍の場合(5倍増幅の場合)での同相入力電圧レベルの上限値である。Vcc=5V時では同相入力電圧レベルの上限値がVccを下回り4Vになり、一方、図6(b)からLSP−INの立ち下がり部でVINN2およびVINP2の電圧が4.3Vおよび4.7Vとなり、この上限値(4V)を上回るのでオペアンプ15が誤動作し、図6で示したようにVout波形が異常波形となる。
差動増幅回路における同相入力電圧レベルの上限値を上昇させる対策の一つがR2(抵抗5の抵抗値)=Rf(抵抗14の抵抗値)=2.5R1(抵抗3の抵抗値)=2.5Rs(抵抗4の抵抗値)のような抵抗比変更(b列の△印)によるものであるが、同相入力電圧レベルの上限値は上昇してVccより高くなるが、差動電圧増幅率が2.5倍に下がる。
つまり、図5の差動増幅回路104では同相入力電圧レベルの上限値を上昇させると、差動電圧増幅率が低下する。このように、従来の差動増幅回路104では同相入力レベルの上限値を上昇させると、差動電圧増幅率が低下するというトレードオフの関係にある。
前記の特許文献1では、第1、第2の基準電圧源を切り替える切り替え手段と、切り替え手段の出力とシャント抵抗の両端の電圧の間の電位差をそれぞれ分圧して2つの電圧信号を生成する分圧手段が必要であり、回路が複雑である。また、本発明と関係するシャント抵抗の高電圧側の電圧と低電位側の電圧を分圧して増幅手段に入力し、同相入力電圧レベルの上限値を上げることは記載されていない。
FIG. 7 is a diagram showing the power supply voltage dependency of the upper limit value of the common-mode input voltage level in the conventional differential amplifier circuit. The circles in column c are the upper limit values of the common-mode input voltage level when the differential voltage amplification factor is 5 times (in the case of 5 times amplification). When Vcc = 5V, the upper limit value of the common-mode input voltage level is 4V, which is lower than Vcc. On the other hand, from FIG. Since this upper limit value (4V) is exceeded, the operational amplifier 15 malfunctions, and the Vout waveform becomes an abnormal waveform as shown in FIG.
One of the measures for increasing the upper limit of the common-mode input voltage level in the differential amplifier circuit is R2 (resistance value of resistor 5) = Rf (resistance value of resistor 14) = 2.5R1 (resistance value of resistor 3) = 2. 5Rs (resistance value of resistor 4), such as a resistance ratio change (Δ mark in row b), the upper limit value of the common-mode input voltage level rises to be higher than Vcc, but the differential voltage gain is Decrease by a factor of 2.5.
That is, in the differential amplifier circuit 104 of FIG. 5, when the upper limit value of the common-mode input voltage level is increased, the differential voltage amplification factor is decreased. Thus, in the conventional differential amplifier circuit 104, there is a trade-off relationship that the differential voltage amplification factor decreases when the upper limit value of the in-phase input level is increased.
In Patent Document 1, the switching means for switching the first and second reference voltage sources, the potential difference between the output of the switching means and the voltage at both ends of the shunt resistor are respectively divided to generate two voltage signals. Pressure means are required and the circuit is complex. Further, there is no description that the voltage on the high voltage side and the voltage on the low voltage side of the shunt resistor related to the present invention are divided and input to the amplifying means to increase the upper limit value of the common-mode input voltage level.

また特許文献2では、本発明と関係するシャント抵抗の高電圧側の電圧と低電位側の電圧を分圧して差動増幅器に入力して同相入力電圧レベルの上限値を上げることは記載されていない。
この発明の目的は、前記の課題を解決して、同相入力電圧レベルの上限値を上げながら(差動増幅回路としての同相入力電圧範囲を拡大させながら)、差動電圧増幅率を大きくできる差動増幅回路とそれを用いた電流制御装置を提供することである。
Patent Document 2 describes that the voltage on the high voltage side and the voltage on the low potential side of the shunt resistor related to the present invention are divided and input to the differential amplifier to increase the upper limit value of the common-mode input voltage level. Absent.
The object of the present invention is to solve the above-mentioned problems and increase the differential voltage gain while increasing the upper limit of the common-mode input voltage level (expanding the common-mode input voltage range as a differential amplifier circuit). It is an object to provide a dynamic amplifier circuit and a current control device using the same.

前記の目的を達成するために、Pch入力型オペアンプ(入力素子としてpチャネルMOSFETを用いたオペアンプのこと)を含む差動増幅回路において、入力電圧を分圧する分圧抵抗を前記オペアンプの入力端子と接続する入力抵抗の前段に設置した構成の差動増幅回路とする。
そして、前記の差動増幅回路を用いた電流制御装置において、
電源とインダクタンス負荷との間に接続されるハイサイド側スイッチング素子と、
前記インダクタンス負荷に直列に接続されたシャント抵抗とグランドとの間に接続されるローサイド側スイッチング素子と、前記ハイサイド側スイッチング素子と前記ローサイド側スイッチング素子との間に接続されるダイオードと、を備え、前記シャント抵抗の両端にそれぞれ前記分圧抵抗を接続し、前記差動増幅回路の出力信号をフィードバック信号としてPWM制御回路へ入力し、該PWM制御回路から前記ローサイド側スイッチング素子のゲート信号を出力する構成の電流制御装置とする。
In order to achieve the above object, in a differential amplifier circuit including a Pch input type operational amplifier (an operational amplifier using a p-channel MOSFET as an input element), a voltage dividing resistor for dividing an input voltage is connected to an input terminal of the operational amplifier. A differential amplifier circuit having a configuration installed in front of the input resistor to be connected is used.
And in the current control device using the differential amplifier circuit,
A high-side switching element connected between the power supply and the inductance load;
And a diode connected between the low-side switching element connected, and the high-side switching element and the low-side switching element between the shunt resistor and the ground connected in series with the inductive load The voltage dividing resistors are connected to both ends of the shunt resistor, the output signal of the differential amplifier circuit is input to the PWM control circuit as a feedback signal, and the gate signal of the low-side switching element is output from the PWM control circuit The current control device is configured as follows.

この発明によれば、オペアンプを含む差動増幅回路の前段を形成する抵抗(R1,R2,Rs,Rf)の他にさらに上流側に分圧抵抗(R1.1、R1.2、Rs1およびRs2)を挿入することで、PchMOSで構成されるオペアンプの入力端子に入力される電圧を低くできるため、同相入力電圧レベルを電源電圧付近以上に高めることができて、差動増幅回路としての同相入力電圧範囲を拡大することができる。
また、この分圧抵抗を差動増幅回路の入力抵抗の一部とし、好適な抵抗値に設定することで、差動電圧増幅率を大きくすることができる。
この差動増幅回路を用いて電流制御装置を作製し、インダクタンス負荷に流れる電流を制御することで、インダクタンス負荷に流れる電流を高精度に制御できる。
この電流制御装置を半導体基板に形成して半導体集積回路装置とすることで、電流制御装置の小型・軽量化を図ることができる。
According to the present invention, in addition to the resistors (R1, R2, Rs, Rf) that form the front stage of the differential amplifier circuit including the operational amplifier, the voltage dividing resistors (R1.1, R1.2, Rs1, and Rs2) are provided further upstream. ) Can be used to lower the voltage input to the input terminal of the operational amplifier composed of PchMOS, so that the common-mode input voltage level can be increased to near the power supply voltage and the common-mode input as a differential amplifier circuit. The voltage range can be expanded.
Further, the differential voltage amplification factor can be increased by setting this voltage dividing resistor as a part of the input resistance of the differential amplifier circuit and setting it to a suitable resistance value.
By producing a current control device using this differential amplifier circuit and controlling the current flowing through the inductance load, the current flowing through the inductance load can be controlled with high accuracy.
By forming this current control device on a semiconductor substrate to form a semiconductor integrated circuit device, the current control device can be reduced in size and weight.

発明の実施の形態を以下の実施例で説明する。尚、以下の図の説明で従来と同一部位には同一の符号を付した。   Embodiments of the invention will be described in the following examples. In the following description of the drawings, the same parts as those in the prior art are denoted by the same reference numerals.

図1は、この発明の第1実施例の差動増幅回路の回路図である。この差動増幅回路101は、オペアンプ15と、オペアンプ15の+入力端子(非反転入力端子)と接続する抵抗9および抵抗13と、抵抗9と接続する抵抗7および抵抗8と、オペアンプ15の−入力端子(反転入力端子)と接続する抵抗12および抵抗14と、抵抗12と接続する抵抗10および抵抗11で構成される。
抵抗13、抵抗11および抵抗8はグランドGNDとそれぞれ接続し、抵抗14はオペアンプ15の出力点28と接続する。抵抗7は第1入力点26(その電圧はVINP1)と接続し、抵抗10は第2入力点27(その電圧はVINN1)と接続する。抵抗9および抵抗12は第3接続点23(その電圧はVINP2)および第4接続点24(その電圧はVINN2)を経由してオペアンプ15の+入力端子および−入力端子とそれぞれ接続する入力抵抗である。
抵抗7および抵抗8はVINP1を分圧する分圧抵抗であり、抵抗10および抵抗11はVINN1を分圧する分圧抵抗である。抵抗9および抵抗13は第1接続点21の電圧を分圧する分圧抵抗であり、抵抗9および抵抗12はオペアンプの入力抵抗である。VINP1はシャント抵抗の高電位側の電圧(第1入力点26の電圧)であり、VINN1はシャント抵抗の低電位側の電圧(第2入力点27の電圧)である。オペアンプ15の出力点28(その電圧は出力電圧Voutである)はマイコンに接続される。
FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention. The differential amplifier circuit 101 includes an operational amplifier 15, a resistor 9 and a resistor 13 connected to the + input terminal (non-inverting input terminal) of the operational amplifier 15, a resistor 7 and a resistor 8 connected to the resistor 9, The resistor 12 and the resistor 14 are connected to the input terminal (inverted input terminal), and the resistor 10 and the resistor 11 are connected to the resistor 12.
The resistors 13, 11, and 8 are connected to the ground GND, and the resistor 14 is connected to the output point 28 of the operational amplifier 15. The resistor 7 is connected to the first input point 26 (its voltage is VINP1), and the resistor 10 is connected to the second input point 27 (its voltage is VINN1). Resistors 9 and 12 are input resistors connected to the + input terminal and the −input terminal of the operational amplifier 15 via the third connection point 23 (its voltage is VINP2) and the fourth connection point 24 (its voltage is VINN2), respectively. is there.
The resistors 7 and 8 are voltage dividing resistors that divide VINP1, and the resistors 10 and 11 are voltage dividing resistors that divide VINN1. The resistors 9 and 13 are voltage dividing resistors that divide the voltage at the first connection point 21, and the resistors 9 and 12 are input resistors of the operational amplifier. VINP1 is a voltage on the high potential side of the shunt resistor (the voltage at the first input point 26), and VINN1 is a voltage on the low potential side of the shunt resistor (the voltage at the second input point 27). The output point 28 of the operational amplifier 15 (its voltage is the output voltage Vout) is connected to the microcomputer.

尚、図中の21は抵抗7と抵抗8と抵抗9を接続する第1接続点、22は抵抗10と抵抗11と抵抗12を接続する第2接続点、23は抵抗9と抵抗13とオペアンプ15の+入力端子とを接続する第3の接続点、24は抵抗12と抵抗14を接続する第4接続点、25は抵抗14とオペアンプの出力点28を接続する第5接続点である。26、27は差動増幅回路の第1、第2入力点である。
R1.1は第1抵抗7の抵抗値、R1.2は第2抵抗8の抵抗値、RS1は第3抵抗10の抵抗値、RS2は第4抵抗11の抵抗値、R1.3は第5抵抗9の抵抗値、R2は第6抵抗13の抵抗値、RS3は第7抵抗12の抵抗値、Rfは第8抵抗14の抵抗値である。
また、VINP1およびVINN1は差動増幅回路に入力される電圧であり、VINP2はオペアンプ15の+入力端子に入力される電圧であり、VINN2はオペアンプの−入力端子に入力される電圧である。
従来の差動増幅回路104との相違は、本発明の差動増幅回路101では抵抗3に相当する抵抗9と抵抗4に相当する抵抗12、抵抗13および抵抗14に加え、分圧の役割を果たす抵抗7、抵抗8、抵抗10および抵抗11が加わった点である。
In the figure, 21 is a first connection point for connecting the resistors 7, 8 and 9, 22 is a second connection point for connecting the resistors 10, 11 and 12, and 23 is a resistor 9, 13 and an operational amplifier. 15 is a third connection point for connecting the + input terminal, 24 is a fourth connection point for connecting the resistor 12 and the resistor 14, and 25 is a fifth connection point for connecting the resistor 14 and the output point 28 of the operational amplifier. Reference numerals 26 and 27 denote first and second input points of the differential amplifier circuit.
R1.1 is the resistance value of the first resistor 7, R1.2 is the resistance value of the second resistor 8, RS1 is the resistance value of the third resistor 10, RS2 is the resistance value of the fourth resistor 11, and R1.3 is the fifth value. The resistance value of the resistor 9, R 2 is the resistance value of the sixth resistor 13, RS 3 is the resistance value of the seventh resistor 12, and Rf is the resistance value of the eighth resistor 14.
VINP1 and VINN1 are voltages input to the differential amplifier circuit, VINP2 is a voltage input to the positive input terminal of the operational amplifier 15, and VINN2 is a voltage input to the negative input terminal of the operational amplifier.
The difference from the conventional differential amplifier circuit 104 is that, in the differential amplifier circuit 101 of the present invention, in addition to the resistor 9 corresponding to the resistor 3, the resistor 12 corresponding to the resistor 4, the resistor 13, and the resistor 14, a voltage dividing role is provided. This is the point that resistance 7, resistance 8, resistance 10, and resistance 11 are added.

ここで、抵抗7(R1.1)と抵抗10(Rs)、抵抗8(R1.1)と抵抗11(Rs2)、抵抗9(R1.3)と抵抗12(Rs3)はそれぞれ等しい抵抗値のものを用いる必要がある。VINP1は、抵抗7、抵抗8により抵抗比(R1.2/(R1.1+R1.2))で分圧され、抵抗9を通じて抵抗13との分圧によりVINP2となりこの電圧がオペアンプ15の+入力端子へ印加される。
一方、VINN1は、抵抗10、11により抵抗比(Rs2/(Rs1+Rs2))で分圧され抵抗12を通してVINN2となり、この電圧がオペアンプ15の−入力端子へ印加される。
この回路による全体の増幅率は、抵抗7(または抵抗10)と抵抗8(または抵抗11)によるレベルシフト率と、抵抗7、8、9(または抵抗10、11、12)と抵抗13(または抵抗14)の抵抗比による増幅率の積で以下のように表現できる。
Here, the resistance 7 (R1.1) and the resistance 10 (Rs), the resistance 8 (R1.1) and the resistance 11 (Rs2), the resistance 9 (R1.3) and the resistance 12 (Rs3) have the same resistance value, respectively. It is necessary to use something. VINP1 is divided by resistors 7 and 8 at a resistance ratio (R1.2 / (R1.1 + R1.2)), and becomes VINP2 by dividing voltage with resistor 13 through resistor 9, and this voltage is the + input terminal of operational amplifier 15 Applied to
On the other hand, VINN1 is divided by resistors 10 and 11 at a resistance ratio (Rs2 / (Rs1 + Rs2)) and becomes VINN2 through resistor 12, and this voltage is applied to the negative input terminal of operational amplifier 15.
The overall amplification factor by this circuit is the level shift rate by the resistor 7 (or resistor 10) and the resistor 8 (or resistor 11), the resistor 7, 8, 9 (or the resistor 10, 11, 12) and the resistor 13 (or It can be expressed as follows by the product of the amplification factors by the resistance ratio of the resistor 14).

Figure 0005130835
または、
Figure 0005130835
Or

Figure 0005130835
但し、R1.1=Rs1、R1.2=Rs2、R1.3=Rs3、R2=Rf
今、電位が低い方の電圧(ここではVINN1)をVcommon、差動電圧をVsとして、VINN1にVcommon、VINP1にVcommon+Vsを印加したときのOUT出力(=Vout)は以下の(1)式〜(3)式の関係式から導き出される。
Figure 0005130835
However, R1.1 = Rs1, R1.2 = Rs2, R1.3 = Rs3, R2 = Rf
Now, when the voltage having the lower potential (here VINN1) is Vcommon, the differential voltage is Vs, and Vcommon is applied to VINN1, and Vcommon + Vs is applied to VINP1, the OUT output (= Vout) is expressed by the following equations (1) to (1): 3) It is derived from the relational expression.

[数3]
VINP2=[R2/{(R1.2/(R1.1+R1.2))+R1.3+R2)}]・(Vcommon+Vs)・・・(1)
[Equation 3]
VINP2 = [R2 / {(R1.2 / (R1.1 + R1.2)) + R1.3 + R2)}]. (Vcommon + Vs) (1)

[数4]
VINN2=[Rf/{(Rs2/(Rs1+Rs2))+Rs3+Rf}]・Vcommon・・・(2)
[Equation 4]
VINN2 = [Rf / {(Rs2 / (Rs1 + Rs2)) + Rs3 + Rf}] · Vcommon (2)

[数5]
VINP2=VINN2(オペアンプのバーチャルショート)・・・(3)
[Equation 5]
VINP2 = VINN2 (virtual short of operational amplifier) (3)

Figure 0005130835
例えば、R1.1=R1.2=Rs1=Rs2=2R、R1.3=Rs3=R、R2=Rf=20Rという任意のRによりVcommonの係数は相殺され、Vout=5Vsという5倍増幅の出力が可能となる。
図2は、図1の本発明の差動増幅回路の同相入力電圧レベルの上限値の電源電圧依存性を示す図である。aが本発明の場合であり、b、c、dは従来の場合である。a列のデータ(黒四角)は差動電圧増幅率が5倍の場合である。図で示すように、同相入力電圧レベルの上限値はVcc=5Vで、9Vとなり、Vcc=15Vでは30Vとなる。つまり、Vccの1.8倍〜2倍にすることができる。また、抵抗比を変更することにより、さらに広い同相入力電圧範囲での差動増幅動作が可能となる。
この差動増幅回路101では、分圧抵抗回路103を構成する分圧抵抗(抵抗7と抵抗8、抵抗10と抵抗11)により差動電圧Vsも分圧されてしまうことから、使用するオペアンプ15は低い同相入力電圧領域ではオフセットが小さいことが望まれる。
本発明の差動増幅回路101とシャント抵抗58を組み合わせ、さらにスイッチングデバイスを加えて電流制御装置を製作し、この電流制御装置で自動車用のソレノイド電流を制御することで、ソレノイド電流を高精度に制御することができる。つぎに、この電流制御装置について説明する。
Figure 0005130835
For example, the coefficient of Vcommon is canceled by an arbitrary R of R1.1 = R1.2 = Rs1 = Rs2 = 2R, R1.3 = Rs3 = R, R2 = Rf = 20R, and an output of 5 times amplification of Vout = 5Vs Is possible.
FIG. 2 is a diagram showing the power supply voltage dependency of the upper limit value of the common-mode input voltage level of the differential amplifier circuit of the present invention shown in FIG. a is the case of the present invention, and b, c, and d are conventional cases. The data in the a column (black square) is when the differential voltage amplification factor is 5 times. As shown in the figure, the upper limit value of the common-mode input voltage level is 9V when Vcc = 5V, and 30V when Vcc = 15V. That is, it can be 1.8 to 2 times Vcc. Further, by changing the resistance ratio, a differential amplification operation in a wider common-mode input voltage range becomes possible.
In this differential amplifier circuit 101, the differential voltage Vs is also divided by the voltage dividing resistors (resistor 7 and resistor 8, resistor 10 and resistor 11) constituting the voltage dividing resistor circuit 103. It is desirable that the offset is small in the low common-mode input voltage region.
By combining the differential amplifier circuit 101 of the present invention and the shunt resistor 58 and further adding a switching device, a current control device is manufactured, and by controlling the solenoid current for automobiles with this current control device, the solenoid current is highly accurate. Can be controlled. Next, the current control device will be described.

図3は、この発明の第2実施例の電流制御装置の回路図である。図5に示す従来の電流制御装置115と異なるのは、差動増幅回路として分圧抵抗を付加した差動増幅回路101を用いた点である。本発明の電流制御装置110は主にPWM回路102と差動増幅回路101で構成され、PWM回路102は、電源51、ハイサイド側のスイッチングデバイス52、ゲート電源53、ダイオード54、シャント抵抗58、ローサイドのスイッチングデバイス55、それを駆動するPWM制御回路56で構成される。
オペアンプ15の出力電圧OUTはマイコン59を経由してフィードバック信号となり、このフィードバック信号をPWM制御回路56に入力し、PWM制御回路56からローサイドのスイッチングデバイス55のゲート電圧LSP−INが出力される。
本発明の電流制御装置110を使用することで、従来の電流制御装置115よりソレノイド電流を高精度に制御することができる。
FIG. 3 is a circuit diagram of a current control apparatus according to the second embodiment of the present invention. The difference from the conventional current control device 115 shown in FIG. 5 is that a differential amplifier circuit 101 to which a voltage dividing resistor is added is used as the differential amplifier circuit. The current control device 110 of the present invention mainly includes a PWM circuit 102 and a differential amplifier circuit 101. The PWM circuit 102 includes a power supply 51, a high-side switching device 52, a gate power supply 53, a diode 54, a shunt resistor 58, The low-side switching device 55 is composed of a PWM control circuit 56 that drives the low-side switching device 55.
The output voltage OUT of the operational amplifier 15 becomes a feedback signal via the microcomputer 59, and this feedback signal is input to the PWM control circuit 56, and the gate voltage LSP-IN of the low-side switching device 55 is output from the PWM control circuit 56.
By using the current control device 110 of the present invention, the solenoid current can be controlled with higher accuracy than the conventional current control device 115.

図4は、この発明の第3実施例の半導体集積回路装置の要部配置図である。図3で示す電流制御装置110の回路を半導体基板111に形成した場合の要部配置図である。半導体基板111に各構成要素を集積して半導体集積回路装置112とすることで電流制御装置110の小型・軽量化を図ることができる。構成要素のうちシャント抵抗58は外付けで示したが半導体基板内に形成することもできる。
尚、図中の61、62、63はソレノイド57やシャント抵抗58と接続するための電極パッドであり、図3の端子29、第1入力点26および第2入力点27にそれぞれ相当する。
FIG. 4 is a layout of the main part of the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 4 is a main part arrangement diagram when the circuit of the current control device 110 shown in FIG. 3 is formed on a semiconductor substrate 111. By integrating each component on the semiconductor substrate 111 to form the semiconductor integrated circuit device 112, the current control device 110 can be reduced in size and weight. Of the components, the shunt resistor 58 is shown as being externally attached, but it can also be formed in the semiconductor substrate.
In the figure, reference numerals 61, 62, and 63 denote electrode pads for connection to the solenoid 57 and the shunt resistor 58, which correspond to the terminal 29, the first input point 26, and the second input point 27 in FIG.

この発明の第1実施例の差動増幅回路の回路図1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention. 図1の本発明の差動増幅回路の同相入力電圧範囲の上限値の電源電圧依存性を示す図The figure which shows the power supply voltage dependence of the upper limit of the common mode input voltage range of the differential amplifier circuit of this invention of FIG. この発明の第2実施例の電流制御装置の回路図Circuit diagram of current controller of second embodiment of this invention この発明の第3実施例の半導体集積回路装置の要部配置図Arrangement of principal part of semiconductor integrated circuit device according to third embodiment of this invention. ソレノイド電流を制御する車載用の電流制御装置の要部回路図Main part circuit diagram of in-vehicle current control device for controlling solenoid current PWM回路102の各部の動作波形を示し、(a)はLSP−INの電圧波形、(b)はVINN1の電圧波形、(c)はVINP1の電圧波形、(d)はIs×Rshuntの電圧波形、(e)はVoutの電圧波形を示す図The operation waveform of each part of the PWM circuit 102 is shown, (a) is a voltage waveform of LSP-IN, (b) is a voltage waveform of VINN1, (c) is a voltage waveform of VINP1, and (d) is a voltage waveform of Is × Rshunt. (E) is a figure which shows the voltage waveform of Vout. 従来の差動増幅回路での同相入力電圧範囲の上限値の電源電圧依存性を示す図The figure which shows the power supply voltage dependence of the upper limit of the common mode input voltage range in the conventional differential amplifier circuit

符号の説明Explanation of symbols

7〜14 抵抗
15 オペアンプ
21〜25 第1〜第5接続点
26、27 第1、第2入力点
28 出力点
29 端子
51 電源
52 スイッチングデバイス(HSP)
53 ゲート電源
54 ダイオード
55 スイッチングデバイス(LSP)
56 PWM制御回路
57 ソレノイド
58 シャント抵抗
59 マイコン
61〜63 電極パッド
101 差動増幅回路
102 PWM回路
103 分圧抵抗回路
110 電流制御装置
111 半導体基板
112 半導体集積回路装置
VINP1 第1入力点の電圧
VINN1 第2入力点の電圧
VINP2 第3接続点の電圧
VINN2 第4接続点の電圧
Vout 出力点の電圧(出力電圧)
HSP−IN HSPのゲート電圧信号
LSP−IN LSPのゲート電圧信号
Vs 差動電圧
Vcommon 同相入力電圧

7-14 resistor 15 operational amplifier 21-25 first to fifth connection point 26, 27 first and second input point 28 output point 29 terminal 51 power supply 52 switching device (HSP)
53 Gate power supply 54 Diode 55 Switching device (LSP)
56 PWM control circuit 57 Solenoid 58 Shunt resistor 59 Microcomputer 61-63 Electrode pad 101 Differential amplifier circuit 102 PWM circuit 103 Voltage dividing resistor circuit 110 Current controller 111 Semiconductor substrate 112 Semiconductor integrated circuit device VINP1 First input point voltage VINN1 First Voltage at two input points VINP2 Voltage at third connection point VINN2 Voltage at fourth connection point Vout Voltage at output point (output voltage)
HSP-IN HSP gate voltage signal LSP-IN LSP gate voltage signal Vs Differential voltage Vcommon In-phase input voltage

Claims (1)

Pch入力型オペアンプを含む差動増幅回路入力電圧を分圧する分圧抵抗を前記オペアンプの入力端子と接続する入力抵抗の前段に設置し
電源とインダクタンス負荷との間に接続されるハイサイド側スイッチング素子と、
前記インダクタンス負荷に直列に接続されたシャント抵抗とグランドとの間に接続されるローサイド側スイッチング素子と、
前記ハイサイド側スイッチング素子と前記ローサイド側スイッチング素子との間に接続されるダイオードと、を備え、
前記シャント抵抗の両端にそれぞれ前記分圧抵抗を接続し、前記差動増幅回路の出力信号をフィードバック信号としてPWM制御回路へ入力し、該PWM制御回路から前記ローサイド側スイッチング素子のゲート信号を出力することを特徴とする電流制御装置。
A voltage dividing resistor that divides the input voltage of the differential amplifier circuit including the Pch input type operational amplifier is installed in front of the input resistor connected to the input terminal of the operational amplifier .
A high-side switching element connected between the power supply and the inductance load;
A low-side switching element connected between a shunt resistor connected in series to the inductance load and a ground;
A diode connected between the high-side switching element and the low-side switching element,
The voltage dividing resistors are connected to both ends of the shunt resistor, the output signal of the differential amplifier circuit is input as a feedback signal to the PWM control circuit, and the gate signal of the low-side switching element is output from the PWM control circuit. A current control device.
JP2007234037A 2007-09-10 2007-09-10 Differential amplifier circuit and current control device using the same Expired - Fee Related JP5130835B2 (en)

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