JP5895726B2 - Receiver circuit device - Google Patents

Description

  The present invention relates to a receiving circuit device that receives a differential signal transmitted through a pair of signal lines.

  For example, in a receiving circuit device in two-wire communication using differential signals such as CAN communication, the input signal is gain-compressed and received when the potential range of the received signal is wider than the circuit power supply range (in-phase input range). The structure which does is employ | adopted (for example, refer patent document 1). Conventionally, the common-mode input range in CAN communication has been defined by ISO11898-2. Further, a threshold value for determining recessive / dominant in CAN communication is defined by, for example, manufacturer authentication SPEC. For this reason, in the conventional receiving circuit device, the gain is set so as to satisfy the in-phase input range defined by ISO11898-2 and also the threshold defined by the manufacturer authentication SPEC.

  However, with the standardization of ISO11898-5, its common-mode input range has become wider. In order to widen the common-mode input range, the compression gain may be increased. However, if the gain is increased, the variation in threshold value due to an error factor due to an offset or the like increases, making it difficult to satisfy the manufacturer certification SPEC.

JP 2011-146904 A

  Patent Document 1 discloses a method of expanding the common-mode input range without changing the gain by switching the center bias voltage according to the input common mode signal level. However, this method cannot be used for CAN communication because a recessive voltage occurs.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a receiving circuit device that expands the common-mode input range as compared with the prior art and at least obtains the same characteristics as the conventional one in the conventional common-mode input range. There is.

  According to the first aspect of the present invention, the differential signal transmitted through the pair of signal lines is received, and the compression circuit, the detection circuit, and the input range optimization unit are provided. The compression circuit outputs a first compressed signal obtained by compressing a voltage between a first input terminal to which one differential signal is applied and a bias terminal to which a bias voltage is applied with a predetermined compression gain. The compression circuit outputs a second compressed signal obtained by compressing the voltage between the second input terminal to which the other differential signal is applied and the bias terminal with a compression gain. The detection circuit includes a comparator that receives the first compressed signal and the second compressed signal and discriminates a differential voltage between the differential signals, and outputs an output of the comparator as a differential signal reception signal.

In such a configuration, when the potential of the differential signal deviates from the predetermined input range, the input optimization means is optimized so that the potentials of the first compressed signal and the second compressed signal are within the in-phase input range of the comparator. Therefore, the in-phase input range can be expanded beyond the predetermined input range. Further, when the potential of the differential signal is within a predetermined input range, the determination of the difference voltage based on the first compressed signal and the second compressed signal compressed in the compression gain of the predetermined input range is performed. In other words, since the reception of the differential signal is performed at a predetermined input range, the predetermined input range equal characteristics can be obtained for characteristics such as variations in the example threshold.

  According to the fifth aspect of the invention, the differential signal transmitted through the pair of signal lines is received, and the compression circuit and the detection circuit are provided. The compression circuit outputs a first compressed signal obtained by compressing a voltage between a first input terminal to which one differential signal is applied and a bias terminal to which a bias voltage is applied with a predetermined compression gain. The compression circuit outputs a second compressed signal obtained by compressing the voltage between the second input terminal to which the other differential signal is applied and the bias terminal with a compression gain. The detection circuit includes a first comparator and a second comparator, and outputs one of the outputs of the first comparator and the second comparator as a reception signal of the differential signal. The first comparator receives the first compressed signal and the second compressed signal and determines a differential voltage between the differential signals. The second comparator receives the differential signal and shifts the input signal by a predetermined level to determine the differential voltage of the differential signal.

In such a configuration, the detection circuit, in the case where the potential of the differential signal is within Tokoro TeiIri force range and outputs an output of the first comparator as a reception signal of the differential signal. That is, when the potential of the differential signal is within Tokoro TeiIri force range, the determination of the difference voltage based on the first compressed signal and the second compressed signal compressed in the compression gain at a predetermined input range is performed. Therefore, since the reception of the differential signal is performed at a predetermined input range, characteristics equivalent to the case of a predetermined input range can be obtained the characteristics of variations in the example threshold.

The detection circuit outputs the output of the second comparator as a reception signal of the differential signal when the potential of the differential signal is out of the predetermined input range. At this time, the second comparator can normally determine the difference voltage by level-shifting the differential signal so that it becomes a signal within its own in-phase input range, for example. That is, when the potential of the differential signal deviates from the predetermined input range, the reception operation is normally performed by the second comparator, so that the in-phase input range can be expanded beyond the conventional input range.

1 is a schematic configuration diagram of a receiving circuit device according to a first embodiment. The figure which shows the relation between the voltage of the bus communication line and the common mode input voltage of the comparator FIG. 1 equivalent diagram showing the second embodiment 2 equivalent diagram FIG. 1 equivalent view showing the third embodiment 2 equivalent diagram FIG. 1 equivalent view showing the fourth embodiment The figure which shows the concrete constitution of the clamp circuit 2 equivalent diagram FIG. 1 equivalent diagram showing the fifth embodiment Equivalent to FIG. 2 equivalent diagram FIG. 1 equivalent view showing the sixth embodiment 2 equivalent diagram The figure which shows the relation between the voltage of the bus communication line and the common mode input voltage of the input level shift comparator FIG. 1 equivalent diagram showing a seventh embodiment 2 equivalent diagram Figure 15 equivalent FIG. 1 equivalent view showing a modification of the sixth embodiment FIG. 1 equivalent view showing a modification of the seventh embodiment

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS. 1 and 2.
A receiving circuit device 1 shown in FIG. 1 is used for CAN (Controller Area Network) communication, and receives a differential signal transmitted through a pair of bus communication lines BP and BM (corresponding to signal lines). The reception circuit device 1 compares the difference voltage (differential component) between the pair of differential signals with a predetermined threshold value, and outputs a reception signal corresponding to the comparison result. The received signal is given to a CPU (not shown) provided in the subsequent stage of the receiving circuit device 1. In this case, the receiving circuit device 1 determines recessive (corresponding to the logic level “1”) when the difference voltage is equal to or lower than the threshold value, and outputs a received signal representing the determination result. In addition, when the difference voltage is equal to or greater than the threshold, the reception circuit device 1 determines that it is dominant (corresponding to the logic level “0”), and outputs a reception signal indicating the determination result.

  The receiving circuit device 1 includes a first input terminal P1, a second input terminal P2, a bias terminal P3, an output terminal P4, resistors R1p to R3p, resistors R1m to R3m, comparators CP1, CP2, an offset voltage source 2, an inverter circuit 3, Switches S1 to S4 are provided. The first input terminal P1 and the second input terminal P2 are connected to two-wire bus communication lines BP and BM, respectively. An intermediate potential Vm (corresponding to a bias voltage) that determines a recessive voltage is applied to the bias terminal P3. The intermediate potential Vm is ½ (= Vcc / 2) of a power supply voltage Vcc described later.

  Resistors R1p to R3p are connected in series in this order between the first input terminal P1 and the bias terminal P3. The resistors R1p to R3p are compression ladder resistors that compress the voltage between the first input terminal P1 and the bias terminal P3 with a predetermined compression gain. Resistors R1m to R3m are connected in series in this order between the second input terminal P2 and the bias terminal P3. The resistors R1m to R3m are compression ladder resistors that compress the voltage between the second input terminal P2 and the bias terminal P3 with a predetermined compression gain. Although details will be described later, the resistors R1p to R3m are provided to keep the voltage of the differential signal (in-phase component) within the in-phase input range of the comparator CP1. The resistors R1p and R1m have the same resistance value R1, the resistors R2p and R2m have the same resistance value R2, and the resistors R3p and R3m have the same resistance value R3. The compression gain is determined according to the resistance values R1 to R3.

  The interconnection node N1p of the resistors R1p and R2p is connected to one inverting input terminal of the comparator CP2, and is connected to the non-inverting input terminal of the comparator CP1 through the switch S2. The interconnection node N2p of the resistors R2p and R3p is connected to the non-inverting input terminal of the comparator CP1 through the switch S1.

  The interconnection node N1m of the resistors R1m and R2m is connected to the other inverting input terminal of the comparator CP2, and is connected to the inverting input terminal of the comparator CP1 through the switch S3 and the offset voltage source 2. The interconnection node N2m of the resistors R2m and R3m is connected to the inverting input terminal of the comparator CP1 through the switch S4 and the offset voltage source 2. The interconnection node Nb of the resistors R3p and R3m is connected to the bias terminal P3.

  The comparator CP1 operates by receiving a single positive power supply voltage Vcc (in this embodiment, + 5V). Therefore, it is necessary to perform circuit design (gain setting, etc.) of the input stage by setting the common-mode input range of the comparator CP1 to a range narrower than 0 V to Vcc, for example, +1 to +4 V. The output terminal of the comparator CP1 is connected to the output terminal P4. Comparator CP2 operates by receiving a single positive power supply voltage Vcc. A reference voltage Vr1 (+ 1V in this embodiment) generated by a reference voltage generation circuit (not shown) is applied to the non-inverting input terminal of the comparator CP2. Note that the reference voltage generation circuit can be configured by a bandgap reference circuit, for example.

  The output terminal of the comparator CP2 is connected to the input terminal of the inverter circuit 3 and to the switching terminals of the switches S1 and S4. The output terminal of the inverter circuit 3 is connected to the switching terminals of the switches S2 and S3. The switches S1 to S4 are turned on when a signal given to the switching terminal becomes H level (for example, a level equivalent to the power supply voltage Vcc). Further, the switches S1 to S4 are turned off when the signal given to the switching terminal becomes L level (for example, 0 V). According to such a configuration, the switches S1 and S4 and the switches S2 and S3 are turned ON / OFF in a complementary manner.

  In the above configuration, the compression circuit 4 is configured by the resistors R1p to R3m. The compression circuit 4 compresses a voltage between the first input terminal P1 and the bias terminal P3 with a predetermined compression gain and a voltage between the second input terminal P2 and the bias terminal P3 with a predetermined compression gain. And the second compressed signal compressed in step. In this case, the signal output from the node N1p or N2p corresponds to the first compressed signal. The compression gain of the first compression signal output from the node N1p is a first set value determined by the ratio of the resistor R1p and the series combined resistance of the resistor R2p and the resistor R3p. In addition, the compression gain of the first compression signal output from the node N2p is a second set value determined by the ratio of the combined resistance of the resistors R1p and R2p and the resistor R3p.

  A signal output from the node N1m or N2m corresponds to the second compressed signal. The compression gain of the second compression signal output from the node N1m is a first set value determined by the ratio of the resistor R1m and the series combined resistance of the resistor R2m and the resistor R3m. The compression gain of the second compression signal output from the node N2m is a second set value determined by the ratio of the combined resistance of the resistors R1m and R2m to the resistor R3m. Note that the first set value is a value such that, for example, a characteristic equivalent to the conventional one can be obtained with respect to a characteristic such as a variation in threshold value. On the other hand, the second set value is higher than the first set value.

  In view of this point, hereinafter, the signal output from the node N1p is also referred to as a low gain first compressed signal, and the signal output from the node N2p is also referred to as a high gain first compressed signal. . A signal output from the node N1m is also referred to as a low gain second compressed signal, and a signal output from the node N2m is also referred to as a high gain second compressed signal.

The resistance values R1 to R3 of the resistors R1p to R3m constituting the compression circuit 4 are set so as to satisfy the following three conditions.
(1) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is −7V, the voltage of the node N1p (node N1m) becomes + 1V.
(2) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is + 12V, the voltage of the node N1p (node N1m) becomes + 4V.
(3) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is −12V, the voltage of the node N2p (node N2m) becomes + 1V.
(4) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is + 17V, the voltage of the node N2p (node N2m) becomes + 4V.

  In the present embodiment, the detection circuit 5 is configured by the comparator CP1 and the offset voltage source 2. The detection circuit 5 discriminates the differential voltage between the differential signals based on the first compressed signal and the second compressed signal supplied from the compression circuit 4. The threshold value used for the determination is determined by the offset voltage VTH (for example, +0.5 to +0.9 V or +0.7 to +0.9 V) generated by the offset voltage source 2.

  In the present embodiment, the input range optimizing means 6 is configured by the comparator CP2, the inverter circuit 3, and the switches S1 to S4. Based on the potential of the differential signal, the input range optimization means 6 makes the potential of the first compressed signal and the second compressed signal applied from the compression circuit 4 to the detection circuit 5 fall within the common-mode input range of the comparator CP1. To optimize. Specifically, the input range optimization means 6 is a low-gain first compressed signal output from the node N1p when the potential (in-phase component) of the differential signal is within the range of −7V to + 12V. The low gain second compressed signal output from the node N1m is input to the comparator CP1. The input range optimizing means 6 also applies the high gain first compression signal output from the node N2p and the high gain second compression output from the node N2m when the potential of the differential signal is less than −7V. The signal is input to the comparator CP1. That is, the input range optimization unit 6 has a function as a gain setting unit that switches (sets) the compression gains of the first compressed signal and the second compressed signal output from the compression circuit 4.

According to the above configuration, the following operations and effects can be obtained.
When the potentials of the differential signals of the bus communication lines BP and BM exceed -7V, the voltages at the nodes N1p and N1m both exceed + 1V (= Vr1). Therefore, the output of the comparator CP2 is at L level, the switches S1 and S4 are turned off, and the switches S2 and S3 are turned on. That is, the low gain first compressed signal and the low gain second compressed signal are input to the comparator CP1. The low gain first compression signal is a voltage (one differential signal) between the first input terminal P1 and the bias terminal P3 compressed with the compression gain of the first set value. Further, the low gain second compressed signal is obtained by compressing the voltage (the other differential signal) between the second input terminal P2 and the bias terminal P3 with the compression gain of the first set value.

  On the other hand, when the potentials of the differential signals of the bus communication lines BP and BM are lower than −7V, the voltages at the nodes N1p and N1m are both lower than + 1V (= Vr1). Therefore, the output of the comparator CP2 is at the H level, the switches S1 and S4 are turned on, and the switches S2 and S3 are turned off. That is, the high gain first compressed signal and the high gain second compressed signal are input to the comparator CP1. The high gain first compressed signal is a signal obtained by compressing one differential signal with the compression gain of the second set value. The high gain second compressed signal is obtained by compressing the other differential signal with the compression gain of the second set value.

Thus, in the receiving circuit device 1, the compression gain in the compression circuit 4 is switched before the first compressed signal and the second compressed signal input to the comparator CP1 fall below the in-phase input range. As a result, as shown in FIG. 2, reception of differential signals in an input range (−12 V to +12 V) wider than a conventional input range (for example, −2 V to +7 V, −5 V to +12 V), which is a predetermined input range. It becomes possible. In addition, when the potential of the differential signal is in the range of −7 V to +12 V, based on the low gain first compressed signal and the low gain second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. A recessive / dominant decision is made. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, according to the present embodiment, the common-mode input range is expanded as compared with the conventional case, and characteristics equivalent to those of the conventional case can be obtained at least in the conventional common-mode input range.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 21 of the present embodiment shown in FIG. 3 includes an input range optimizing unit 22 instead of the input range optimizing unit 6 with respect to the receiving circuit device 1 of the first embodiment shown in FIG. Is different. The input range optimization unit 22 differs from the input range optimization unit 6 in that a comparator CP3 is provided instead of the comparator CP2. With this change, the connection of the part related to the input of the comparator CP3 is also changed.

  That is, one non-inverting input terminal of the comparator CP3 is connected to the node N1p. The other non-inverting input terminal of the comparator CP3 is connected to the node N1m. A reference voltage Vr2 is applied to the inverting input terminal of the comparator CP3. The reference voltage Vr2 is generated by a reference voltage generation circuit (not shown), and is + 4V in this embodiment.

According to such a configuration, the following operations and effects can be obtained.
When the potentials of the differential signals of the bus communication lines BP and BM are lower than + 12V, the voltages at the nodes N1p and N1m are both lower than + 4V (= Vr2). Therefore, the output of the comparator CP3 is L level, the switches S1 and S4 are turned off, and the switches S2 and S3 are turned on. That is, the low gain first compressed signal and the low gain second compressed signal are input to the comparator CP1. On the other hand, when the potentials of the differential signals of the bus communication lines BP and BM exceed + 12V, the voltages at the nodes N1p and N1m both exceed + 4V (= Vr2). Therefore, the output of the comparator CP3 is at the H level, the switches S1 and S4 are turned on, and the switches S2 and S3 are turned off. That is, the high gain first compressed signal and the high gain second compressed signal are input to the comparator CP1.

  Thus, in the receiving circuit device 1, the compression gain in the compression circuit 4 is switched before the first compressed signal and the second compressed signal input to the comparator CP1 exceed the in-phase input range. As a result, as shown in FIG. 4, it is possible to receive a differential signal in an input range (−7 V to +17 V) wider than a conventional input range (for example, −2 V to +7 V, −7 V to +12 V). In addition, when the potential of the differential signal is in the range of −7 V to +12 V, based on the low gain first compressed signal and the low gain second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. A recessive / dominant decision is made. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the first embodiment.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 31 of the present embodiment shown in FIG. 5 includes an input range optimizing unit 32 instead of the input range optimizing unit 6 as compared with the receiving circuit device 1 of the first embodiment shown in FIG. Is different. The input range optimizing unit 32 is different from the comparator CP2 in that it includes a comparator CP2 ′ and a new comparator CP3 ′, inverter circuits 33 and 34, and an OR circuit 35.

  One non-inverting input terminal of the comparator CP2 'is connected to the node N1p. The other non-inverting input terminal of the comparator CP2 'is connected to the node N1m. A reference voltage Vr1 (+1 V as in the first embodiment) is applied to the inverting input terminal of the comparator CP2 '. One inverting input terminal of the comparator CP3 'is connected to the node N1p. The other inverting input terminal of the comparator CP3 'is connected to the node N1m. A reference voltage Vr2 (+4 V as in the second embodiment) is applied to the non-inverting input terminal of the comparator CP3 '.

  The output terminal of the comparator CP <b> 2 ′ is connected to the input terminal of the inverter circuit 33. The output terminal of the inverter circuit 33 is connected to one input terminal of the OR circuit 35. The output terminal of the comparator CP3 'is connected to the input terminal of the inverter circuit 34. The output terminal of the inverter circuit 34 is connected to the other input terminal of the OR circuit 35. The output terminal of the OR circuit 35 is connected to the input terminal of the inverter circuit 3 and to the switching terminals of the switches S1 and S4. The output terminal of the inverter circuit 3 is connected to the switching terminals of the switches S2 and S3.

According to such a configuration, the following operations and effects can be obtained.
When the potentials of the differential signals of the bus communication lines BP and BM are higher than -7V and lower than + 12V, the voltages of the nodes N1p and N1m are both higher than + 1V (= Vr1) and lower than + 4V (= Vr2). Therefore, the outputs of the comparators CP2 ′ and CP3 ′ are both at the H level. Accordingly, since the output of the OR circuit 35 becomes L level, the switches S1 and S4 are turned off, and the switches S2 and S3 are turned on. That is, the low gain first compressed signal and the low gain second compressed signal are input to the comparator CP1.

  On the other hand, when the potentials of the differential signals of the bus communication lines BP and BM are lower than −7V, the voltages at the nodes N1p and N1m are both lower than + 1V (= Vr1). Therefore, the output of the comparator CP2 'is L level, and the output of the comparator CP3' is H level. Accordingly, since the output of the OR circuit 35 is at the H level, the switches S1 and S4 are turned on and the switches S2 and S3 are turned off. That is, the high gain first compressed signal and the high gain second compressed signal are input to the comparator CP1.

  When the potentials of the differential signals of the bus communication lines BP and BM exceed + 12V, the voltages at the nodes N1p and N1m both exceed + 4V (= Vr2). Therefore, the output of the comparator CP2 'is H level, and the output of the comparator CP3' is L level. Accordingly, since the output of the OR circuit 35 is at the H level, the switches S1 and S4 are turned on and the switches S2 and S3 are turned off. That is, the high gain first compressed signal and the high gain second compressed signal are input to the comparator CP1.

  Thus, in the receiving circuit device 1, the compression gain in the compression circuit 4 is switched before the first compressed signal and the second compressed signal input to the comparator CP1 exceed the in-phase input range. As a result, as shown in FIG. 6, it is possible to receive a differential signal in an input range (−12 V to +17 V) wider than a conventional input range (for example, −2 V to +7 V, −7 V to +12 V). In addition, when the potential of the differential signal is in the range of −7 V to +12 V, based on the low gain first compressed signal and the low gain second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. A recessive / dominant decision is made. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the above embodiments.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 41 according to the present embodiment shown in FIG. 7 is different from the receiving circuit device 1 according to the first embodiment shown in FIG. The difference is that an input range optimizing unit 43 is provided instead of the optimizing unit 6.

  The compression circuit 42 includes resistors R41p, R42p, R41m, and R42m. Resistors R41p and R42p are connected in series in this order between the first input terminal P1 and the bias terminal P3. Resistors R41m and R42m are connected in series in this order between the second input terminal P2 and the bias terminal P3. The resistors R41p and R41m have the same resistance value R41, and the resistors R42p and R42m have the same resistance value R42. The compression gain is determined according to the resistance values R41 and R42.

  The interconnection node N41p of the resistors R41p and R42p is connected to the non-inverting input terminal of the comparator CP1. The interconnection node N41m of the resistors R41m and R42m is connected to the inverting input terminal of the comparator CP1 through the offset voltage source 2. The interconnection node Nb of the resistors R42p and R42m is connected to the bias terminal P3.

  The compression circuit 42 compresses a voltage between the first input terminal P1 and the bias terminal P3 with a predetermined compression gain and a voltage between the second input terminal P2 and the bias terminal P3 with a predetermined compression gain. And the second compressed signal compressed in step. In this case, the signal output from the node N41p corresponds to the first compressed signal. The compression gain of the first compression signal output from the node N41p is a first set value determined by the ratio of the resistor R41p and the resistor R42p. Further, the signal output from the node N41m corresponds to the second compressed signal. The compression gain of the second compression signal output from the node N41m is a first set value determined by the ratio of the resistor R41m and the resistor R42m. Note that the first set value is a value such that, for example, a characteristic equivalent to the conventional one can be obtained with respect to a characteristic such as a variation in threshold value.

The resistance values R41 and R42 of the resistors R41p to R42m constituting the compression circuit 42 are set so as to satisfy the following two conditions.
(1) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is −5V, the voltage of the node N41p (node N41m) becomes + 1V.
(2) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is + 12V, the voltage of the node N41p (node N41m) becomes + 4V.

  The input range optimizing unit 43 includes resistors R43p and R43m and clamp circuits 44p and 44m. One terminal of the resistor R43p is connected to the node N41p. The other terminal of the resistor R43p is connected to the output terminal of the clamp circuit 44p. One terminal of the resistor R43m is connected to the node N41m. The other terminal of the resistor R43m is connected to the output terminal of the clamp circuit 44m. The resistors R43p and R43m have the same resistance value R43.

  The clamp circuits 44p and 44m clamp the output terminal voltage to the clamp voltage VCL (+1 V in the present embodiment), and correspond to clamp means. Therefore, in the receiving circuit device 41 of the present embodiment, the first compression input to the comparator CP1 when the potential of the differential signal is less than −5V (corresponding to the lower limit value of the conventional input range in the present embodiment). The potential of the signal and the second compressed signal is clamped to a value (+1 V) that does not fall below the common-mode input range.

  The specific configuration of the clamp circuits 44p and 44m is as shown in FIG. The clamp circuit shown in FIG. 8A includes resistors R44 and R45 and a transistor T41. The resistors R44 and R45 are connected in series between a power supply terminal P41 to which, for example, + 5V power is supplied and a ground terminal P42. The transistor T41 is an NPN bipolar transistor. The base of the transistor T41 is connected to the interconnection node N42 of the resistors R44 and R45. The collector of the transistor T41 is connected to the power supply terminal P41. The emitter of the transistor T41 is an output terminal for the clamp voltage VCL. The resistance values of the resistors R44 and R45 are set such that the voltage at the node N42 is + 1.7V.

  In the clamp circuit shown in FIG. 8B, a resistor R46 and a transistor T42 are added to the configuration shown in FIG. The transistor T42 is a PNP type bipolar transistor. The base of the transistor T42 is connected to the node N42. The collector of the transistor T42 is connected to the ground terminal P42. The emitter of the transistor T42 is connected to the power supply terminal P41 via the resistor R46, and is connected to the base of the transistor T41. In this case, the resistance values of the resistors R44 and R45 are set so that the voltage at the node N42 becomes + 1V. According to such a configuration of FIG. 8B, fluctuation of the clamp voltage VCL due to the temperature characteristics of the forward voltage of the transistor is suppressed as compared with the configuration of FIG.

  The clamp circuit shown in FIG. 8C is different from the configuration shown in FIG. 8A in that an OP amplifier OP41 is provided instead of the transistor T41. The OP amplifier OP41 is connected in the form of a voltage follower, and its non-inverting input terminal is connected to the node N42. The output terminal of the OP amplifier OP41 is an output terminal for the clamp voltage VCL. Also in this case, the resistance values of the resistors R44 and R45 are set such that the voltage at the node N42 is + 1V.

  As shown in FIG. 9, according to the reception circuit device 41 configured as described above, the common-mode voltage of the first compression signal and the second compression signal in the region where the potential of the differential signal is less than −5 V (the conventional non-operation region). Is clamped to + 1V. For this reason, the input signal of the comparator CP1 does not fall below the in-phase input range. As a result, it is possible to receive a differential signal in an input range (−12 V to +12 V) wider than a conventional input range (for example, −2 V to +7 V, −5 V to +12 V).

In this case, the voltage V (+) at the non-inverting input terminal and the voltage V (−) at the inverting input terminal of the comparator CP1 are expressed by the following equations (1) and (2), respectively. However, the voltage of the first input terminal P1 is BP, and the voltage of the second input terminal P2 is BM.
V (+) = (BP-VCL). (R43 / (R41 + R43)) + VCL (1)
V (-) = VTH + (BM-VCL). (R43 / (R41 + R43)) + VCL (2)

The following expression (3) is derived from the above expressions (1) and (2) and “V + = V−”.
BP-BM = VTH · ((R1 + R3) / R3) (3)
As shown in the above equation (3), the comparator CP1 of this embodiment compares the differential voltage (differential component) of the differential signal with a predetermined threshold value VTH, and outputs a received signal corresponding to the comparison result. Therefore, the receiving circuit device 41 of this embodiment can perform recessive / dominant determination (detection).

  However, strictly speaking, a current also flows to the bias terminal P3 via the resistors R42p and R42m. Therefore, the receiving circuit device 41 according to the present embodiment is reduced in accuracy by the amount of the current flowing (an error occurs), but the circuit elements of each circuit element are satisfied so as to satisfy a required standard (for example, ISO11898-5). What is necessary is just to set a constant.

  In addition, when the potential of the differential signal is in the range of −5V to + 12V, the recessive / reverse signal is generated based on the first compressed signal and the second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. A dominant decision is made. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the above embodiments.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 51 of the present embodiment shown in FIG. 10 is provided with an input range optimizing unit 52 instead of the input range optimizing unit 43 with respect to the receiving circuit device 41 of the fourth embodiment shown in FIG. Is different. The input range optimization unit 52 differs from the input range optimization unit 43 in that it includes clamp circuits 53p and 53m instead of the clamp circuits 44p and 44m.

  The clamp circuits 53p and 53m clamp the output terminal voltage to the clamp voltage VCL (+4 V in this embodiment), and correspond to clamp means. Therefore, in the receiving circuit device 51 of the present embodiment, when the potential of the differential signal exceeds + 12V (corresponding to the upper limit value of the conventional input range), the first compressed signal and the second compressed signal input to the comparator CP1. Is clamped to a value (+ 4V) that does not exceed the common-mode input range.

  The specific configuration of the clamp circuits 53p and 53m is as shown in FIG. The clamp circuit shown in FIG. 11A includes resistors R54 and R55 and a transistor T51. The resistors R54 and R55 are connected in series between a power supply terminal P51 to which, for example, + 5V power is supplied and a ground terminal P52. The transistor T51 is a PNP bipolar transistor. The base of the transistor T51 is connected to the interconnection node N52 of the resistors R54 and R55. The collector of the transistor T51 is connected to the ground terminal P52. The emitter of the transistor T51 is an output terminal for the clamp voltage VCL. The resistance values of resistors R54 and R55 are set such that the voltage at node N52 is + 3.3V.

  In the clamp circuit shown in FIG. 11B, a resistor R56 and a transistor T52 are added to the configuration shown in FIG. The transistor T52 is an NPN bipolar transistor. The base of the transistor T52 is connected to the node N52. The collector of the transistor T52 is connected to the power supply terminal P51. The emitter of the transistor T52 is connected to the ground terminal P52 through the resistor R56 and is connected to the base of the transistor T51. In this case, the resistance values of the resistors R54 and R55 are set such that the voltage at the node N52 is + 4V. According to such a configuration of FIG. 11B, fluctuations in the clamp voltage VCL due to the temperature characteristics of the forward voltage of the transistor are suppressed as compared with the configuration of FIG.

  The clamp circuit shown in FIG. 11C is different from the configuration shown in FIG. 11A in that an OP amplifier OP51 is provided instead of the transistor T51. The OP amplifier OP51 is connected in the form of a voltage follower, and its non-inverting input terminal is connected to the interconnection node N52. The output terminal of the OP amplifier OP51 is an output terminal for the clamp voltage VCL. Also in this case, the resistance values of the resistors R54 and R55 are set such that the voltage at the node N52 is + 4V.

  As shown in FIG. 12, according to the reception circuit device 51 configured as described above, in the region where the potential of the differential signal exceeds +12 V (the conventional non-operation region), the common-mode voltage of the first compressed signal and the second compressed signal is Clamped to + 4V. Therefore, the input signal of the comparator CP1 does not exceed the in-phase input range. As a result, it is possible to receive a differential signal in an input range (−5 V to +17 V) wider than a conventional input range (for example, −2 V to +7 V, −5 V to +12 V).

  In this case, the receiving circuit device 51 according to the present embodiment can perform recessive / dominant determination (detection) in the same manner as the receiving circuit device 41 according to the fourth embodiment. In addition, when the potential of the differential signal is in the range of −5V to + 12V, the recessive / reverse signal is generated based on the first compressed signal and the second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. A dominant decision is made. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the above embodiments.

(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 61 of this embodiment shown in FIG. 13 is different from the receiving circuit device 41 of the fourth embodiment shown in FIG. Instead, the difference is that a detection circuit 62 is provided.

  The detection circuit 62 further includes an AND circuit 63, an input level shift comparator 64, and resistors R61 and R62 in addition to the configuration of the detection circuit 5. In the present embodiment, the comparator CP1 corresponds to the first comparator, and the input level shift comparator 64 corresponds to the second comparator. The output terminal of the comparator CP1 is pulled up to the power supply voltage Vcc via the resistor R61 and is connected to one input terminal of the AND circuit 63. When an input outside the in-phase input range is given to the comparator CP1, its output becomes OPEN (non-operating state). However, according to the above configuration, when the comparator CP1 is in a non-operating state, its output signal is fixed at the H level. Note that when the comparator CP1 is configured such that the output is fixed to the H level when an input outside the common-mode input range is applied, the pull-up by the resistor R61 may be omitted.

  The input level shift comparator 64 inputs a differential signal transmitted through the bus communication lines BP and BM, and determines the difference voltage between the differential signals by level-shifting the input signal by a predetermined level. The input level shift comparator 64 includes a comparator CP61, a bias terminal P5, resistors R63p, R63m, R64p, R64m, R65p, R65m and current sources 65p, 65m.

  A bias voltage Vbias (0 V in this embodiment) is applied to the bias terminal P5. Resistors R63p and R64p are connected in series in this order between the first input terminal P1 and the bias terminal P5. The resistors R63p and R64p are compression ladder resistors that compress the voltage between the first input terminal P1 and the bias terminal P5 with a predetermined compression gain. Resistors R63m and R64m are connected in series in this order between the second input terminal P2 and the bias terminal P5. The resistors R63m and R64m are compression ladder resistors that compress the voltage between the second input terminal P2 and the bias terminal P5 with a predetermined compression gain. The resistors R63p and R63m have the same resistance value R63, and the resistors R64p and R64m have the same resistance value R64. The compression gain is determined according to the resistance values R63 and R64.

The resistance values R63 and R64 of the resistors R63p to R64m are set so as to satisfy the following two conditions.
(1) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is −5V, the interconnection node N61p of the resistors R63p and R64p (interconnection node N61m of the resistors R63m and R64m) The voltage becomes -2V.
(2) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is −12V, the voltage of the node N61p (node N61m) becomes −4.8V.

  The node N61p is connected to the non-inverting input terminal of the comparator CP61 through the resistor R65p. The node N61m is connected to the inverting input terminal of the comparator CP61 via the resistor R65m. The interconnection node N62 of the resistors R64p and R64m is connected to the bias terminal P5. The current source 65p is connected between the power supply terminal to which the power supply voltage Vcc is supplied and the terminal on the comparator CP61 side of the resistor R65p. Thereby, the current source 65p functions as a constant current source for flowing a constant current Ip from the power supply terminal toward the resistor R65p. The current source 65m is connected between the power supply terminal and the terminal on the comparator CP61 side of the resistor R65m. Thereby, the current source 65m functions as a constant current source for flowing a constant current Im from the power supply terminal toward the resistor R65m.

With this configuration, the voltage V (+) obtained by shifting the voltage of the node N61p to the high potential side by a predetermined level is applied to the non-inverting input terminal of the comparator CP61. The voltage V (−) obtained by shifting the voltage of the node N61m to the high potential side by a predetermined level is applied to the inverting input terminal of the comparator CP61. In this case, the voltage BP1 at the node N61p and the voltage BM1 at the node N61m are expressed by the following equations (4) and (5), respectively.
BP1 = BP. (R64 / (R63 + R64)) (4)
BM1 = BM · (R64 / (R63 + R64)) (5)

The voltage V (+) and the voltage V (−) are expressed by the following formulas (6) and (7), respectively. However, the parallel combined resistance of the resistors R63p and R64p and the parallel combined resistance of the resistors R63m and R64m are represented by “R63 // R64”, and the resistance values of the resistors R65p and R65m are represented by R65p and R65m.
V (+) = BP1 + Ip.R65p + Ip. (R63 // R64) (6)
V (−) = BM1 + Im · R65m + Im · (R63 // R64) (7)

  As shown in the above equations (4) to (7), the level shift setting (setting of the predetermined level to be shifted) can be arbitrarily set by setting the values of Ip, Im, R65p, R65m, and the like. is there. In the present embodiment, when the voltages BP and BM are in the range of -5V to -12V (when the voltages BP1 and BM1 are in the range of -2V to -4.8V), the input voltage of the comparator CP61 is + 1V to + 4V. The level shift setting is performed so as to be in the range (in-phase input range).

  The comparator CP61 operates in response to the supply of a single positive power supply voltage Vcc, similarly to the comparator CP1. Therefore, the common-mode input range of the comparator CP61 is the same as that of the comparator CP1. The output terminal of the comparator CP61 is pulled up to the power supply voltage Vcc via the resistor R62 and is connected to the other input terminal of the AND circuit 63. When an input outside the in-phase input range is given to the comparator CP61, its output becomes OPEN (non-operating state). However, according to the above configuration, when the comparator CP61 is in a non-operating state, its output signal is fixed at the H level. Note that when the comparator CP61 is configured such that the output is fixed to the H level when an input outside the in-phase input range is given, the pull-up by the resistor R62 may be omitted. The output terminal of the AND circuit 63 is connected to the output terminal P4.

In the input level shift comparator 64 (comparator CP61), the threshold value VTH (offset setting) used to determine the differential voltage of the differential signal can be set by the values of the currents Ip and Im and the values of the resistors R65p and R65m. In this case, when BP = BM (BP1 = BM1), the offset may be set so that V (+) + VTH = V (−). Therefore, for example, if the values of the currents Ip and Im are equal to each other, the threshold value VTH can be set by setting the values of the resistors R65p and R65m so as to satisfy the following equation (8).
I · R65p + VTH = I · R65m (8)

According to such a configuration, the following operations and effects can be obtained.
When the potentials of the differential signals on the bus communication lines BP and BM are in the range of −5V to + 12V, the voltages at the nodes N1p and N1m are both in the range of + 1V to + 4V as shown in FIG. Therefore, the comparator CP1 operates normally and the output signal is given to one input terminal of the AND circuit 63. At this time, as shown in FIG. 15, the input (V (+), V (−)) of the comparator CP61 exceeds + 4V. For this reason, the comparator CP61 is deactivated, and its output signal is fixed at the H level. Accordingly, the output signal of the AND circuit 63 is equivalent to the output signal of the comparator CP1, and the output signal is output from the output terminal P4 as a differential signal reception signal.

  On the other hand, when the potentials of the differential signals of the bus communication lines BP and BM are in the range of −5V to −12V, the voltages at the nodes N1p and N1m are both below + 1V, as shown in FIG. For this reason, the comparator CP1 is inactivated, and its output signal is fixed at the H level. At this time, as shown in FIG. 15, the inputs (V (+), V (−)) of the comparator CP61 are in the range of + 1V to + 4V. Therefore, the comparator CP61 operates normally, and the output signal is given to the other input terminal of the AND circuit 63. Accordingly, the output signal of the AND circuit 63 is equivalent to the output signal of the comparator CP61, and the output signal is output from the output terminal P4 as a differential signal reception signal.

  Thus, in the receiving circuit device 61, when the potential of the differential signal is in the range of −5V to + 12V, the output of the comparator CP1 is output as the received signal of the differential signal, and the potential of the differential signal is Is in the range of −5V to −12V, the output of the comparator CP61 is output as a differential signal. As a result, as shown in FIGS. 14 and 15, it is possible to receive a differential signal in an input range (−12 V to +12 V) wider than a conventional input range (for example, −2 V to +7 V, −5 V to +12 V). Become. In addition, when the potential of the differential signal is in the range of −5 V to +12 V, the recessive / dominant is based on the first compressed signal and the second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. Is determined. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the above embodiments.

(Seventh embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to FIGS.
The receiving circuit device 71 of the present embodiment shown in FIG. 16 differs from the receiving circuit device 61 of the seventh embodiment shown in FIG. 13 in that a detecting circuit 72 is provided instead of the detecting circuit 62. The detection circuit 72 is different from the detection circuit 62 in setting the resistance values of the resistors R63p to R64m and the connection positions and functions of the current sources 65p and 65m.

The resistance values R63 and R64 of the resistors R63p to R64m are set so as to satisfy the following two conditions.
(1) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is + 12V, the voltage of the node N61p (node N61m) of the resistors R63p and R64p becomes + 6V.
(2) When the voltage of the differential signal applied to the first input terminal P1 (second input terminal P2) is + 17V, the voltage of the node N61p (node N61m) becomes + 9V.

  The current source 65p is connected between a terminal of the resistor R65p on the comparator CP61 side and a ground terminal to which a ground potential (0 V) is applied. Thereby, the current source 65p functions as a constant current source for flowing a constant current Ip from the resistor R65p toward the ground terminal. The current source 65m is connected between the terminal on the comparator CP61 side of the resistor R65m and the ground terminal. Thereby, the current source 65m functions as a constant current source for flowing a constant current Im from the resistor R65m toward the ground terminal.

With such a configuration, the voltage V (+) obtained by shifting the voltage of the node N61p to the low potential side by a predetermined level is applied to the non-inverting input terminal of the comparator CP61. Further, the voltage V (−) obtained by shifting the voltage of the node N61m to the low potential side by a predetermined level is applied to the inverting input terminal of the comparator CP61. In this case, the voltage V + and the voltage V− are expressed by the following equations (9) and (10), respectively.
V (+) = BP1-Ip.R65p-Ip. (R63 // R64) (9)
V (-) = BM1-Im.R65m-Im. (R63 // R64) (10)

  As shown in the above formulas (9) and (10), the level shift setting can be arbitrarily set by setting the values of Ip and Im, the values of R65p and R65m, and the like. In this embodiment, when the voltages BP and BM are in the range of + 12V to + 18V (when the voltages BP1 and BM1 are in the range of + 6V to + 9V), the input voltage of the comparator CP61 is in the range of + 1V to + 4V (in-phase input range). ) So that the level shift is set.

In the input level shift comparator 64 (comparator CP61), the threshold value VTH (offset setting) used to determine the differential voltage of the differential signal can be set by the values of the currents Ip and Im and the values of the resistors R65p and R65m. In this case, when BP = BM (BP1 = BM1), the offset may be set so that V (+) + VTH = V (−). Therefore, for example, if the values of the currents Ip and Im are equal to each other, the threshold value VTH can be set by setting the values of the resistors R65p and R65m so that the following equation (11) is satisfied.
I · R65p = I · R65m + VTH (11)

According to such a configuration, the following operations and effects can be obtained.
When the potentials of the differential signals of the bus communication lines BP and BM are in the range of −5V to + 12V, the voltages at the nodes N1p and N1m are both in the range of + 1V to + 4V as shown in FIG. Therefore, the comparator CP1 operates normally and the output signal is given to one input terminal of the AND circuit 63. At this time, as shown in FIG. 18, the inputs (V (+), V (−)) of the comparator CP61 are lower than + 1V. For this reason, the comparator CP61 is deactivated, and its output signal is fixed at the H level. Accordingly, the output signal of the AND circuit 63 is equivalent to the output signal of the comparator CP1, and the output signal is output from the output terminal P4 as a differential signal reception signal.

  On the other hand, when the potentials of the differential signals of the bus communication lines BP and BM are in the range of + 12V to + 17V, the voltages at the nodes N1p and N1m are both higher than + 4V as shown in FIG. For this reason, the comparator CP1 is inactivated, and its output signal is fixed at the H level. At this time, as shown in FIG. 18, the input (V (+), V (−)) of the comparator CP61 is in the range of + 1V to + 4V. Therefore, the comparator CP61 operates normally, and the output signal is given to the other input terminal of the AND circuit 63. Accordingly, the output signal of the AND circuit 63 is equivalent to the output signal of the comparator CP61, and the output signal is output from the output terminal P4 as a differential signal reception signal.

  Thus, in the receiving circuit device 61, when the potential of the differential signal is in the range of −5V to + 12V, the output of the comparator CP1 is output as the received signal of the differential signal, and the potential of the differential signal is Is in the range of + 12V to + 17V, the output of the comparator CP61 is output as a differential signal. As a result, as shown in FIGS. 17 and 18, it is possible to receive a differential signal in an input range (−5 V to +17 V) wider than a conventional input range (for example, −2 V to +7 V, −5 V to +12 V). Become. In addition, when the potential of the differential signal is in the range of −5 V to +12 V, the recessive / dominant is based on the first compressed signal and the second compressed signal compressed by the compression gain (first set value) equivalent to the conventional one. Is determined. That is, since differential signals are received in the same manner as in the past, for example, characteristics similar to those in the past can be obtained with respect to characteristics such as threshold variation. Therefore, the present embodiment can provide the same effects as those of the above embodiments.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The input range optimizing means 6, 22, 32 (gain setting means) is configured to switch the compression gain of the first compressed signal and the second compressed signal in two stages, but the number of stages of switching is three or more (multistage) ), Or a configuration in which the compression gain is switched steplessly (linearly).

  The relationship (correlation) between the bus voltage (the voltages of the bus communication lines BP and BM) and the common-mode input voltage of the comparator CP1 in the receiving circuit device of each of the above embodiments is shown in FIGS. 2, 4, 6, 9, and 12. 14 and 17, and may be changed as appropriate according to the specifications of the device to be applied. Similarly, the relationship between the bus voltage and the common-mode input voltage of the input level shift comparator 64 may be changed as appropriate.

The receiving circuit device 61 shown in FIG. 13 and the receiving circuit device 71 shown in FIG. 16 can be modified as a receiving circuit device 81 shown in FIG. 19 and a receiving circuit device 91 shown in FIG. That is, as shown in FIG. 19 (FIG. 20), an offset voltage source 82 (92) is added between the resistor R65m and the inverting input terminal of the comparator CP61. In this case, the values of the currents Ip and Im are set to be the same, and the values of the resistors R65p and R65m are set to be the same. Thereby, in the input level shift comparator 64, the threshold value used to determine the differential voltage of the differential signal is determined by the offset voltage VTH generated by the offset voltage source 82 (92).
The present invention is not limited to a receiving circuit device used for CAN communication, but can be applied to any receiving circuit device that receives a differential signal transmitted through a pair of signal lines.

  In the drawing, 1, 21, 31, 41, 51, 61, 71, 81, 91 are receiving circuit devices, 4, 42 are compression circuits, 5, 62, 72 are detection circuits, and 6, 22, 32 are optimum input ranges. 43, 52 are input range optimizing means, 44p, 44m, 53p, 53m are clamp circuits (clamp means), 64 is an input level shift comparator (second comparator), and BP, BM are buses. Communication line (signal line), CP1 is a comparator (first comparator), P1 is a first input terminal, P2 is a second input terminal, and P3 is a bias terminal.

Claims (5)

A receiving circuit device (1, 21, 31, 41, 51) for receiving a differential signal transmitted through a pair of signal lines,
A first compressed signal obtained by compressing a voltage between a first input terminal (P1) to which one of the differential signals is applied and a bias terminal (P3) to which a bias voltage is applied with a predetermined compression gain, and the other differential A compression circuit (4, 42) for outputting a second compressed signal obtained by compressing a voltage between a second input terminal (P2) to which a signal is applied and the bias terminal (P3) with the compression gain;
A comparator (CP1) that receives the first compressed signal and the second compressed signal and discriminates a differential voltage between the differential signals, and outputs an output of the comparator (CP1) as a reception signal of the differential signal. A detection circuit (5);
Input Range optimization means for optimizing such potential is within the common mode input range of the comparator of the first compressed signal and said second compressed signal when the potential of the differential signal is out of Tokoro TeiIri force range ( 6, 22, 32, 43, 52),
A receiving circuit device comprising: The input range optimization means (6, 22, 32)
When the potential of the differential signal is within the predetermined input range, the compression gain is set to the first set value, and when the potential of the differential signal is out of the predetermined input range, The receiving circuit device according to claim 1, further comprising gain setting means for setting a compression gain to a second setting value higher than the first setting value. The input range optimizing means (43)
Clamping means for clamping the potential of the first compressed signal and the second compressed signal to a value that does not fall below the in-phase input range of the comparator (CP1) when the potential of the differential signal is below the predetermined input range. The receiving circuit device according to claim 1, comprising: (44p, 44m). The input range optimizing means (52)
Clamping means for clamping the potential of the first compressed signal and the second compressed signal to a value not exceeding the in-phase input range of the comparator (CP1) when the potential of the differential signal exceeds the predetermined input range. The receiving circuit device according to claim 1, comprising: (53p, 53m). A receiving circuit device (61, 71, 81, 91) for receiving a differential signal transmitted through a pair of signal lines,
A first compressed signal obtained by compressing a voltage between a first input terminal (P1) to which one of the differential signals is applied and a bias terminal (P3) to which a bias voltage is applied with a predetermined compression gain, and the other differential A compression circuit (42) for outputting a second compressed signal obtained by compressing a voltage between a second input terminal (P2) to which a signal is applied and the bias terminal (P3) with the compression gain;
A first comparator (CP1) that inputs the first compressed signal and the second compressed signal to determine a differential voltage of the differential signal, and inputs the differential signal and shifts the input signal by a predetermined level. A second comparator (64) for determining a differential voltage of the differential signal, and any one of the outputs of the first comparator (CP1) and the second comparator (64) is a reception signal of the differential signal. Detection circuit (62, 72) for outputting as
With
The detection circuit (62, 72)
Wherein in a case the potential of the differential signal is within Tokoro TeiIri force range to an output of said first comparator (CP1) as a received signal of the differential signals,
When the potential of the differential signal deviates from the predetermined input range, an output of the second comparator (64) is output as a reception signal of the differential signal.

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