JP5127244B2 - Display device and electronic apparatus including the display device - Google Patents

Description

  The present invention relates to a display device. In particular, the present invention relates to a display device including an inspection circuit that simplifies inspection of a display device, improves reliability, and improves shipping yield. The present invention also relates to a display device including an inspection circuit, and to a correction circuit for correcting a signal input to a display device having a defect detected by the inspection circuit.

  In recent years, the demand for thin displays has rapidly expanded mainly for TVs, PC monitors, mobile terminals, and the like, and further development is being promoted. Examples of the thin display include a display device using a liquid crystal element (Liquid Crystal Display; LCD) and a display device including a light emitting element.

  As a display device using a light-emitting element and a liquid crystal element, an active matrix display device shown in FIG. 20 can be given.

  The display device illustrated in FIG. 20 includes a connection terminal portion 2005 in which a gate signal line driver circuit 2001, a source signal line driver circuit 2002, a pixel portion 2003, and a plurality of connection terminals 2004 are formed over a substrate 2000. A gate line 2006 is connected to the gate signal line driver circuit 2001, and a source line 2007 is connected to the source signal line driver circuit 2002. A pixel 2008 in the pixel portion 2003 is connected to a gate line 2006, a source line 2007, and a power supply line 2009. The pixel 2008 is provided with a transistor for writing a signal from the source line 2007 to a light-emitting element or a liquid crystal element provided in the pixel by the signal of the gate line 2006. Terminals are connected to a gate line 2006 and a source line 2007. Further, the connection terminal portion 2005 is connected to an FPC (Flexible Printed Circuit: not shown) for inputting an external signal. The substrate 2000 is completed as a display module by attaching a counter substrate 2010 for sealing a light emitting element or a liquid crystal element provided in the pixel 2008.

  In FIG. 20, when display is performed in the pixel portion, if the low potential of the gate line 2006 is grounded, the low potential of the source line 2007 is higher than the low potential of the gate line 2006 and the source line 2007 has a low potential. The difference between the low potential and the low potential of the gate line 2006 is preferably a potential equal to or higher than the threshold voltage (Vth) of the transistor connected to the gate line 2006 for writing. The low potential of the source line 2007 is lower than the low potential of the gate line 2006, and the difference between the low potential of the source line 2007 and the low potential of the gate line 2006 is equal to the threshold voltage (Vth) of the transistor for writing. If the value is less than the value, current tends to leak from the transistor for writing, and the display device cannot perform normal display.

  Note that the high potential and the low potential of the source line and the gate line respectively indicate a case where the potential is relatively high and a case where the potential is low. The high potential is a value at which the transistor is turned on and the low potential is What is necessary is just to determine so that it may have a predetermined potential difference with a High electric potential and a Low electric potential so that it may become a value which turns off a transistor.

  In the display device using the liquid crystal element or the light-emitting element in FIG. 20, the pixel is driven by the potential relationship of signals from the gate signal line driver circuit and the source signal line driver circuit. Therefore, in the manufacturing process and the product shipping process, it is possible to detect a defect in the display device such that the above-described potential is not held by inspecting the potential of the signal from the gate signal line driver circuit and the source signal line driver circuit. Is desirable.

Therefore, in a display device using a light-emitting element or a liquid crystal element, in order to inspect a defect of the display device, a sample of modules once completed as shown in FIG. 21A is used as a sample as shown in FIG. The counter substrate is peeled off and the inspection is performed using the probe 2101 by the measuring device, or the inspection is performed using the probe by the measuring device before being bonded to the counter substrate (see, for example, Patent Document 1).
JP 2002-221547 A

  In a conventional display device using a liquid crystal element or a light emitting element, the gate signal line driver circuit and the source signal line driver circuit to the pixels are located in the sealing region of the display device. For this reason, it is extremely difficult to perform inspection by peeling off the counter substrate of all display modules after the manufacturing process and inspecting the potential relationship after the counter substrate bonding process, and finding defects between the counter substrate bonding process and shipment. Was not done enough.

  In addition, in the method described in Patent Document 1, if a defect is found after the manufacturing process, the defect cannot be repaired, and the shipping yield may be deteriorated. Had occurred.

  In some cases, the source line and the gate line are simply extended to the connection terminal portion by wiring and bonded to the counter substrate, and then the inspection is performed by measuring the potential of the connection terminal portion. However, it is not sufficient as an inspection because it includes elements such as a voltage drop and a delay in the parasitic capacitance caused by the wiring.

  Accordingly, the present invention provides a display device having a highly accurate inspection circuit in a process after bonding to a counter substrate and a pre-shipment inspection, and a display device including a correction circuit inside the display device when a defect occurs. The task is to do.

  In order to solve the above-described problems, the present invention is characterized in that an inspection circuit for determining a defect in the pixel portion is provided. A signal output from the inspection circuit is output to the connection terminal through the wiring. Further, the invention is characterized in that a correction circuit for correcting a defect of the pixel portion is provided by a signal output from the inspection circuit. Hereinafter, a specific configuration of the present invention will be described.

  One embodiment of the display device of the present invention includes a gate line, a source line, a pixel portion driven by the potential of the gate line and the source line, a first wiring arranged in parallel with the gate line, and a parallel to the source line. And a test circuit connected to the first wiring and the second wiring, and the test circuit uses the potential of the first wiring and the second wiring to generate a pixel portion. The display device is characterized in that it outputs a signal for discriminating defects.

  Another display device of the present invention includes a gate line, a source line, a pixel portion driven by the potential of the gate line and the source line, a first wiring arranged in parallel with the gate line, A second wiring arranged in parallel with the source line, a first wiring and a test circuit connected to the second wiring, a first connection terminal and a second connection terminal connected to the test circuit, The inspection circuit includes a first circuit connected to the first wiring and the second wiring, a second circuit connected to the second wiring, and the first wiring and the second circuit. And the first circuit compares the potential of the first wiring with the potential of the second wiring, and the potential of the second wiring is equal to that of the first wiring. When the potential falls below the first potential, the first potential is output to the first connection terminal, and the second circuit uses the second wiring as the reference Is input to the third circuit, and the third circuit compares the potential of the first wiring with the second potential, and the second potential is In the display device, the third potential is output to the second connection terminal when the potential is lower than the potential.

  Another display device of the present invention includes a gate line, a source line, a pixel portion driven by a potential of the gate line and the source line, a first wiring arranged in parallel with the gate line, and a source A second wiring arranged in parallel with the line, a test circuit connected to the first wiring and the second wiring, a correction circuit connected to the test circuit, and a first connection connected to the test circuit A test circuit, a first circuit connected to the first wiring and the second wiring, a second circuit connected to the second wiring, and a second circuit connected to the second wiring; And a third circuit connected to the first wiring and the second circuit, the first circuit compares the potential of the first wiring with the potential of the second wiring, and the second circuit When the potential of the wiring is lower than the potential of the first wiring, the first potential is output to the first connection terminal, and the second time Inputs a second potential obtained by subtracting a reference potential from the potential of the second wiring to the third circuit, and the third circuit compares the potential of the first wiring with the second potential. When the second potential is lower than the potential of the first wiring, the third potential is output to the second connection terminal, and the correction circuit outputs the third potential to the second connection terminal. In addition, in the display device, the potential output to the first connection terminal and the second connection terminal is corrected by making the potential of the second wiring higher than the potential of the first wiring. is there.

  Another display device of the present invention includes a gate line, a source line, a driver circuit for supplying a signal to the source line, a pixel portion driven by a potential of the gate line and the source line, a gate line and a source A switching circuit connected to the line, and an inspection circuit. The switching circuit connects the gate line and the source line to the inspection circuit when a signal for controlling writing of the source line is not supplied to the driver circuit. The inspection circuit is a display device that outputs a signal for determining a defect of the pixel portion based on the inputted potential of the gate line and the potential of the source line.

  Another display device of the present invention includes a gate line, a source line, a driver circuit for supplying a signal to the source line, a pixel portion driven by a potential of the gate line and the source line, a gate line and a source A switching circuit connected to the line; an inspection circuit; and a first connection terminal and a second connection terminal connected to the inspection circuit, wherein the inspection circuit is connected to the gate line and the source line. 1 circuit, a second circuit connected to the source line, and a third circuit connected to the gate line and the second circuit, and the switching circuit controls the writing of the source line Is not supplied to the driver circuit, the gate line and the source line are connected to the inspection circuit, and the first circuit is input from the potential of the input gate line and the source line. The first circuit outputs the first potential to the first connection terminal when the input source line potential is lower than the gate line potential, and the second circuit outputs the input source line potential. The second potential obtained by subtracting the reference potential is input to the third circuit, and the third circuit compares the input potential of the gate line with the second potential, and the second potential is the gate potential. In the display device, the third potential is output to the second connection terminal when the potential is lower than the potential of the line.

Another display device of the present invention includes a gate line, a source line, a driver circuit for supplying a signal to the source line, a pixel portion driven by a potential of the gate line and the source line, a gate line and a source A switching circuit connected to the line, an inspection circuit, a first connection terminal and a second connection terminal connected to the inspection circuit, and a correction circuit connected to the inspection circuit and the second connection terminal. The inspection circuit includes a first circuit connected to the gate line and the source line, a second circuit connected to the source line, a third circuit connected to the gate line and the second circuit, And the switching circuit connects the gate line and the source line to the inspection circuit when the signal for controlling writing to the source line is not supplied to the driver circuit, and the first circuit receives the input signal. The potential of the gate line and the potential of the source line are compared, and when the potential of the source line is lower than the potential of the gate line, the first potential is output to the first connection terminal. A second potential obtained by subtracting a reference potential from the source line potential is input to the third circuit, and the third circuit compares the input gate line potential with the second potential; When the second potential is lower than the potential of the gate line, the third potential is output to the second connection terminal, and the correction circuit generates a source when the third potential is output to the second connection terminal. The display device is characterized in that the potential output to the first connection terminal and the second connection terminal is corrected by making the potential of the line higher than the potential of the gate line.

  In the present invention, the first connection terminal and the second connection terminal may be provided outside a region sealed by the substrate on which the pixel portion is formed and the counter substrate.

  In the present invention, the pixel portion includes a transistor connected to the gate line and the source line, and the transistor is selected by a signal input to the gate line and a signal from the source line is written. Good.

  In the present invention, the transistor may be an N-channel transistor.

  Another aspect of the present invention is an electronic device including the display device described in this specification in a display portion.

  Note that the display device of the present invention includes a liquid crystal display device, a DMD (Digital Micromirror Device), and a PDP (Plasma Display Panel) in addition to a display device including a light emitting element typified by an organic light emitting element (OLED) in each pixel. , A display device that performs display by signals input to a FED (Field Emission Display) gate line and a source line is included in its category.

  In this specification, a light-emitting element includes an element whose luminance is controlled by current or voltage in its category. Specifically, an OLED (Organic Light Emitting Diode), an inorganic EL (Electro Luminescence), a MIM type electron source element (electron emitting element) used in FED (Field Emission Display), and the like are included.

  The display device includes a panel in which the light-emitting element is sealed, and a module in which an IC including a controller is mounted on the panel. The display device includes a panel in which the liquid crystal element is sealed and a module in which an IC including a controller is mounted on the panel.

  Note that as a transistor used in the display device of the present invention, a polycrystalline semiconductor, a microcrystalline semiconductor (including a semi-amorphous semiconductor), or a thin film transistor using an amorphous semiconductor can be used; however, the transistor used in the display device of the present invention Is not limited to a thin film transistor. A transistor formed using single crystal silicon or a transistor using SOI may be used. In addition, a transistor using an organic semiconductor, a transistor using carbon nanotubes, or a transistor using zinc oxide may be used. Further, the transistor provided in the pixel of the display device of the present invention may have a single gate structure, a double gate structure, or a multi-gate structure having three or more gates.

  In accordance with the present invention, by adopting a configuration including an inspection circuit, inspection of a display device that can only be performed by peeling off the counter substrate after bonding or bonding to the counter substrate is performed in any step. be able to. Therefore, even in the process after bonding to the counter substrate, a display defect of the display device due to the potential relationship between the gate line and the source line can be detected.

  Further, the present invention has a configuration including a correction circuit in addition to the configuration including the inspection circuit. Therefore, the display device of the present invention can correct the display defect of the display device due to the potential relationship between the gate line and the source line by the display device alone based on the signal for determining the defect output from the inspection circuit. Become. Therefore, the inspection and correction of the display device can be performed reliably, and the shipping yield can be improved.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.
(Embodiment 1)

  FIG. 1 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. Note that a display device in the present invention refers to a device having a display element (a liquid crystal element, a light-emitting element, or the like). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, the display device may include one provided with a flexible printed circuit (FPC) or a printed wiring board (PWB). A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

  FIG. 1 shows the basic configuration of the present invention. The display device illustrated in FIG. 1 includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, a connection terminal portion 105 in which a plurality of connection terminals 104 are formed, and an inspection circuit 106 over a substrate 100. Have. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. A pixel 109 in the pixel portion 103 is connected to the gate line 107 and the source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light-emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. Each terminal of the transistor in each pixel is The gate line 107 and the source line 108 are connected. The connection terminal unit 105 is connected to an FPC (Flexible Printed Circuit: not shown) for inputting an external signal. The substrate 100 is completed as a display module by attaching a counter substrate 110 for sealing a light emitting element or a liquid crystal element provided in the pixel 109.

  The inspection circuit 106 includes a dummy gate line (also referred to as a first wiring) 117 formed in a direction parallel to the gate line and a dummy source line (also referred to as a first wiring) 117 formed in a direction parallel to the source line. 118 (also referred to as a second wiring) is provided on the opposite side of the pixel portion 103 and the portion connected to the source signal line driver circuit 102, and connected to the dummy gate line 117 and the dummy source line 118. Yes. In this embodiment mode, the dummy gate line 117 is a dummy line in which one of the gate lines is connected to a pixel different from a pixel contributing to display in the display device, and is formed at the same time as the gate line 107. The same signal as 107 is supplied. The dummy source line 118 is a dummy line in which one of the source lines 108 is connected to a pixel different from a pixel contributing to display in the display device, and is formed at the same time as the source line 108 and is similar to the source line 108. A signal is supplied. In this embodiment mode, a pixel that is provided on the same line as another pixel and does not contribute to display is referred to as a dummy pixel. The aforementioned dummy pixel, dummy gate line 117 and dummy source line 118 are provided so as not to affect display by being connected to the inspection circuit 106. The dummy pixels can be inspected by shielding the display surface without affecting other pixel displays. Note that the same signal as that supplied to the gate line is supplied at the same time as the gate line 107, that is, the same signal is used. In addition, the same signal as that of the source line is supplied, that is, the signal is formed at the same time as the source line 108, that is, the same material is used.

  In the inspection circuit 106, the potential relationship between the gate line 107 and the source line 108 in the pixel portion is such that the potential of the source line 108 is lower than the potential of the gate line 107 and the low potential of the source line 108 and the low potential of the gate line 107. A failure caused when the difference from the potential is less than the threshold voltage (Vth) of the transistor for writing a signal from the source line 108 is detected. Specifically, the inspection circuit 106 compares the potential of the dummy gate line 117 with the potential of the dummy source line 118, and when the potential of the dummy gate line 117 falls below the potential of the dummy source line 118, High. A first circuit 111 (also referred to as a first comparison circuit) that outputs a potential, and a second circuit 112 (also referred to as a subtraction circuit) that subtracts a reference potential from the potential of the dummy source line 118 and outputs the result. A third circuit 113 (also referred to as a second comparison circuit) that compares the potential of the dummy gate line 117 with the output of the second circuit 112 and outputs the same is provided. The inspection circuit 106 includes a connection terminal 114 for outputting a result of comparison in the first circuit 111, a connection terminal 115 to which a reference potential is input to the second circuit 112, The connection terminals 116 for outputting signals from the third circuit 113 are connected from the connection terminal portion 105 to the inspection circuit 106, respectively. Note that in this specification, the reference potential input to the second circuit 112 is substantially the same potential as the threshold voltage (Vth) of a transistor for writing a signal from a source line provided in a pixel. It is desirable that the voltage be about 0.1 to 2.0V.

  Specific examples of the pixel configuration of the pixel 109 are shown in FIGS. In this embodiment mode, a typical pixel structure using a light emitting element in FIG. 2 and a liquid crystal element in FIG. 3 as a display medium will be described.

  In FIG. 2, a light-emitting element is used as a display medium, an N-channel transistor is used as a first transistor 201 (also referred to as a writing transistor) that performs signal writing from a source line, and a second transistor 202 that drives the light-emitting element. A pixel structure in the case where a P-channel transistor is used as a driving transistor is also described.

  In FIG. 2, when the gate line 107 becomes a high potential, the first transistor 201 is turned on, the potential of the source line 108 is held in the holding capacitor 203 and reflected in the potential of the node Ng. When the gate line 107 is at a low potential, the first transistor 201 is turned off, and the potential held in the storage capacitor 203 is reflected in the potential of the node Ng regardless of the potential of the source line 108. When the potential of the node Ng is a high potential, the potential of the node Nd is a low potential because the second transistor 202 is off. Further, the potential of the node Nd becomes a high potential because the second transistor 202 is on when the potential of the node Ng is the low potential, so that a current flows from the power supply line 204. The potential of the node Nd flows through the light emitting element 205 to the counter electrode 206.

  Note that in this specification, a transistor is on refers to a state in which the voltage between the gate and the source of the transistor exceeds the threshold voltage and current flows between the source and the drain, and the transistor is turned off. In this case, the voltage between the gate and the source of the transistor is lower than the threshold voltage, and no current flows between the source and the drain.

  In this specification, one pixel means one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels. The color elements are not limited to three colors, and three or more colors may be used, for example, RGBW (W is white). As another example, in the case where brightness is controlled using a plurality of areas for one color element, one area corresponds to one pixel. Therefore, as an example, when performing area gradation, there are a plurality of areas for controlling the brightness for each color element, and the gradation is expressed as a whole. One portion is defined as one pixel. Therefore, in that case, one color element is composed of a plurality of pixels. In that case, the size of the region contributing to the display may be different depending on the pixel. Further, in a plurality of brightness control areas for one color element, that is, in a plurality of pixels constituting one color element, a signal supplied to each is slightly different to widen the viewing angle. You may do it. Note that the description of one pixel (for three colors) is a case where three pixels of R, G, and B are considered as one pixel. In the case of describing one pixel (for one color), it is assumed that when there are a plurality of pixels for one color element, they are collectively considered as one pixel.

  FIG. 3 shows a pixel structure in the case where a liquid crystal element is used as a display medium and a transistor 301 for writing a source line signal is an n-channel transistor.

  In FIG. 3, when the gate line 107 becomes a high potential, the transistor 301 is turned on, and the potential of the source line 108 is held in the holding capacitor 302 and reflected in the potential of the node Ne. When the gate line 107 is at a low potential, the transistor 301 is turned off, and the potential held in the storage capacitor 302 is reflected in the potential of the node Ne regardless of the potential of the source line 108. The liquid crystal element 303 is driven by the potential of the node Ne and the potential of the counter electrode 304.

  Next, FIG. 4 shows a display medium according to the present invention in which a light emitting element using an organic material for a light emitting layer is adopted for each pixel. Each pixel has a structure including the first transistor and the second transistor, the storage capacitor, and the light-emitting element which are illustrated in FIG. In FIG. 4, connections in the first circuit 111, the second circuit 112, and the third circuit 113 in the inspection circuit 106 described in FIG. 1 will be described. 5, 6, and 7, circuit configurations of the first circuit 111, the second circuit 112, and the third circuit 113 will be described.

  FIG. 4 shows the basic configuration of the present invention shown in FIG. 1 in more detail. In FIG. 4, the same parts as those in FIG. 4 is a connection in which a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, and a plurality of connection terminals (not shown) are formed on a substrate (not shown). A terminal portion (not shown) and an inspection circuit 106 are provided. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. Note that a write control signal SWE is input from the connection terminal 401 to the source signal line driver circuit. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The substrate is completed as a display module by attaching a counter substrate (not shown) for sealing the light emitting element or the liquid crystal element provided in the pixel 109.

  Further, the inspection circuit 106 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion in which the potential of the source line 108 is lower than the potential of the gate line 107 and less than the threshold voltage (Vth) of the first transistor 201. Detects a defect caused by Specifically, the inspection circuit compares the potential of the dummy gate line 117 with the potential of the dummy source line 118, and sets the High potential when the potential of the dummy gate line 117 is lower than the potential of the dummy source line 118. A first circuit 111 (also referred to as a first comparison circuit) to output, a second potential to be output by subtracting a reference potential from the potential of the dummy source line 118 (also referred to as a subtraction circuit), and a dummy A third circuit 113 (also referred to as a second comparison circuit) that compares the potential of the gate line 117 with the output of the second circuit 112 and outputs the same is provided. The inspection circuit 106 includes a connection terminal 114 for outputting a result of comparison in the first circuit 111, a connection terminal 115 to which a reference potential is input to the second circuit 112, 3 is connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the circuit 113.

  In the test circuit 106 in FIG. 4, a dummy gate line 117, a dummy source line 118, and a connection terminal 114 are connected to the first circuit 111. In addition, a dummy source line 118, a connection terminal 115 to which a reference potential is input, and a third circuit 113 are connected to the second circuit 112. The third circuit 113 is connected to the second circuit 112, the dummy gate line 117, and a connection terminal 116 for outputting a signal from the third circuit 113. Note that in this specification, the reference potential input to the second circuit 112 is preferably substantially the same potential as the threshold voltage (Vth) of the first transistor 201 provided in the pixel. It is desirable that the voltage be about 0.0V.

  Note that a write control signal SWE (source write enable signal) in FIG. 4 is a signal for selecting writing or erasing of a signal of a source line, and a high potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line.

  Note that in the present invention, the term “connected” includes the case of being electrically connected and the case of being directly connected. Therefore, the configuration disclosed by the present invention includes other than the predetermined connection relationship. For example, a circuit A (hereinafter referred to as a circuit A) is electrically connected to a circuit B (hereinafter referred to as a circuit B) means that the circuit A is electrically connected to the circuit B between the circuit A and the circuit B. Other elements (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, and a diode) that enable easy connection may be arranged. Alternatively, the fact that the circuit A is directly connected to the circuit B may be arranged without interposing another element between the circuit A and the circuit B. Note that the circuit A is connected to the circuit B only when the circuit A is directly connected to the circuit B, and the circuit A is directly connected to the circuit B. When not including the case of being electrically connected, it is described as being directly connected or directly connected.

  Next, the circuit configurations and connections of the first circuit 111, the second circuit 112, and the third circuit 113 will be described with reference to FIGS.

  FIG. 5 shows a block diagram and a circuit diagram of the first circuit 111 in FIGS. In the first circuit 111, a dummy gate line 117 is connected to the non-inverting input terminal of the operational amplifier shown in FIG. 5 and a dummy source line 118 is connected to the inverting input terminal. The potential of the dummy gate line 117 and the dummy source line are connected. It is a comparison circuit that compares the potential of 118. The first circuit 111 can detect whether the potential of the dummy source line 118 is lower than the potential of the dummy gate line 117 with respect to the potential relationship between the dummy gate line 117 and the dummy source line 118. With respect to the potential relationship between the line 107 and the source line 108, it can be detected whether the potential of the source line 108 is lower than the potential of the gate line 107. When the potential of the source line 108 is lower than the potential of the gate line 107, a high potential is output from the output terminal of the operational amplifier to the connection terminal 114. Note that it is preferable to use a power supply having a potential 2 V lower than the low potential of the gate line 107 as the negative power supply used for the operational amplifier in the first circuit 111.

  Next, FIG. 6 shows a block diagram and a circuit diagram of the second circuit 112 in FIGS. The second circuit 112 is composed of a subtracting circuit composed of an operational amplifier and a resistor. In the second circuit 112, the potential of the dummy source line 118 is connected to the non-inverting input terminal of the operational amplifier, and the reference potential input to the connection terminal 115 is connected to the inverting input terminal of the operational amplifier. The second circuit 112 outputs a potential obtained by subtracting the reference potential from the potential of the dummy source line 118 to the third circuit 113. At this time, it is preferable that the resistances of the subtracting circuits in the second circuit 112 are all equal. The reference potential is preferably substantially the same as the threshold voltage (Vth) of the first transistor provided in the pixel, and is preferably about 0.1 to 2.0V.

  Next, FIG. 7 shows a block diagram and a circuit diagram of the third circuit 113 in FIGS. The third circuit 113 is a comparison circuit configured by an operational amplifier, and compares the potential of the output of the second circuit 112 with the potential of the dummy gate line 117. In the third circuit, the output of the second circuit 112 is connected to the inverting input terminal of the operational amplifier, and the potential of the dummy gate line 117 is input to the non-inverting input terminal. Then, the potential of the dummy gate line 117 and the output potential of the second circuit 112 are compared. When the output potential of the second circuit 112 is lower than the potential of the dummy gate line 117, the high potential is output from the output terminal of the operational amplifier. It is output to the connection terminal 116. A potential obtained by subtracting the threshold voltage (Vth) of the first transistor 201 from the potential of the dummy source line 118 can be detected immediately before the potential of the dummy gate line 117 is decreased. Can be detected.

  As a result, a display device in which the inspection circuit 106 and the pixel portion 103 are provided over the same substrate and the inspection circuit and the pixel portion are sealed with the counter substrate 110 in FIG. 1 can be manufactured. In the display device of this embodiment, since the connection terminal 114 is outside the region sealed by the counter substrate, the connection is made from the first circuit 111 that is the output of the inspection circuit 106 even when the display panel is displaying. A signal output to the terminal 114 can be used to detect a defect in the display device using a probe connected to a measuring instrument from the outside of the region sealed on the counter substrate. In addition, since the connection terminal 116 is outside the region sealed with the counter substrate, the potential of the pixel is determined from the potential of the dummy source line 118 output from the third circuit 113 even when the display panel is displaying. A signal obtained by subtracting the threshold voltage of one transistor can be inspected using a probe connected to a measuring instrument from the outside of the region sealed on the counter substrate. Note that the connection terminal 114, the connection terminal 115, and the connection terminal 116 may be provided in the same place as the connection terminal to which a video signal or timing signal for display is input, or may be provided in a different place. It is good also as a structure which provides a connection terminal ahead of it.

  Next, specific operations in FIGS. 1 and 4 will be described with reference to a timing chart shown in FIG.

  8 is a timing chart regarding the write control signal (SWE), the potential of the source line (SL), the potential of the gate line (GL), each signal of the connection terminal 114 and the connection terminal 116, and the potential of each wiring. It is. Note that SL and GL in FIG. 8 indicate a potential relationship with each other, and here, it can be read that SL is higher than normal GL. In FIG. 8, no signal is input to the source line in a period in which the potential of the write control signal is continuously input at a low potential, for example, in a blanking period in the display device. Therefore, SL falls during the blanking period. Since the potential is lower than GL and the first transistor in the pixel shown in FIG. 2 cannot maintain a desired operation, it can be said that the display device is defective (see SL in FIG. 8).

  In FIG. 8, as described in the above description of the inspection circuit, when the signal output from the first circuit 111 in the inspection circuit 106 is a high potential at the connection terminal 114, SL is lower than GL. Is the time. A reference potential input to the second circuit 112 is indicated by an arrow 801 in FIG. At this time, when GL falls below the potential obtained by subtracting the potential difference of the arrow 801 corresponding to the threshold voltage (Vth) of the first transistor 201 from SL, the High potential is output from the connection terminal 116. In this embodiment mode, the delay of the signal of each wiring does not affect the actual operation in FIG. 8, and therefore the potential of each wiring is described in synchronization with the rising and falling of the signal. .

  Note that although a light-emitting element is described as an example of a display element in this embodiment mode, any display element that performs display in an active matrix display device that is driven by a gate line and a source line may be used. For example, EL elements (organic EL elements, inorganic EL elements or EL elements including organic and inorganic substances), electron emitting elements, liquid crystal elements, electronic ink, grating light valves (GLV), plasma display panels (PDP), digital micromirror devices A display medium whose contrast is changed by an electromagnetic action, such as (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be used as a display element. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). There is a liquid crystal display as a display device using an element, and an electronic paper as a display device using electronic ink.

Note that this embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.
(Embodiment 2)

  In this embodiment, a structure different from the above embodiment will be described. In addition, about the structure which has the same function as Embodiment 1, the same code | symbol is attached | subjected and description of Embodiment 1 is used.

  FIG. 9 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. Note that in the present invention, a display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, the display device may include one provided with a flexible printed circuit (FPC) or a printed wiring board (PWB). A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

  FIG. 9 shows the configuration of the present embodiment. A display device illustrated in FIG. 9 includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, a connection terminal portion 105 in which a plurality of connection terminals 104 are formed, an inspection circuit 106, A correction circuit 901 is included. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The connection terminal unit 105 is connected to an FPC (Flexible Printed Circuit: not shown) for inputting an external signal. The substrate 100 is completed as a display module by attaching a counter substrate 110 for sealing a light emitting element or a liquid crystal element provided in the pixel 109.

  In the inspection circuit 106, a dummy gate line 117 and a dummy source line 118 are provided on the opposite side of the gate signal line driving circuit 101 and the source signal line driving circuit 102, and a dummy gate line 117 and a dummy source line are provided. 118. Note that in FIG. 9, dummy gate lines 117 and dummy source lines 118 connected in the inspection circuit are gate lines and source lines connected to pixels different from the pixels contributing to display in the display device. In the present embodiment, pixels that do not contribute to display provided in the same line as pixels that contribute to display are dummy pixels, source lines connected to the dummy pixels, gate lines are dummy lines in the source line direction, gate line directions Called the dummy line. The aforementioned dummy pixels and dummy lines are provided so as not to affect the display by being connected to the inspection circuit 106. Therefore, in this embodiment, a dummy line connected to the dummy pixel is connected to the inspection circuit 106. The dummy pixels can be inspected by shading the display surface without affecting the pixel display that contributes to the display. In this embodiment, a dummy line that is formed at the same time as the gate line and supplied with the same signal as the gate line is formed at the same time as the first wiring and the source line, and the same signal as that of the source line is supplied. The dummy line is called a second wiring. Note that the same signal as that supplied to the gate line is supplied at the same time as the gate line, that is, the same signal is formed. Further, the same signal is supplied to the source line is assumed to be formed at the same time as the source line, that is, composed of the same material.

  In the inspection circuit 106, the potential relationship between the gate line 107 and the source line 108 in the pixel portion is such that the potential of the source line 108 is lower than the potential of the gate line 107 and the low potential of the source line 108 and the low potential of the gate line 107. A defect caused when the difference from the potential is less than the threshold voltage (Vth) of the transistor for writing a signal from the source line 108 is detected. Specifically, the inspection circuit 106 compares the potential of the dummy gate line 117 with the potential of the dummy source line 118, and sets the High potential when the potential of the dummy source line 118 is lower than the potential of the dummy gate line 117. A first circuit 111 (also referred to as a first comparison circuit) for output, a second circuit 112 (also referred to as a subtraction circuit) for subtracting and outputting a reference potential from the potential of the dummy source line 118, a dummy circuit A third circuit 113 (also referred to as a second comparison circuit) that compares and outputs the potential of the gate line 117 with the output of the second circuit 112 is provided. The inspection circuit 106 has a connection terminal 114 for outputting a result of comparison in the first circuit 111 by a routed wiring, a connection terminal 115 to which a reference potential is input to the second circuit, a first terminal 3 is connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the circuit 113. Note that in this specification, the reference potential input to the second circuit 112 is substantially the same potential as the threshold voltage (Vth) of a transistor for writing a signal from a source line provided in a pixel. Desirably, about 0.1 to 2.0V is desirable.

  Further, the correction circuit 901 is connected to the wiring routed from the inspection circuit 106 to the connection terminal 116, the connection terminal 401, and the connection terminal 902. Note that a signal output from the third circuit 113 is input to the connection terminal 116 connected to the inspection circuit 106, a write control signal SWE is input to the connection terminal 401, and a write control signal is input to the connection terminal 902. A signal SWEWE for control is input. A write control signal controlled by the correction circuit 901 is input to the source signal line driver circuit.

  Note that in FIG. 9, a write control signal SWE (source write enable signal) is a signal for selecting writing or erasing of the signal of the source line, and the high potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line. In FIG. 9, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential of SWEWE. Further, when the High potential of the signal SWEWE for controlling the write control signal is input to the correction circuit, the output of the write control signal SWE to the source signal line driver circuit is selected to be supplied or stopped. And

  Note that the description of the example shown in FIGS. 2 and 3 in Embodiment 1 is used for the pixel configuration of the pixel 109.

  Next, in FIG. 10, connection in the first circuit 111, the second circuit 112, and the third circuit 113 in the inspection circuit 106 described in FIG. 9 will be described. Note that in FIG. 10, as in FIG. 4, a light-emitting element using an organic material in a light-emitting layer is used for each pixel as a display medium, and the first transistor, the second transistor, a storage capacitor, and a light-emitting element are included. The configuration will be described, and in the present embodiment, the same description will be given below. Note that for the circuit structures of the first circuit 111, the second circuit 112, and the third circuit 113, the description of the example shown in FIGS. 5, 6, and 7 in Embodiment 1 is cited. . As the structure, a structure including the first transistor and the second transistor, the storage capacitor, and the light-emitting element which are illustrated in FIGS.

  FIG. 10 shows the basic configuration of the present invention shown in FIG. 9 in more detail. 10, the same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted. 10 includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, and a plurality of connection terminals (not shown) formed on a substrate (not shown). A terminal portion (not shown), an inspection circuit 106, and a correction circuit 901 are provided. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. Note that a write control signal SWE is input from the connection terminal 401 to the source signal line driver circuit. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The substrate is completed as a display module by attaching a counter substrate (not shown) for sealing the light emitting element or the liquid crystal element provided in the pixel 109.

  Further, the inspection circuit 106 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion in which the potential of the source line 108 is lower than the potential of the gate line 107 and less than the threshold voltage (Vth) of the first transistor 201. Detects a defect caused by Specifically, the inspection circuit compares the potential of the dummy gate line 117 with the potential of the dummy source line 118, and sets the High potential when the potential of the dummy gate line 117 is lower than the potential of the dummy source line 118. A first circuit 111 (also referred to as a first comparison circuit) to output, a second potential to be output by subtracting a reference potential from the potential of the dummy source line 118 (also referred to as a subtraction circuit), and a dummy A third circuit 113 (also referred to as a second comparison circuit) for comparing the potential of the gate line 117 with the output of the second circuit 112 and outputting the same is provided. The inspection circuit 106 is connected to a connection terminal 114 for outputting a result of comparison in the first circuit 111 by a routed wiring, a connection terminal 115 to which a reference potential is input to the second circuit 112, The terminals are connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the third circuit 113.

  In the test circuit 106 in FIG. 10, a dummy gate line 117, a dummy source line 118, and a connection terminal 114 are connected to the first circuit 111. The second circuit 112 is connected to a dummy source line 118, a connection terminal 115 to which a reference potential is input, and a third circuit 113. The third circuit 113 is connected to the second circuit 112, the dummy gate line 117, and a connection terminal 116 for outputting a signal from the third circuit 113. Note that in this specification, the reference potential input to the second circuit 112 is preferably substantially the same potential as the threshold voltage (Vth) of the first transistor 201 provided in the pixel. It is desirable that the voltage be about 0.0V.

  Further, the correction circuit 901 is connected to the wiring routed from the inspection circuit 106 to the connection terminal 116, the connection terminal 401, and the connection terminal 902. Note that a signal output from the third circuit 113 is input to the connection terminal 116 connected to the inspection circuit 106, a write control signal SWE is input to the connection terminal 401, and a write control signal is input to the connection terminal 902. A signal SWEWE for control is input. A write control signal controlled by the correction circuit 901 is input to the source signal line driver circuit.

  Note that in FIG. 10, a write control signal SWE (source write enable signal) is a signal for selecting writing or erasing of a signal of the source line, and the high potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line. In FIG. 10, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential of SWEWE. Further, when the High potential of the signal SWEWE for controlling the write control signal is input to the correction circuit, the output of the write control signal SWE to the source signal line driver circuit is selected to be supplied or stopped. And

  Note that in the present invention, the term “connected” includes the case of being electrically connected and the case of being directly connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, other elements (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that can be electrically connected are arranged. May be. Or you may arrange | position, without inserting another element in between. In addition, it is a case where it is connected without interposing other elements that enable electrical connection, and includes only the case where it is directly connected, and does not include the case where it is electrically connected Is described as being directly connected or directly connected. Note that the description of being electrically connected includes the case of being electrically connected and the case of being directly connected.

  Next, the circuit configuration and connection of the correction circuit 901 will be described with reference to FIG.

  FIG. 11 shows a block diagram and a circuit diagram of the correction circuit 901 in FIGS. The correction circuit 901 controls a memory circuit 1101 for holding a signal output from the inspection circuit 106 to the connection terminal 116 for a certain period, a first inverter circuit 1102 for inverting a signal from the memory circuit, and a write control signal. NAND circuit 1103 for taking the negative logical product of the signal SWEWE and the output of the first inverter circuit, the second inverter circuit 1104 for inverting the output signal of the NAND circuit 1103, and the output from the second inverter circuit By a signal from the third inverter circuit 1105 for inverting the output, the analog switch 1106 controlled by the output from the second inverter circuit 1104 and the output from the third inverter circuit 1105, and the second inverter circuit A transistor 1107 to be controlled is included. The node of the output terminal of the NAND circuit 1103 is N (NAND).

  The memory circuit 1101 includes a signal switching circuit 1101A and a signal holding circuit 1101B. The signal switching circuit 1101A is a circuit for switching input or non-input of a signal from the inspection circuit 106. The signal holding circuit 1101B is a circuit that holds the output from the signal switching circuit 1101A for a certain period. Note that the node of the input terminal of the signal switching circuit 1101A is N (116), the node of the input terminal of the signal holding circuit 1101B is N (in), and the node of the output terminal of the signal holding circuit 1101B is N (out).

  In addition, the write control signal SWE is input to the correction circuit 901. In the correction circuit 901, the write control signal SWE is input to the input terminals of the signal switching circuit 1101A, the signal holding circuit 1101B, and the analog switch 1106.

  In this embodiment, the transistor 1107 is an N-channel transistor, and an output from the second inverter circuit 1104 is output to the gate of the transistor 1107. When the signal from the second inverter circuit 1104 is a Low signal, the transistor 1107 is turned off, the analog switch 1106 is turned on, and a write control signal is output from the output terminal of the analog switch 1106 to the source signal line driver circuit. When the signal from the second inverter circuit 1104 is a high signal, the analog switch 1106 is turned off, the transistor 1107 is turned on, and the GND potential connected to the first terminal of the transistor 1107 is from the second terminal of the transistor 1107. It is output to the source signal line driver circuit.

  Note that in this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in the present invention, regions functioning as a source and a drain are referred to as a first terminal and a second terminal, respectively. In a transistor, a gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, or the like). Note that a source refers to the whole or part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, or the like). The drain is the same as the source.

  Next, in FIG. 22, circuit configurations of the signal switching circuit 1101A and the signal holding circuit 1101B in FIG. 11 will be described. Note that the circuit configuration shown in FIG. 22 is merely an example, and the present invention is not limited to this.

  FIG. 22A is an example of the signal switching circuit 1101A in FIG. 11 and includes an inverter circuit 2201, an analog switch 2202, and a transistor 2203. A transistor 2203 in FIG. 22A is an N-channel transistor, and a write control signal SWE is output to the gate of the transistor 2203 through the inverter circuit 2201. When the signal of the write control signal SWE is a high signal, the transistor 2203 is turned off, the analog switch 2202 is turned on, and the potential of the node N (116) is output from the output terminal of the analog switch 2202 to the node N (in). . When the signal of the write control signal SWE is a Low signal, the analog switch 2202 is turned off and the transistor 2203 is turned on, so that the GND potential from the first terminal of the transistor 2203 is at the node N (in) from the second terminal of the transistor 2203. Is output.

  FIG. 22B is an example of the signal holding circuit 1101B in FIG. 11, and is a D flip-flop circuit including a terminal Q, a terminal QB, a terminal CLK, a terminal D, and a terminal XR. FIG. 22B shows a circuit configuration of the D flip-flop circuit of FIG. The D flip-flop circuit is composed of a plurality of NAND circuits. In the D flip-flop circuit in FIG. 22B, the terminal Q is connected to the node N (out), the terminal QB is connected to the terminal D, the terminal CLK is connected to the node N (in), and the terminal XR is connected. A write control signal is input.

  FIG. 22C illustrates a basic operation of the D flip-flop circuit illustrated in FIG. At the rise of the signal input to the terminal CLK, the potential of the terminal Q is switched to the high potential and the potential of the terminal QB is switched to the low potential. The potentials of the terminal Q and the terminal QB are held until the potential rises at the next terminal CLK or until the Low potential is input to the terminal XR.

  Next, specific operations in FIGS. 10 and 11 will be described with reference to a timing chart shown in FIG.

  The timing chart shown in FIG. 12 includes a write control signal SWE, a signal SWEWE for controlling the write control signal, a node N (out), a node N (NAND), a connection terminal 114, a connection terminal 116, a node N (in), 5 is a timing chart for each signal of a potential SL of a source line and a potential GL of a gate line and a potential of each wiring. Note that the potential SL of the source line and the potential GL of the gate line in FIG. 12 also indicate a mutual potential relationship. Here, it can be read that the potential of SL is higher than the potential of GL. In FIG. 12, the write control signal SWE reflects the potential of the write control signal SWE on the potential SL of the source line when the signal SWEWE for controlling the write control signal is at the low potential, and controls the write control signal. When the signal SWEWE is at a high potential, the potential of the write control signal SWE is not reflected on the potential SL of the source line. Therefore, the potential of the source line drops when the signal SWEWE for controlling the write control signal is at a high potential. When the potential SL of the source line falls below the threshold voltage (Vth) of the first transistor 201, a high potential is output from the above-described inspection circuit 106, and the potential of the connection terminal 116 increases. When the potential of the connection terminal 116 increases, the correction circuit 901 operates and the source line takes in the potential when the write control signal is at the high potential, so that the source line potential SL is lower than the gate line potential GL. Can be raised before. Therefore, the High potential of the connection terminal 114 that is output when the potential SL of the source line is lower than the potential of the gate line is not detected. That is, the display device can maintain a good display. Note that the potential of the connection terminal 116 is delayed from the length of one wavelength of the output waveform of the write control signal SWE by the amount of passing through the pixel portion and the inspection circuit, and thus the potential of the write control signal SWE is held. The correction circuit 901 can perform correction using the high potential of the inspection circuit.

  In FIG. 12, as described above for the inspection circuit, when the signal output from the first circuit 111 in the inspection circuit 106 detects the High potential at the connection terminal 114, the potential SL of the source line is This is when it falls below the potential GL of the gate line. Further, a reference potential input to the second circuit 112 is indicated by an arrow 801 in FIG. 8 described in Embodiment 1. At this time, when the potential GL of the gate line falls below the potential obtained by subtracting the potential difference indicated by the arrow 801 corresponding to the threshold voltage (Vth) of the first transistor 201 from the potential SL of the source line, the High potential is output from the connection terminal 116. Is done.

  As a result, depending on the output from the first circuit 111, which is the output of the inspection circuit 106, to the connection terminal 114, the correction circuit 901 always corrects the source line potential SL so that it does not fall below the gate line potential GL. Display can be performed satisfactorily. Further, the correction can be performed by a correction circuit built in the display device by performing the correction using a signal output from the third circuit 113 to the connection terminal 116. Needless to say, a signal obtained by subtracting the threshold voltage of the first transistor of the pixel from the potential SL of the source line output from the connection terminal is applied to the counter substrate even when the display panel which is the effect shown in Embodiment Mode 1 is displaying. It is also possible to inspect using a probe connected to the measuring instrument from outside the sealed area. Note that the connection terminal 114, the connection terminal 115, and the connection terminal 116 may be provided in the same place as the connection terminal to which a video signal or timing signal for display is input, or may be provided in a different place. It is good also as a structure which provides a connection terminal ahead of it.

  Note that although a light-emitting element is described as an example of a display element in this embodiment mode, any display element that performs display in an active matrix display device that is driven by a gate line and a source line may be used. For example, EL elements (organic EL elements, inorganic EL elements or EL elements including organic and inorganic substances), electron emitting elements, liquid crystal elements, electronic ink, grating light valves (GLV), plasma display panels (PDP), digital micromirror devices A display medium whose contrast is changed by an electromagnetic action, such as (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be used as a display element. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). There is a liquid crystal display as a display device using an element, and an electronic paper as a display device using electronic ink.

Note that this embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.
(Embodiment 3)

  In this embodiment, a structure different from the above embodiment will be described. In addition, about the structure which has the same function as Embodiment 1 and Embodiment 2, the same code | symbol is attached | subjected and description of Embodiment 1 and Embodiment 2 is used.

  FIG. 13 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. Note that in the present invention, a display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, the display device may include one provided with a flexible printed circuit (FPC) or a printed wiring board (PWB). A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

  FIG. 13 shows the configuration of this embodiment. A display device illustrated in FIG. 13 includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, a connection terminal portion 105 in which a plurality of connection terminals 104 are formed, an inspection circuit 126, A switching circuit 1301 is included. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The connection terminal unit 105 is connected to an FPC (Flexible Printed Circuit: not shown) for inputting an external signal. The substrate 100 is completed as a display module by attaching a counter substrate 110 for sealing a light emitting element or a liquid crystal element provided in the pixel 109.

  The switching circuit 1301 is provided on the opposite side where the gate line 107 and the source line 108 are connected to the gate signal line driver circuit 101 and the source signal line driver circuit 102, and is connected to the gate line 107 and the source line 108. Note that the switching circuit 1301 receives a signal SWEWE for controlling a write control signal input to the switching circuit 1301 and a constant potential signal from the connection terminal 1302 to the inspection circuit 106. The switching circuit 1301 outputs a constant potential signal from the connection terminal 1302 to the inspection circuit when the inspection circuit 106 is not inspected, and when the inspection circuit 106 inspects the potential of the gate line and the source line, A signal is output to the inspection circuit by switching to output to the potential and the potential of the source line.

  Note that a write control signal SWE (source write enable signal) in FIG. 13 is a signal for selecting writing or erasing of a signal on the source line, and the High potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line. In FIG. 13, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal SWEWE for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential.

  The inspection circuit 126 is provided on the opposite side where the gate line 107 and the source line 108 are connected to the gate signal line driver circuit 101 and the source signal line driver circuit 102, and is connected to the gate line 107 and the source line 108. In FIG. 13, the gate line 107 and the source line 108 connected to the inspection circuit via the switching circuit 1301 are a gate line and a source line connected to pixels contributing to display in the display device. This is different from the first embodiment and the second embodiment. In this embodiment mode, the inspection circuit 126 evaluates the potentials of the source line and the gate line connected to the pixel contributing to display, thereby evaluating the pixel contributing to more accurate display. It is possible to perform a more accurate inspection than in the first and second embodiments.

  In addition, the inspection circuit 126 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion input via the switching circuit 1301, the potential of the source line 108 is lower than the potential of the gate line 107, and A failure caused when the voltage is lower than the threshold voltage (Vth) of the transistor for writing the signal is detected. Specifically, the inspection circuit 126 compares the potentials of the gate line 107 and the source line 108 and outputs a high potential when the potential of the source line 108 falls below the potential of the gate line 107 (first circuit 121 A third circuit 122 that compares and outputs the potential of the gate line 107 with the output of the second circuit 122. Circuit 123 is provided. The inspection circuit 106 has a connection terminal 114 for outputting a result of comparison in the first circuit 121 by the drawn wiring, a connection terminal 115 to which a reference potential is input to the second circuit 122, a first terminal 3 is connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the circuit 123. Note that in this specification, the reference potential input to the second circuit 122 is substantially the same potential as the threshold voltage (Vth) of a transistor for writing a signal from a source line provided in a pixel. Desirably, about 0.1 to 2.0V is desirable.

  Note that the description of the example shown in FIGS. 2 and 3 in Embodiment 1 is used for the pixel configuration of the pixel 109.

  Next, one configuration of the switching circuit 1301 will be described with reference to FIG.

  The switching circuit 1301 includes an analog switch 1401 and an inverter circuit 1402 for supplying the potential of the gate line 107 to the inspection circuit when the signal SWEWE for controlling the write control signal is a high potential, that is, when no signal is supplied to the source line. Have Further, when the signal SWEWE for controlling the write control signal is a low potential, that is, when a signal is supplied to the source line, a potential for causing the inspection circuit 126 to not malfunction is supplied to the inspection circuit 126. A transistor 1403 is included. Further, an analog switch 1404 and an inverter circuit 1405 are provided for supplying the potential of the source line 108 to the inspection circuit when the signal SWEWE for controlling the write control signal is a high potential, that is, when no signal is supplied to the source line. Further, when the signal SWEWE for controlling the write control signal is a low potential, that is, when a signal is supplied to the source line, a potential for causing the inspection circuit 126 to not malfunction is supplied to the inspection circuit 126. A transistor 1406 is included.

  The operation of the switching circuit 1301 will be briefly described. When a high potential is input as the signal SWEWE for controlling the write control signal from the connection terminal 902, the switching circuit 1301 outputs the potentials of the gate line 107 and the source line 108 to the inspection circuit 106, respectively. When a low potential is input as the signal SWEWE for controlling the write control signal from the connection terminal 902, the GND potential is input to the inspection circuit 106 connected to the gate line 107 and is connected to the source line 108 side. The inspection circuit 106 receives a potential higher than the GND potential from the connection terminal 1302. This prevents the potential input to the inspection circuit 106 from determining that the potential of the gate line 107 and the source line 108 is defective while the inspection circuit 106 is not connected to the gate line 107 and the source line 108. Therefore, the potential input to the inspection circuit 126 may be a potential that does not determine that the potentials of the gate line 107 and the source line 108 are defective.

  Note that when a test is performed by directly connecting the test circuit 106 to the gate line 107 and the source line 108 in the display device, a current flows from the gate line 107 and the source line 108 to the test circuit 126, resulting in poor display. Inconvenient. In the present invention, more accurate inspection can be performed by performing inspection while paying attention when the source line is not written, in which the signal for controlling the write control signal by the switching circuit is a high potential.

  Next, FIG. 15 shows a display medium according to the present invention in which a light emitting element using an organic material for a light emitting layer is adopted for each pixel. Each pixel has a structure including the first transistor and the second transistor in FIG. 2 described in Embodiment Mode 1, a storage capacitor, and a light-emitting element as its structure. In FIG. 15, connection in the first circuit 121, the second circuit 122, and the third circuit 123 in the inspection circuit 126 described in FIG. 13 is described.

  FIG. 15 shows the basic configuration of the present invention shown in FIG. 1 in more detail. In FIG. 15, the same parts as those in FIG. In the display device illustrated in FIG. 15, a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, and a plurality of connection terminals (not illustrated) are formed over a substrate (not illustrated). A terminal portion (not shown) and an inspection circuit 126 are provided. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. Note that a write control signal SWE is input from the connection terminal 401 to the source signal line driver circuit. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The substrate 100 is completed as a display module by attaching a counter substrate (not shown) for sealing the light emitting element or the liquid crystal element provided in the pixel 109.

  The inspection circuit 126 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion where the potential of the source line 108 is lower than the potential of the gate line 107 and less than the threshold voltage (Vth) of the first transistor 201. Detects a defect caused by Specifically, the inspection circuit 126 compares the potentials of the gate line 107 and the source line 108 and outputs a high potential when the potential of the source line 108 falls below the potential of the gate line 107 (first circuit 121 (Also referred to as a comparison circuit), a second circuit 122 (also referred to as a subtraction circuit) that subtracts a reference potential from the potential of the source line 108 and outputs it, and compares the potential of the gate line 107 with the output of the second circuit 122. In addition, a third circuit 123 (also referred to as a second comparison circuit) for output is provided. The inspection circuit 126 has a connection terminal 114 for outputting a result of comparison in the first circuit 121 through a wiring, a connection terminal 115 to which a reference potential is input to the second circuit 122, a third terminal Connection terminals 116 for outputting signals from the circuit 123 are connected to each other.

  In the test circuit 126 in FIG. 15, the gate line 107, the source line 108, and the connection terminal 114 are connected to the first circuit 121. The second circuit 122 is connected to the source line 108, the connection terminal 115 to which a reference potential is input, and the third circuit 123. The third circuit 123 is connected to the second circuit 122, the gate line 107, and a connection terminal 116 for outputting a signal from the third circuit 123. Note that in this specification, the reference potential input to the second circuit 122 is preferably substantially the same potential as the threshold voltage (Vth) of the first transistor 201 provided in the pixel. It is desirable that the voltage be about 0.0V.

  Next, with reference to FIGS. 23, 24, and 25, circuit configurations and connections of the first circuit 121, the second circuit 122, and the third circuit 123 will be described.

  FIG. 23 shows a block diagram and a circuit diagram of the first circuit 121 in FIGS. The first circuit 121 connects the gate line 107 to the non-inverting input terminal of the operational amplifier shown in FIG. 5 and the source line 108 to the inverting input terminal with respect to the gate line 107 and the source line 108. It is a comparison circuit that compares the potential of the source line 108. The first circuit 121 can detect whether the potential of the source line 108 is lower than the potential of the gate line 107 with respect to the potential relationship between the gate line 107 and the source line 108. When the potential of the source line 108 is lower than the potential of the gate line 107, a high potential is output from the output terminal of the operational amplifier to the connection terminal 114. Note that in the first circuit 121, it is preferable to use a power supply having a potential 2 V lower than the low potential of the gate line 107 as the negative power supply used for the operational amplifier.

  Next, FIG. 24 shows a block diagram and a circuit diagram of the second circuit 122 in FIGS. The second circuit 122 is composed of a subtracting circuit composed of an operational amplifier and a resistor. In the second circuit 122, the potential of the source line 108 is connected to the non-inverting input terminal of the operational amplifier, and the reference potential input to the connection terminal 115 is connected to the inverting input terminal of the operational amplifier. The second circuit 122 outputs a potential obtained by subtracting the reference potential from the potential of the source line 108 to the third circuit 123. At this time, it is preferable that the resistances of the subtracting circuits in the second circuit 122 are all equal. The reference potential is preferably substantially the same as the threshold voltage (Vth) of the first transistor provided in the pixel, and is preferably about 0.1 to 2.0V.

  Next, FIG. 25 shows a block diagram and a circuit diagram of the third circuit 123 in FIGS. The third circuit 123 is a comparison circuit including an operational amplifier, and compares the potential of the output of the second circuit 122 with the potential of the gate line 107. In the third circuit 123, the output of the second circuit 122 is connected to the inverting input terminal of the operational amplifier, and the potential of the gate line 107 is input to the non-inverting input terminal. Then, the potential of the gate line 107 is compared with the output potential of the second circuit 122. When the output potential of the second circuit 122 is lower than the potential of the gate line 107, a high potential is output from the output terminal of the operational amplifier to the connection terminal 116. Is output. Then, it is possible to detect immediately before the potential obtained by subtracting the threshold voltage (Vth) of the first transistor 201 from the potential of the source line 108 is lower than the potential of the gate line 107, and to detect when the potential is lower than the potential of the gate line 107. Can do.

  Note that the operation of the inspection circuit 126 is similar to the operation of the inspection circuit 106 of Embodiment 1, and thus the description of FIG. 8 in Embodiment 1 is used here.

  According to this embodiment, a display device in which the inspection circuit 126 and the pixel portion 103 are provided over the same substrate and the inspection circuit and the pixel portion are sealed by the counter substrate 110 can be manufactured. In the display device of this embodiment, since the connection terminal 114 is outside the region sealed with the counter substrate, the connection is made from the first circuit 121 that is the output of the inspection circuit 126 even when the display panel is displaying. A signal output to the terminal 114 can be used to detect a defect in the display device using a probe connected to a measuring instrument from the outside of the region sealed on the counter substrate. Further, since the connection terminal 116 is outside the region sealed with the counter substrate, the threshold voltage of the first transistor of the pixel output from the third circuit 123 is subtracted even when the display panel is displaying. The signal can be inspected using a probe connected to the measuring instrument from the outside of the region sealed on the counter substrate. In particular, in this embodiment, since the inspection can be performed by outputting the potential of the gate line and the source line contributing to the actual display to the inspection circuit while switching with the switching circuit, more accurate inspection in the display device is performed. It can be carried out. Note that the connection terminal 114, the connection terminal 115, and the connection terminal 116 may be provided in the same place as the connection terminal to which a video signal or timing signal for display is input, or may be provided in a different place. It is good also as a structure which provides a connection terminal ahead of it.

Note that this embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.
(Embodiment 4)

  In this embodiment, a structure different from the above embodiment will be described. Note that components having the same functions as those of the first to third embodiments are denoted by the same reference numerals, and the description of the first to third embodiments is incorporated.

  FIG. 16 shows a block diagram of a display device in this embodiment mode, which will be described in detail below. Note that in the present invention, a display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, the display device may include one provided with a flexible printed circuit (FPC) or a printed wiring board (PWB). A light-emitting device refers to a display device including a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

  FIG. 16 shows the configuration of this embodiment. A display device illustrated in FIG. 16 includes a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, a connection terminal portion 105 in which a plurality of connection terminals 104 are formed, an inspection circuit 106, A correction circuit 901 and a switching circuit 1301 are included. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. In addition, an FPC (Flexible Print Circuit: not shown) for inputting a signal from the outside is connected to the connection terminal unit 105. The substrate 100 is completed as a display module by attaching a counter substrate 110 for sealing a light emitting element or a liquid crystal element provided in the pixel 109.

  The switching circuit 1301 is provided on the opposite side where the gate line 107 and the source line 108 are connected to the gate signal line driver circuit 101 and the source signal line driver circuit 102, and is connected to the gate line 107 and the source line 108. Note that a signal having a constant potential input from the connection terminal 1302 and a signal SWEWE for controlling a write control signal are input to the switching circuit 1301. The switching circuit 1301 outputs a constant potential signal from the connection terminal 1302 to the inspection circuit when the inspection circuit 126 is not inspected. When the inspection circuit 126 inspects the potentials of the gate line and the source line, A signal is output to the inspection circuit by switching to output to the potential and the potential of the source line.

  Note that in FIG. 16, a write control signal SWE (source write enable signal) is a signal for selecting writing or erasing of a signal of the source line, and the High potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line. In FIG. 13, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal SWEWE for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential.

  The inspection circuit 126 is provided on the opposite side where the gate line 107 and the source line 108 are connected to the gate signal line driver circuit 101 and the source signal line driver circuit 102, and is connected to the gate line 107 and the source line 108. Note that the gate line 107 and the source line 108 connected to the inspection circuit via the switching circuit 1301 in FIG. 16 are gate lines and source lines connected to pixels contributing to display in the display device. This is different from the first embodiment and the second embodiment. In this embodiment mode, the inspection circuit 126 evaluates the potentials of the source line and the gate line connected to the pixel contributing to display, thereby evaluating the pixel contributing to more accurate display. It is possible to perform a more accurate inspection than in the first and second embodiments. In addition, in this embodiment mode, the correction circuit 901 can further correct the potential of the source line.

  The inspection circuit 126 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion, in which the potential of the source line 108 is lower than the potential of the gate line 107 and the low potential of the source line 108 and the low potential of the gate line 107. A defect caused when the difference from the potential is less than the threshold voltage (Vth) of a transistor for writing a signal from the source line is detected. Specifically, the inspection circuit 126 compares the potentials of the gate line 107 and the source line 108, and outputs a high potential when the potential of the source line 108 is lower than the potential of the gate line 107 (first circuit 121) And the second circuit 122 (also referred to as a subtractor circuit) that outputs the reference potential from the potential of the source line 108 and the output of the second circuit 122. And a third circuit 123 (also referred to as a second comparison circuit) for outputting. The inspection circuit 126 is connected to a connection terminal 114 for outputting a result of comparison in the first circuit 121 by a routed wiring, a connection terminal 115 to which a reference potential is input to the second circuit 122, The terminals are connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the third circuit 123. Note that in this specification, the reference potential input to the second circuit 122 is substantially the same potential as the threshold voltage (Vth) of a transistor for writing a signal from a source line provided in a pixel. Desirably, about 0.1 to 2.0V is desirable.

  Further, the correction circuit 901 is connected to the wiring routed from the inspection circuit 126 to the connection terminal 116, the connection terminal 401, and the connection terminal 902. Note that a signal output from the third circuit 123 is input to the connection terminal 116 connected to the inspection circuit 126, a write control signal SWE is input to the connection terminal 401, and a write control signal is input to the connection terminal 902. A signal SWEWE for control is input. A write control signal controlled by the correction circuit 901 is input to the source signal line driver circuit.

  Note that a write control signal SWE (source write enable signal) in FIG. 16 is a signal for selecting writing or erasing of a signal on the source line, and the high potential of the write control signal SWE is supplied to the source signal line driver circuit 102. The high potential is written to the source line by being input, and the low potential of the write control signal SWE is input to the source signal line driver circuit 102 to write the low potential to the source line. In FIG. 16, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal SWEWE for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential. Further, when the High potential of the signal SWEWE for controlling the write control signal is input to the correction circuit, the output of the write control signal SWE to the source signal line driver circuit is selected to be supplied or stopped. To do.

  Note that the description of the example shown in FIGS. 2 and 3 in Embodiment 1 is used for the pixel configuration of the pixel 109.

  Next, in FIG. 17, connections in the first circuit 121, the second circuit 122, and the third circuit 123 in the inspection circuit 126 described in FIG. Note that in FIG. 17, as in FIG. 4, a light-emitting element using an organic material for a light-emitting layer is used for each pixel as a display medium, and the first and second transistors, a storage capacitor, and a light-emitting element are included. The configuration will be described, and in the present embodiment, the same description will be given below. Note that for the circuit configurations of the first circuit 121, the second circuit 122, and the third circuit 123, the description of the example shown in FIGS. 23, 24, and 25 in Embodiment 3 is cited. . As the structure, a structure including the first transistor and the second transistor, the storage capacitor, and the light-emitting element which are illustrated in FIGS.

  FIG. 17 shows the basic configuration of the present invention shown in FIG. 16 in more detail. In FIG. 17, the same parts as those in FIG. 17 is a connection in which a gate signal line driver circuit 101, a source signal line driver circuit 102, a pixel portion 103, and a plurality of connection terminals (not shown) are formed on a substrate (not shown). A terminal portion (not shown), an inspection circuit 126, a correction circuit 901, and a switching circuit 1301 are provided. A gate line 107 is connected to the gate signal line driver circuit 101, and a source line 108 is connected to the source signal line driver circuit 102. Note that a write control signal SWE is input from the connection terminal 401 to the source signal line driver circuit. A pixel 109 in the pixel portion 103 is connected to a gate line 107 and a source line 108. The pixel 109 is provided with a transistor for writing a signal from the source line 108 to a light emitting element or a liquid crystal element provided in the pixel by a signal of the gate line 107. The terminals are connected to the gate line 107 and the source line 108. The substrate is completed as a display module by attaching a counter substrate (not shown) for sealing the light emitting element or the liquid crystal element provided in the pixel 109.

  The inspection circuit 126 has a potential relationship between the gate line 107 and the source line 108 in the pixel portion where the potential of the source line 108 is lower than the potential of the gate line 107 and less than the threshold voltage (Vth) of the first transistor 201. Detects a defect caused by Specifically, the inspection circuit compares the potentials of the gate line 107 and the source line 108 and outputs a high potential when the potential of the source line 108 falls below the potential of the gate line 107 (first comparison 121). A second circuit 122 (also referred to as a subtraction circuit) that outputs a reference potential subtracted from the potential of the source line 108, and a potential of the gate line 107 is compared with the output of the second circuit 122. A third circuit 123 (also referred to as a second comparison circuit) for output is provided. The inspection circuit 126 is connected to a connection terminal 114 for outputting a result of comparison in the first circuit 121 by a routed wiring, a connection terminal 115 to which a reference potential is input to the second circuit 122, The terminals are connected to the connection terminal portion 105 of the connection terminal 116 for outputting a signal from the third circuit 123.

  In the inspection circuit 126 in FIG. 17, the gate line 107, the source line 108, and the connection terminal 114 are connected to the first circuit 121. The second circuit 122 is connected to the source line 108, the connection terminal 115 to which a reference potential is input, and the third circuit 123. The third circuit 123 is connected to the second circuit 122, the gate line 107, and a connection terminal 116 for outputting a signal from the third circuit 123. Note that in this specification, the reference potential input to the second circuit 122 is preferably substantially the same potential as the threshold voltage (Vth) of the first transistor 201 provided in the pixel. It is desirable that the voltage be about 0.0V.

  Further, the correction circuit 901 is connected to the wiring routed from the inspection circuit 126 to the connection terminal 116, the connection terminal 401, and the connection terminal 902. Note that a signal output from the third circuit 123 is input to the connection terminal 116 connected to the inspection circuit 126, a write control signal SWE is input to the connection terminal 401, and a write control signal is input to the connection terminal 902. A signal SWEWE for control is input. A write control signal controlled by the correction circuit 901 is input to the source signal line driver circuit 102.

  Note that in FIG. 17, a write control signal SWE (source write enable signal) is a signal for selecting writing or erasing of a signal of the source line, and the High potential of the write control signal SWE is input to the source signal line driver circuit. Thus, the High potential is written to the source line, and the Low potential of the write control signal SWE is input to the source signal line driver circuit, whereby the Low potential is written to the source line. In FIG. 17, a signal SWEWE for controlling the write control signal is a signal for selecting supply of the write control signal to the source signal line driver circuit, and a signal for controlling the write control signal to the correction circuit. It is assumed that the write control signal SWE to the source signal line driver circuit is supplied by inputting the low potential of SWEWE. Further, when the High potential of the signal SWEWE for controlling the write control signal is input to the correction circuit, the output of the write control signal SWE to the source signal line driver circuit is selected to be supplied or stopped. And

  Note that in this embodiment, the circuit configurations of the first circuit 121, the second circuit 122, and the third circuit 123 in the inspection circuit 126 are the same as those in Embodiment 3 shown in FIGS. The description of the example shown using is used. For the circuit configuration of the correction circuit 901, the description of the example shown in FIGS. 11 and 22 for the second embodiment is incorporated. Further, since the operation of the inspection circuit 126 is similar to the operation of the inspection circuit 106 of Embodiment 1, the description of FIG. 8 in Embodiment 1 is used here. Since the operation of the correction circuit 901 is the same as that of the second embodiment, the description of FIG. 12 in the second embodiment is used here.

  As a result, the output from the first circuit 121 to the connection terminal 114, which is the output of the inspection circuit 126, is always corrected by the correction circuit 901 so that the source line potential SL does not fall below the gate line potential. It can be done well. Further, the correction can be performed by the correction circuit 901 incorporated in the display device by performing the correction using a signal output from the third circuit 123 to the connection terminal 116. Of course, a signal obtained by subtracting the threshold voltage of the first transistor of the pixel from the potential SL of the source line output to the connection terminal is sealed in the counter substrate even when the display panel, which is the effect described in Embodiment Mode 1, is displaying. It is also possible to inspect using a probe connected to the measuring instrument from outside the stopped area. In particular, in the embodiment of the present invention, inspection can be performed by outputting the potential of the gate line and the source line contributing to actual display to the inspection circuit 126 while being switched by the switching circuit 1301, so that the display device can be more Accurate display can be performed. Note that the connection terminal 114, the connection terminal 115, and the connection terminal 116 may be provided in the same place as the connection terminal to which a video signal or timing signal for display is input, or may be newly provided in another place. It is also possible to provide a structure in which a connection terminal is newly provided ahead of the wiring.

  Note that this embodiment can be implemented in combination with any of the other embodiments in this specification as appropriate.

  The pixel included in the display device of the present invention is not limited to the structure shown in FIG. FIG. 18A illustrates one mode of a pixel included in the display device of the present invention. The pixel shown in FIG. 18 includes a light-emitting element 1801, a switching transistor 1802, a driving transistor 1803, and a current control transistor 1804 that selects whether or not current is supplied to the light-emitting element 1801. Further, although not shown in FIG. 18A, a capacitor for holding the voltage of the video signal may be formed in the pixel.

  The driving transistor 1803 and the current control transistor 1804 may have either the same polarity or different polarities. The driving transistor 1803 is operated in the saturation region, and the current control transistor 1804 is operated in the linear region. Note that the driving transistor 1803 is desirably operated in a saturation region; however, the present invention is not necessarily limited to this structure, and the driving transistor 1803 may be operated in a linear region. The switching transistor 1802 is operated in a linear region. The switching transistor 1802 may be either n-channel type or p-channel type.

  As shown in FIG. 18A, in the case where the driving transistor 1803 is a p-type transistor, the anode of the light-emitting element 1801 is preferably used as a first electrode and the cathode is preferably used as a second electrode. On the other hand, when the driving transistor 1803 is an n-type, it is preferable to use the cathode of the light-emitting element 1801 as the first electrode and the anode as the second electrode.

  The gate of the switching transistor 1802 is connected to the scanning line Gj (j = 1 to y). One of the source and drain of the switching transistor 1802 is connected to the signal line Si (i = 1 to x), and the other is connected to the gate of the current control transistor 1804. The gate of the driving transistor 1803 is connected to the power supply line Vi (i = 1 to x). The driving transistor 1803 and the current control transistor 1804 are supplied from the power supply line Vi so that the current supplied from the power supply line Vi is supplied to the light emitting element 1801 as the drain current of the driving transistor 1803 and the current control transistor 1804. The light emitting element 1801 is connected. In this embodiment mode, the source of the driving transistor 1803 is connected to the power supply line Vi, and the current control transistor 1804 is provided between the driving transistor 1803 and the first electrode of the light emitting element 1801.

  In the case of forming a capacitor element, one of the two electrodes included in the capacitor element is connected to the power supply line Vi and the other electrode is connected to the gate of the current control transistor 1804. The capacitor element is provided to hold the gate voltage of the current control transistor 1804.

  Note that the structure of the pixel illustrated in FIG. 18A is merely one embodiment of the present invention, and the light-emitting device of the present invention is not limited to FIG. For example, as shown in FIG. 18B, the drain terminal of the driving transistor 1803 is connected to the first electrode of the light emitting element 1801, and a current control transistor 1804 is formed between the driving transistor 1803 and the power supply line Vi. May be. Note that in FIG. 18B, the same reference numerals are given to those already shown in FIG.

  Note that this embodiment can be implemented in combination with any of the embodiment modes and other embodiments in this specification as appropriate.

  Since the display device of the present invention can increase the yield by inspecting and correcting display defects after sealing with the counter substrate, the mobile phone, the portable game machine or the electronic book, the video camera, It is most suitable for use as a display portion of a mass-produced electronic device such as a digital still camera.

  Other electronic devices that can use the display device of the present invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), and a notebook type personal computer. And an image playback device (typically, a device having a display that can play back a recording medium such as a DVD: Digital Versatile Disc and display the image). Specific examples of these electronic devices are shown in FIGS.

  FIG. 19A illustrates a mobile phone, which includes a main body 1901, a display portion 1902, a sound input portion 1903, a sound output portion 1904, and operation keys 1905. By using the display device of the present invention for the display portion 1902, a mobile phone which is one of the electronic devices of the present invention can be completed.

  FIG. 19B illustrates a video camera, which includes a main body 1906, a display portion 1907, a housing 1908, an external connection port 1909, a remote control reception portion 1910, an image receiving portion 1911, a battery 1912, an audio input portion 1913, operation keys 1914, and an eyepiece. Part 1915 and the like. By using the display device of the present invention for the display portion 1907, a video camera which is one of the electronic devices of the present invention can be completed.

  FIG. 19C illustrates a display, which includes a housing 1916, a display portion 1917, a speaker portion 1918, and the like. By using the display device of the present invention for the display portion 1917, a display display which is one of the electronic devices of the present invention can be completed. The display display includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

  Note that this embodiment can be implemented in combination with any of the embodiment modes and other embodiments in this specification as appropriate.

The block diagram regarding the structure of this invention. 1 is a circuit diagram relating to a pixel configuration of the present invention. 1 is a circuit diagram relating to a pixel configuration of the present invention. The block diagram regarding the structure of this invention. The circuit diagram regarding the test | inspection circuit of this invention. The circuit diagram regarding the test | inspection circuit of this invention. The circuit diagram regarding the test | inspection circuit of this invention. The timing chart figure regarding the structure of this invention. The block diagram regarding the structure of this invention. The block diagram regarding the structure of this invention. The circuit diagram regarding the correction circuit of this invention. The timing chart figure regarding the structure of this invention. The block diagram regarding the structure of this invention. The circuit diagram of the switching circuit in the display apparatus of this invention. The block diagram regarding the structure of this invention. The block diagram regarding the structure of this invention. The block diagram regarding the structure of this invention. 1 is a circuit diagram relating to a pixel configuration of the present invention. FIG. 11 is a diagram related to an electronic device including the display device of the invention. The block diagram explaining a prior art example. Explanatory drawing at the time of inspecting about a prior art example. The circuit diagram and timing chart figure regarding the correction circuit of this invention. The circuit diagram regarding the test | inspection circuit of this invention. The circuit diagram regarding the test | inspection circuit of this invention. The circuit diagram regarding the test | inspection circuit of this invention.

Explanation of symbols

100 Substrate 101 Gate signal line driver circuit 102 Source signal line driver circuit 103 Pixel portion 104 Connection terminal 105 Connection terminal portion 106 Inspection circuit 107 Gate line 108 Source line 109 Pixel 110 Counter substrate 111 First circuit 112 Second circuit 113 Second 3 circuit 114 connection terminal 115 connection terminal 116 connection terminal 117 dummy gate line 118 dummy source line 121 first circuit 122 second circuit 123 third circuit 126 test circuit 201 first transistor 202 second transistor 203 Storage capacitor 204 Power supply line 205 Light emitting element 206 Counter electrode 301 Transistor 302 Storage capacitor 303 Liquid crystal element 304 Counter electrode 401 Connection terminal 901 Correction circuit 902 Connection terminal 1101 Memory circuit 1102 Inverter circuit 1103 NAN Circuit 1104 Inverter circuit 1105 Inverter circuit 1106 Analog switch 1107 Transistor 1301 Switching circuit 1302 Connection terminal 1401 Analog switch 1402 Inverter circuit 1403 Transistor 1404 Analog switch 1405 Inverter circuit 1406 Transistor 1801 Light emitting element 1802 Switching transistor 1803 Driving transistor 1804 Current control transistor 1901 Main body 1902 Display unit 1903 Audio input unit 1904 Audio output unit 1905 Operation key 1906 Main unit 1907 Display unit 1908 Case 1909 External connection port 1910 Remote control reception unit 1911 Image receiving unit 1912 Battery 1913 Audio input unit 1914 Operation key 1915 Eyepiece unit 1916 Case Body 1917 Display 1918 -Car portion 2000 substrate 2001 gate signal line drive circuit 2002 source signal line drive circuit 2003 pixel portion 2004 connection terminal 2005 connection terminal portion 2006 gate line 2007 source line 2008 pixel 2009 power supply line 2010 counter substrate 2101 probe 2201 inverter circuit 2202 analog switch 2203 transistor 1101A Signal switching circuit 1101B Signal holding circuit

Claims (10)

The gate line,
Source line,
A pixel portion driven by a potential of the gate line and the source line;
A first wiring disposed in parallel with the gate line;
A second wiring arranged in parallel with the source line;
A gate signal line driving circuit for outputting a first signal to the gate line and the first wiring;
A source signal line driver circuit for outputting a second signal before Kiso baselines and the second wiring,
An inspection circuit connected to the first wiring and the second wiring;
A first connection terminal and a second connection terminal connected to the inspection circuit;
The inspection circuit includes:
A first circuit connected to the first wiring and the second wiring;
A second circuit connected to the second wiring;
A third circuit connected to the first wiring and the second circuit,
The first circuit compares the potential of the first wiring and the potential of the second wiring in a retrace period, and the potential of the second wiring is lower than the potential of the first wiring. A first potential is output to the first connection terminal when
The second circuit inputs a second potential obtained by subtracting a reference potential from the potential of the second wiring to the third circuit,
The third circuit compares the potential of the first wiring with the second potential, and if the second potential is lower than the potential of the first wiring, the third circuit compares the potential of the first wiring with the second potential. A display device that outputs to two connection terminals. The gate line,
Source line,
A pixel portion driven by a potential of the gate line and the source line;
A first wiring disposed in parallel with the gate line;
A second wiring arranged in parallel with the source line;
A gate signal line driving circuit for outputting a first signal to the gate line and the first wiring;
A source signal line driver circuit for outputting a second signal before Kiso baselines and the second wiring,
An inspection circuit connected to the first wiring and the second wiring;
A correction circuit connected to the inspection circuit;
A first connection terminal and a second connection terminal connected to the inspection circuit;
The inspection circuit includes:
A first circuit connected to the first wiring and the second wiring;
A second circuit connected to the second wiring;
A third circuit connected to the first wiring and the second circuit,
The first circuit compares the potential of the first wiring and the potential of the second wiring in a retrace period, and the potential of the second wiring is lower than the potential of the first wiring. Output a first potential to the first connection terminal,
The second circuit inputs a second potential obtained by subtracting a reference potential from the potential of the second wiring to the third circuit,
The third circuit compares the potential of the first wiring with the second potential, and if the second potential is lower than the potential of the first wiring, the third circuit compares the potential of the first wiring with the second potential. 2 to the connection terminal,
The correction circuit increases the potential of the second wiring higher than the potential of the first wiring when the third potential is output to the second connection terminal. A display device that corrects a potential output to a connection terminal and the second connection terminal. In claim 1 or claim 2 ,
Said first connecting terminal and the second connection terminal, a display device, characterized in that are provided outside of the region sealed by the substrate and a counter substrate on which the pixel portion is formed. The gate line,
Source line,
A drive circuit for supplying a signal to the source line;
A pixel portion driven by a potential of the gate line and the source line;
A switching circuit connected to the gate line and the source line;
An inspection circuit;
A first connection terminal and a second connection terminal connected to the inspection circuit;
The inspection circuit includes:
A first circuit connected to the gate line and the source line;
A second circuit connected to the source line;
A third circuit connected to the gate line and the second circuit,
The switching circuit is in the blanking period, when the signal for controlling the writing of the source line is not supplied to the driving circuit, is connected to the gate line and the source line and said test circuit,
The first circuit compares the inputted potential of the gate line with the inputted potential, and when the inputted potential of the source line falls below the potential of the gate line, the first potential Is output to the first connection terminal,
The second circuit inputs a second potential obtained by subtracting a reference potential from the input source line potential to the third circuit,
The third circuit compares the input potential of the gate line with the second potential,
The display device, wherein the third potential is output to the second connection terminal when the second potential is lower than the potential of the gate line. The gate line,
Source line,
A drive circuit for supplying a signal to the source line;
A pixel portion driven by a potential of the gate line and the source line;
A switching circuit connected to the gate line and the source line;
An inspection circuit;
A first connection terminal and a second connection terminal connected to the inspection circuit;
A correction circuit connected to the inspection circuit and the second connection terminal,
The inspection circuit includes:
A first circuit connected to the gate line and the source line;
A second circuit connected to the source line;
A third circuit connected to the gate line and the second circuit,
The switching circuit connects the gate line and the source line and the inspection circuit when a signal for controlling writing to the source line is not supplied to the driving circuit in a blanking period,
The first circuit compares the input potential of the gate line and the potential of the source line, and if the potential of the source line falls below the potential of the gate line, the first potential is set to the first potential. Output to the connection terminal of
The second circuit inputs a second potential obtained by subtracting a reference potential from the input source line potential to the third circuit,
The third circuit compares the input potential of the gate line with the second potential,
When the second potential is lower than the gate line potential, a third potential is output to the second connection terminal;
The correction circuit sets the potential of the source line higher than the potential of the gate line when the third potential is output to the second connection terminal. A display device that corrects a potential output to a second connection terminal. In claim 4 or claim 5 ,
Said first connecting terminal and the second connection terminal, a display device, characterized in that are provided outside of the region sealed by the substrate and a counter substrate on which the pixel portion is formed. In any one of Claims 1 thru | or 6 ,
The pixel portion includes a transistor connected to the gate line and the source line,
The transistor is selected by a signal input to the gate line, and a signal from the source line is written thereto. In claim 7 ,
The display device is characterized in that the transistor is an N-channel transistor. In any one of Claims 1 thru | or 8 ,
The display device is characterized in that the pixel portion includes a pixel which is driven by the potential of the first wiring and the potential of the second wiring and does not contribute to display. It claims 1 to an electronic apparatus, characterized by comprising a display unit to display device according to any one of claims 9.

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