JP5120850B2 - ストリーム・レジスタを用いてスヌープ要求をフィルタする方法、装置及びコンピュータ・プログラム - Google Patents

ストリーム・レジスタを用いてスヌープ要求をフィルタする方法、装置及びコンピュータ・プログラム Download PDF

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JP5120850B2
JP5120850B2 JP2008504137A JP2008504137A JP5120850B2 JP 5120850 B2 JP5120850 B2 JP 5120850B2 JP 2008504137 A JP2008504137 A JP 2008504137A JP 2008504137 A JP2008504137 A JP 2008504137A JP 5120850 B2 JP5120850 B2 JP 5120850B2
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snoop
cache
address
register
filter
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JP2008535093A (ja
JP2008535093A5 (https=
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ブルームリッチ、マシアス、エー．
ガラ、アラン、ジー．
サラプラ、ヴァレンティナ
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2008504137A 2005-03-29 2006-03-17 ストリーム・レジスタを用いてスヌープ要求をフィルタする方法、装置及びコンピュータ・プログラム Expired - Fee Related JP5120850B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/093,130 US7392351B2 (en) 2005-03-29 2005-03-29 Method and apparatus for filtering snoop requests using stream registers
US11/093,130 2005-03-29
PCT/US2006/010038 WO2006104747A2 (en) 2005-03-29 2006-03-17 Method and apparatus for filtering snoop requests using stream registers

Publications (3)

Publication Number Publication Date
JP2008535093A JP2008535093A (ja) 2008-08-28
JP2008535093A5 JP2008535093A5 (https=) 2012-05-10
JP5120850B2 true JP5120850B2 (ja) 2013-01-16

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JP2008504137A Expired - Fee Related JP5120850B2 (ja) 2005-03-29 2006-03-17 ストリーム・レジスタを用いてスヌープ要求をフィルタする方法、装置及びコンピュータ・プログラム

Country Status (6)

Country Link
US (2) US7392351B2 (https=)
EP (1) EP1864224B1 (https=)
JP (1) JP5120850B2 (https=)
KR (1) KR101013237B1 (https=)
CN (1) CN100568206C (https=)
WO (1) WO2006104747A2 (https=)

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KR102485999B1 (ko) * 2015-07-01 2023-01-06 삼성전자주식회사 마스터-사이드 필터를 포함하는 캐시 코히런트 시스템과 이를 포함하는 데이터 처리 시스템
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Publication number Publication date
US7392351B2 (en) 2008-06-24
WO2006104747A2 (en) 2006-10-05
US8135917B2 (en) 2012-03-13
EP1864224A2 (en) 2007-12-12
US20060224836A1 (en) 2006-10-05
EP1864224B1 (en) 2013-05-08
JP2008535093A (ja) 2008-08-28
KR101013237B1 (ko) 2011-02-08
CN101189590A (zh) 2008-05-28
KR20070119653A (ko) 2007-12-20
EP1864224A4 (en) 2011-08-10
CN100568206C (zh) 2009-12-09
US20080244194A1 (en) 2008-10-02
WO2006104747A3 (en) 2007-12-21

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