Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
  • G06F12/0815—Cache consistency protocols
  • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
  • G06F12/0815—Cache consistency protocols
  • G06F12/0817—Cache consistency protocols using directory methods
  • G06F12/0822—Copy directories
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
  • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
  • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the snoop filter described utilizes stream registers for tracking data loaded into a local cache memory associated with the processor unit, and identifies most of the snoop requests which would result in cache misses by filtering them out, but never filtering out a snoop requests for data which are indicated in the stream registers to be locally cached. Reducing the number of snoop requests per processor increases system performance and reduces power.
• the snoop block 310 additionally includes a stream register block 430 and snoop token control block 426.
• each port snoop filter 400a,...,40On monitors all memory read access requests 412 from its associated processor which miss in the processor's Ll level cache. This information is also provided to the stream register block 430 for use as will be described in greater detail herein.
• the filters may be arranged in parallel or in series (in which case the output of one filter is the input to the next, for example). If a filter has inputs from more than one source (i.e., is shared between multiple sources), it has to have its own input queue and an arbiter to serialize snoop requests. A final ordered subset of all snoop requests is placed in the snoop queue 472, and snoop requests are forwarded to the processor via the processor snoop interface 474.
• no snoop request is forwarded to the snoop queue 506 and the snoop queue arbiter 508. If no match is found in the snoop cache 502a,...,502n for the current snoop request, the address of the snoop requests is added to the snoop cache using the signals 514a,...,514n. Concurrently, the snoop request is forwarded to the snoop queue 506.
• the "tag" field of the snoop request is checked against all tag fields in the snoop cache associated with the snoop source i. If the snoop request address tag is the same as one of the address tags stored in the snoop cache, the address tag field has hit in the snoop cache. After this, the valid line vector of the snoop cache entry for which a hit was detected is compared to the valid line vector of the snoop request. If the bit of the valid line vector in the snoop cache line corresponding to the bit set in the valid line vector of the snoop request is set, the valid line vector has hit as well.
• FIG. 6 there is depicted the control flow for updating two stream register sets and the cache wrap detection logic block for the replaced cache lines.
• all stream registers and masks are reset and the cache wrap detection logic is cleared as indicated at step 750, and first set of registers is activated.
• the address of the memory request is added to a first set of stream registers, referred to as an active address stream register set. All address stream registers from the first set of registers are checked to select the best match — as specified by the implemented register selection criteria; alternately, the first empty stream register may be selected.
• step 764 determines if a cache wrap condition exists. If no cache wrap event is detected in the step 764, the system waits for the next processor memory request by returning to step 760. If, however, the cache wrap event is detected, the first set of registers and masks will be used again. Thus, all registers and. paired masks from the first set of registers are reset, the cache wrap detection logic is cleared in the step 766. The first set of registers are going to be used again as active for approximating the content of the cache, and the control flow is looped back to the step 752.
• S_new S_old bit-wise-or V. This keeps a Scoreboard of the number of different bits in each group that occur simultaneously.
• Figure 19(a) particularly depicts one embodiment of logic implemented for detecting the wrap of a single partition of a single set (set "z" in the embodiment depicted) within the logic block 920.
• this logic When this logic has detected a wrap in set i, it asserts the set_wrap(i) signal 910.
• Figure 19(b) shows how the individual set_wrap(i) 910 signals from all N sets of the cache are combined with a logic OR function to produce the cache_wrap 912 signal, which asserts when the entire cache (i.e. all sets) have wrapped. It is understood that the logic and circuitry depicted in Figures 19(a) and 19(b) is only one example implementation and skilled artisans will recognize that many variations and modifications may be made thereof without departing from the scope of the invention.
• a third embodiment of the cache wrap detection logic will work with a cache that implements any replacement policy, including least recently used and random.
• a Scoreboard 940 is used to keep track of the precise cache way 914 that is overwritten. Specifically, it is used to detect the first write to any way.
• a counter 942 keeps track of the number of times that a Scoreboard bit was first set (i.e. goes from 0 tol). It does this by only counting Scoreboard writes where the overwritten bit (old_bit) is zero.
• the counter 942 is pre-loaded to the partition size 936 (i.e. number of ways in the partition), so once this counter reaches zero, the entire cache partition has wrapped. This is indicated by the cache_wrap 912 signal being asserted, causing the counter 942 to be reloaded (assuming Load takes precedence over Down) and the Scoreboard 940 to be cleared (i.e. reset).
• the operation of a filter subunit is programmable.
• This can be in the form of configurable aspects of a snoop filter, e.g., by configuring programmable aspects such as associativity of the cache being snooped, the coherence architecture being implemented, and so forth.
• the filter subunit is implemented in programmable microcode, whereby a programmable engine executes a sequence of instructions to implement the aspects of one or more preferred embodiments described herein. In one aspect, this is a general microcode engine.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
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• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Memory System Of A Hierarchy Structure (AREA)

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• 2005
  • 2005-03-29 US US11/093,130 patent/US7392351B2/en not_active Expired - Fee Related
• 2006
  • 2006-03-17 EP EP06739000.5A patent/EP1864224B1/en not_active Expired - Lifetime
  • 2006-03-17 JP JP2008504137A patent/JP5120850B2/ja not_active Expired - Fee Related
  • 2006-03-17 KR KR1020077021818A patent/KR101013237B1/ko not_active Expired - Fee Related
  • 2006-03-17 CN CNB2006800101519A patent/CN100568206C/zh not_active Expired - Fee Related
  • 2006-03-17 WO PCT/US2006/010038 patent/WO2006104747A2/en not_active Ceased
• 2008
  • 2008-06-11 US US12/137,325 patent/US8135917B2/en not_active Expired - Fee Related

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