KR101013237B1 - 스트림 레지스터를 이용하여 스누프 요구를 필터링하는방법 및 장치 - Google Patents

스트림 레지스터를 이용하여 스누프 요구를 필터링하는방법 및 장치 Download PDF

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KR101013237B1
KR101013237B1 KR1020077021818A KR20077021818A KR101013237B1 KR 101013237 B1 KR101013237 B1 KR 101013237B1 KR 1020077021818 A KR1020077021818 A KR 1020077021818A KR 20077021818 A KR20077021818 A KR 20077021818A KR 101013237 B1 KR101013237 B1 KR 101013237B1
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snoop
cache
register
address
stream
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KR20070119653A (ko
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마티아스 에이 블럼리치
알렌 지 가라
발렌티나 살라퓨라
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인터내셔널 비지네스 머신즈 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020077021818A 2005-03-29 2006-03-17 스트림 레지스터를 이용하여 스누프 요구를 필터링하는방법 및 장치 Expired - Fee Related KR101013237B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/093,130 US7392351B2 (en) 2005-03-29 2005-03-29 Method and apparatus for filtering snoop requests using stream registers
US11/093,130 2005-03-29

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KR20070119653A KR20070119653A (ko) 2007-12-20
KR101013237B1 true KR101013237B1 (ko) 2011-02-08

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US (2) US7392351B2 (https=)
EP (1) EP1864224B1 (https=)
JP (1) JP5120850B2 (https=)
KR (1) KR101013237B1 (https=)
CN (1) CN100568206C (https=)
WO (1) WO2006104747A2 (https=)

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US20080183972A1 (en) * 2007-01-26 2008-07-31 James Norris Dieffenderfer Snoop Filtering Using a Snoop Request Cache
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CN104583956B (zh) 2012-06-15 2019-01-04 英特尔公司 用于实现加载存储重新排序和优化的指令定义
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TWI646422B (zh) 2012-06-15 2019-01-01 英特爾股份有限公司 在處理器中之免消歧義失序載入／儲存佇列方法、微處理器、和非暫態性電腦可讀取儲存媒體
US9274955B2 (en) * 2012-08-17 2016-03-01 Futurewei Technologies, Inc. Reduced scalable cache directory
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DE112013001361B4 (de) * 2013-03-15 2023-06-15 Tahoe Research, Ltd. System auf einem Chip, Verfahren, maschinenlesbares Medium und System für die Bereitstellung einer Snoop-Filterung zugeordnet mit einem Datenpuffer
US9058273B1 (en) 2013-12-20 2015-06-16 International Business Machines Corporation Frequency determination across an interface of a data processing system
US9639470B2 (en) * 2014-08-26 2017-05-02 Arm Limited Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit
US9507716B2 (en) * 2014-08-26 2016-11-29 Arm Limited Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit
US9727466B2 (en) * 2014-08-26 2017-08-08 Arm Limited Interconnect and method of managing a snoop filter for an interconnect
CN105793832B (zh) * 2014-09-18 2018-12-18 上海兆芯集成电路有限公司 处理器及其操作方法、以及计算机可读存储介质
KR102485999B1 (ko) * 2015-07-01 2023-01-06 삼성전자주식회사 마스터-사이드 필터를 포함하는 캐시 코히런트 시스템과 이를 포함하는 데이터 처리 시스템
US9626232B2 (en) * 2015-07-23 2017-04-18 Arm Limited Event queue management
US10268586B2 (en) * 2015-12-08 2019-04-23 Via Alliance Semiconductor Co., Ltd. Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests
US9900260B2 (en) 2015-12-10 2018-02-20 Arm Limited Efficient support for variable width data channels in an interconnect network
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US10262721B2 (en) * 2016-03-10 2019-04-16 Micron Technology, Inc. Apparatuses and methods for cache invalidate
US9990292B2 (en) * 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
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US10761985B2 (en) * 2018-08-02 2020-09-01 Xilinx, Inc. Hybrid precise and imprecise cache snoop filtering
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Also Published As

Publication number Publication date
US7392351B2 (en) 2008-06-24
WO2006104747A2 (en) 2006-10-05
JP5120850B2 (ja) 2013-01-16
US8135917B2 (en) 2012-03-13
EP1864224A2 (en) 2007-12-12
US20060224836A1 (en) 2006-10-05
EP1864224B1 (en) 2013-05-08
JP2008535093A (ja) 2008-08-28
CN101189590A (zh) 2008-05-28
KR20070119653A (ko) 2007-12-20
EP1864224A4 (en) 2011-08-10
CN100568206C (zh) 2009-12-09
US20080244194A1 (en) 2008-10-02
WO2006104747A3 (en) 2007-12-21

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