JP5119673B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit incorporating a circuit block that requires trimming after manufacturing in order to correct variations in the manufacturing process.

  For example, liquid crystal display panels are widely used in portable devices typified by cellular phones and PDAs (Personal Digital Assistance: personal digital assistants) that have become widespread in recent years. In order to realize multi-gradation of a liquid crystal display panel, a gradation voltage generation circuit that generates a plurality of gradation voltages corresponding to a desired number of gradations is configured in an IC (semiconductor integrated circuit). Such a gradation voltage generation circuit includes a plurality of voltage dividing resistors, and a plurality of gradation voltages are generated by dividing the reference voltage by the voltage dividing resistors.

  By the way, the luminance of the liquid crystal display panel is not determined only by the gradation voltage, but is influenced by the characteristics of the liquid crystal and the like constituting the liquid crystal display panel. Accordingly, the liquid crystal display panel has gradation characteristics specific to the manufacturer. Therefore, in the gradation voltage generation circuit built in the IC, it is necessary to set the gradation voltage in accordance with the specifications of each liquid crystal display panel. Furthermore, since variations in the manufacturing process also occur in individual ICs, such variations may be corrected after the IC is manufactured.

  In general, trimming is widely known as a means for correcting variations in the manufacturing process. There are various trimming techniques. For example, trimming data is stored in a storage circuit such as a fuse circuit or a non-volatile memory at the time of IC inspection or shipping adjustment, and this trimming data is latched when the IC is turned on. Trimming data is supplied from a holding circuit to a circuit block that requires trimming by taking it into a holding circuit such as a circuit or a register.

  However, the content held in the trimming holding circuit may be rewritten due to noise caused by static electricity. Therefore, Patent Document 1 below discloses a fuse circuit that is not affected by external noise without increasing the circuit scale. This fuse circuit is a fuse circuit for adjusting an analog value, and a latch circuit for storing a setting state of a fuse element and a latch clock for taking in the setting state of the fuse element in the latch circuit based on a periodic signal. The latch circuit periodically fetches the setting state of the fuse element based on the latch clock, and the analog value is adjusted based on the setting state of the fuse element fetched into the latch circuit. Is done.

According to Patent Document 1, the content held in the trimming holding circuit can be periodically refreshed, but power is consumed to read the trimming data stored in the storage circuit, so the refresh interval If the length is shortened, the power consumption of the IC is considerably increased. On the other hand, if the refresh interval is increased, there is a problem that the period during which the device malfunctions becomes longer when the contents of the trimming holding circuit are rewritten due to noise or the like. For example, when the frequency division ratio is set by trimming in the oscillation circuit, if the content of the trimming holding circuit is rewritten, a frequency different from the original frequency continues to be output.
JP 2004-103873 (first page, FIG. 1)

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit capable of refreshing the contents of a trimming holding circuit in a timely manner without increasing current consumption so much.

  In order to solve the above-described problem, a semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit including a circuit block that requires trimming after manufacturing, and includes a plurality of bits used for trimming the circuit block. A storage circuit for storing the trimming data, a holding circuit for holding the trimming data read from the storage circuit, and a corresponding bit of the trimming data held in the holding circuit from the first level to the second level A plurality of change detection circuits that output a positive pulse when changed and a negative pulse when the bit changes from the second level to the first level, and output from a plurality of change detection circuits A plurality of binary signal generation circuits that respectively generate a plurality of binary signals activated in response to positive or negative pulses, and a plurality of binary signals A logic circuit that activates a detection signal when at least one of a plurality of binary signals respectively generated by the generation circuit is activated, and a detection signal that is output from the logic circuit is activated, And a refresh circuit that updates the trimming data held in the holding circuit with the trimming data read from the storage circuit.

  Here, the storage circuit includes a fuse circuit having a plurality of fuses set in a state of being cut or not cut corresponding to a plurality of bits of trimming data, and the holding circuit is output from the refresh circuit A plurality of latch circuits may be included which read the setting states of the plurality of fuses in response to the signal and respectively hold a plurality of bits of trimming data corresponding to the setting states of the plurality of fuses.

  Alternatively, the storage circuit includes a non-volatile memory that stores multi-bit trimming data, and the holding circuit includes a register having a plurality of D flip-flops each holding multi-bit trimming data read from the non-volatile memory. It may be included.

  Each of the plurality of change detection circuits is a first detection unit having two P-channel MOS transistors in which a source and a drain are connected in series between a first power supply potential and an output node. The bit corresponding to the trimming data held in the circuit is input to the gate of one P-channel MOS transistor, and the bit is delayed and inverted and input to the gate of the other P-channel MOS transistor. A first detection unit that outputs a positive pulse when changing from a high level to a low level, and two N-channel MOS transistors in which a drain and a source are connected in series between an output node and a second power supply potential And the bit is input to the gate of one N-channel MOS transistor, and A second detection unit that outputs a negative pulse when the bit is delayed and inverted and input to the gate of the other N-channel MOS transistor and the bit changes from low level to high level, and two P-channel MOS transistors A potential setting unit for setting a predetermined potential between a high level and a low level at an output node when at least one of the transistors and at least one of the two N-channel MOS transistors are in an off state; You may make it.

  In that case, the first detection unit inverts the data output from the first delay circuit and the first delay circuit to which the corresponding bit of the trimming data held in the holding circuit is input, A first inverter that is applied to the gate of the P-channel MOS transistor, and the second detection unit includes a second delay circuit to which the bit is input and data output from the second delay circuit. And a second inverter that applies the voltage to the gate of the other N-channel MOS transistor, and the potential setting unit includes a first resistor connected between the first power supply potential and the output node. A second resistor connected between the output node and the second power supply potential may be included.

  Further, each of the plurality of binary signal generation circuits binarizes a signal output from a corresponding one of the plurality of change detection circuits based on a first determination potential larger than a predetermined potential. Thus, a first determination circuit that outputs a binary signal that is activated in response to a positive pulse of the signal, and a second determination potential that is smaller than a predetermined potential is used as the signal output from the change detection circuit. A second determination circuit that outputs a binary signal that is activated in response to a negative pulse of the signal, and a binary signal that is output from the first determination circuit; A second logic circuit that generates a binary signal representing the logical sum by obtaining a logical sum with the binary signal output from the second determination circuit may be included.

  According to the present invention, since the refresh is performed when the trimming data held in the holding circuit changes due to noise or the like, the current consumption is not increased so much. Further, since the holding circuit is refreshed immediately after the trimming data changes, the period during which the device malfunctions can be shortened as much as possible to avoid actual harm.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit includes a circuit block 100 that requires trimming after manufacturing. Specifically, the circuit block 100 corresponds to a gradation voltage generation circuit, an oscillation circuit, a D / A (digital / analog) conversion circuit, an A / D (analog / digital) conversion circuit, and the like.

  For example, a liquid crystal driver IC for driving a liquid crystal display panel in which TFTs (Thin Film Transistors) are arranged in a two-dimensional matrix generates a plurality of gradation voltages, and these gradation voltages are used as a source drive circuit. Has a built-in gradation voltage generation circuit for supplying to The gradation voltage generation circuit generates a plurality of output voltages by dividing the stabilized power supply voltage by a plurality of resistors. After the liquid crystal driver IC is manufactured, the output voltage can be adjusted (trimmed) by short-circuiting some of the resistors by a switch circuit.

  Referring to FIG. 1, the semiconductor integrated circuit according to the present embodiment includes a fuse circuit 10 having a plurality of fuses set in a cut or uncut state corresponding to a plurality of bits of trimming data, and Based on the set state of the fuse, a plurality of latch circuits 21 to 28 holding the multi-bit trimming data TD1 to TD8 and a change in the trimming data TD1 to TD8 held in the latch circuits 21 to 28 are detected and detected. The detection circuit 30 that activates the signal for a predetermined period and the trimming data read from the fuse circuit 10 when the detection signal output from the detection circuit 30 is activated are held in the latch circuits 21 to 28. And a refresh circuit 40 for updating the trimming data TD1 to TD8. Here, as an example, the number of bits of trimming data is 8 bits.

The fuse circuit 10 corresponds to a storage circuit that stores trimming data corresponding to a state where a plurality of fuses are cut or not cut. A power supply potential V _DD is supplied to one end of the plurality of fuses, and the other end is connected to the latch circuits 21 to 28. Each of the latch circuits 21 to 28 includes an inverter and a NOR circuit. When a high level pulse is supplied from the refresh circuit 40 as a latch clock signal, the setting states of a plurality of fuses are read and This corresponds to a holding circuit that holds a plurality of bits of trimming data TD1 to TD8 corresponding to the set state.

  The detection circuit 30 activates the detection signal for a predetermined period when at least one bit of the multi-bit trimming data TD1 to TD8 held in the latch circuits 21 to 28 changes. The refresh circuit 40 outputs a high-level pulse as a latch clock signal when resetting when power is turned on and when a detection signal output from the detection circuit 30 is activated. As a result, the trimming data held in the latch circuits 21 to 28 is updated, and the latch circuits 21 to 28 are refreshed.

  As described above, even when the trimming data held in the latch circuits 21 to 28 is rewritten due to noise or the like, the latch circuits 21 to 28 are immediately refreshed, so that the period during which the device malfunctions is minimized. be able to. The refresh circuit 40 may be configured not to output the latch clock signal pulse for a while after the latch clock signal pulse is output once. Thus, when the trimming data is rewritten due to noise or the like, it is possible to prevent the refresh from being performed twice.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 2, the semiconductor integrated circuit includes a non-volatile memory (E ² PROM) 50 storing multi-bit trimming data TD1 to TD8, and a multi-bit trimming data TD1 read from the non-volatile memory 50. A register 60 having a plurality of D flip-flops 61 to 68 for holding TD8, a detection circuit 30 for detecting a change in the trimming data TD1 to TD8 held in the register 60 and activating a detection signal for a predetermined period; And a refresh circuit 70 that updates the trimming data TD1 to TD8 held in the register 60 with the trimming data read from the nonvolatile memory 50 when the detection signal output from the detection circuit 30 is activated. It is out. Here, as an example, the number of bits of trimming data is 8 bits.

  The nonvolatile memory 50 corresponds to a storage circuit that stores trimming data, and reads and outputs the trimming data in response to a read signal output from the refresh circuit 70. The register 60 corresponds to a holding circuit that holds trimming data. The D flip-flops 61 to 68 input data when the latch clock signal input from the refresh circuit 70 to the clock signal input terminal C rises to a high level. The multi-bit trimming data input to the terminal D is held.

  The detection circuit 30 activates the detection signal for a predetermined period when at least one bit of the multi-bit trimming data TD1 to TD8 held in the D flip-flops 61 to 68 changes. The refresh circuit 70 activates the read signal for a predetermined period at the time of reset when the power is turned on and when the detection signal output from the detection circuit 30 is activated, and as a latch clock signal Outputs a high level pulse. As a result, a plurality of bits of trimming data is read from the nonvolatile memory 50, whereby the trimming data held in the D flip-flops 61 to 68 is updated, and the register 60 is refreshed.

  Thus, even when the trimming data held in the register 60 is rewritten due to noise or the like, the register 60 is immediately refreshed, so that the period during which the device malfunctions can be shortened as much as possible. The refresh circuit 70 may not activate the read signal and the latch clock signal for a while after once activating the read signal and the latch clock signal. Thus, when the trimming data is rewritten due to noise or the like, it is possible to prevent the refresh from being performed twice.

Next, a specific example of the detection circuit used in the semiconductor integrated circuit according to the first and second embodiments will be described.
FIG. 3 is a diagram illustrating a specific example of a detection circuit used in the semiconductor integrated circuit according to the first and second embodiments. As shown in FIG. 3, the detection circuit 30 includes a plurality of change detection circuits 311 to 318, a plurality of binary signal generation circuits 321 to 328, and a logic circuit configured by a plurality of OR circuits 331 to 337. It is out.

  The change detection circuits 311 to 318 output a positive pulse when the corresponding bits of the trimming data TD1 to TD8 held in the holding circuit change from the first level to the second level, and the bits are When changing from the second level to the first level, a negative pulse is output.

  For example, the change detection circuit 311 includes a first detection unit including two P-channel MOS transistors QP1 and QP2, a delay circuit 31, and an inverter 32, two N-channel MOS transistors QN1 and QN2, and a delay circuit 33. And a second detection unit configured by the inverter 34 and a potential setting unit configured by the resistors R1 and R2. Here, each of the delay circuits 31 and 33 can be configured by connecting a plurality of gates (for example, inverters) in series. The configuration of the other change detection circuits 312 to 318 is the same as that of the change detection circuit 311.

The sources and drains of the transistors QP1 and QP2 are connected in series between the first power supply potential V _DD and the output node N4. The first bit TD1 of trimming data is input to the gate (node N1) of the transistor QP1, and the first bit TD1 of trimming data is delayed and delayed by the delay circuit 31 and the inverter 32 to the gate (node N2) of the transistor QP2. Inverted and input. As a result, as shown in FIG. 4, when the level of the node N1 changes from the high level to the low level, the level of the node N2 also becomes the low level during the period corresponding to the delay time of the delay circuit 31, and the transistors QP1 and Both QP2 are turned on, and a positive pulse (potential V _DD ) is output to the output node N4. Even if the position of the transistor QP1 and the position of the transistor QP2 are reversed, the same result can be obtained.

The drains and sources of the transistors QN2 and QN1 are connected in series between the output node N4 and a second power supply potential V _SS (in this embodiment, the ground potential). The first bit TD1 of trimming data is input to the gate (node N1) of the transistor QN1, and the first bit TD1 of trimming data is delayed by the delay circuit 33 and the inverter 34 to the gate (node N3) of the transistor QN2. Inverted and input. As a result, as shown in FIG. 4, when the level of the input node N1 changes from the low level to the high level, the level of the node N3 also becomes the high level during the period corresponding to the delay time of the delay circuit 33, and the transistor QN1 And QN2 are both turned on, and a negative pulse (potential V _SS ) is output to the output node N4. Note that the same result can be obtained even if the position of the transistor QN1 and the position of the transistor QN2 are reversed.

Resistor R1 is connected between a first power supply potential V _DD and an output node N4, the resistor R2 is connected between the output node N4 and the second power supply potential V _SS. When at least one of the transistors QP1 and QP2 and at least one of the transistors QN1 and QN2 are in an off state, the potential of the output node 4 is set by the resistors R1 and R2. Accordingly, the potential of the output node 4 becomes a predetermined potential (R2 · V _DD + R1 · V _SS ) / (R1 + R2) between the high level (V _DD ) and the low level (V _SS ), but the resistor R1 And the value of the resistor R2 are equal to each other, the potential of the output node 4 becomes (V _DD + V _SS ) / 2 as shown in FIG. Thus, the signals output from each of the change detection circuits 311 to 318 are ternary signals. A plurality of ternary signals output from the change detection circuits 311 to 318 are input to the corresponding binary signal generation circuits 321 to 328, respectively.

  For example, the binary signal generation circuit 321 is output from the change detection circuit 311 and the first determination circuit 35 that outputs a binary signal that is activated in response to the positive pulse output from the change detection circuit 311. A second determination circuit 36 that outputs a binary signal that is activated in response to a negative pulse, a binary signal that is output from the first determination circuit 35, and a second signal that is output from the second determination circuit 36. It includes a logic circuit (OR circuit) 37 that generates a binary signal representing the logical sum by obtaining a logical sum with the binary signal. Other configurations of the binary signal generation circuits 322 to 328 are the same as those of the binary signal generation circuit 321.

The first determination circuit 35 is configured by a buffer that binarizes the ternary signal input from the change detection circuit 311 based on the _first determination potential V1, and as illustrated in FIG. A binary signal S1 that is activated in response to the included positive pulse P1 is output. The second judging circuit 36 is constituted by a ternary signal inputted from the change detecting circuit 311 second determination potential V ₂ 2 binarized by inverter for inverting on the basis of, as shown in FIG. 5, A binary signal S2 that is activated in response to a negative pulse P2 included in the ternary signal is output.

Here, the relationship between the determination potentials V ₁ and V ₂ and the power supply potentials V _DD and V _SS is set as follows.
V _SS <V ₂ <(R 2 · V _DD + R 1 · V _SS ) / (R ₁ + R 2) <V ₁ <V _DD
In particular, when the value of the resistor R1 is equal to the value of the resistor R2, this relationship is set as follows.
V _SS <V ₂ <(V _DD + V _SS ) / 2 <V ₁ <V _DD
More preferably, this relationship is set as follows.
V ₁ = (3V _DD + V _SS ) / 4, V ₂ = (V _DD + 3V _SS ) / 4

  The OR circuit 37 calculates a logical sum of the binary signal output from the first determination circuit 35 and the binary signal output from the second determination circuit 36, thereby obtaining a binary signal representing the logical sum. Generate. Accordingly, the binary signal generation circuits 321 to 328 can generate a plurality of binary signals that are activated in response to positive or negative pulses output from the change detection circuits 311 to 318, respectively. Further, the logic circuit constituted by the OR circuits 331 to 337 activates the detection signal when at least one of the plurality of binary signals generated by the binary signal generation circuits 321 to 328 is activated. Turn into. Therefore, the detection signal can be activated when at least one bit of the trimming data held in the holding circuit changes.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the specific example of the detection circuit in 1st and 2nd embodiment. FIG. 4 is a diagram for explaining the operation of the change detection circuit shown in FIG. 3. FIG. 4 is a diagram for explaining the operation of the binary signal generation circuit shown in FIG. 3.

Explanation of symbols

10 fuse circuit, 21 to 28 latch circuit, 30 detection circuit, 31, 33 delay circuit, 32, 34 inverter, 35 first determination circuit, 36 second determination circuit, 37 OR circuit, 40, 70 refresh circuit, 50 Nonvolatile memory (E ² PROM), 60 registers, 61-68 D flip-flop, 100 circuit block requiring trimming, 311 to 318 change detection circuit, 321 to 328 binary signal generation circuit, 331 to 337 OR circuit, R1, R2 resistors, QP1, QP2 P-channel MOS transistors, QN1, QN2 N-channel MOS transistors

Claims (6)

A semiconductor integrated circuit having a circuit block that requires trimming after manufacturing,
A storage circuit for storing a plurality of bits of trimming data used for trimming the circuit block;
A holding circuit for holding trimming data read from the storage circuit;
When the corresponding bit of the trimming data held in the holding circuit changes from the first level to the second level, a positive pulse is output, and the bit is changed from the second level to the first level. A plurality of change detection circuits that output a negative pulse when changed, and
A plurality of binary signal generation circuits that respectively generate a plurality of binary signals that are activated in response to positive or negative pulses output from the plurality of change detection circuits;
A logic circuit that activates a detection signal when at least one of a plurality of binary signals respectively generated by the plurality of binary signal generation circuits is activated;
A refresh circuit for updating trimming data held in the holding circuit with trimming data read from the storage circuit when a detection signal output from the logic circuit is activated;
A semiconductor integrated circuit comprising: The storage circuit includes a fuse circuit having a plurality of fuses set in a state of being cut or not cut corresponding to a plurality of bits of trimming data;
A plurality of latches for reading the setting states of the plurality of fuses in response to a signal output from the refresh circuit and holding a plurality of bits of trimming data corresponding to the setting states of the plurality of fuses; The semiconductor integrated circuit according to claim 1, comprising a circuit. The storage circuit includes a non-volatile memory for storing a plurality of bits of trimming data;
The semiconductor integrated circuit according to claim 1, wherein the holding circuit includes a register having a plurality of D flip-flops each holding a plurality of bits of trimming data read from the nonvolatile memory. Each of the plurality of change detection circuits is
Correspondence of trimming data held in the holding circuit, which is a first detection unit having two P-channel MOS transistors whose source and drain are connected in series between the first power supply potential and the output node When the bit is input to the gate of one P-channel MOS transistor, the bit is delayed and inverted and input to the gate of the other P-channel MOS transistor, and the bit changes from high level to low level. The first detector for outputting a positive pulse;
A second detection unit having two N-channel MOS transistors whose drain and source are connected in series between the output node and a second power supply potential, wherein the bit is the gate of one N-channel MOS transistor; And the bit is delayed and inverted and input to the gate of the other N-channel MOS transistor, and a negative pulse is output when the bit changes from low level to high level. And
When at least one of the two P-channel MOS transistors and at least one of the two N-channel MOS transistors are in an off state, a predetermined potential between a high level and a low level is applied to the output node. A potential setting section to be set;
The semiconductor integrated circuit according to claim 1, comprising: The first detection unit inverts the data output from the first delay circuit and the first delay circuit to which the corresponding bit of the trimming data held in the holding circuit is input, and the other And a first inverter applied to the gate of the P-channel MOS transistor.
The second detection unit inverts the data output from the second delay circuit to which the bit is input and the second delay circuit and applies the inverted data to the gate of the other N-channel MOS transistor. And further having an inverter
A first resistor connected between the first power supply potential and the output node; and a second resistor connected between the output node and the second power supply potential. The semiconductor integrated circuit according to claim 4, further comprising: Each of the plurality of binary signal generation circuits includes:
By binarizing a signal output from a corresponding one of the plurality of change detection circuits based on a first determination potential that is larger than a predetermined potential, it corresponds to a positive pulse of the signal. A first determination circuit for outputting a binary signal to be activated;
By binarizing the signal output from the change detection circuit based on a second determination potential smaller than a predetermined potential, a binary signal activated in response to a negative pulse of the signal is output. A second determination circuit that
A second signal for generating a binary signal representing the logical sum is obtained by calculating a logical sum of the binary signal output from the first determination circuit and the binary signal output from the second determination circuit. Logic circuit;
The semiconductor integrated circuit according to claim 5, comprising:

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