JP2008192959A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which refreshes the content of a holding circuit for trimming, timely without increasing power consumption excessively. <P>SOLUTION: The semiconductor integrated circuit incorporates a circuit block requiring trimming after it is manufactured. The semiconductor integrated circuit has: a storage circuit for storing trimming data used for trimming the circuit block; a holding circuit for holding the trimming data read from the storage circuit; a detection circuit for detecting a change in the trimming data held by the holding circuit to change the logic level of a detection signal; and a refresh circuit for updating the trimming data held by the holding circuit by the trimming data read from the storage circuit when the logic level of the detection signal outputted from the detection circuit is changed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit incorporating a circuit block that requires trimming after manufacturing in order to correct variations in the manufacturing process.

  For example, liquid crystal display panels are widely used in portable devices typified by cellular phones and PDAs (Personal Digital Assistance: personal digital assistants) that have become widespread in recent years. In order to realize multi-gradation of a liquid crystal display panel, a gradation voltage generation circuit that generates a plurality of gradation voltages corresponding to a desired number of gradations is configured in an IC (semiconductor integrated circuit). Such a gradation voltage generation circuit includes a plurality of voltage dividing resistors, and a plurality of gradation voltages are generated by dividing the reference voltage by the voltage dividing resistors.

  By the way, the luminance of the liquid crystal display panel is not determined only by the gradation voltage, but is influenced by the characteristics of the liquid crystal and the like constituting the liquid crystal display panel. Accordingly, the liquid crystal display panel has gradation characteristics specific to the manufacturer. Therefore, in the gradation voltage generation circuit built in the IC, it is necessary to set the gradation voltage in accordance with the specifications of each liquid crystal display panel. Furthermore, since variations in the manufacturing process also occur in individual ICs, such variations may be corrected after the IC is manufactured.

  In general, trimming is widely known as a means for correcting variations in the manufacturing process. There are various trimming techniques. For example, trimming data is stored in a storage circuit such as a fuse circuit or a non-volatile memory at the time of IC inspection or shipping adjustment, and this trimming data is latched when the IC is turned on. Trimming data is supplied from a holding circuit to a circuit block that requires trimming by taking it into a holding circuit such as a circuit or a register.

  However, the content held in the trimming holding circuit may be rewritten due to noise caused by static electricity. Therefore, Patent Document 1 below discloses a fuse circuit that is not affected by external noise without increasing the circuit scale. This fuse circuit is a fuse circuit for adjusting an analog value, and a latch circuit for storing a setting state of a fuse element and a latch clock for taking in the setting state of the fuse element in the latch circuit based on a periodic signal. The latch circuit periodically fetches the setting state of the fuse element based on the latch clock, and the analog value is adjusted based on the setting state of the fuse element fetched into the latch circuit. Is done.

According to Patent Document 1, the content held in the trimming holding circuit can be periodically refreshed, but power is consumed to read the trimming data stored in the storage circuit, so the refresh interval If the length is shortened, the power consumption of the IC is considerably increased. On the other hand, if the refresh interval is increased, there is a problem that the period during which the device malfunctions becomes longer when the contents of the trimming holding circuit are rewritten due to noise or the like. For example, when the frequency division ratio is set by trimming in the oscillation circuit, if the content of the trimming holding circuit is rewritten, a frequency different from the original frequency continues to be output.
JP 2004-103873 (first page, FIG. 1)

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit capable of refreshing the contents of a trimming holding circuit in a timely manner without increasing current consumption so much.

  In order to solve the above-described problem, a semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit including a circuit block that requires trimming after manufacturing, and includes trimming data used for trimming the circuit block. A storage circuit for storing the trimming data read from the storage circuit, a detection circuit for detecting a change in the trimming data held in the holding circuit and changing the logic level of the detection signal, And a refresh circuit that updates the trimming data held in the holding circuit with the trimming data read from the storage circuit when the logic level of the detection signal output from the detection circuit changes.

  Here, the storage circuit includes a fuse circuit having a plurality of fuses set in a state of being cut or not cut corresponding to a plurality of bits of trimming data, and the holding circuit is output from the refresh circuit A plurality of latch circuits may be included which read the setting states of the plurality of fuses in response to the signal and respectively hold a plurality of bits of trimming data corresponding to the setting states of the plurality of fuses.

  Alternatively, the storage circuit includes a non-volatile memory that stores multi-bit trimming data, and the holding circuit includes a register having a plurality of D flip-flops each holding multi-bit trimming data read from the non-volatile memory. It may be included.

  In addition, the detection circuit has a plurality of delay circuits that respectively input a plurality of bits of trimming data held in the holding circuit, a plurality of bits of trimming data that are held in the holding circuit, and a plurality of delay circuits that are output from the plurality of delay circuits A plurality of first logic circuits for detecting a change in trimming data of a plurality of bits held in the holding circuit by obtaining an exclusive OR with the bit trimming data, and a plurality of first logic circuits; A second logic circuit that activates the detection signal in a predetermined period when at least one bit of the trimming data held in the holding circuit changes based on the output signal may be included.

  Alternatively, the detection circuit inputs a plurality of bits of trimming data held in the holding circuit to the first terminal, a plurality of first capacitors, a second terminal of the plurality of first capacitors, and a reference potential The ethics of the detection signal when at least one bit of the trimming data held in the holding circuit changes by detecting the change in the voltage across the second capacitor and the second capacitor connected between A change detection circuit for changing the level may be included.

  Alternatively, the detection circuit may include a plurality of first capacitors that input a plurality of bits of trimming data held in the holding circuit to the first terminal, a second terminal of the plurality of first capacitors, and a reference potential. A second capacitor connected between the first capacitor, a first change detector that detects an increase in the voltage across the second capacitor, and a second change detector that detects a decrease in the voltage across the second capacitor Based on the output signal of the first change detection unit and the output signal of the second change detection unit, the detection signal in a predetermined period when at least one bit of the trimming data held in the holding circuit changes And a logic circuit that activates.

  According to the present invention, since the refresh is performed when the trimming data held in the holding circuit changes due to noise or the like, the current consumption is not increased so much. Further, since the holding circuit is refreshed immediately after the trimming data changes, the period during which the device malfunctions can be shortened as much as possible to avoid actual harm.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit includes a circuit block 100 that requires trimming after manufacturing. Specifically, the circuit block 100 corresponds to a gradation voltage generation circuit, an oscillation circuit, a D / A (digital / analog) conversion circuit, an A / D (analog / digital) conversion circuit, and the like.

  For example, a liquid crystal driver IC for driving a liquid crystal display panel in which TFTs (Thin Film Transistors) are arranged in a two-dimensional matrix generates a plurality of gradation voltages, and these gradation voltages are used as a source drive circuit. Has a built-in gradation voltage generation circuit to be supplied to The gradation voltage generation circuit generates a plurality of output voltages by dividing the stabilized power supply voltage by a plurality of resistors. After the liquid crystal driver IC is manufactured, the output voltage can be adjusted (trimmed) by short-circuiting some of the resistors by a switch circuit.

  Referring to FIG. 1, the semiconductor integrated circuit according to the present embodiment includes a fuse circuit 10 having a plurality of fuses set in a cut or uncut state corresponding to a plurality of bits of trimming data, and Based on the set state of the fuse, a plurality of latch circuits 21 to 28 holding the multi-bit trimming data TD1 to TD8 and a change in the trimming data TD1 to TD8 held in the latch circuits 21 to 28 are detected and detected. The detection circuit 30 that changes the logic level of the signal and the trimming data read from the fuse circuit 10 when the logic level of the detection signal output from the detection circuit 30 changes are held in the latch circuits 21 to 28. And a refresh circuit 40 for updating the trimming data TD1 to TD8. Here, as an example, the number of bits of trimming data is 8 bits.

The fuse circuit 10 corresponds to a storage circuit that stores trimming data corresponding to a state where a plurality of fuses are cut or not cut. A power supply potential V _DD is supplied to one end of the plurality of fuses, and the other end is connected to the latch circuits 21 to 28. Each of the latch circuits 21 to 28 includes an inverter and a NOR circuit. When a high level pulse is supplied from the refresh circuit 40 as a latch clock signal, the setting states of a plurality of fuses are read and This corresponds to a holding circuit that holds a plurality of bits of trimming data TD1 to TD8 corresponding to the set state.

  The detection circuit 30 changes the logic level of the detection signal when at least one bit of the multi-bit trimming data TD1 to TD8 held in the latch circuits 21 to 28 changes. The refresh circuit 40 outputs a high-level pulse as a latch clock signal when resetting when power is turned on and when the logic level of the detection signal output from the detection circuit 30 changes. As a result, the trimming data held in the latch circuits 21 to 28 is updated, and the latch circuits 21 to 28 are refreshed.

  As described above, even when the trimming data held in the latch circuits 21 to 28 is rewritten due to noise or the like, the latch circuits 21 to 28 are immediately refreshed, so that the period during which the device malfunctions is minimized. be able to. The refresh circuit 40 may be configured not to output the latch clock signal pulse for a while after the latch clock signal pulse is output once. Thus, when the trimming data is rewritten due to noise or the like, it is possible to prevent the refresh from being performed twice.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 2, the semiconductor integrated circuit includes a non-volatile memory (E ² PROM) 50 storing multi-bit trimming data TD1 to TD8, and a multi-bit trimming data TD1 read from the non-volatile memory 50. A register 60 having a plurality of D flip-flops 61 to 68 for holding TD8, a detection circuit 30 for detecting a change in the trimming data TD1 to TD8 held in the register 60 and changing the logic level of the detection signal; And a refresh circuit 70 that updates the trimming data TD1 to TD8 held in the register 60 with the trimming data read from the nonvolatile memory 50 when the logic level of the detection signal output from the detection circuit 30 changes. It is out. Here, as an example, the number of bits of trimming data is 8 bits.

  The nonvolatile memory 50 corresponds to a storage circuit that stores trimming data, and reads and outputs the trimming data in response to a read signal output from the refresh circuit 70. The register 60 corresponds to a holding circuit that holds trimming data. The D flip-flops 61 to 68 input data when the latch clock signal input from the refresh circuit 70 to the clock signal input terminal C rises to a high level. The multi-bit trimming data input to the terminal D is held.

  The detection circuit 30 changes the logic level of the detection signal when at least one bit of the multi-bit trimming data TD1 to TD8 held in the D flip-flops 61 to 68 changes. The refresh circuit 70 activates the read signal for a predetermined period at the time of resetting when the power is turned on and when the logic level of the detection signal output from the detection circuit 30 changes, and the latch clock signal Output a high-level pulse. As a result, a plurality of bits of trimming data is read from the nonvolatile memory 50, whereby the trimming data held in the D flip-flops 61 to 68 is updated, and the register 60 is refreshed.

  Thus, even when the trimming data held in the register 60 is rewritten due to noise or the like, the register 60 is immediately refreshed, so that the period during which the device malfunctions can be shortened as much as possible. The refresh circuit 70 may not activate the read signal and the latch clock signal for a while after once activating the read signal and the latch clock signal. Thus, when the trimming data is rewritten due to noise or the like, it is possible to prevent the refresh from being performed twice.

Next, a specific example of the detection circuit used in the semiconductor integrated circuit according to the first and second embodiments will be described.
FIG. 3 is a diagram showing a first specific example of the detection circuit used in the semiconductor integrated circuit according to the first and second embodiments. As shown in FIG. 3, the detection circuit 30 includes a plurality of delay circuits 311 to 318 that receive a plurality of bits of trimming data TD1 to TD8 held in the holding circuit, and a plurality of bits of trimming held in the holding circuit. A plurality of exclusives for detecting a change in the plurality of bits of trimming data held in the holding circuit by obtaining an exclusive OR of the data TD1 to TD8 and the plurality of bits of trimming data output from the delay circuits 311 to 318. Based on the output signals of the OR (EOR) circuits 321 to 328 and the EOR circuits 321 to 328, the detection signal is activated in a predetermined period when at least one bit of the trimming data held in the holding circuit changes. OR circuit 33 to be included. Here, each of the delay circuits 311 to 318 can be configured by connecting a plurality of gates (for example, inverters) in series.

  If the trimming data does not change, the output signals of the EOR circuits 321 to 328 are maintained at a low level. When any bit of the trimming data changes from high level to low level, or changes from low level to high level, the output signal of the corresponding EOR circuit becomes high level. The period during which the output signal is high is determined by the delay time of the corresponding delay circuit. As a result, the detection signal output from the OR circuit 33 is also activated to a high level in the same period.

  FIG. 4 is a diagram showing a second specific example of the detection circuit used in the semiconductor integrated circuit according to the first and second embodiments. In this example, no delay circuit is used. As shown in FIG. 4, the detection circuit 30 includes a plurality of capacitors C1 to C8 that input a plurality of bits of trimming data TD1 to TD8 held in the holding circuit to a first terminal, and second capacitors C1 to C8. And the 8-bit held in the holding circuit by detecting the change in the voltage across the capacitor C0 and the capacitor C0 connected between the terminal of the capacitor and the reference potential (in this embodiment, the ground potential). And a change detection circuit 34 that changes the logic level of the detection signal when at least one bit of the trimming data TD1 to TD8 changes.

Here, it is assumed that the trimming data takes the power supply potential V _DD as the high level and the ground potential as the low level. When the capacitances of the capacitors C1 to C8 are C _A and the capacitance of the capacitor C0 is C _B , the change ΔV in the voltage across the capacitor C0 when the logic level of 1 bit among the 8 bits of the trimming data changes is expressed by the following equation: It is represented by
ΔV = V _DD · C _A / (8C _A + C _B )

In particular, when C _A = C _B , the change ΔV in the voltage across the capacitor C0 is a value obtained by dividing the power supply potential V _DD by nine. In order to detect this voltage change ΔV, the change detection circuit 34 includes a decoupling capacitor C9 having a capacity sufficiently smaller than the capacities of the capacitors C0 to C8, high resistances R1 to R4 for bias, and high resistance for feedback. R5 and a comparator 35 are included.

For example, by setting all the resistance values of the resistors R1 to R4 to be equal, the potentials of the non-inverting input terminal and the inverting input terminal of the comparator 35 are approximately the midpoint potential V _DD / 2. Therefore, even if the voltage change ΔV is not a very large value, this can be detected. Further, by providing hysteresis characteristics with the feedback resistor R5, it is possible to prevent malfunctions due to variations in resistance values, noise, and the like. The change detection circuit 34 maintains the detection signal at a high level when detecting a positive voltage change ΔV, and maintains the detection signal at a low level when detecting a negative voltage change ΔV. As a result, the ethical level of the detection signal can be changed when at least one bit of the trimming data held in the holding circuit changes. However, in this detection circuit, a change in trimming data cannot be detected when a positive voltage change continues or a negative voltage change continues.

  FIG. 5 is a diagram showing a third specific example of the detection circuit used in the semiconductor integrated circuit according to the first and second embodiments. As shown in FIG. 5, the detection circuit 30 includes a plurality of capacitors C1 to C8 that input a plurality of bits of trimming data TD1 to TD8 held in the holding circuit to a first terminal, and second capacitors C1 to C8. And the trimming data held in the holding circuit by detecting the change in the voltage across the capacitor C0 and the capacitor C0 connected between the terminal of the capacitor C0 and the reference potential (in this embodiment, the ground potential). And a change detection circuit 36 that activates a detection signal for a predetermined period when at least one bit of the signal changes.

The change detection circuit 36 includes a first change detection unit having a decoupling capacitor C10, a biasing high resistance R10, a clamping diode D10, and a buffer 37 for determining a signal level. The reference potential V _R1 applied to the resistor R10 and the anode of the diode D10 is, for example, a value slightly lower than the midpoint potential V _DD / 2. Accordingly, when the voltage across the capacitor C0 increases, the first change detection unit detects this, and the output signal of the buffer 37 becomes high level for a predetermined period.

Further, the change detection circuit 36 includes a second change detection unit having a decoupling capacitor C11, a biasing high resistance R11, a clamping diode D11, and an inverter 38 for determining a signal level. The reference potential V _R2 applied to the resistor R11 and the cathode of the diode D11 is, for example, a value slightly higher than the midpoint potential V _DD / 2. Therefore, when the voltage across the capacitor C0 decreases, the second change detection unit detects this, and the output signal of the inverter 38 becomes high level for a predetermined period.

  The OR circuit 39 obtains a logical sum of the output signal of the buffer 37 and the output signal of the inverter 38, and based on these signals, when the voltage across the capacitor C0 increases or decreases, the OR circuit 39 outputs a detection signal as a predetermined signal. Activate in the period. Therefore, the detection signal can be activated when at least one bit of the trimming data held in the holding circuit changes.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the 1st specific example of the detection circuit in 1st and 2nd embodiment. The figure which shows the 2nd specific example of the detection circuit in 1st and 2nd embodiment. The figure which shows the 3rd specific example of the detection circuit in 1st and 2nd embodiment.

Explanation of symbols

10 fuse circuit, 21-28 latch circuit, 30 detection circuit, 40, 70 refresh circuit, 50 nonvolatile memory (E ² PROM), 60 register, 61-68 D flip-flop, 100 circuit block requiring trimming, 311 318 delay circuit, 321 to 328 EOR circuit, 33 OR circuit C1 to C11 capacitor, 34 and 36 change detection circuit, 35 comparator, 37 buffer, 38 inverter, 39 OR circuit, R1 to R5, R10, R11 resistor, D10, D11 Diode

Claims (6)

A semiconductor integrated circuit having a circuit block that requires trimming after manufacturing,
A storage circuit for storing trimming data used for trimming the circuit block;
A holding circuit for holding trimming data read from the storage circuit;
A detection circuit for detecting a change in trimming data held in the holding circuit and changing a logic level of a detection signal;
A refresh circuit that updates trimming data held in the holding circuit with trimming data read from the storage circuit when a logic level of a detection signal output from the detection circuit changes;
A semiconductor integrated circuit comprising: The storage circuit includes a fuse circuit having a plurality of fuses set in a state of being cut or not cut corresponding to a plurality of bits of trimming data;
A plurality of latches for reading the setting states of the plurality of fuses in response to a signal output from the refresh circuit and holding a plurality of bits of trimming data corresponding to the setting states of the plurality of fuses; The semiconductor integrated circuit according to claim 1, comprising a circuit. The storage circuit includes a non-volatile memory for storing a plurality of bits of trimming data;
The semiconductor integrated circuit according to claim 1, wherein the holding circuit includes a register having a plurality of D flip-flops each holding a plurality of bits of trimming data read from the nonvolatile memory. The detection circuit comprises:
A plurality of delay circuits that respectively input a plurality of bits of trimming data held in the holding circuit;
A plurality of bits held in the holding circuit by respectively obtaining an exclusive OR of the plurality of bits of trimming data held in the holding circuit and the plurality of bits of trimming data output from the plurality of delay circuits. A plurality of first logic circuits for detecting a change in the trimming data of
A second logic circuit that activates a detection signal in a predetermined period when at least one bit of trimming data held in the holding circuit changes based on output signals of the plurality of first logic circuits When,
The semiconductor integrated circuit according to claim 1, comprising: The detection circuit comprises:
A plurality of first capacitors that respectively input a plurality of bits of trimming data held in the holding circuit to a first terminal;
A second capacitor connected between a second terminal of the plurality of first capacitors and a reference potential;
A change detection circuit that changes the ethical level of the detection signal when at least one bit of the trimming data held in the holding circuit changes by detecting a change in the voltage across the second capacitor;
The semiconductor integrated circuit according to claim 1, comprising: The detection circuit comprises:
A plurality of first capacitors that respectively input a plurality of bits of trimming data held in the holding circuit to a first terminal;
A second capacitor connected between a second terminal of the plurality of first capacitors and a reference potential;
A first change detector for detecting an increase in voltage across the second capacitor;
A second change detector for detecting a decrease in voltage across the second capacitor;
Based on the output signal of the first change detection unit and the output signal of the second change detection unit, a predetermined period when at least one bit of the trimming data held in the holding circuit changes A logic circuit for activating the detection signal;
The semiconductor integrated circuit according to claim 1, comprising:

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