JP2006338780A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To repair fuse information to be normal by speedily carrying out self repairing operation without supplying power again when the fuse information is set to be in an erroneous state. <P>SOLUTION: A semiconductor storage device 20 includes memory cell arrays 1a to 1m, memory cell replacement judging circuits 2a to 2m, fuse information holding circuits 3a to 3m, fuse information holding control circuits 4a to 4m, and a refresh control circuit 5. The fuse information holding circuits 3a to 3m include self-repairing circuits for speedily repairing fuse information different from fuse information held in advance to the fuse information held in advance when initialization which is carried out after supplying power is finished. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device having a fuse circuit.

  In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a spare memory cell is provided in advance as a repair measure when a defect occurs in a part of a memory cell array, and a defective memory cell is based on fuse information. A method of replacing with a spare memory cell is frequently used (for example, see Patent Document 1).

  In a semiconductor memory device having a fuse circuit described in Patent Document 1, a set state of a fuse latch circuit is evaluated based on a pulse signal during initialization setting after power is turned on, and a fuse set in error Only the latch circuit is newly set to a normal state.

For this reason, if the fuse information is different from the “High” level or “Low” level correct fuse information stored in advance due to a malfunction, an incorrect setting state will occur unless the power is turned on again. There is a problem that cannot be corrected. In addition, after the initialization setting performed after the power is turned on, if the fuse information is changed to incorrect fuse information that is different from the correct fuse information stored in “High” level or “Low” level, the fuse information is changed. There is a problem that it is not corrected. Further, when incorrect fuse information is generated, the repair operation is not performed immediately, so that the failure mode may persist and the characteristics of the semiconductor memory device may be deteriorated, resulting in an increase in current consumption of the semiconductor memory device. There is a point.
Japanese Patent Laid-Open No. 10-69798 (page 6, FIG. 1 and page 7, FIG. 4)

  The present invention provides a semiconductor memory device having a fuse circuit capable of quickly performing self-repair operation without restoring power and restoring fuse information to a normal state when fuse information is set in an incorrect state. .

  In order to achieve the above object, a semiconductor memory device according to one embodiment of the present invention reads a refresh control circuit that generates a refresh signal, a first fuse that stores fuse information, and reads and holds the fuse information when power is turned on. Thereafter, a first reading and holding unit that reads and holds the fuse information again based on the refresh signal from the refresh control circuit, and the fuse information that is held in advance in the first reading and holding unit includes the fuse information. And a fuse information holding circuit having a first self-repairing means for self-repairing to the previously held fuse information.

  To achieve the above object, a semiconductor memory device according to another aspect of the present invention includes a memory cell array having memory cells and spare memory cells, a refresh control circuit for generating a refresh signal, a power-on signal, and the refresh signal. The fuse information holding control circuit that controls reading and holding of fuse information, the first fuse that holds fuse information, and the fuse information is read and held by the power-on signal from the fuse information holding control circuit After that, based on the refresh signal from the fuse information holding control circuit, a first reading holding means for reading and holding the fuse information again, and the fuse information held in advance in the first reading holding means Changed to fuse information in a different state from the relevant fuse information A fuse information holding circuit having a first self-repairing means for self-repairing to the previously stored fuse information, and based on the fuse information output from the fuse information holding circuit, And a memory cell replacement determination circuit for determining which of the spare memory cells is to be replaced with which spare cell.

  According to the present invention, when a fuse information is set in an incorrect state, a semiconductor memory device having a fuse circuit that can quickly perform a self-repair operation without restoring power and restore the fuse information to a normal state. Can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor memory device. In this embodiment, a plurality of fuse information holding circuits are provided in a semiconductor memory device as a DRAM.

  As shown in FIG. 1, the semiconductor memory device 20 includes a memory cell array 1a to a memory cell array 1m, a memory cell replacement determination circuit 2a to a memory cell replacement determination circuit 2m, a fuse information holding circuit 3a to a fuse information holding circuit 3m, and fuse information. A holding control circuit 4a to a fuse information holding control circuit 4m and a refresh control circuit 5 are provided.

  Here, a plurality of the memory cell array 1, the memory cell replacement determination circuit 2, the fuse information holding circuit 3, and the fuse information holding control circuit 4 are provided, and the memory cell array 1a and the memory cell array 1m, the memory cell replacement determination circuit 2a and the memory are provided. The cell replacement determination circuit 2m, the fuse information holding circuit 3a and the fuse information holding circuit 3m, and the fuse information holding control circuit 4a and the fuse information holding control circuit 4m have the same configuration.

  In the semiconductor memory device 20, when the semiconductor memory device 20 is first turned on, a power-on completion signal PowerOn notifying that the internal potential setting is completed is sent to the fuse information holding control circuit 4a to the fuse information holding control circuit 4m, respectively. Entered.

  The fuse information holding control circuit 4a inputs a power-on completion signal PowerOn and then outputs a fuse information initialization signal bFPUP0 to the fuse information holding circuit 3a. Then, after a predetermined time has elapsed, the fuse information holding control circuit 4a outputs a fuse information confirmation signal FPUP0 to the fuse information holding circuit 3a.

  The refresh control circuit 5 generates a plurality of refresh signals RFSH, for example, outputs the refresh signal RFSH0 to the memory cell array 1a and the fuse information holding control circuit 4m at a predetermined interval, and holds the refresh signal RFSHm to the memory cell array 1m and the fuse information. Output to the control circuit 4a.

  The fuse information holding circuit 3a is provided between the memory cell replacement determination circuit 2a and the fuse information holding control circuit 4a, and is also called a fuse latch circuit. The fuse information holding signal 3FP is initialized by the fuse information initialization signal bFPUP0, and the fuse information determination signal The fuse information is read by FPUP0 and held. Then, even after the initialization setting performed after power-on is completed, even if the fuse information is changed to incorrect fuse information, a self-recovery function for restoring the information to correct fuse information is provided. A detailed description of the self-repair function will be given later. Here, correct fuse information is fuse information in a state of “High” level or “Low” level stored in advance, and incorrect fuse information is a fuse in a state different from the state stored in advance. Information.

  The memory cell replacement determination circuit 2a is provided between the memory cell array 1a and the fuse information holding circuit 3a. Based on the fuse information output from the fuse information holding circuit 3a, which memory cell is replaced with which spare cell A determination is made every time a memory cell is accessed.

  The memory cell array 1a has a plurality of memory cells and spare memory cells, and receives the refresh signal RFSH0 output from the refresh control circuit 5 and the signal output from the memory cell replacement determination circuit 2a. Based on these signals, the defective memory cell is replaced with a spare memory cell and functions as a correct memory cell.

  Next, every time the refresh signal RFSHm is input, the fuse information holding control circuit 4a outputs the fuse information initialization signal bFPUP0 and the fuse information confirmation signal FPUP0 to the fuse information holding circuit 3a. Repeat reading and holding of fuse information. Even after the initialization setting performed after the power is turned on, even if the fuse information is changed to incorrect fuse information, the incorrect fuse information is quickly restored to correct fuse information by the self-recovery function of the fuse information holding circuit 3a. .

  Here, the memory cell array 1m, the memory cell replacement determination circuit 2m, the fuse information holding circuit 3m, and the fuse information holding control circuit 4m are respectively a memory cell array 1a, a memory cell replacement determination circuit 2a, a fuse information holding circuit 3a, and a fuse information. Since it is similar to the holding control circuit 4a, the description thereof is omitted.

  Next, a specific circuit configuration of the fuse information holding circuit will be described with reference to FIGS. FIG. 2 is a circuit diagram showing a fuse information holding circuit, and FIG. 3 is a block diagram showing a self-restoring circuit in the fuse information holding circuit.

  As shown in FIG. 2, the fuse information holding circuit 3a includes a first fuse 6a, a first self-restoring circuit 7a, and a first fuse information reading and holding unit 60a. The first fuse information reading and holding unit 60a includes Nch MOS transistors N1 to Nch MOS transistor N5 and Pch MOS transistors P1 to Pch MOS transistor P4, and reads and holds fuse information held in the first fuse 6a. To do.

  In the Pch MOS transistor P1, the source is connected to the high potential side power supply Vcc, the drain is connected to the drain of the Nch MOS transistor N1, and the fuse information initialization signal (node 30) bFPUP0 as a reset signal is input to the gate. N-channel MOS transistor N1 receives a fuse information determination signal (node 31) FPUP0 as a set signal at its gate.

  The first fuse 6a has one end connected to the source of the Nch MOS transistor N1 and the other end connected to the low potential side power source Vss. Here, the first fuse 6a can be cut by a laser or the like. For example, a laser fuse made of a polycrystalline silicon film is used. However, a fuse that can electrically change the circuit state or an EEPROM (Electrically Erasable Programmable). Read Only Memory) may be used.

  The Pch MOS transistor P2 has a source connected to the high potential side power supply Vcc, a drain connected to the drain of the Nch MOS transistor N2, and a gate that is an output terminal of the drain of the Pch MOS transistor P1 and the drain of the Nch MOS transistor N1. 32. The Nch MOS transistor N2 has a source connected to the low potential side power supply Vss and a gate connected to the node 32. The Pch MOS transistor P2 and the Nch MOS transistor N2 function as a first inverter INV1 that inverts the signal level of the node 32, and outputs an inverted signal to the node 33 that is the output terminal.

  The Pch MOS transistor P3 has a source connected to the high potential side power supply Vcc, a drain connected to the drain of the Nch MOS transistor N5 and the node 32, and a gate connected to the output side of the first inverter INV1. The source of the Nch MOS transistor N5 is connected to the drain of the Nch MOS transistor N3, and the fuse information initialization signal (node 30) bFPUP is input to the gate. The Nch MOS transistor N3 has a source connected to the low potential side power supply Vss and a gate connected to the output side of the first inverter INV1. The Pch MOS transistor P3 and the Nch MOS transistor N3 function as the second inverter INV2 when the Nch MOS transistor N5 is turned on when the fuse information initialization signal (node 30) bFPUP is at “High” level.

  Here, the first inverter INV1 and the second inverter INV2 function as a latch circuit. A fuse conduction information signal INTACT, which is a signal of the node 33, is output outside the fuse information holding circuit 3a.

  The Pch MOS transistor P4 has a source connected to the high potential side power supply Vcc, a drain connected to the drain of the Nch MOS transistor N4, and a gate connected to the node 33. The Nch MOS transistor N4 has a source connected to the low potential side power supply Vss and a gate connected to the node 33. The Pch MOS transistor P4 and the Nch MOS transistor N4 function as a third inverter INV3 that inverts the signal level of the node 33, and outputs an inverted signal of the fuse cutting information signal BROWN to the node 34 as the output terminal. To do. The fuse cutting information signal BROWN is output outside the fuse information holding circuit 3a.

  The first self-healing circuit 7a has one end connected to the node 34 and the other end connected to the node 32. The node 34 receives the information of the node 34, repairs the information of the node 34, and returns correct fuse information as a feedback. 32.

  As shown in FIG. 3, the first self-restoring circuit 7a includes a delay circuit 8, a first clocked inverter CINV1 to a third clocked inverter CINV3, a fourth inverter INV4 to a sixth inverter INV6, The circuit includes a 2-input NAND circuit NAND1 and a 2-input XOR (also called Ex-OR) circuit XOR1.

  The first clocked inverter CINV1 includes a fuse cutting information signal BROWN at the node 34, an inverted trigger signal bTRG that is an inverted signal of the trigger signal TRG at the gate of the high potential side transistor, and a trigger signal TRG at the gate of the low potential side transistor. Is output and an output signal is output to the node 35 which is an output terminal. Here, an external clock signal is used as the trigger signal TRG, but a clock signal in the semiconductor memory device 20 such as a self-refresh command signal may be used.

  The second clocked inverter CINV2 is provided between the clocked inverter CINV1 and the XOR circuit XOR1, the output signal of the clocked inverter CINV1 (the signal of the node 35), the trigger signal TRG, An inversion trigger signal bTRG is input to the gate of the potential side transistor, and a logic operation is performed to output an output signal to the node 36 which is an output terminal.

  The XOR circuit XOR1 inputs the fuse cutting information signal BROWN of the node 34 and the output signal of the second clocked inverter CINV2 of the node 36, and performs a logic operation to output an output signal to the node 37 which is an output terminal. Here, when the signal level of the node 34 and the signal level of the node 36 are both “High” level or “Low” level, the XOR circuit XOR1 outputs a “Low” level signal. When the signal levels of 36 are different, a “High” level signal is output.

  The delay circuit 8 is provided between the XOR circuit XOR1 and the fourth inverter INV4, and includes an inverter chain that delays the signal at the node 37. Here, instead of the inverter chain, a delay resistor, a delay capacitor, or an RC circuit may be used for the delay circuit 8. The fourth inverter INV4 is provided between the delay circuit 8 and the 2-input NAND circuit NAND1, inverts the signal output from the delay circuit 8, and outputs an output signal to the node 38 that is the output end.

  The NAND circuit NAND1 receives the signal of the node 37 and the signal of the node 38 that is the output signal of the fourth inverter INV4, and performs a logical operation to output an output signal to the node 39 that is the output terminal. Here, the NAND circuit NAND1 outputs a “Low” level signal when the signal level of the node 37 and the signal level of the node 38 are both “High” level, and otherwise outputs a “High” level signal. Output.

  The fifth inverter INV5 is provided between the second clocked inverter CINV2 and the third clocked inverter CINV3, receives the signal of the node 36, and inverts this signal. The sixth inverter INV6 receives the signal of the node 39, inverts this signal, and outputs an output signal to the node 40 that is the output terminal.

  The third clocked inverter CINV3 performs logical operation by inputting the output signal of the fifth inverter INV5, the signal of the node 39 to the gate of the transistor on the high potential side, and the signal of the node 40 to the gate of the transistor on the low potential side. Output the output signal. Here, the output signal of the third clocked inverter CINV3 is output to the node 32 as feedback.

  Next, the operation of the fuse information holding circuit will be described with reference to FIG. FIG. 4 is a timing chart circuit diagram showing the operation of the fuse information holding circuit. Here, the fuse is cut in advance, and the fuse cutting information signal BROWN is set to the “High” level.

  As shown in FIG. 4, when the fuse cutting information signal BROWN is “High” level as correct information, the signal level of the node 32 is “High”, the signal level of the node 35 is “Low”, and the signal level of the node 36 is The signal level of the node 37 is set to “Low”, the signal level of the node 38 is set to “High”, and the signal level of the node 39 is set to “High”.

  Next, for example, a transistor or a circuit in the fuse information holding circuit 3a malfunctions due to a soft error caused by an alpha ray entering from the outside, and the signal at the node 32 is “Low” level, fuse information. When the fuse cutting information signal BROWN, which is the output signal of the holding circuit 3a, becomes “Low” level, which is incorrect information, the XOR circuit XOR1 outputs the “Low” level fuse cutting information signal BROWN and the node 36 “High”. A level signal is input to perform logical operation. As a result, the signal at the node 37 at the output end changes from the “Low” level to the “High” level. Here, due to the delay occurrence by the delay circuit 8, the signal at the node 38 at the output terminal of the inverter INV4 is maintained at the “High” level for a predetermined period.

  Subsequently, the NAND circuit NAND1 inputs the “High” level signal of the node 37 and the “High” level signal of the node 38 and performs a logical operation. As a result, the signal at the node 39 at the output end changes from the “High” level to the “Low” level.

  The third clocked inverter CINV3 includes a “Low” level signal output from the fifth inverter INV5, a “Low” level signal at the node 39 at the gate of the high potential side transistor, and a low potential side transistor. The “Hgih” level signal of the node 40 is input to the gate of No. 4 to perform a logical operation. As a result, the output signal of the third clocked inverter CINV3 changes from the “Low” level to the “High” level.

  Next, the output signal of the third clocked inverter CINV3 is restored to the “High” level signal which is the correct information of the “Low” level signal which is incorrect information, and is fed back to the node 32 as correct information. The fuse cutting information signal BROWN, which is the output signal of the fuse information holding circuit 3a, is restored to the correct information at the “High” level. Here, the period until the erroneous information is repaired is the sum of the time required for the operations of the XOR circuit XOR1, the NAND circuit NAND1, the sixth inverter INV6, and the third clocked inverter CINV3.

  In parallel, the “High” level fuse cutting information signal BROWN is input to the self-repair circuit 7, the signal of the node 37 changes from “High” level to “Low” level which is correct information, and the signal of the node 39 becomes “Low”. The data is sequentially restored from the “level” to the “High” level which is correct information. As a result, each node of the first self-repair circuit 7a has the original correct information level.

  As described above, in the semiconductor memory device of the present embodiment, fuse information is once read into the fuse information holding circuit 3a when the power is turned on, and the fuse information is held again every time a refresh signal is output thereafter. Since it is read by the circuit 3a, it can be restored to the correct state any number of times without turning on the power even if the held fuse information becomes incorrect.

  Further, the fuse information holding circuit 3a is provided with a self-repair circuit 7a for restoring correct fuse information when incorrect fuse information is generated after completion of initialization setting performed after power-on. Even if no signal is output, it can be quickly restored to the correct state.

In this embodiment, a MOS transistor (also referred to as a MOSFET) whose gate insulating film is a silicon oxide film is used. However, the gate insulating film is a stacked layer of silicon nitride film (Si ₃ N ₄ ) / silicon oxide film. A MIS transistor (also referred to as a MISFET) made of a film, a SiNxOy film obtained by thermally nitriding a silicon oxide film, or a high dielectric film (High-K gate insulating film) may be used. Further, although fuse information is used for replacement with spare memory cells, the fuse in the fuse information holding circuit may be used as information means for changing or correcting the characteristics of a specific circuit.

  Next, a semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. 5 is a block diagram showing a redundancy control circuit used in a semiconductor memory device as a DRAM, FIG. 6 is a circuit diagram showing an enable fuse information holding circuit, FIG. 7 is a circuit diagram showing a disable fuse information holding circuit, and FIG. Is a block showing a self-healing circuit in the disable fuse information holding circuit. In this embodiment, the fuse information holding circuit, the enable fuse information holding circuit, and the disable fuse information holding circuit are provided with a self-recovery function corresponding to the generation of erroneous fuse information after the initialization setting at the time of power-on. ing.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the redundancy control circuit 50 includes a fuse information holding circuit 3a to a fuse information holding circuit 3n, an enable fuse information holding circuit 8, a disable fuse information holding circuit 9, a comparison circuit 10a to a comparison circuit 10n, and A logic circuit 11 is provided.

  In the redundancy control circuit 50, the input address signal is compared with the address programmed by the fuse, and a selection signal corresponding to the comparison result is output. By this signal, either the memory cell selection word line or the spare memory cell selection word line is selected. Further, when the set spare memory cell selection word line cannot be used for storing data, the spare memory cell selection word line cannot be used by the disable fuse information holding circuit 9.

  Here, the fuse information holding circuit 3 and the comparison circuit 10 are provided in the same number as the number of bits of the address signals A0 to An, respectively, and the fuse information holding circuit 3a to the fuse information holding circuit 3n and the comparison circuit 10a to the comparison circuit 10n are respectively provided. It is the same configuration. Note that illustrations and descriptions relating to the memory cell selection word line are omitted.

  The comparison circuit 10a receives the address signal A0 and the output signal output from the fuse information holding circuit 3a, and compares the signals. The comparison circuit 10n receives the address signal An and the output signal output from the fuse information holding circuit 3n, and compares the signals.

  The logic circuit 11 inputs the output signal output from the comparison circuit 10a to the comparison circuit 10n, the output signal output from the enable fuse information holding circuit 8, and the output signal output from the disable fuse information holding circuit 9. A word line selection signal RWL is output to instruct whether or not redundancy is activated by performing a logic operation. When the word line selection signal RWL is at “High” level, the spare memory cell selection word line is activated.

  As shown in FIG. 6, the enable fuse information holding circuit 8 includes a second fuse 6b, a second self-restoring circuit 7b, and a second fuse information reading and holding unit 60b. With the same configuration as the circuit 3a, the fuse conduction information signal INTACT is not output, and only the fuse cutting information signal BROWN is output. The second fuse information reading and holding unit 60b includes Nch MOS transistors N1 to Nch MOS transistor N5 and Pch MOS transistors P1 to Pch MOS transistor P4, and reads and holds fuse information held in the second fuse 6b. To do.

  In the Pch MOS transistor P1, the source is connected to the high potential side power supply Vcc, the drain is connected to the drain of the Nch MOS transistor N1, and the fuse information initialization signal (node 30) bFPUP as a reset signal is input to the gate. The Nch MOS transistor N1 has a gate to which a fuse information determination signal (node 31) FPUP as a set signal is input.

  Here, the fuse is cut in advance, the fuse cutting information signal BROWN is set to “High” level, the transistor or circuit in the enable fuse information holding circuit 8 malfunctions due to a soft error or the like, and the fuse cutting information signal BROWN is erroneous. When the information becomes the “Low” level, the second self-repair circuit 7b operates to quickly restore the fuse cutting information signal BROWN to the “High” level that is correct information.

  As shown in FIG. 7, the disable fuse information holding circuit 9 includes a third fuse 6c, a third self-healing circuit 7c, and a third fuse information reading holding unit 60c. The third inverter INV3 is omitted from the holding circuit 3a, and only the fuse conduction information signal INTACT is output. The third fuse information reading and holding unit 60c includes Nch MOS transistors N1 to Nch MOS transistors N3, Nch MOS transistors N5, and Pch MOS transistors P1 to Pch MOS transistors P3, and is held in the third fuse 6c. Read and hold fuse information.

  As shown in FIG. 8, the third self-repair circuit 7c includes a delay circuit 8, a first clocked inverter CINV1 to a third clocked inverter CINV3, a fourth inverter INV4 to a seventh inverter INV7, and two inputs. The circuit includes a NAND circuit NAND1 and a two-input XOR (also called Ex-OR) circuit XOR1, and a seventh inverter INV7 is added to the first self-repair circuit 7a of the first embodiment.

  The seventh inverter INV7 receives the fuse conduction information signal INTACT output from the disable fuse information holding circuit 9, inverts the signal, and outputs an inverted signal to the node 41 that is the output terminal. Note that the signal level of the node 41 is the same as the signal level of the node 34.

  Here, the fuse is cut in advance, the fuse conduction information signal INTACT is set to the “Low” level, the transistor or the circuit in the disable fuse information holding circuit 9 malfunctions due to a soft error or the like, and the fuse conduction information signal INTACT is erroneous. When the “High” level is reached, the third self-repair circuit 7 c operates to quickly restore the fuse conduction information signal INTACT to the “Low” level, which is the correct information.

  As described above, in the semiconductor memory device of this embodiment, the fuse information holding circuit 3a to the fuse information holding circuit 3n and the enable fuse information holding circuit 8 are erroneously set after the initialization setting performed after power-on is completed. A second self-healing circuit 7b is provided for restoring the correct fuse information when fuse information is generated. When the set spare memory cell selection word line cannot be used to store data, the disable fuse information holding circuit 9 that disables the use of the spare memory cell selection word line is provided after the power is turned on. A third self-repair circuit 7c is provided for restoring the correct fuse information when incorrect fuse information is generated after the initialization setting is completed.

  For this reason, in addition to the effects of the first embodiment, even if erroneous fuse information is generated in the enable fuse information holding circuit 8 and the disable fuse information holding circuit 9, it can be quickly restored to the correct state. When the spare memory cell selection word line thus made cannot be used for storing data, the spare memory cell selection word line can be surely disabled.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the first and second embodiments, the fuse information holding circuit having a self-repair function is applied to the DRAM, but may be applied to a semiconductor memory device such as an SRAM (Static Random Access Memory) or an EEPROM. In addition, the fuse information holding circuit and the fuse information holding circuit in which the fuse has an ECC (Error Check and Correct) function are provided in the semiconductor memory device without providing a self-restoring circuit in the fuse information holding circuit, so that the wrong fuse When information is generated, a hold data inversion failure of the fuse information holding circuit may be detected, and a self-repair operation may be performed based on the detected signal.

1 is a block diagram showing a semiconductor memory device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a fuse information holding circuit according to Embodiment 1 of the present invention. 1 is a block diagram showing a self-repair circuit in a fuse information holding circuit according to Embodiment 1 of the present invention. 3 is a timing chart showing the operation of the fuse information holding circuit according to the first embodiment of the present invention. The block diagram which shows the redundancy control circuit which concerns on Example 2 of this invention. FIG. 6 is a circuit diagram illustrating an enable fuse information holding circuit according to a second embodiment of the invention. FIG. 6 is a circuit diagram showing a disable fuse information holding circuit according to Embodiment 2 of the present invention. The block diagram which shows the self-repair circuit in the disable fuse information holding circuit which concerns on Example 2 of this invention.

Explanation of symbols

1a, 1m Memory cell array 2a, 2m Memory cell replacement determination circuit 3a, 3m Fuse information holding circuit 4a, 4m Fuse information holding control circuit 5 Refresh control circuit 6a First fuse 6b Second fuse 6c Third fuse 7a First Self-repair circuit 7b Second self-repair circuit 7c Third self-repair circuit 8 Enable fuse information holding circuit 9 Disable fuse information holding circuit 10a, 10n Comparison circuit 11 Logic circuit 20 Semiconductor memory devices 30 to 41 Node 50 Redundancy control Circuit 60a First fuse information reading and holding unit 60b Second fuse information reading and holding unit 60c Third fuse information reading and holding unit bFPUP, bFPUP0, bFPUPm Fuse information initialization signal BROWN Fuse cutting information signal bTRG Inversion trigger No. CINV1-3 Clocked inverters FPUP, FPUP0, FPUPm Fuse information determination signal INTACT Fuse conduction information signals INV1-7 INVERTER N1-5 Nch MOS transistor NAND1 NAND circuit P1-4 Pch MOS transistor PowerOn Power-on completion signal RFSH0, RFSHm RWL Word line selection signal TRG Trigger signal Vcc High potential side power supply Vss Low potential side power supply XOR1 XOR (Ex-OR) circuit

Claims (5)

A refresh control circuit for generating a refresh signal;
A first fuse for holding fuse information; and a first reading and holding means for reading and holding the fuse information again based on the refresh signal from the refresh control circuit after reading and holding the fuse information upon power-on. The first self-healing means for self-repairing to the previously held fuse information when the fuse information previously held in the first reading and holding means is changed to fuse information in a state different from the fuse information. A fuse information holding circuit comprising:
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, wherein the fuse is used for replacement with a spare memory cell, or for changing or correcting characteristics of a specific circuit. A memory cell array having memory cells and spare memory cells;
A refresh control circuit for generating a refresh signal;
A fuse information holding control circuit that inputs a power-on signal and the refresh signal, and controls reading and holding of fuse information;
A first fuse that holds fuse information; and the fuse information is read and held by the power-on signal from the fuse information holding control circuit, and then the fuse information is based on the refresh signal from the fuse information holding control circuit. The first reading holding means for reading again and holding, and when the fuse information held in advance in the first reading holding means is changed to fuse information in a state different from the fuse information, the information is stored in advance. A fuse information holding circuit having first self-healing means for self-healing to fuse information;
A memory cell replacement determining circuit for determining which address of the memory cell is to be replaced with which spare cell of the spare memory cell based on the fuse information output from the fuse information holding circuit; ,
A semiconductor memory device comprising: A refresh control circuit for generating a refresh signal;
First fuse that holds fuse information of fuse cutting information or fuse conduction information, and after reading and holding the fuse information upon power-on, the fuse information is read and held again based on the refresh signal from the refresh control circuit When the fuse information held in advance in the first reading holding means and the first reading holding means is changed to fuse information in a state different from the fuse information, the fuse information held in advance is self-repaired. A fuse information holding circuit for outputting the fuse cutting information signal and the fuse conduction information signal;
A second fuse that holds fuse information of fuse cutting information or fuse conduction information, and after reading and holding the fuse information upon power-on, the fuse information is read and held again based on the refresh signal from the refresh control circuit When the fuse information held in advance in the second reading holding means and the second reading holding means changes to fuse information in a state different from the fuse information, the fuse information held in advance An enable fuse information holding circuit for outputting the fuse cutting information signal, and having a second self-healing means for repairing;
A third fuse that holds fuse information of fuse cutting information or fuse conduction information, and after reading and holding the fuse information upon power-on, the fuse information is read and held based on the refresh signal from the refresh control circuit When the fuse information held in advance in the third reading and holding means and the third reading and holding means is changed to fuse information in a state different from the fuse information, self-repair is performed to the previously held fuse information. The spare memory cell selection word line when the spare memory cell selection word line cannot be used for storing data, and outputs the fuse conduction information signal. Disabling enable fuse information holding circuit that disables
A semiconductor memory device comprising:   The fuse information holding circuit includes a fuse having one end connected to a low potential power source, a first Pch MOS transistor having a source connected to a high potential power source, and a gate to which a fuse information initialization signal is input, a drain Is connected to the drain of the first Pch MOS transistor, the source is connected to the other end of the fuse, and the first Nch MOS transistor that inputs a fuse information determination signal to the gate; and the first Pch MOS transistor A first inverter that inverts a signal output from a drain and a drain of the first Nch MOS transistor; a second Nch MOS transistor that inputs the fuse information initialization signal to a gate; and a first inverter When an output signal is input, the second Nch MOS transistor is turned on. Read holding means comprising: a second inverter that operates as an inverter and outputs an inverted signal to the input side of the first inverter; and a third inverter that inverts the output signal of the first inverter; , One end is connected to the input side of the first inverter, the other end is connected to the output side of the third inverter, and the fuse information previously held in the read holding means is different from the fuse information. 2. The information processing apparatus according to claim 1, further comprising: a self-recovery circuit that self-repairs the fuse information stored in advance when the fuse information is changed, and the first and second inverters function as a latch circuit. 5. The semiconductor memory device according to any one of items 1 to 4.

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