JP2015207329A - Semiconductor device and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform redundancy relief on a word line to be relieved having a defective memory cell by using a relieving redundant word line, while holding data accumulated in memory cells on the word line to be relieved even after the redundancy relief.SOLUTION: A semiconductor device is configured to break an anti-fuse element and replace a word line to be relieved with a relieving redundant word line. Data held in memory cells on the word line to be relieved is copied to redundant memory cells on the relieving redundant word line.

Description

  The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device capable of replacing a defective memory cell with a redundant cell and a control method thereof.

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory), the capacity is increasing with the improvement of the miniaturization technology. However, as miniaturization progresses, the number of memory cell defects in the memory array due to crystal defects and impurities tends to increase.

  In order to relieve a defect in a memory cell, a system in which a spare memory cell is provided in advance in a memory chip and a defective memory cell is replaced in units of rows or columns has been put into practical use. For example, Patent Document 1 describes a semiconductor memory device in which a defective memory cell can be replaced even after package sealing.

  Also, JEDEC (Joint Electron Device Engineering Council), an industry group of semiconductors, uses an antifuse element in a DRAM to redundantly repair a word line in which a defective memory cell exists (that is, a memory cell on the source word line) In recent years, a specification called “PPR (Post Package Repair)” has been adopted as a specification for replacing a redundant memory cell on a redundant word line as a repair destination.

  In PPR, even when unnecessary memory cells are replaced with redundant memory cells, a refresh command (Auto Refresh) can be interrupted and data on a memory cell array other than a bank to be relieved by PPR is required to be retained. ing.

  That is, in PPR, data held in memory cells on word lines other than the word line to be repaired is retained after redundancy repair by a refresh operation. On the other hand, the value held in the memory cell on the word line to be repaired in which a defective memory cell exists is not guaranteed after redundancy repair.

Japanese Patent Laid-Open No. 11-16385

  The entire disclosure of the above patent document is incorporated herein by reference. The following analysis was made by the present inventors.

  As described above, in the PPR (Post Package Repair) specification, data stored in memory cells on word lines other than the word line to be repaired is held based on a refresh operation. On the other hand, since the memory cells on the word line to be repaired are replaced with the redundant memory cells on the redundant word line to which no value is written, the value is guaranteed for the data held in the memory cell on the word line to be repaired It has not been.

  A semiconductor device according to a first aspect of the present invention is a semiconductor device configured to destroy an antifuse element and replace a repair-source word line with a repair-destination redundant word line, on the repair-source word line. The data held in the memory cell is copied to the redundant memory cell on the redundant word line of the rescue destination.

  According to a second aspect of the present invention, there is provided a method for controlling a semiconductor device, comprising: a step in which a semiconductor device destroys an antifuse element and replaces a repair-source word line with a repair-destination redundant word line; Copying the data held in the memory cell to the redundant memory cell on the redundant word line of the rescue destination.

  According to the semiconductor device and the control method thereof according to the present invention, when the anti-fuse element is destroyed and the repair-source word line is replaced with the repair-destination redundant word line, the data held in the memory cell on the repair-source word line is repaired. By copying to the redundant memory cell on the previous redundant word line, it is possible to retain the data stored in the memory cell on the original word line after the redundant relief.

1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment. It is a block diagram which illustrates the structure of the circuit relevant to PPR and PPR copy. It is a block diagram which illustrates the detailed structure of a column address control circuit. FIG. 3 is a circuit diagram illustrating a configuration of an interrupt control circuit. It is a circuit diagram which illustrates the composition of a counter circuit. 3 is a circuit diagram illustrating a configuration of a PPR copy control circuit. FIG. It is a table which illustrates operation | movement of a PPR copy control circuit. 6 is a timing diagram illustrating an operation of PPR copy of the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view illustrating the structure of an antifuse element provided in the AF circuit of the semiconductor device according to the first embodiment. FIG.

  First, an outline of one embodiment will be described. Note that the reference numerals of the drawings attached to this summary are merely examples for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  FIG. 1 is a block diagram illustrating the configuration of a semiconductor device according to an embodiment. In the semiconductor device according to the embodiment, the anti-fuse element is destroyed and the relief source word line (the word line WL of the memory cell array 101) is replaced with the relief destination redundancy word line (the redundancy word line provided in the row redundancy circuit 102). The data stored in the memory cells on the relief source word line is copied to the redundancy memory cells on the relief destination redundant word line.

  According to such a semiconductor device, for example, when the anti-fuse element is destroyed and the relief source word line is replaced with a relief destination redundant word line, the data held in the memory cell on the relief source word line is transferred to the relief destination redundancy word line. By copying to the redundant memory cell, it is possible to retain the data stored in the memory cell on the word line of the repair source even after the redundancy repair. Hereinafter, the copy is referred to as “PPR copy”.

  FIG. 2 is a block diagram illustrating a configuration related to the PPR copy operation in the configuration of the semiconductor device. FIG. 3 is a block diagram illustrating the configuration of the column address control circuit 16 shown in FIG. FIG. 5 is a circuit diagram illustrating the configuration of the counter circuit 22 shown in FIG. Referring to FIG. 5, the semiconductor device uses a counter circuit 22 that generates a count value by performing a count operation, and a plurality of lower bits when the count value is expressed in binary, and a repair source word line and a repair A control circuit (PPR copy control circuit 24) that generates at least one of a signal for activating the previous redundant word line, a data read signal from the repaired source word line, and a data write signal to the repaired redundant word line ) And.

  Referring to FIG. 5, the semiconductor device uses a plurality of upper bits when the count value generated by the counter circuit 22 is expressed as a binary number as a column address, and receives data from the memory cells on the relief source word line. The read data may be written to the redundant memory cell on the redundant word line as the rescue destination.

  Further, referring to FIG. 3, the semiconductor device may include an interrupt control circuit 18 that generates an enable signal for enabling the copy operation after the replacement operation is completed. At this time, the counter circuit 22 starts a count operation in response to the activation of the enable signal.

  Further, after activating the enable signal, the interrupt control circuit 18 deactivates the enable signal when the refresh operation for the data held in the memory cell on the word line other than the repair target by the redundant word line is started, and the refresh is performed. When the operation ends, the enable signal may be activated again.

  According to such a semiconductor device, the refresh command can be interrupted even during the PPR copy operation.

<Embodiment 1>
The semiconductor device according to the first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is a semiconductor memory device such as a DRAM. In the semiconductor device of the present embodiment, the data stored in the memory cell existing on the repair-source word line is transferred to the redundancy memory cell on the repair-destination redundant word line during the redundancy repair based on PPR (Post Package Repair). make a copy. The copy is hereinafter referred to as “PPR copy”.

  In the present embodiment, during the tGPM period defined by the PPR specification added as the specification of JEDEC DDR4, the data held by all the memory cells on the word line of the repair source is made redundant on the redundant word line using the internal logic. A case of copying to a memory cell will be described.

  Here, the tGPM period in the PPR specification refers to a period in which address information is allocated by destroying an antifuse element based on a relief address input from the outside. The tGPM period defined in the above specification is 200 ms, and there is sufficient time for completing the PPR copy operation of this embodiment during the tGPM period. Therefore, in the present embodiment, during the tPGM period after the completion of the antifuse destruction specified by the PPR specification, the data of the memory cell on the relief source word line corresponding to the corresponding row address is read, and the read data is used as it is. Copy to a redundant memory cell on the redundant word line of the rescue destination.

  FIG. 1 is a block diagram illustrating the configuration of the semiconductor device according to this embodiment. The semiconductor device shown in FIG. 1 is a stacked memory integrated on one chip, and includes a memory cell array 101 divided into eight banks BANK0 to BANK7. The memory cell array 101 includes a plurality of word lines WL and a plurality of bit lines BL, and memory cells MC are arranged at the intersections. For the sake of simplicity, FIG. 1 shows only one word line WL, one bit line BL, and one memory cell MC arranged at the intersection of these.

  Of the plurality of word lines included in the memory cell array 101, defective word lines are replaced with redundant word lines included in the row redundancy circuit 102. Of the plurality of bit lines included in the memory cell array 101, defective bit lines are replaced with redundant bit lines included in the column redundancy circuit 103. Here, the defective word line is not only when the word line itself is defective but also when one or more memory cells selected by the word line are defective even though the word line itself is not defective. Including cases. Similarly, a defective bit line is not only a case where the bit line itself is defective, but one or more memory cells connected to the bit line are defective although the bit line itself is not defective. Including cases.

  Row access to the memory cell array 101 is performed by the row decoder 104. The row decoder 104 decodes the row address XADD supplied from the row address control circuit 110 and selects one of the word lines included in the memory cell array 101 based on the decoding result. Also, the row decoder 104 replaces the row redundancy in place of the word line in the memory cell array 101 when the row address XADD supplied from the row address control circuit 110 matches the defective address held in the relief control circuit 140. Alternative access is performed to the redundant word line in the circuit 102.

  On the other hand, column access to the memory cell array 101 is performed by the column decoder 105. The column decoder 105 decodes the column address YADD supplied from the column address control circuit 111, and selects any column switch included in the column control circuit 107 based on the decoding result. The column switch is a switch for connecting one of the sense amplifiers included in the sense amplifier row 106 to the column control circuit 107. When one of the switches becomes conductive, a predetermined bit is passed through the corresponding sense amplifier. The line and the column control circuit 107 are connected. Further, the column decoder 105 replaces the column redundancy in place of the bit line in the memory cell array 101 when the column address YADD supplied from the column address control circuit 111 coincides with the defective address held in the relief control circuit 140. An alternative access is made to the redundant bit line in the circuit 103.

  The row address control circuit 110 and the column address control circuit 111 are supplied with addresses A0 to A15 and bank addresses BA0 to BA2 via an address terminal 112 and an address buffer 113. The addresses A0 to A15 are portions used as the row address XADD or the column address YADD, and the bank addresses BA0 to BA2 are portions used to select the banks BANK0 to BANK7.

  In addition to the address terminal 112, the semiconductor device is provided with a command terminal 120, a control terminal 121, and a clock terminal 122.

  The command terminal 120 is a terminal group to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and a chip select signal / CS are input. These command signals input to the command terminal 120 are supplied to the command decoder 124 and the mode register 125 via the command buffer 123. The command decoder 124 is a circuit that generates an internal command by decoding a command signal and supplies the internal command to the control logic 127 or the like. The mode register 125 is a register in which a set value can be rewritten using addresses A0 to A15, and the set value is supplied to the control logic 127 and the like.

  The control terminal 121 is a terminal group including a terminal to which a data mask signal DM, an on-die termination signal ODT and a reset signal / RESET are input, and a calibration terminal ZQ. These control signals input to the control terminal 121 are supplied to the control logic 127 via the control buffer 126. The control logic 127 is a circuit that generates various control signals based on the control signal, the internal command, and the set value of the mode register 125. The generated control signal is supplied to the row address control circuit 110, the column address control circuit 111, and the data control circuit 108, and controls the operation of these circuit blocks.

  The clock terminal 122 is a terminal group to which the clock signal CK, the inverted clock signal / CK, and the clock enable signal CKE are input. These clock signals input to the clock terminal 122 are supplied to the clock generation circuit 129 via the clock buffer 128. The clock generation circuit 129 is a circuit that generates an internal clock signal based on these clock signals, and the generated internal clock signal is supplied to various circuit blocks. A part of the internal clock signal is supplied to the DLL circuit 130. The DLL circuit 130 is a circuit that generates an output clock that is phase-controlled based on an internal clock signal, and the generated output clock is supplied to the data control circuit 108 and the input / output buffer 109.

  The data control circuit 108 latches the read data output in parallel via the column control circuit 107, converts this into serial data, supplies it to the input / output buffer 109, and inputs it serially via the input / output buffer 109. The write data is latched, converted into parallel data, and supplied to the column control circuit 107. The input / output buffer 109 is connected to the data system terminal 131. The data system terminal 131 includes data input / output terminals DQ0 to DQ7 and data strobe terminals DQS and / DQS. Data input / output terminals DQ0 to DQ7 are terminals for outputting read data and write data, and data strobe terminals DQS and / DQS are terminals for inputting and outputting complementary data strobe signals.

  With this configuration, when a read command is input via the command terminal 120, a read operation is performed on the memory cells specified by the addresses A0 to A15 and the bank addresses BA0 to BA2, and the read data read out The data is output via data input / output terminals DQ0 to DQ7. On the other hand, when a write command is input via the command terminal 120, a write operation is performed on the memory cells specified by the addresses A0 to A15 and the bank addresses BA0 to BA2, and the data input / output terminals DQ0 to DQ7 are used. The write data input is written. In the read operation and the write operation, when the access destination memory cell is a defective memory cell, an alternative access is made to the row redundancy circuit 102 or the column redundancy circuit 103. As described above, the address of the defective memory cell is held in the repair control circuit 140.

  The defective address held in the relief control circuit 140 is transferred from the optical fuse circuit 141 and the AF circuit 142. The optical fuse circuit 141 is a circuit that stores information by cutting a fuse element by laser beam irradiation. The AF circuit 142 is a circuit that stores information by applying a high voltage to the fuse element. The AF circuit 142 has a plurality of antifuse elements. The antifuse element stores information by breaking down an insulating film by applying a high voltage.

  Thus, in the semiconductor device according to the present embodiment, one redundant word line can be used for either the optical fuse circuit 141 or the AF circuit 142. Similarly, one redundant bit line can be used in either the optical fuse circuit 141 or the AF circuit 142. Of course, the same redundant word line or the same redundant bit line cannot be used in the optical fuse circuit 141 and the AF circuit 142 at the same time. Redundant word lines and redundant bit lines are used for primary relief by the optical fuse circuit 141, and the remaining redundant word lines and redundant bit lines not used in the primary relief are used for secondary relief by the AF circuit 142. The

  Detection of a defective memory cell in the secondary remedy is performed by a data determination circuit 107 a provided in the column control circuit 107, and a determination signal P / F obtained as a result of the determination is supplied to the analysis circuit 143. The determination signal P / F indicates “pass” when the read data does not include an error, and indicates “fail” when the read data includes an error.

  When the determination signal P / F indicates failure, the analysis circuit 143 identifies the address of the defective memory cell by referring to the accessed address, and shows the relationship with the address of the already detected defective memory cell. To analyze. The analysis memory 144 is used for the analysis work by the analysis circuit 143. As an example, the analysis memory 144 is composed of SRAM. In addition to the determination signal P / F and the address, the analysis circuit 143 is supplied with an internal clock signal, an internal command, and a control signal from the DFT circuit 145.

  FIG. 2 is a block diagram showing circuits related to the PPR operation and the PPR copy operation in the semiconductor device shown in FIG. The AF control circuit 12 corresponds to the analysis circuit 143 and the analysis memory 144, the command control circuit 26 corresponds to the control logic 127, and the I / O control circuit 28 and the data amplifier 38 correspond to the data control circuit 108.

  The command control circuit 26 sends a PPR command to the AF (AntiFuse) control circuit 12 as a signal signal_0. The AF control circuit 12 starts the operation in response to the PPR command.

  Further, the command control circuit 26 receives a command in the PPR and transmits a latch signal of the row address to be repaired to the row address control circuit 14 as a signal signal_1.

  The row address control circuit 14 transmits the signal signal_2 to the row decoder 34 and the AF circuit 34, and selects / deselects a word line for the row address originally latched at the PPR. When a row redundancy repair skip signal generated by a PPR copy control circuit 24 (FIG. 6) described later is at a high level, a repair source word line repaired by PPR is activated. On the other hand, when the row redundancy repair skip signal is at the low level, the signal signal_10 output from the AF circuit 34 is at the high level, and the redundancy word line of the repair destination in the PPR is activated.

  The AF control circuit 12 transmits the relief control signal group in the PPR to the AF circuit 32 as the signal signal_3. Note that the PPR copy operation starts after the control based on the signal signal_3 is completed.

  The AF control circuit 12 transmits a repair completion signal (PPR_AF repair signal described later) indicating the completion of repair based on the PPR to the column address control circuit 16 as the signal signal_4. The operation relating to the PPR copy starts upon receiving the signal.

  The column address control circuit 16 transmits a PPR copy WL active Act signal and a PPR copy WL inactive Pre signal generated by a PPR copy control circuit 24 (FIG. 6), which will be described later, to the command control circuit 26 as a signal signal_5, thereby Generate control commands. Further, the column address control circuit 16 transmits a data read signal and a data write signal generated by the PPR copy control circuit 24 (FIG. 6) to the command control circuit 26 as a signal signal_5 to generate a column control command.

  The command control circuit 26 transmits a data read signal and a data write signal received by the command control circuit 26 during the operation of the circuit related to PPR copying to the I / O control circuit 28 as a signal signal_6. Note that the command control circuit 26 transmits a signal that prevents the I / O control circuit 28 from operating during the above control to the I / O control circuit 28 as a signal signal_6.

  The command control circuit 26 transmits a read signal generated based on the data read signal to the data amplifier 38 as a signal signal — 7 to operate the data amplifier 38.

  The data amplifier 38 transfers the signal to be copied to a desired local I / O by exchanging the signal signal_8 through the I / O line group connected to the memory cell array.

  The I / O line group provided between the I / O control circuit 28 and the data amplifier 38 temporarily latches the data of the rescue source as the signal signal_9 during the operation of the circuit related to the PPR copy. Further, the data latched as the signal signal_9 on the I / O line group is transmitted as the signal signal_8 via the data amplifier 38 when writing to the redundant memory cell on the redundant word line of the rescue destination.

  The AF circuit 32, when an X redundancy repair skip signal, which will be described later, is at a low level, hits an address repaired by PPR, activates a repair destination row redundant word line, and does not activate a repair source word line Is transmitted to the row decoder 34 as a signal signal_10.

  The column address control circuit 16 transmits a column address generated by a counter circuit 22 (FIG. 5), which will be described later, to the column decoder 36 and the AF circuit 32 as a signal signal_11.

  The command control circuit 26 uses a write signal generated based on the data write signal generated by the PPR copy control circuit (FIG. 6) (that is, a write command for the redundant word line of the rescue destination in the PPR) as the signal signal_12. Transmit to the data amplifier 38.

  When the data amplifier 38 receives the write signal, it passes the signal signal_9 for latching data read from the memory cell on the relief source word line to the signal signal_8.

  FIG. 3 is a block diagram illustrating a detailed configuration of the column address control circuit 16. Referring to FIG. 3, the column address control circuit 16 includes an interrupt control circuit 18, a counter circuit 22, and a PPR copy control circuit 24.

  The interrupt control circuit 18 receives the PPR_AF relief signal from the AF control circuit 12, receives the PPR signal and the AutoRef_Start signal from the command control circuit 26, receives the AutoRef_End signal from the row address control circuit 14, and receives the signal TCA10B from the counter circuit 22. And generates a PPR copy signal based on these received signals, and outputs the generated PPR copy signal to the counter circuit 22 and the PPR copy control circuit 24.

  The AF control circuit 12 generates a high-level PPR_AF repair signal during the internal operation of the PPR (that is, redundant repair based on the antifuse element). The operation related to the PPR copy of the present embodiment is started in response to the fall of the PPR_AF repair signal (completed redundancy repair). The command control circuit 26 outputs a high level PPR signal during the PPR period. When receiving the normal command REF, the PR command control circuit 26 generates an AutoRef_Start signal at the start of the refresh operation. The AutoRef_Start signal is used to stop the PPR copy operation when a refresh operation interrupt occurs during the PPR copy operation. The row address control circuit 14 generates an AutoRef_End signal at the end of the refresh operation. The AutoRef_End signal is used to restart the PPR copy operation after the refresh operation is completed. The counter circuit 22 generates a signal TCA10B as the most significant bit of a shift register described later. When the signal TCA10B transitions to the low level, the PPR copy operation is completed.

  FIG. 4 is a circuit diagram illustrating the configuration of the interrupt control circuit 18. Referring to FIG. 4, the interrupt control circuit 18 includes inverter elements IN1 to IN4, delay elements DL1 to DL4, NAND elements NAND1 to NAND7, and an AND element AND1. The interrupt control circuit 18 outputs a high-level PPR copy signal when the PPR_AF relief signal transitions from a high level to a low level when the PPR signal is at a high level, the AutoRef_Start signal, the AutoRef_End signal, and the TCA10B signal are at a low level. When the interrupt control circuit 18 receives a one-shot pulse of the AutoRef_Start signal during the output of the high-level PPR copy signal, the interrupt control circuit 18 generates and outputs a low-level PPR copy signal. Further, when receiving the one-shot pulse of the AutoRef_End signal while outputting the low-level PPR copy signal, the interrupt control circuit 18 generates and outputs a high-level PPR copy signal again.

  The counter circuit 22 receives the normal column address <3: 9> from the address terminal ADD_Pin, receives the PPR signal from the command control circuit 26, receives the PPR copy signal from the interrupt control circuit 18, and receives signals TCA0B to TCA10B and Column address <3: 9> is generated, the generated signals TCA0B to TCA2B are output to the PPR copy control circuit 24, the signal TCA10B is output to the interrupt control circuit 18, and the column address <3: 9> is output to the AF circuit 32 and Output to the column decoder 36.

  FIG. 5 is a circuit diagram illustrating the configuration of the counter circuit 22. Referring to FIG. 5, the counter circuit 22 includes a delay element DL6, NAND elements NAND9 and NAND10, inverter elements IN6 and IN7, flip-flops FF1 to FF3, and a selector element SEL1. When the counter circuit 22 receives the high-level PPR copy signal, the counter circuit 22 starts a count-up operation, outputs signals TCA0B to TCA2B corresponding to the lower bits of the count value to the PPR copy control circuit 24, and signals corresponding to the upper bits. TCA3T to TCA9T are output as column addresses <3: 9> to the AF circuit 32 and the column decoder 36, and a signal TCA10B corresponding to the most significant bit is output to the interrupt control circuit 18. The signals TCA0B and TCA1B are used in the PPR copy control circuit 24 as signals for controlling activation, deactivation, reading, writing, and the like of the relief source word line and the relief destination redundant word line. On the other hand, the signal TCA10B transitions to the low level after the scanning of all the column addresses is completed, and the PPR copy operation is completed.

  The PPR copy control circuit 24 receives the PPR copy signal from the interrupt control circuit 18, receives the test mode signal TXREDSKIP from the command control circuit 26, receives the signals TCA0B to TCA2B from the counter circuit 22, and receives the PPR copy WL activation Act signal. , PPR copy WL inactive Pre signal, row redundancy repair skip signal, data read signal and data write signal are generated, and the generated RRP copy WL active Act signal and PPR copy WL inactive Pre signal are sent to the row address control circuit 14 and the command. It outputs to the control circuit 26, outputs a row redundancy repair skip signal to the AF circuit 32, and outputs a data read signal and a data write signal to the command control circuit 26.

  FIG. 6 is a circuit diagram illustrating the configuration of the PPR copy control circuit 24. Referring to FIG. 6, the PPR copy control circuit 24 includes AND elements AND12 to AND14, OR elements OR1 and OR2, AND elements AND3 to AND7, delay elements DL8 and DL9, and inverter elements IN9 and IN10.

  FIG. 7 is a table showing logical functions of the PPR copy control circuit 24 according to the levels of the signals TCA0B to TCA2B when the PPR copy signal is at a high level. The PPR copy control circuit 24 generates a high-level row redundancy repair skip signal based on the high-level test mode signal TXREDSKIP signal and the high-level signal TCA2B, and is provided with a row redundancy circuit (not shown). Output to the circuit 32. At this time, the redundant word line of the PPR repair destination is not selected, and the word line of the PPR repair source is selected. On the other hand, the PPR copy control circuit 24 generates a low-level row redundancy repair skip signal based on the low-level signal TCA2B and outputs it to the AF circuit 32. At this time, the redundant word line of the PPR repair destination is selected and the word line of the PPR repair source is not selected.

  The PPR copy control circuit 24 generates a one-shot pulse of the PPR copy WL activation Act signal in response to the transition of the signals TCA0B and TCA1B to the high level, and outputs the one-shot pulse to the row address control circuit 14 and the command control circuit 26. . As a result, the relief source word line or the relief destination redundant word line is activated. On the other hand, the PPR copy control circuit 24 generates a one-shot pulse of the PPR copy WL inactive Pre signal in response to the transition of the signals TCA0B and TCA1B to the low level, and outputs the one-shot pulse to the row address control circuit 14 and the command control circuit 26. . As a result, the repair source word line or the repair destination redundant word line is deactivated.

  Further, the PPR copy control circuit 24 generates a high-level data read signal based on the low-level signal TCA0B, the high-level signal TCA1B, and the high-level signal TCA2B, and outputs the high-level data read signal to the command control circuit 26. At this time, data is read from the memory cell on the word line of the PPR relief source. On the other hand, the PPR copy control circuit 24 generates a high-level data write signal based on the low-level signal TCA0B, the high-level signal TCA1B, and the low-level signal TCA2B, and outputs it to the command control circuit 26. At this time, data is written to the redundant memory cell on the redundant word line of the PPR relief destination.

  FIG. 8 is a timing diagram illustrating the operation of the PPR copy by the semiconductor device of this embodiment. With reference to FIG. 8, the PPR copy operation of the semiconductor device of this embodiment will be described.

  The AF control circuit 12 generates a low-level PPR_AF repair signal after the assignment of information to the antifuse element of the PPR repair target address, and the interrupt control circuit 18 provided in the column address control circuit 16 (FIG. 2). (FIG. 3).

  When receiving the low-level PPR_AF relief signal, the interrupt control circuit 18 generates a high-level PPR copy signal and outputs it to the counter circuit 22 and the PPR copy control circuit 24.

  When the counter circuit 22 receives the high-level PPR copy signal, the counter circuit 22 starts a count-up operation of the 11-bit count value. The signal TCA0B assigned to the least significant bit of the count value in the counter circuit 22 starts the clocking operation at a timing corresponding to the delay amount set in the counter circuit 22. The half cycle of the signal TCA0B has a delay amount that satisfies tRCD / tRP. The signals TCA3T to TCA9T generated by the counter circuit 22 are used as they are as column addresses. Note that the command control circuit 26 invalidates the I / O control circuit 28 by a signal signal — 6 to the I / O control circuit 28.

  When the signal TCA2B becomes high level when the PPR copy signal is at high level, the PPR copy control circuit 24 performs high level low based on the OR operation by the OR element OR2 between the test mode signal TXREDSKIP signal and the signal TCA2B. A redundant repair skip signal is generated and output to the AF circuit 32. At this time, the row redundancy logic existing in the AF circuit 32 is invalidated.

  Further, when the signals TCA1B and TCA2B transition to a high level (TCA0B = “H”, TCA1B = “H”, TCA2B = “H”), the PPR copy control circuit 24 generates a one-shot pulse as a PPR copy WL activation Act signal. It is generated and output to the row address control circuit 14 and the command control circuit 26. At this time, the command control circuit 26 generates a bank active signal based on the bank information captured by the PPR. The relief source word line is activated according to the bank active signal, the high level row information relief skip signal, and the relief row address information already taken in by the PPR.

  Next, when the signal TCA0B transitions to a low level (TCA0B = “L”, TCA1B = “H”, TCA2B = “H”), the PPR copy control circuit 24 generates a high-level data read signal and performs command control. It outputs to the circuit 26. The command control circuit 26 generates a normal read command from the high level data read signal and the bank information captured by the PPR, and the column address generated from the signals TCA3T to TCA9T of the counter circuit 22 <3: When 9> is selected, a data read operation corresponding to the burst length is started from the memory cell on the word line of the repair source. Note that the read data is not output to the outside of the chip but is held as it is on the I / O bus (signal signal_8 or signal signal_9 in FIG. 2) inside the chip.

  Next, when the signals TCA0B and TCA1B become low level (TCA0B = “L”, TCA1B = “L”, TCA2B = “H”), the PPR copy control circuit 24 outputs a one-shot pulse as a PPR copy WL inactive Pre signal. It is generated and output to the row address control circuit 14 and the command control circuit 26. At this time, the command control circuit 26 generates a precharge signal and returns the currently selected relief source word line to an inactive state.

  Next, when the signals TCA0B and TCA1B are at the high level and the signal TCA2B is at the low level (TCA0B = “H”, TCA1B = “H”, TCA2B = “L”), the PPR copy control circuit 24 skips the low-level row redundancy repair skip. A signal is generated and output to the AF circuit 32. At this time, the row redundancy logic in the AF circuit 32 is validated, and the repair-destination redundant word line is activated instead of the repair-source word line.

  Next, when the signal TCA0B transitions to a low level (TCA0B = “L”, TCA1B = “H”, TCA2B = “L”), the PPR copy control circuit 24 generates a high-level data write signal and performs command control. It outputs to the circuit 26. Then, when TCA0B = “L”, TCA1B = “H”, and TCA2B = “H”, the data that is read from the memory cell on the repair source word line and exists as the signal signal_8 or signal_9 is the selected repair destination. Are written in redundant memory cells corresponding to the corresponding column addresses on the redundant word line.

  Next, when the signals TCA0B and TCA1B transition to a low level (TCA0B = “L”, TCA1B = “L”, TCA2B = L), the PPR copy control circuit 24 generates a one-shot pulse as a PPR copy WL inactive Pre signal. Then, the data is output to the row address control circuit 14 and the command control circuit 26. At this time, the command control circuit 26 generates a precharge signal and returns the currently selected redundancy word line of the repair destination to the inactive state.

  When the most significant bit TCA10B of the counter circuit 22 is switched by repeating the 3-bit transition of the signals TCA0B to TCA2B shown in FIG. 7 up to YMAX (7 bits of TCA3T to TCA9T) existing on the word line, The operation of copying the data read from the memory cell to the relief memory cell on the redundancy word line as the relief destination is completed.

  The interrupt control circuit 18 shown in FIG. 4 outputs a low-level PPR copy signal when receiving a one-shot pulse of the AutoRef_Start signal during a PPR copy operation (while outputting a high-level PPR copy signal). When the interrupt control circuit 18 receives the one-shot pulse of the AutoRef_End signal while outputting the low-level PPR copy signal, the interrupt control circuit 18 again outputs the high-level PPR copy signal. According to the interrupt control circuit 18, if a refresh operation interrupt occurs during the PPR copy, the PPR copy is stopped, and after the refresh operation is completed, the PPR copy operation is restarted from the beginning.

  However, in this embodiment, when an interrupt for a refresh operation occurs during the PPR copy operation (that is, when the PPR copy signal is at a high level), the interrupt may not be accepted.

  Next, a specific element structure of the antifuse element in the AF circuit 32 of the semiconductor device according to the present embodiment will be described. FIG. 9 is a cross-sectional view illustrating the element structure of an antifuse element. Referring to FIG. 9, an active region 202 surrounded by an element isolation region 206 is provided on a semiconductor substrate 210, and a gate insulating film 204 is formed on the surface of the active region 202. The gate electrode 201 is provided on the active region 202 with the gate insulating film 204 interposed therebetween. A diffusion layer 205 into which an impurity having a conductivity type different from that of the semiconductor substrate 210 is introduced is formed in the active region 202 in a self-aligned manner with respect to the gate electrode 201. The gate electrode 201 and the diffusion layer 205 are connected to the upper wiring 209 via a contact plug 208 provided in the interlayer insulating film 207. Note that the element structure shown in FIG. 9 is merely an example, and the element structure of the antifuse in this embodiment is not limited to the illustrated mode.

  According to the semiconductor device of this embodiment, data held in a memory cell on a PPR repair source word line, which is not guaranteed in the PPR specification added to JEDEC, is copied to a redundancy memory cell on a repair destination redundant word line. By doing so, it is possible to guarantee data.

  In addition, when the user uses an ECC-equipped DIMM system and error correction is required for the check bit on the DIMM side, it is normal to use the PPR function for MONO alone that can be restored with the ECC function. It is possible to replace it with a redundant word line that operates in a short time.

  It should be noted that the entire disclosure of the above patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the framework of the entire disclosure of the present invention. is there. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

12 AF control circuit 14 Row address control circuit 16 Column address control circuit 18 Interrupt control circuit 22 Counter circuit 24 PPR copy control circuit 26 Command control circuit 28 I / O control circuit 32 AF circuit 34 Row decoder 36 Column decoder 38 Data amplifier 101 Memory Cell array 102 row redundancy circuit 103 column redundancy circuit 104 row decoder 105 column decoder 106 sense amplifier array 107 column control circuit 107a data determination circuit 108 data control circuit 109 input / output buffer 110 row address control circuit 111 column address control circuit 112 address terminal 113 address Buffer 120 Command terminal 121 Control terminal 122 Clock terminal 123 Command buffer 124 Command decoder 125 Mode register Star 126 Control buffer 127 Control logic 128 Clock buffer 129 Clock generation circuit 130 DLL circuit 131 Data system terminal 140 Relief control circuit 141 Optical fuse circuit 142 AF circuit 143 Analysis circuit 144 Analysis memory 145 DFT circuit 201 Gate electrode 202 Active region 204 Gate Insulating film 205 Diffusion layer 206 Element isolation region 207 Interlayer insulating film 208 Contact plug 209 Upper wiring 210 Semiconductor substrate AND1, AND3-AND7 AND elements DL1-DL4, DL6, DL8, DL9 Delay elements FF1-FF3 Flip-flops IN1-IN4, IN6 , IN7, IN9, IN10 Inverter elements NAND1 to NAND7, NAND9, NAND10 NAND elements NAND12 to NAND14 NA ND element SEL1 selector element

Claims (12)

A semiconductor device configured to destroy an antifuse element and replace a relief source word line with a relief destination redundant word line,
Copying the data held in the memory cells on the relief source word line to the redundancy memory cells on the redundancy word line of the relief destination;
A semiconductor device. A counter circuit that generates a count value by performing a count operation;
A signal for activating the relief source word line and the relief destination redundant word line, a data read signal from the relief source word line, using a plurality of lower bits when the count value is expressed in binary number; And a control circuit that generates at least one of data write signals to the redundancy word line of the rescue destination,
The semiconductor device according to claim 1. Using a plurality of upper bits when the count value is expressed in binary notation as a column address, data is read from the memory cell on the repair-source word line and the redundancy memory cell on the repair-destination redundant word line is read Configured to write the read data,
The semiconductor device according to claim 2. An interrupt control circuit for generating an enable signal for enabling the copy operation after the replacement operation is completed;
The counter circuit starts the counting operation in response to activation of the enable signal.
The semiconductor device according to claim 2. After activating the enable signal, the interrupt control circuit deactivates the enable signal when a refresh operation for data held in a memory cell on a word line other than a relief target by a redundant word line is started, When the refresh operation is completed, the enable signal is reactivated.
The semiconductor device according to claim 4. After the enable signal is activated, the interrupt control circuit keeps the enable signal activated when the refresh operation for the data held in the memory cell on the word line other than the repair target by the redundant word line is started. To
The semiconductor device according to claim 4. A step in which the semiconductor device destroys the anti-fuse element and replaces the relief source word line with a relief destination redundant word line;
Copying the data held by the memory cells on the relief source word line to the redundancy memory cells on the redundancy word line of the relief destination,
A method for controlling a semiconductor device. The semiconductor device generates a count value by performing a count operation;
A signal for activating the relief source word line and the relief destination redundant word line, a data read signal from the relief source word line, using a plurality of lower bits when the count value is expressed in binary number; And generating at least one of data write signals to the redundancy word line of the rescue destination,
A method for controlling a semiconductor device according to claim 7. The semiconductor device uses a plurality of upper bits when the count value is expressed in binary notation as a column address, and reads data from a memory cell on the relief source word line;
Writing the read data to the redundant memory cell on the redundant word line of the rescue destination,
The method for controlling a semiconductor device according to claim 8. The semiconductor device includes a step of generating an enable signal for enabling the copy operation after the replacement operation is completed,
In response to activation of the enable signal, the counting operation is started.
A method for controlling a semiconductor device according to claim 8. After the semiconductor device activates the enable signal, when a refresh operation for data held in a memory cell on a word line other than a target to be repaired by a redundant word line is started, the semiconductor device deactivates the enable signal and the refresh signal Activating the enable signal again when the operation ends,
The method for controlling a semiconductor device according to claim 10. After activating the enable signal, the semiconductor device keeps the enable signal activated when a refresh operation for data held in a memory cell on a word line other than a relief target by a redundant word line is started. ,
The method for controlling a semiconductor device according to claim 10.

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