JP5109647B2 - Driver circuit - Google Patents

Description

  The present invention relates to a driver circuit for outputting output data such as calculation results and data read from a memory to an external device in a semiconductor integrated circuit.

In a semiconductor integrated circuit, when data is output from an internal circuit to an external device, for example, when data read from a memory cell or the like is output to an external circuit, in order to directly output the data, Since the output power is small, power is amplified and output via an output driver (see, for example, Patent Document 1).
JP 2004-303283 A

  However, in the conventional semiconductor device such as Patent Document 1, due to manufacturing variations, output characteristics vary, that is, variations in signal rise time and fall time, and also variations occur between output buffers. There is a problem that operation characteristics corresponding to the street cannot be obtained.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a driver circuit that can suppress variations in output characteristics due to manufacturing variations as compared to conventional ones.

  The driver circuit according to the present invention includes a first MOS transistor group composed of a plurality of first MOS transistors each having a different size connected between a first power supply and an output terminal, and between the output terminal and the second power supply. A second MOS transistor group composed of a plurality of second MOS transistors each having a different size connected thereto, and an ON state for supplying an output signal to each gate of the first switch in the first switch group; Alternatively, a first switch group including a first switch that individually controls whether or not the first control signal for turning off the first MOS transistor is applied to each of the second switches in the second switch group. Whether the second control signal for applying the output signal to each gate or applying the second control signal for turning off is applied to each of the second MOS transistors. A first control circuit that controls whether the second switch group including two switches and the first switch in the first switch group or the combination is turned on by the first control signal And a second control circuit for controlling which one of the second switches in the second switch group or a combination is turned on by the second control signal.

  In the driver circuit according to the present invention, the first and second control circuits each include a memory circuit, and the first and second control information indicating whether or not each of the first and second switches is turned on. The first and second control signals are output according to the first and second control information, respectively.

  In the driver circuit of the present invention, when the calibration signal is input to the first and second control circuits, the first and second control circuits are input from the outside instead of the first and second control information stored in the storage unit. Whether or not each of the first and second switches is turned on is controlled by external control information.

  The driver circuit according to the present invention is characterized in that the first control information and the second control information are externally written to or changed in the memory circuits of the first and second control circuits.

  In the driver circuit of the present invention, the first MOS transistor is formed by a plurality of p-channel transistors having different transistor sizes, and the second MOS transistor is formed by a plurality of n-channel transistors having different transistor sizes. It is characterized by.

  As described above, according to the present invention, even if the output characteristics vary, that is, the rise time and fall time of the signal vary due to manufacturing variation, and the output buffers vary, the rise corresponding to the design value is achieved. By selecting the first and second switches so that the time and the fall time can be obtained, the rise time and the fall time of the output signal can be corrected in accordance with the set values. An effect is obtained that operational characteristics corresponding to the design can be obtained.

Hereinafter, an output driver according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an output driver according to the embodiment.
In this figure, the output driver has a control unit 1, an output transistor unit 2, a switch group 3, and inverters 100 and 101.
The control unit 1 includes a first control unit 11 that controls switches in the switch group 3, a storage unit 12 that stores first control information used by the first control unit 11, and a switch group 3 2 has a second control unit 13 for controlling the switch, and a storage unit 14 in which the first control information used by the second control unit 13 is stored.
The transistor unit 2 includes, for example, p-channel MOS transistors (hereinafter referred to as p-type transistors) MP1, MP2, MP3 and MP4, and n-channel MOS transistors (hereinafter referred to as n-type transistors) MN1, MN2, MN3 and MN4. Has been.

In the p-type transistors MP1, MP2, MP3, and MP4, the source is connected to the power supply terminal TVOH to which the first power supply VOH is input, and the drain is connected to the output terminal TOUT from which the output signal is output. The gate of the p-type transistor MP1 is connected to the output terminal of the inverter 101. The connection of the gates of the p-type transistors MP2, MP3 and MP4 will be described later.
The n-type transistors MN1, MN2, MN3 and MN4 have their sources connected to the power supply terminal TVOL to which the second power supply VOL is input, and their drains connected to the output terminal TOUT from which the output signal is output. The gate of the p-type transistor MN1 is connected to the output terminal of the inverter 100. The connection of the gates of the n-type transistors MN2, MN3, and MN4 will be described later.

As an example of the transistor size, the p-type transistors MP1, MP2, MP3, and MP4 have different transistor sizes (channel widths). When the default value of the current capacity is 100%, the p-type transistor MP1 is 84%, the p-type transistor MP2 is 16%, the p-type transistor MP3 is 8%, and the p-type transistor MP4 is 4%.
Similarly, the n-type transistors MN1, MN2, MN3, and MN4 have different transistor sizes. When the default value of the current capacity is 100%, the n-type transistor MN1 is 84%, the n-type transistor MN2 is 16%, the n-type transistor MN3 is 8%, and the n-type transistor MN4 is 4%.

The switch group 3 includes switches SWP2, SWP3, and SWP4 as the first switch group, and switches SWN2, SWN3, and SW4 as the second switch group.
The switch SWP2 is interposed between the output terminal of the inverter 101 and the gate of the p-type transistor MP2, and the switch SWP3 is interposed between the output terminal of the inverter 101 and the gate of the p-type transistor MP4.
The switch SWN2 is interposed between the output terminal of the inverter 100 and the gate of the n-type transistor MN2, and the switch SWN3 is interposed between the output terminal of the inverter 100 and the gate of the n-type transistor MNP4.

Whether the switch SWP2 is turned on between the output terminal of the inverter 101 and the gate of the p-type transistor MP2 or is turned off by setting the gate of the p-type transistor MP2 to “H” level. It is controlled by the first control signal S1 input from the control unit 11.
Similarly, each of the switches SWP3 and SWP4 is turned on between the output terminal of the inverter 101 and the gates of the p-type transistors MP3 and MP4, or turned off by setting the gates of the p-type transistors MP3 and MP4 to the “H” level. The state is controlled by the first control signal S1 input from the first control unit 11.
Here, the first control signal S1 has a 3-bit configuration of S1 {P2, P3, P4}. For example, if P2 = 1, the switch SWP2 is turned on, and if P2 = 0, the switch SWP2 Turns off the p-type transistor MP2. That is, when the first control signal S1 {P2, P3, P4} = S1 {1, 0, 1}, the switches SWP2 and SWP4 are turned on and the p-type transistor MP3 is turned off. Therefore, the transistors to be driven by the input signal are p-type transistors MP2 and MP4.

Further, whether the switch SWN2 is turned on between the output terminal of the inverter 100 and the gate of the n-type transistor MN2 or whether the gate of the n-type transistor MN2 is turned “L” level is turned off. The second control signal S <b> 2 input from the second control unit 13 is controlled.
Similarly, each of the switches SWN3 and SWN4 is turned on between the output terminal of the inverter 100 and the gates of the n-type transistors MN3 and MN4, or is turned off by setting the gates of the n-type transistors MN3 and MN4 to “L” level. The state is controlled by the second control signal S2 input from the second control unit 13.
Here, the second control signal S2 has a 3-bit configuration of S2 {N2, N3, N4}. For example, if N2 = 1, the switch SWN2 is turned on, and if N2 = 0, the switch SWN2 Turns off the n-type transistor MN2. That is, when the second control signal S2 {N2, N3, N4} = S2 {1, 0, 1}, the switches SWN2 and SWN4 are turned on, and the n-type transistor MN3 is turned off. Therefore, the transistors to be driven by the input signals are n-type transistors MN2 and MN4.

The storage unit 12 stores first control information for generating the first control signal S1, that is, 3-bit bit information of S1 {P2, P3, P4}.
The first control unit 11 reads the first control information stored in the storage unit 12 when the driver of the present embodiment is activated, and the first control information corresponding to the first control information. S1 is generated and output to the switches SWP2, SWP3, and SWP4 of the first switch group.
Similarly, the storage unit 14 stores second control information for generating the first control signal S2, that is, 3-bit bit information of S2 {N2, N3, N4}.
The second control unit 13 reads the second control information stored in the storage unit 14 when the driver of the present embodiment is activated, and the second control information corresponding to the second control information. S2 is generated and output to the switches SWN2, SWN3, and SWN4 of the second switch group.
The storage units 12 and 14 may use either non-volatile or volatile memory, and use a one-time ROM or the like when only one setting is required, and use a flash memory, DRAM or SRAM when rewriting. Use.

Further, when the calibration signal CAL is input to the control unit 1, the first control unit 11 is not the first control information S1 stored in the storage unit 12, but the control signal S1 { P2, P3, and P4} are output as the first control signal S1 to the switches SWP2, SWP3, and SWP4 in the first switch group.
Similarly, when the calibration signal CAL is input to the control unit 1, the second control unit 13 is not the second control information S2 stored in the storage unit 14, but the control signal GS2 input from the outside. {N2, N3, N4} is generated as a second control signal S2 and output to the switches SWN2, SWN3, and SWN4 in the second switch group.
That is, when the calibration signal CAL is input, the first control unit 11 receives the control signal S1 input from the outside instead of the first control signal S1 stored in the storage unit 12 as the first switch. Output for groups.
Similarly, when the calibration signal CAL is input, the second control unit 13 receives the control signal S2 input from the outside instead of the second control signal S2 stored in the storage unit 14. Output to the switch group 2.
As described above, the control signal GS1 {P2, P3, P4} input from the outside corresponds to the first control signal S1 {P2, P3, P4}, and the control signal GS2 {N2 input from the outside. , N3, N4} correspond to the control signal S2 {N2, N3, N4}.
Further, in the calibration process described above, the output waveform in which the control signal S1 {P2, P3, P4} and the control signal S2 {N2, N3, N4} input from an external measuring instrument satisfy the specifications of the output driver 2 is satisfied. When it is determined that the rising time and the rising time are, the writing signal W is input from the measuring device to the first control unit 11 and the second control unit 13. Here, the first control unit 11 writes each bit of the control signal S1 in the storage unit 12 as the first control signal S1. The second control unit 13 writes each bit of the control signal S2 in the storage unit 14 as the second control signal S2.

Next, the operation of this embodiment will be described with reference to FIG. When testing a semiconductor device equipped with the output driver according to the present embodiment at the time of shipment, the test signal is input from the outside to the output driver.
As a result, the test signal is input to the control unit 1, and the first control unit 11 and the control unit 12 transmit the first control signal to each switch of the switch group 2 by the external control signal G input from the outside. S1 and S2 are output, respectively.
For example, the calibration signal CAL is input to the first control unit 11 and the second control unit 13 from an external measuring device, respectively, and the external control signal GS1 {P2, P3, P4} = GS1 {1, 0, 0 }, When the external control signal GS2 {N2, N3, N4} = GS2 {1, 0, 0} is input, the first control unit 11 sends the control signal S1 {1, 0, 0} to the first The control signal S1 is output to the first switch group, and the second control unit 13 outputs the control signal S2 {1, 0, 0} as the second control signal to the second switch group.

When the first control signal S1 {1, 0, 0} is input, the switch SWP2 is turned on, the p-type transistors MP3 and MP4 are fixed off, and the transistor driven by the input signal is p Type transistors MP1 and MP2.
When the second control signal S2 {1, 0, 0} is input, the switch SWN2 is turned on, the p-type transistors MN3 and MN4 are fixed off, and the transistor driven by the input signal Are set as n-type transistors MN1 and MN2.
In the above setting, the amount of current that the transistor drives relative to the design value, that is, the driving capability is 100%.

In this state, the rise time and fall time of the output signal OUT are measured, and when the rise time is slow, in addition to the switch SWP2, either or both of the switches SWP3 and SWP4 are turned on, and the transistor driven by the input signal The rise time of the output signal OUT is adjusted by increasing the current capacity by changing the value of each bit of the control signal S1 so as to control the on state and the off state of each switch.
On the other hand, when the rise time is early, the switch SWP2 is not turned on, the p-type transistor MP2 is fixed to the off state, and one or both of the other switches SWP3 and SWP4 are turned on and driven by the input signal. The rise time of the output signal OUT is adjusted by changing the value of each bit of the control signal S1 so as to control the combination of the transistors, that is, the on state and the off state of each switch, thereby reducing the current capacity.

Similarly, when the fall time is slow, in addition to the switch SWN2, either or both of the switches SWN3 and SWN4 are turned on to control the combination of transistors driven by the input signal, that is, the on and off states of each switch. The fall time of the output signal OUT is adjusted by changing the value of each bit of the control signal S2 to increase the current capacity.
On the other hand, when the fall time is early, the switch SWN2 is not turned on, the n-type transistor MN2 is fixed to the off state, and one or both of the other switches SWN3 and SWN4 are turned on and driven by the input signal. The rise time of the output signal OUT is adjusted by changing the combination of transistors, that is, by changing the value of each bit of the control signal S1 so as to control the on and off states of each switch and reducing the current capacity. To do.

Then, the control signal S1 {P2, P3, P4} and the control signal S2 {N2, N3, N4} from the outside having the rise time and the fall time corresponding to the design value are obtained by the above-described operation characteristic test process. The data of the respective bits P2 to P4 and N2 to N4 is selected and stored in the storage units 12 and 14 when the external measuring device gives the write signal W in a state where the calibration signal CAL is input. Let
Here, if the storage units 12 and 14 are one-time ROMs, the first control unit 11 sends the bit information of P2 to P4 in the control signal S1 {P2, P3, P4} from the outside to the storage unit 12. 1 and the second control unit 13 writes the bit information of N2 to N4 in the control signal S2 {N2, N3, N4} from the outside as the second control information S2. .

In the case of a nonvolatile memory, when the mounted semiconductor device is activated, the output driver uses the first and second control information stored in the storage units 12 and 14 to switch the switch group 3. Each switch is turned on, or the connected transistor is turned off, and the output signal OUT for the input signal is externally generated by the rise time and fall time waveforms corrected to correspond to the design values by the test. Output to.
Therefore, even if the rise time and the fall time fluctuate with respect to the design value due to manufacturing variations of the transistors in the transistor section 2 of the output driver, it can be adjusted by the above-described processing. Characteristics can be obtained.

FIG. 2 is a graph showing simulation results, in which the horizontal axis represents time and the vertical axis represents the signal level (amplitude voltage value).
The waveform of the output signal OUT is shown with respect to the input signal IN, and the leftmost waveform in the rising waveform is the first control signal S1 = S1 {1, 1, 1}, and the second control signal S2 = S2 {1, 1, 1}, and since all of the p-type transistors MP1 to MP4 and the n-type transistors MN1 to MN4 are driven by the input signal, the rise time and fall time are the fastest. I understand.
In the rising waveform, the rightmost waveform is the first control signal S1 = S1 {0, 0, 0}, the second control signal S2 = S2 {0, 0, 0}, and the p-type transistor MP1 and the n-type transistor Since only the transistor MN1 is driven by the input signal, it can be seen that the rise time and the fall time are the slowest.
Thereby, the drive capability of the transistor part 2 can be changed by changing bit information in the control signals S1 and S2.

It is a block diagram which shows the structural example of the output driver by one Embodiment of this invention. 2 is a graph showing simulation results of rise time and fall time of the output driver (driver circuit) of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control part 2 ... Transistor part 3 ... Switch group 11 ... 1st control part 12, 14 ... Memory | storage part 13 ... 2nd control part 100, 101 ... Inverter MN1, MN2, MN3, MN4 ... n-type transistor MP1, MP2, MP3, MP4... P-type transistors SWN1, SWN2, SWN3, SWN4... Switch SWP1, SWP2, SWP3, SWP4.

Claims (4)

A first MOS transistor group composed of a plurality of first MOS transistors each having a different size connected between a first power source and an output terminal;
A second MOS transistor group composed of a plurality of second MOS transistors of different sizes connected between the output terminal and the second power supply;
A first switch group comprising a first switch for controlling each of said first MOS transistor in said first MOS transistor group in the ON state or OFF state,
A second switch group comprising a second switch for controlling each of said second MOS transistor in said second MOS transistor group in the ON state or OFF state,
A first memory circuit that stores first control information indicating whether each of the first switches of the first switch group is turned on or off;
A second storage circuit for storing second control information indicating whether each of the second switches of the second switch group is turned on or off;
A first control circuit that controls each of the first switches of the first switch group by reading the first control information from the first memory circuit ;
A second control circuit for reading and controlling the second control information from the second memory circuit for each of the second switches in the second switch group ;
I have a,
When a calibration signal is input, the first and second control circuits are not based on the first and second control information stored in the storage circuit, but by external control information input from the outside. Control whether each of the first and second switches is turned on or off, adjust the shape of the output waveform of the driver circuit,
The driver circuit, wherein the first control information and the second control information stored in the storage circuit are changed to the external control information having the output waveform corresponding to a design value . When the calibration signal is input, in each of the first MOS transistor group and the second MOS transistor group, a first MOS transistor group that is turned on, a second MOS transistor group, The driver circuit according to claim 1, wherein the waveform is adjusted. The first MOS transistor is formed by a plurality of p-channel transistors having different transistor sizes, and the second MOS transistor is formed by a plurality of n-channel transistors having different transistor sizes. The driver circuit according to claim 1 or 2 . Each of the first MOS transistors of the first MOS transistor group includes four p-channel transistors having different channel widths, and each of the second MOS transistors of the second MOS transistor group has different channel widths. 4. The driver circuit according to claim 1, comprising four n-channel transistors. 5.

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