JP5115707B2 - Matrix converter and output voltage control method thereof - Google Patents

Description

  The present invention relates to a matrix converter and an output voltage control method thereof.

The conventional matrix converter includes a commutation sequence control circuit group and a shift register that change the commutation order according to the logic state of the input voltage detection signal and the output current detection signal, and does not cause a power supply short circuit or an output open at the time of commutation. An accurate voltage is output (see, for example, Patent Document 1).
In FIG. 3, 1 is an AC power source, 2 is an AC line filter, 3 is a power supply voltage detection circuit, 4 is a gate driver, 5 is a commutation sequence control circuit group, 6 is a controller, 7 is a current direction detection circuit group, and 8 is An AC motor, 9 is a bidirectional switch module, and 10 to 18 are bidirectional switches. Further, signal A is a detected input current phase, signal B is a gate drive signal for driving the bidirectional switch module 9, signal C is a gate signal that is a command signal to the gate driver 4, and signal D is for outputting a voltage. The PWM command, signal E, is the direction of the detected output current.

FIG. 5 is a circuit configuration diagram for one bidirectional switch of the commutation sequence control circuit group 5. The commutation sequence control circuit group 5 of FIG. 4 includes a circuit for controlling nine bidirectional switches. Exists. In the figure, 19 and 20 are latch circuits, 21 is an edge detection circuit, 22 is a logic decision circuit, 23 is a shift register A, 24 is a shift register B, 25 is a shift register C, and the edge detection circuit 21 is a latch circuit. The update timing edge of the PWM command is detected at the change timing of the signals F and G from the signals 19 and 20, and the signal H is output to the logic determination circuit 22 at that timing.
Signal F is the next PWM command, signal G is the current PWM command, and signal H is the PWM command update edge signal.
The shift registers A, B, and C are n-bit shift registers, and data is shifted from a lower bit to an upper bit by a shift clock (not shown) and the most significant bit is output. This shift clock is input from the controller 6 with a period of ΔT / n. ΔT is the switching delay time of the bidirectional switch. As a result, the data in the shift registers A, B, and C are all updated as the switching delay time ΔT elapses. Further, the shift register A is set to “1” by the output I of the logic judgment circuit 17 and the shift register B is set to “1” by the output J of the logic judgment circuit 17, and the bit “1” has a delay time ΔT due to commutation. Correction is made. The output signal C of the shift register C becomes a gate signal and is input to the gate driver 4.

Thus, the conventional matrix converter uses the shift register and the logic determination circuit, corrects the switching delay time ΔT, and outputs an accurate voltage command without causing a power supply short circuit or an output opening.
JP 2006-158063 A (Page 4-5, FIGS. 1 and 3)

The conventional matrix converter tries to output even a voltage command that becomes a very small PWM signal that cannot be output in the first place, so an extremely excessive reverse recovery surge voltage is generated and exceeds the withstand voltage product guaranteed value of the bidirectional switch. There was a fear.
The present invention has been made in view of such problems, and provides a highly reliable matrix converter and its output voltage control method that suppress switching surge voltage and eliminate the possibility of damage to the bidirectional switch. For the purpose.

In order to solve the above problem, the present invention is configured as follows.
According to one aspect of the present invention, a controller for calculating a voltage command to be output to the AC motor, and detects the voltage phase of the AC power input, an input voltage detection circuit for outputting an input voltage detection signal, the output current It detects an output current detection circuit for outputting an output current detection signal, based on the logic state of the input voltage detection decyne item and the output current detection No. decyne, commutation sequence for switching the firing order of the bidirectional switch and a control circuit group, and the phases of the AC motor and each phase of the AC power supply connected with the bidirectional switches, the third level of the maximum voltage, intermediate voltage and the minimum voltage a voltage corresponding to the voltage command met matrix converter and outputting the at PWM signal to drive the bi-directional switch to the AC motor, the controller, PW of the intermediate voltage at a predetermined transition timing of the PWM signal And signal ON time a predetermined time ensure (minimum time securing process), the commutation sequence control circuit group, a dead time correction process P WM signal of said third level to using a shift register for switching delay time correction alms, further, ON time and OFF time of the three levels of the P WM signal after the dead time correction process for a given value or less parts, in which a predetermined time allocating (adding correction processing).

According to a second aspect of the present invention, in the matrix converter according to the first aspect, the minimum time securing process includes a transition timing from the intermediate voltage PWM signal to the maximum voltage PWM signal and the maximum voltage. At the timing of transition from the PWM signal of the intermediate voltage to the PWM signal of the intermediate voltage, at least the ON time of the PWM signal of the intermediate voltage is extended or the OFF time of the PWM signal of the maximum voltage is extended.
Further, the invention according to claim 3, in the matrix converter according to claim 1 or 2, wherein additional correction process, the upper and lower bits of the shift register using a shift register for minimum time ensuring " 1 ", and""a long if therebetween bits are all" 1 0 "is long if between bits" and generates a P WM signal of said third level 0 ".

In order to solve the above problem, the present invention is as follows.
In the invention according to claim 4, each phase of the AC power source and each phase of the AC motor are connected by a bidirectional switch, and the voltage corresponding to the voltage command is represented by a three-level PWM signal of maximum voltage, intermediate voltage, and minimum voltage. A matrix converter output voltage control method for driving the bidirectional switch to output to the AC motor, detecting a voltage phase of an input AC power supply, outputting an input voltage detection signal, and an output current Detecting and outputting an output current detection signal, switching the firing order of bidirectional switches based on the logic state of the input voltage detection signal and the output current detection signal, and the PWM signal of the intermediate voltage from the PWM signal At the timing of the transition to the maximum voltage PWM signal and the timing of the transition from the maximum voltage PWM signal to the intermediate voltage PWM signal, at least before Or extending the ON time of the intermediate voltage PWM signal, or a to step if extended the OFF time of the PWM signal of the maximum voltage, with respect to P WM signal of the third level, dead using a shift register for switching delay time correction and line cormorant step time correction process, the ON time and the OFF time of the three-level PWM signal to a predetermined value or less parts, if upper bits and lower bits of the shift register for minimum time ensured "1" therebetween bits are all "1", "0" is between bits long and includes the steps of: generating a P WM signal of the third level as "0", the updating of the PWM signal for each cycle To do it.

  According to the invention described in the claims, the PWM signal of the output voltage command can secure predetermined minimum ON time and minimum OFF time, and the surge voltage generated at the time of PWM switching can be made lower than the withstand voltage of the bidirectional switch. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a matrix converter of the present invention. In the figure, the same parts as those in FIG. 3 which is a block diagram of the prior art will not be described, and different portions 5 ′ will be described below.
Reference numeral 5 'denotes a commutation sequence control circuit group, which is commutated according to the logical state of the PWM command D from the controller 6, the input voltage phase A from the input power supply voltage detection circuit 3, and the output current direction E from the output current detection circuit 7. The gate signal C ′ to which the delay time ΔT and the minimum ON time ΔT ′ are added is output to the gate driver 4.
The present invention is different from the prior art in that a commutation sequence control circuit group 5 ′ is provided instead of the commutation sequence control circuit group 5, and a gate signal C ′ is output instead of the gate signal C. .

FIG. 2 is a circuit configuration diagram of one bidirectional switch of the commutation sequence control circuit group 5 ′. In the figure, instead of inputting the output signal of the shift register B (24) in FIG. 4 of the prior art to the shift register C (25), the output signal is changed to the input to the shift register D (26). The output signal K is input to the shift register D (26). In the shift register D (26), the PWM signal L in which the minimum time ΔT ′ is secured is generated and output to the shift register C (25).
In order to secure the minimum time ΔT ′, the minimum time ΔT ′ is taken into consideration by the number of bits corresponding to the time required to shift 1 bit, and is added to each signal as a pulse width corresponding to the number of bits. This is realized.
Thus, the commutation sequence control circuit group 5 ′ is configured.

Next, the operation of the shift register D (26) will be described with reference to FIG.
The shift register D (26) in the figure is composed of a register having a bit number (hereinafter referred to as m bits) corresponding to the minimum time ΔT ′. The data input from the shift register B (24) is shifted from the lower bit to the upper bit by the shift clock, and the shifted out bit is output as the signal L to the shift register C (25).
The shift register D (26) performs the following operation using the shift register D set signal K from the logic determination circuit 22 as a trigger.
If the bit state in the shift register D (26) is “0” between both the upper bit and the lower bit “1”, all the bits between them are set to “1”. If there is “1” between “0”, all the bits between them are “0”. Then, the state other than the above is output as it is, and the bit state in the shift register D (26) is changed / updated.
In this way, the shift register D (26) outputs the PWM signal L that secures the minimum time ΔT ′.

Next, the operation of the commutation sequence performed using the commutation sequence control circuit group 5 ′ will be described with reference to the flowchart showing the processing procedure of FIG.
First, in step 1, the controller 6 calculates an output voltage command to be output to the motor 8 by V / f constant control or the like (not shown), and uses the input voltage phase signal A from the input power supply voltage detection circuit 3. Then, the intermediate voltage command and the maximum voltage command are determined, and the intermediate pulse command MID, the maximum pulse command MAX, and the minimum pulse command MIN are obtained by comparing with the carrier signal for PWM control.
Next, in step 2, the controller 6 sets the maximum pulse command MAX for a period corresponding to m bits from the rising edge of the intermediate pulse command MID to “0”, and further changes to m bits from the falling edge of the intermediate pulse command MID. The maximum pulse command MAX for the corresponding period is set to “0”.
In this way, the controller 6 sets the maximum pulse command MAX to “0” at the timing of transition from the intermediate pulse command MID to the maximum pulse command MAX and the timing of transition from the maximum pulse command MAX to the intermediate pulse command MID. An intermediate pulse command MID that secures “1” for the time ΔT ′ is generated.

  Next, in step 3, the controller 6 outputs the intermediate pulse command MID, the maximum pulse command MAX, and the minimum pulse command MIN generated in step 2 to the commutation sequence circuit group 5 'as the PWM signal D. In the commutation sequence circuit group 5 ′, dead time correction processing for the commutation delay time ΔT is performed on the input PWM signal D. The logic determination circuit 22 in the commutation sequence circuit group 5 ′ uses the shift register A (23) as a trigger for the shift register A set signal I and the shift register B (24) as a trigger for the shift register B set signal J. Data is shifted bit by bit from lower bits to upper bits. The shifted out bit is input to the next shift register in accordance with the arrow of the circuit shown in FIG. Note that the dead time correction processing performed here is performed using the output current direction E 2 output from the output current detection circuit 7 and the input current phase signal A from the input power supply voltage detection circuit 3, which is the same as in the prior art. Since this is a process, a description thereof will be omitted.

Next, in step 4, the shift register D (26) uses the shift register D set signal K from the logic determination circuit 22 as a trigger, and inputs the bit shifted out from the shift register B (24) to the least significant bit. , One bit at a time is shifted from the lower bit to the upper bit. The bit shifted out is input to the shift register C (25).
Similarly, the shift register C (25) shifts 1 bit, and the bit shifted out at this time is output to the gate driver 4 as the gate signal C ′ of the corresponding bidirectional switch 10-18.
Thereafter, if the upper bit and the lower bit in the shift register D (26) are “1”, all the bits between them are “1”, and if it is “0”, the bit between them is “0”. Update the bit in (26).
With these operations, the gate signal C ′ ensures a predetermined minimum ON time and minimum OFF time.
The above steps are performed in synchronization with the PWM command update edge signal H.
In step 2, even if the time of “1” of the intermediate pulse command MID is extended by the same method using the shift register, the intermediate pulse command MID that secures “1” for the minimum time ΔT ′ is generated. Needless to say, you can.
In this way, the commutation sequence is performed.

  As described above, since the minimum time securing process for securing the minimum time ΔT ′ at the predetermined transition timing of the PWM signal, the dead time correcting process, and the additional correcting process for securing the minimum time ΔT ′ are performed, the output voltage command Each of the PWM signals satisfies the ON and OFF conditions of a predetermined minimum time, and can suppress a surge voltage generated during PWM switching.

1 is a block diagram of a matrix converter showing a first embodiment of the present invention. Circuit diagram of commutation sequence control circuit group 5 'of the present invention The flowchart which shows the process sequence of this invention Block diagram of conventional matrix converter Circuit configuration diagram of conventional commutation sequence control circuit group 5

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 AC power supply 2 Line filter 3 Input power supply voltage detection circuit 4 Gate driver 5, 5 'Commutation sequence control circuit group 6 Controller 7 Output current detection circuit 8 Motor 9 Bidirectional switch module 10-18 Bidirectional switch 19, 20 Latch circuit 21 Edge detection circuit 22 Logic determination circuit 23 Shift register A
24 Shift register B
25 Shift register C
26 Shift register D
A input current phase B gate drive signal C, C ′ gate signal D PWM command E output current direction F next PWM command G current PWM command H PWM command update edge signal I shift register A set signal J shift register B set signal K shift register D set signal L PWM signal ensuring minimum time ΔT '

Claims (4)

A controller for calculating a voltage command to be output to the AC motor, and detects the voltage phase of the AC power input, an input voltage detection circuit for outputting an input voltage detection signal, detects the output current, the output current detection signal an output current detection circuit for outputting, based on the logic state of the input voltage detection decyne item and the output current detection No. decyne, with a commutation sequence control circuits for switching the firing order of the two-way switch, the said the phases and each phase of the AC motor of the AC power supply connected with the bidirectional switches, drives the bidirectional switch a voltage corresponding to the voltage command at the third level of the PWM signal of the maximum voltage, intermediate voltage and the minimum voltage A matrix converter for outputting to the AC motor,
The controller, the above at a predetermined transition timing of the PWM signal intermediate voltage ON time of the PWM signal for a predetermined time ensure the (minimum time securing process),
The commutation sequence control circuit group, the three relative levels of P WM signal subjected to dead time correction by using the shift register of the switching delay time correction, addition, of the three levels after the deadtime correction process P A matrix converter characterized in that a predetermined time is secured (additional correction processing) for a portion where an ON time and an OFF time of a WM signal are not more than a predetermined value .   The minimum time securing process includes at least the intermediate voltage at a timing of transition from the PWM signal of the intermediate voltage to the PWM signal of the maximum voltage and at a timing of transition from the PWM signal of the maximum voltage to the PWM signal of the intermediate voltage. 2. The matrix converter according to claim 1, wherein the ON time of the PWM signal is extended or the OFF time of the PWM signal having the maximum voltage is extended. The additional correction process, all minimum time between bits when the higher-order bits and the lower bits of the shift register is "1" using a shift register for securing is a "1", in between if "0" matrix converter according to claim 1 or 2 bits and generates a P WM signal of the third level as "0". Each phase of the AC power supply and each phase of the AC motor are connected by a bidirectional switch, and the bidirectional switch is driven by a three-level PWM signal of a maximum voltage, an intermediate voltage, and a minimum voltage according to a voltage command. An output voltage control method for a matrix converter that outputs to an AC motor,
Detecting the voltage phase of the input AC power supply and outputting an input voltage detection signal;
Detecting an output current and outputting an output current detection signal;
Switching the firing order of the bidirectional switch based on the logical state of the input voltage detection signal and the output current detection signal;
At least the ON time of the intermediate voltage PWM signal at the timing of transition from the intermediate voltage PWM signal to the maximum voltage PWM signal and the transition timing from the maximum voltage PWM signal to the intermediate voltage PWM signal. and to step it extend the OFF time of the PWM signal of extended or, alternatively the maximum voltage,
The relative third level of P WM signal, and row Cormorant step dead time correction by using the shift register of the switching delay time correction,
The relative ON time and the OFF time is equal to or less than a predetermined value portion of the three-level PWM signal, the upper and lower bits of the shift register for a minimum time ensured a "1" if it therebetween bits are all "1" , during which the bit if "0" is a step of generating a P WM signal of the third level as "0",
It includes an output voltage control method for a matrix converter which comprises carrying out the updating of the PWM signal for each cycle.

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