JP4664166B2 - Multi-relative multi-phase power converter - Google Patents

Description

  The present invention relates to a multi-relative multi-phase power converter that directly converts AC power of an AC power source into desired AC power and supplies it to a load while preventing a power supply short circuit or load end opening from occurring when commutating the load current. About.

  When the AC power is directly converted into desired AC power by controlling the matrix converter, a dead time time is provided to commutate the load current while preventing the load end from being opened or the power supply from being short-circuited. However, if a gate control signal is generated by providing a dead time time for the commutation operation of the load current, it takes time from the start to the end of the commutation operation. Therefore, an error occurs between the time of commutation of the load current given by the output voltage command value and the time of actual commutation of the load current. As a result, this output voltage command value and the actual time An error also occurs between the output voltage supplied to the load and the waveform distortion occurs. Therefore, output voltage error correction is necessary to eliminate the output voltage error.

Therefore, as output voltage error correction, the product of the maximum line voltage of AC power supply, dead time, and control frequency multiplied by the parameter based on the polarity determination result of the load current is used as the output voltage error, and the output voltage command value is set. to correct.
In addition, the number of times of switching between the maximum voltage and the intermediate voltage of the AC power supply in one control cycle, the number of times of switching between the intermediate voltage and the minimum voltage of the AC power supply, the maximum voltage and the minimum voltage of the AC power supply, The output voltage command value is corrected with the product of the value obtained based on the number of times of switching between the dead time, the control frequency multiplied by the parameter based on the polarity determination result of the load current as the output voltage error (For example, refer to Patent Document 1).

JP 2005-20799 A

However, since the maximum line voltage used to calculate the output voltage error is not necessarily equal to the line voltage connected to the load, the output voltage error calculated in this way is a good approximation of the actual output voltage error. There is a problem of not.
Further, in addition to the voltage of the AC power supply, it is necessary to conditionally obtain the number of switching from the switching pattern in the control cycle, and there is a problem that the amount of calculation of the output voltage error increases.

  An object of the present invention is to provide a multi-relative multi-phase power converter that can obtain a high-accuracy output voltage error without increasing the amount of calculation.

The multi-relative multi-phase power conversion device according to the present invention includes a plurality of switches that are connected between an AC power source and a load and are selectively controlled so as to directly convert AC power of the AC power source into predetermined AC power. Based on the main circuit to be configured, and a predetermined output voltage command value and a carrier having a control frequency, the switch is provided with a dead time so that a load end is not opened or a power supply is not short-circuited when a load current is commutated. In a multi-relative multi-phase power converter having gate control means for generating an on / off signal for turning on / off, the output voltage command value is determined by an output voltage error over two consecutive control periods obtained based on the polarity of the load current. an output voltage error correction means for correcting said output voltage error correction unit, a pair of the multi-phase of the AC power to the load in one control period When two phases or two pairs of two phases are connected, the product of the average value of the pair of two-phase line voltages or the two pairs of two-phase line voltages, the dead time, and the control frequency The output voltage error is obtained by multiplying the parameter indicating the polarity of the load current.

  The effect of the multi-relative multi-phase power converter according to the present invention is that two line voltages that are selectively connected to the load in the control cycle when the load current is commutated according to the state of the load current. The output voltage error is calculated as an average error in two consecutive control cycles by multiplying the product of the average value, the open prevention time, and the control frequency by a parameter indicating the polarity of the load current. Since the calculation is performed, a highly accurate output voltage error calculation result can be obtained without increasing the calculation amount.

Embodiment 1 FIG.
FIG. 1 is a block diagram of a multi-relative multi-phase power converter according to Embodiment 1 of the present invention.
As shown in FIG. 1, the multi-relative multi-phase power conversion device 1 according to Embodiment 1 of the present invention is connected between an AC power supply 2 and a load 3, and each phase of the AC power supply 2 and each load 3 are connected. The main circuit 4 that directly converts the AC power of the AC power source 2 into desired AC power by selectively connecting the phases and supplies it to the load 3, and the output that commands the AC power that the main circuit 4 should supply to the load 3 Based on the voltage command means 5 for outputting the voltage command value, the voltage of the AC power source 2 obtained from the voltage detector 6 and the current of the load 3 obtained from the current detector 7, the output voltage command value is corrected and the output voltage command Based on the output voltage error correction means 8 for outputting the correction value, the output voltage command correction value, the voltage of the AC power supply 2 and the current of the load 3, a gate control signal for selectively controlling the main circuit 4 is provided. The gate control means 9 given to is provided.
In the following description, a three-relative three-phase power conversion device will be described as an example of the multi-relative multi-phase power conversion device 1. The three phases of the AC power source 2 are referred to as R phase, S phase, T phase, and the three phases of the load 3 are referred to as U phase, V phase, and W phase.

FIG. 2 is a configuration diagram of the main circuit 4 according to the first embodiment.
As shown in FIG. 2, main circuit 4 directly connects each phase of AC power supply 2 and each phase of load 3 to each other via switches 11UR to 11WT.
FIG. 3 is a configuration diagram of the switch 11UR according to the first embodiment.
Since the switches 11UR to 11WT are similar, only the switch 11UR will be described. As shown in FIG. 3, the switch 11UR includes two semiconductor switch element groups 12URF and 12URR connected in reverse parallel. This semiconductor switch element group 12URF, 12URR is a semiconductor switch element that conducts current in one direction, for example, an emitter of an insulated gate bipolar transistor (hereinafter referred to as IGBT) and an anode of a diode connected at intermediate connection points 13a, 13b. Is.
The semiconductor switch element groups 12URF and 12URR may be configured by connecting the cathode of the diode and the collector of the IGBT at an intermediate connection point.
Further, when the IGBT has resistance to a voltage in the direction opposite to the direction of current application, the diode may be omitted and the IGBT may be configured only.
In the case where the semiconductor switch element groups 12URF and 12URR each have an intermediate connection point, the intermediate connection points may be connected to each other.

  In the three-relative three-phase power conversion device 1 in which the switches 11UR to 11WT have such a configuration, the gate control means 9 provides two gate control signals to the respective IGBTs of the two semiconductor switch element groups constituting the switches 11UR to 11WT. Is normally supplied as the same gate control signal synchronized with the on / off of the switches 11UR to 11WT. In the stage of switching these gate control signals from off to on or from on to off, the gate control means 9 delays the switching operation for one gate control signal by a fixed time, or both gates. By providing a dead time time that delays the switching operation of the control signal by a fixed time different from each other, the current of the load 3 is changed from one phase of the AC power supply 2 without causing a power supply short circuit and a load end opening. To one phase. The dead time includes a short circuit prevention time tp that is a delay time for preventing a power supply short circuit from occurring, and an open prevention time to that is a delay time for preventing the load end from being opened.

FIG. 4 is a diagram of a portion connected to the U phase of the load 3 of the three-relative three-phase power converter 1 of FIG.
The U phase of the load 3 and each phase of the AC power supply 2 are directly connected by the switches 11UR, 11US, and 11UT, and one end of each of the switches 11UR, 11US, and 11UT is connected to the R, S, and T phases of the AC power supply 2, respectively. Are connected to the U phase of the load 3. Among the semiconductor switch element groups constituting the switches 11UR, 11US, and 11UT, the semiconductor switch element groups that conduct current in the direction from the AC power supply 2 to the load 3 are respectively 12URF, 12USF, and 12UTF, and the direction from the load 3 to the AC power supply 2 The semiconductor switch element groups that pass current through are 12URR, 12USR, and 12UTR, respectively. The R, S, and T phase voltages of the AC power supply 2 are Vr, Vs, Vt, R-S, S-T, and T-R line voltages are Vrs, Vst, Vtr, and load 3, respectively. Let Uu be the current of the U phase.

As an example of the commutation operation of the load current, when performing the commutation operation from the switch 11US to 11UR, a gate control signal to be given to the IGBTs of the semiconductor switch element groups 12URF, 12URR, 12USF, and 12USR constituting the switches 11UR and 11US, respectively. Timing charts showing changes in TURF, TURR, TUSF, and TUSR are shown in FIGS. These timing charts are divided into a commutation operation according to the state of the load current and a commutation operation according to the state of the AC power supply 2, and the former for each state of the load current and the latter for the AC power supply 2. Each state is shown separately.
In the following timing chart, the opening prevention time to is longer than the short-circuit prevention time tp, but the same applies even when the opening prevention time to is shorter than the short-circuit prevention time tp or when the opening prevention time to is equal to the short-circuit prevention time tp. is there. Further, the hatched portion in the figure means that each gate control signal is 1, and an ON signal is given to the IGBT.

FIG. 5 is a timing chart showing a commutation operation according to the state of the load current when the load current flows from the AC power supply 2 to the load 3. In period (1), TUSR and TURF are prevented from being turned on at the same time to prevent a power supply short circuit, and in period (2), TURF and TUSF are prevented from being turned off at the same time to prevent load end opening. In (3), a power supply short circuit is prevented by preventing TUSF and TURR from being turned on simultaneously.
FIG. 6 is a timing chart showing a commutation operation according to the state of the load current when the load current flows from the load 3 to the AC power supply 2. In period (1), TUSF and TURR are prevented from being turned on at the same time to prevent a power supply short circuit, and in period (2), TURR and TUSR are prevented from being turned off at the same time to prevent load end opening. In (3), a power supply short circuit is prevented by preventing TUSR and TURF from being turned on simultaneously.
FIG. 7 is a timing chart showing a commutation operation according to the state of the AC power supply 2 when the line voltage Vrs between the R phase and the S phase of the AC power supply 2 of FIG. 4 is positive. In period (1), TURR and TUSR are prevented from being turned off at the same time to prevent the load end from being opened. In period (2), TUSR and TURF are prevented from being turned on at the same time to prevent a power supply short circuit. In (3), the load end is prevented from opening by preventing TURF and TUSF from turning off at the same time.
FIG. 8 is a timing chart showing a commutation operation according to the state of the AC power supply 2 when the line voltage Vrs between the R phase and the S phase of the AC power supply 2 of FIG. 4 is negative. In period (1), TURF and TUSF are prevented from being turned off at the same time to prevent the load end from being opened. In period (2), TUSF and TURR are prevented from being turned on at the same time to prevent a power supply short circuit. (3) prevents the load end from being opened by preventing TURR and TUSR from turning off at the same time.

FIG. 9 is a block diagram of the output voltage error correction means 8 according to the first embodiment of the present invention.
As shown in FIG. 9, the output voltage error correction means 8 according to the first embodiment is selected as the load 3 in the control cycle from the line voltages Vrs, Vst, Vtr of the AC power supply 2 obtained from the voltage detector 6. A line voltage extractor 21 that extracts two line voltages connected in series, an average value calculator 22 that calculates an average value of the two line voltages extracted by the line voltage extractor 21, and the average value Regarding the first multiplier 23 that outputs the product of the open prevention time to and the control frequency fc, and the currents Iu, Iv, and Iw of the load 3, the direction of each current is the direction from the AC power supply 2 to the load 3. 1 if there is a direction from the load 3 to the AC power supply 2 -1 if the current polarity parameter is output as a current polarity parameter, and the result obtained by multiplying the calculation result of the first multiplier 23 and the current polarity parameter. The result is output The second multiplier 25 that is output as an error, the output voltage error that is output from the second multiplier 25, and an operation that corrects the output voltage command values Vu1 *, Vv1 *, and Vw1 * output from the voltage command means 5, A voltage corrector 26 that outputs the calculation result as output voltage command correction values Vu2 *, Vv2 *, Vw2 * is provided.

FIG. 10 shows a pulse pattern when a commutation operation according to the state of the load current is performed at the time of commutation of the load current in a modulation system in which power is supplied to the load 3 by pulse width modulation of a virtual DC voltage. It is a timing chart which showed an example of voltage behavior, and shows about two continuous control periods of 3 relative 3 phase power converters.
In this modulation method, the line voltage of the two phases is regarded as a constant virtual DC voltage in a sufficiently short time to connect the two phases of the AC power supply 2 to one phase of the load 3, and the line voltage is The output voltage is supplied to the load 3 by controlling in the same manner as the PWM inverter. In the PWM modulation method, generally, a pulse pattern for turning on / off each switch is generated by a triangular carrier wave in which one cycle as a carrier is one control cycle and a voltage command value Vu *. A method for generating a pulse pattern in this method is described in Japanese Patent Publication No. 8-32177 “3-relative three-phase power conversion device”, and detailed description thereof will be omitted.

On-off signals TUR, TUS, TUT for turning on / off the switches 11UR, 11US, 11UT are generated from the voltage command value Vu * and the triangular carrier wave generated for each control cycle, and the time-series voltage command generated in the U phase from these on-off signals VuT * is obtained.
Since the voltage command value Vu * is an average value in the control cycle of the time series voltage command VuT *, assuming that the voltage of the AC power supply 2 is constant in the two consecutive control cycles, the voltage command value Vu *. Is obtained by equation (1).

Vu * = (Vr × Tr + Vs × Ts + Vt × Tt) / (Tr + Ts + Tt)
= (Vr * Tr + Vs * Ts + Vt * Tt) * fc (1)

  The gate control signals TURF to TUTR are generated as pulse patterns such that the time-series voltage command VuT * appears in the U phase according to the on / off signals TUR, TUS, TUT, but when the load current is commutated, FIG. The pulse pattern is obtained by giving a dead time to the ON / OFF operation of the gate control signal so that the commutation operation according to the load current state of 6 is performed. As a result, an error occurs between the time series voltage VuT actually appearing in the U phase and the time series voltage command VuT *, and the time series voltage average voltage Vu (not shown) and the voltage command value Vu * A voltage error will also occur between the two.

FIG. 11A shows the behavior of the pulse pattern of the gate control signals TURF to TUTR and the time series voltage VuT when the load current flows from the AC power supply 2 to the load 3.
Times TtA1, TsA1, TrA1, TrA2, TsA2, TtA2 for connecting the three phases of the AC power supply 2 to the U phase of the load 3 in the first control period and the second control period are the voltages of the time-series voltage command VuT *. In terms of behavior, the time Tr, Ts, Tt, the short-circuit prevention time tp, and the open prevention time to that connect the three phases of the AC power supply 2 to the U-phase of the load 3 are obtained by the equations (2) to (7).

TtA1 = Tt + tp + to (2)
TsA1 = Ts-to (3)
TrA1 = Tr−tp (4)
TrA2 = Tr + tp + to (5)
TsA2 = Ts-to (6)
TtA2 = Tt−tp (7)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 11A is obtained by Expression (8).

Vu = {Vr × (TrA1 + TrA2) + Vs × (TsA1 + TsA2) +
Vt × (TtA1 + TtA2)} / (TrA1 + TrA2 + TsA1 +
TsA2 + TtA1 + TtA2)
= {Vr × (2 × Tr + to) + Vs × (2 × Ts−2 × to) +
Vt × (2 × Tt + to)} × fc / 2 (8)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Equation (9).

ΔVu = Vu−Vu *
= {Vr * to + Vs * (-2 * to) + Vt * to} * fc / 2
= (Vrs + Vts) / 2 × to × fc (9)

The voltage Vrs is a line voltage between the R phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 in one control cycle, and can be handled as a virtual DC voltage. . The voltage Vts is a line voltage between the T phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 for the remainder of the control cycle. Therefore, the product of the average value of the two line voltages connected to the load 3, the open prevention time to, and the control frequency fc is the output voltage error ΔV.
FIG. 11B shows the behavior of the pulse pattern of the gate control signals TURF to TUTR and the time-series voltage VuT when the load current flows from the load 3 to the AC power supply 2.
Times TtB1, TsB1, TrB1, TrB2, TsB2, and TtB2 for connecting the three phases of the AC power source 2 to the U phase of the load 3 are respectively set to the three phases of the AC power source 2 in the voltage behavior of the time series voltage command VuT *. Using the times Tr, Ts, Tt, the short-circuit prevention time tp, and the open-circuit prevention time to, which are connected to the U phase, are obtained by the equations (10) to (15).

TtB1 = Tt + tp (10)
TsB1 = Ts + to (11)
TrB1 = Tr-tp-to (12)
TrB2 = Tr + tp (13)
TsB2 = Ts + to (14)
TtB2 = Tt-tp-to (15)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 11B is obtained by Expression (16).

Vu = {Vr × (TrB1 + TrB2) + Vs × (TsB1 + TsB2) +
Vt × (TtB1 + TtB2)} / (TrB1 + TrB2 + TsB1 +
TsB2 + TtB1 + TtB2)
= {Vr × (2 × Tr−to) + Vs × (2 × Ts + 2 × to) +
Vt × (2 × Tt-to)} × fc / 2 (16)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Equation (17).

ΔVu = Vu−Vu *
= {Vr × (−to) + Vs × 2 × to + Vt × (−to)} × fc / 2
= − (Vrs + Vts) / 2 × to × fc (17)

As the polarity of the load current is reversed in this way, the polarity of the output voltage error ΔV is also reversed.
The output voltage error ΔV can be calculated in the same manner for the other phases of the load 3. Moreover, even when the polarities of the voltages Vr, Vs, and Vt of the AC power supply 2 are different, or when the combination of the line voltages of the AC power supply 2 that is selectively connected to the load 3 is different in the control cycle, the same operation can be performed. . Furthermore, even when the open prevention time to is shorter than the short circuit prevention time tp, or when the open prevention time to is equal to the short circuit prevention time tp, the same operation can be performed.

  Therefore, the output voltage command correction values Vu2 *, Vv2 *, Vw2 obtained by correcting the output voltage command values Vu1 *, Vv1 *, Vw1 * output by the voltage command means of FIG. 1 with the output voltage errors ΔVu, ΔVv, ΔVw. * Is obtained by the equations (18) to (20). Here, sgn (Iu), sgn (Iv), and sgn (Iw) are current polarity parameters representing polarities of the U-phase load current Iu, the V-phase load current Iv, and the W-phase load current Iw, respectively, , Iv, Iw is 1 if positive, and -1 if negative.

Vu2 * = Vu1 * − (average value of two line voltages connected to the load)
× to × fc × sgn (Iu) (18)
Vv2 * = Vv1 * − (average value of two line voltages connected to the load)
× to × fc × sgn (Iv) (19)
Vw2 * = Vw1 * − (average value of two line voltages connected to the load)
× to × fc × sgn (Iw) (20)

  In the above calculation, the output voltage error is calculated as an average error of two consecutive control cycles. However, such a calculation is performed every two control cycles even if every calculation cycle is performed. However, there is no problem even if the calculation interval is not set.

  When such a multi-relative multi-phase power converter 1 performs a load current commutation operation in accordance with the state of the load current, the two relative line voltage selectively connected to the load 3 in the control cycle is obtained. The average value is calculated, and the product of the average value, the open prevention time, and the control frequency is multiplied by a parameter indicating the polarity of the load current, thereby calculating the output voltage error as an average error in two consecutive control cycles. As a result, a highly accurate output voltage error calculation result can be obtained without increasing the amount of calculation.

Embodiment 2. FIG.
FIG. 12 is a block diagram of the output voltage error correction means 8B according to Embodiment 2 of the present invention.
The multi-relative multi-phase power converter according to the second embodiment of the present invention performs a load current commutation operation according to the state of the AC power supply 2. As shown in FIG. 12, the output voltage error correction unit 8B according to the second embodiment is similar to the output voltage error correction unit 8 according to the first embodiment except that a polarity inverter 31 is provided after the current polarity parameter calculator 24. Since the first multiplier 23B is different, and the others are the same, the same parts are denoted by the same reference numerals, and the description thereof is omitted.
The first multiplier 23B according to the second embodiment multiplies the calculation result of the average value calculator 22 by the control frequency fc and the short-circuit prevention time tp. If the calculation results of the output voltage errors ΔVu, ΔVv, ΔVw input to the voltage corrector 26 are the same as the calculation results in the configuration of FIG. 10, the polarity inverter 31 is provided at any position in the figure. Also good.
The voltage command value Vu * and the triangular carrier wave generated for each control cycle in the second embodiment are the same as those in FIG. 10, and as a result, the on / off signals TUR, TUS, TUT and the time series voltage command VuT * are also shown in FIG. Is the same as
FIG. 13 shows a pulse pattern in which a dead time is given to the on / off operation of the gate control signal with respect to the on / off signals TUR, TUS, TUT, and the gate control signals TURF to TUTR are the alternating currents of FIG. 7 or FIG. The commutation operation is set according to the state of the power supply.
FIG. 13A shows the behavior of the pulse pattern of the gate control signals TURF to TUTR and the time series voltage VuT when the load current flows from the AC power supply to the load. The times TtC1, TsC1, TrC1, TrC2, TsC2, and TtC2 for connecting the three phases of the AC power supply in the two consecutive control periods to the U phase of the load are the three of the AC power supply 2 in the voltage behavior of the time series voltage command VuT *. Using the times Tr, Ts, Tt, the short-circuit prevention time tp, and the open-circuit prevention time to that each phase is connected to the U phase of the load 3, the values are obtained by the equations (21) to (26).

TtC1 = Tt + to (21)
TsC1 = Ts + tp (22)
TrC1 = Tr-to-tp (23)
TrC2 = Tr + to (24)
TsC2 = Ts + tp (25)
TtC2 = Tt-to-tp (26)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 13A is obtained by Expression (27).

Vu = {Vr × (TrC1 + TrC2) + Vs × (TsC1 + TsC2) +
Vt × (TtC1 + TtC2)} / (TrC1 + TrC2 + TsC1 +
TsC2 + TtC1 + TtC2)
= {Vr × (2 × Tr−tp) + Vs × (2 × Ts + 2 × tp) +
Vt × (2 × Tt−tp)} × fc / 2 (27)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Equation (28).

ΔVu = Vu−Vu *
= {Vr × (−tp) + Vs × 2 × tp + Vt × (−tp)} × fc / 2
= − (Vrs + Vts) / 2 × tp × fc (28)

  The voltage Vrs is a line voltage between the R phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 in one control cycle, and can be handled as a virtual DC voltage. . The voltage Vts is a line voltage between the T phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 for the remainder of the control cycle. Therefore, the product of the average value of the two line voltages, the short-circuit prevention time tp, and the control frequency fc is the output voltage error ΔVu. However, the polarity of the output voltage error is opposite to the polarity of the output voltage error that occurs when a load current commutation operation is performed according to the state of the load current.

  FIG. 13B shows the pulse pattern of the gate control signals TURF to TUTR and the behavior of the time series voltage VuT when the load current flows from the load 3 to the AC power supply 2. Times TtD1, TsD1, TrD1, TrD2, TsD2, and TtD2 for connecting the three phases of the AC power source 2 to the U phase of the load 3 are respectively set to the three phases of the AC power source 2 in the voltage behavior of the time series voltage command VuT *. It is calculated | required by Formula (29)-Formula (34) using the time Tr, Ts, Tt, the short circuit prevention time tp, and the open prevention time to which connect to U phase.

TtD1 = Tt + to + tp (29)
TsD1 = Ts−tp (30)
TrD1 = Tr-to (31)
TrD2 = Tr + to + tp (32)
TsD2 = Ts−tp (33)
TtD2 = Tt-to (34)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 13B is obtained by Expression (35).

Vu = {Vr × (TrD1 + TrD2) + Vs × (TsD1 + TsD2) +
Vt × (TtD1 + TtD2)} / (TrD1 + TrD2 + TsD1 +
TsD2 + TtD1 + TtD2)
= {Vr × (2 × Tr + tp) + Vs × (2 × Ts−2 × tp) +
Vt × (2 × Tt + tp)} × fc / 2 (35)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Expression (36).

ΔVu = Vu−Vu *
= {Vr * tp + Vs * (-2 * tp) + Vt * tp} * fc / 2
= (Vrs + Vts) / 2 × tp × fc (36)

In other words, when the polarity of the load current is reversed, the polarity of the output voltage error is also reversed. The polarity of the output voltage error is also opposite to the polarity of the output voltage error that occurs when performing a load current commutation operation in accordance with the state of the load current.
The calculation of the output voltage error as described above can be similarly performed for other phases of the load. The same can be done even when the polarities of the voltages Vr, Vs, Vt of the AC power supply are different, or when the combination of the line voltages of the AC power supply selectively connected to the load is different in the control cycle. Furthermore, even when the open prevention time to is shorter than the short circuit prevention time tp, or when the open prevention time to is equal to the short circuit prevention time tp, the same operation can be performed.
Therefore, the output voltage command correction values Vu2 *, Vv2 *, Vw2 * obtained by correcting the output voltage command values Vu1 *, Vv1 *, Vw1 * output by the voltage command means 5 with the output voltage errors ΔVu, ΔVv, ΔVw are: It is calculated | required by Formula (37)-Formula (38).

Vu2 * = Vu1 * + (average value of two line voltages connected to the load)
* Tp * fc * sgn (Iu) (37)
Vv2 * = Vv1 * + (average value of two line voltages connected to the load)
× tp × fc × sgn (Iv) (38)
Vw2 * = Vw1 * + (average value of two line voltages connected to the load)
* Tp * fc * sgn (Iw) (39)

  In the above calculation, the output voltage error is calculated as an average error of two consecutive control cycles. However, such a calculation is performed every two control cycles even if every calculation cycle is performed. However, there is no problem even if the calculation interval is not set.

  Such a multi-relative multi-phase power converter extracts two line voltages that are selectively connected to the load 3 in the control cycle when performing a load current commutation operation in accordance with the state of the AC power supply 2. Then, the average value thereof is calculated, and the product of the average value, the short-circuit prevention time tp and the control frequency fc is multiplied by a parameter indicating the polarity of the load current, whereby the output voltage error is calculated for two control cycles. Since the calculation is performed as the average error, a highly accurate output voltage error can be obtained without increasing the calculation amount.

  Thus, in both cases where the load current is commutated in accordance with the state of the load current or the state of the AC power supply, a highly accurate output voltage error can be obtained without increasing the amount of calculation.

Embodiment 3 FIG.
FIG. 14 is a configuration diagram of a main circuit of a three-relative three-phase power conversion device according to Embodiment 3 of the present invention.
In the main circuit 4C of the three-relative three-phase power conversion device according to the third embodiment, the three phases of the AC power supply 2 and the terminals 34P and 34N of the DC circuit 33 are directly connected to each other via switches 35PR to 35NT. The terminals 34P and 34N of the DC circuit 33 and the three phases of the load 3 are connected to each other via the half bridge circuits 36UB to 36WB.
The switches 35PR to 35NT have the same configuration as that shown in FIG. 3, and the gate control signals given to the two IGBTs constituting the switches 35PR to 35NT are the same gate control signals synchronized with the on / off of the switches 35PR to 35NT. In the configuration of the main circuit 4C, when these gate control signals are switched from OFF to ON or from ON to OFF, all phases of the load 3 are short-circuited at the terminal 34P or 34N of the DC circuit 33 by the half bridge circuits 36UB to 36WB. By setting this in a circulating state, the current flowing between the AC power supply 2 and the load 3 via the terminals 34P and 34N of the DC circuit 33 can be made zero. Therefore, it is not necessary to provide an opening prevention time for preventing the load end from being opened, and it is not necessary to perform the commutation operation according to the load current of FIG. It is only necessary to simply provide the short-circuit prevention time tp for preventing the short circuit between off and on.

  On the other hand, in the half bridge circuits 36UB to 36WB, in order to prevent a short circuit between the terminals 34P and 34N of the DC circuit 33, gate control signals given to the two IGBTs 37UP and 37UN constituting the half bridge circuits 36UB to 36WB are respectively provided. Provide a short-circuit prevention time when switching.

FIG. 15 is a timing chart showing an example of a pulse pattern and voltage behavior in the main circuit configuration of FIG. 14, and shows two consecutive control periods of the three-relative three-phase power converter.
The voltage command value Vu * and the triangular carrier wave generated for each control cycle are the same as in FIG. At this time, the switches 35PR, 35PS, 35PT, 35NR, 35NS, and 35NT are turned on / off signals TPR, TPS, TPT, TNR, TNS, TNT, and the half-bridge circuit 36UB are connected to the terminals 34P and 34N of the DC circuit 33, respectively. An output control signal TU indicating which of the two is connected is generated, and a time series voltage command VuT * generated in the U phase is obtained from these signals. This time series voltage command VuT * is the same as in FIG. .

  The gate control signals TUP and TUN for turning on and off the IGBTs 37UP and 37UN of the half-bridge circuit 36UB are generated as a pulse pattern such that the time series voltage command VuT * appears in the U phase according to the output control signal TU. When switching between and 34N, a pulse pattern in which a dead time tp is given to the ON operation so as to prevent a short circuit is obtained. As a result, an error occurs between the time series voltage VuT actually appearing in the U phase and the time series voltage command VuT *, and the time series voltage average voltage Vu (not shown) and the voltage command value Vu * A voltage error will occur between the two.

  FIG. 16A shows the behavior of the pulse pattern of the gate control signals TUP and TUN and the time series voltage VuT when the load current flows from the AC power supply 2 to the load 3. The times TtE1, TsE1, TrE1, TrE2, TsE2, and TtE2 at which the three phases of the AC power source 2 appear in the U phase of the load 3 are respectively set to the three phases of the AC power source 2 in the voltage behavior of the time series voltage command VuT *. Using the times Tr, Ts, Tt and the short-circuit prevention time tp for connecting to the U phase, the values are obtained by the equations (40) to (45).

TtE1 = Tt (40)
TsE1 = Ts + tp (41)
TrE1 = Tr−tp (42)
TrE2 = Tr (43)
TsE2 = Ts + tp (44)
TtE2 = Tt−tp (45)

  Since the average voltage Vu is an average value of the time series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 16A is obtained by the equation (46).

Vu = {Vr × (TrE1 + TrE2) + Vs × (TsE1 + TsE2) +
Vt × (TtE1 + TtE2)} / (TrE1 + TrE2 + TsE1 +
TsE2 + TtE1 + TtE2)
= {Vr × (2 × Tr−tp) + Vs × (2 × Ts + 2 × tp) +
Vt × (2 × Tt−tp)} × fc / 2 (46)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Equation (47).

ΔVu = Vu−Vu *
= {Vr × (−tp) + Vs × 2 × tp + Vt × (−tp)} × fc / 2
= − (Vrs + Vts) / 2 × tp × fc (47)

The voltage Vrs is a line voltage between the R phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 in one control cycle, and can be handled as a virtual DC voltage. . The voltage Vts is a line voltage between the T phase and the S phase of the three phases of the AC power supply 2 connected to the load 3 for the remainder of the control cycle. Therefore, the product of the average value of the two line voltages connected to the load 3 and the short-circuit prevention time tp and the control frequency fc is an output voltage error. This output voltage error is the same as the output voltage error obtained in the second embodiment.
FIG. 16B shows the behavior of the pulse pattern of the gate control signals TUP and TUN and the time-series voltage VuT when the load current flows from the load 3 to the AC power supply 2. The times TtF1, TsF1, TrF1, TrF2, TsF2, and TtF2 at which the voltage of the AC power supply 2 appears in the U phase respectively connect the three phases of the AC power supply 2 to the U phase of the load 3 in the voltage behavior of the time series voltage command VuT *. It calculates | requires by Formula (48)-Formula (53) using time Tr, Ts, Tt to perform, and short circuit prevention time tp.

TtF1 = Tt + tp (48)
TsF1 = Ts−tp (49)
TrF1 = Tr (50)
TrF2 = Tr + tp (51)
TsF2 = Ts−tp (52)
TtF2 = Tt (53)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 16B is obtained by Expression (54).

Vu = {Vr × (TrF1 + TrF2) + Vs × (TsF1 + TsF2) +
Vt × (TtF1 + TtF2)} / (TrF1 + TrF2 + TsF1 +
TsF2 + TtF1 + TtF2)
= {Vr × (2 × Tr + tp) + Vs × (2 × Ts−2 × tp) +
Vt × (2 × Tt + tp)} × fc / 2 (54)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Equation (55).

ΔVu = Vu−Vu *
= {Vr * tp + Vs * (-2 * tp) + Vt * tp} * fc / 2
= (Vrs + Vts) / 2 × tp × fc (55)

In other words, when the polarity of the load current is reversed, the polarity of the output voltage error is also reversed. This output voltage error is also the same as the output voltage error obtained in the second embodiment.
Such calculation of the output voltage error can be similarly performed for the other phases of the load 3. Moreover, even when the polarities of the voltages Vr, Vs, and Vt of the AC power supply 2 are different, or when the combination of the line voltages of the AC power supply 2 that is selectively connected to the load 3 is different in the control cycle, the same operation can be performed. .
Therefore, the output voltage command correction values Vu2 *, Vv2 *, Vw2 * obtained by correcting the output voltage command values Vu1 *, Vv1 *, Vw1 * output by the voltage command means 5 with the output voltage errors ΔVu, ΔVv, ΔVw are: The output voltage command correction value obtained by the equations (56) to (58) and obtained in the second embodiment is the same as that of the second embodiment, and the configuration of the output voltage error correction means 8 in the third embodiment is also the same as that of the third embodiment. 2 may be the same.

Vu2 * = Vu1 * + (average value of two line voltages connected to a DC circuit)
× tp × fc × sgn (Iu) (56)
Vv2 * = Vv1 * + (average value of two line voltages connected to a DC circuit)
* Tp * fc * sgn (Iv) (57)
Vw2 * = Vw1 * + (average value of two line voltages connected to a DC circuit)
* Tp * fc * sgn (Iw) (58)

  In the above calculation, the output voltage error is calculated as an average error of two consecutive control cycles. However, such a calculation is performed every two control cycles even if every calculation cycle is performed. However, there is no problem even if the calculation interval is not set.

  In such a multi-relative multi-phase power converter, each phase of the AC power supply 2 and the terminals 34P and 34N of the DC circuit 33 are directly connected to each other via the switches 35PR to 35NT, and the terminal 34P of the DC circuit 33 is connected. , 35N and the load 3 have main circuits 4C that are connected to each other via half-bridge circuits 36UW to 36WB, respectively, the average value of the two line voltages and the short-circuit prevention time tp By correcting the output voltage command value using the product of the control frequency fc as the output voltage error, the output voltage error can be accurately corrected without increasing the amount of calculation.

Embodiment 4 FIG.
Unlike the modulation method employed in the multi-relative multi-phase power converter 1 according to the first embodiment, the multi-relative multi-phase power converter according to the fourth embodiment of the present invention is an AC power source 2 in one control cycle. The other modulation method is employed in which one line voltage is connected to the load 3, and the others are the same. One line voltage may be the maximum, intermediate or minimum of the line voltages of the AC power supply 2.

FIG. 17 is a timing chart showing an example of a pulse pattern and a voltage behavior in a modulation method in which one line voltage of AC power supply 2 is connected to load 3 in one control cycle according to Embodiment 4 of the present invention. .
The triangular carrier wave generated in each control cycle is a right and left triangular wave, and on / off signals TUR, TUS, TUT indicating on / off of the switches 11UR, 11US, 11UT of FIG. 4 are generated from this triangular carrier wave and the voltage command value Vu *. The time-series voltage command VuT * generated in the U phase is obtained from these on / off signals. Assuming that the voltage of the AC power supply 2 is equal in the two consecutive control cycles, the voltage command value Vu * is obtained by the equation (59).

Vu * = (Vr × TrP + Vs × TsM + Vr × TrS) /
(TrP + TsM + TrS)
= (Vr * TrP + Vs * TsM + Vr * TrS) * fc (59)

FIG. 18A shows the behavior of the pulse pattern of the gate control signals TURF to TUTR and the time series voltage VuT when the load current is flowing from the AC power supply 2 to the load 3. The gate control signals TURF to TUTR are turned on or off so that the commutation operation according to the state of the load current shown in FIG. 4 or 5 is performed when the load current is commutated. Is a pulse pattern in which a delay time is given.
The times TrG1, TsG1, TrG2, TrG3, TsG2, and TrG4 for connecting the voltage of the AC power supply 2 to the U phase of the load 3 are respectively the voltages of the AC power supply 2 in the voltage behavior of the time series voltage command VuT *. The phase connection times TrP, TsM, TrS, the short-circuit prevention time tp, and the open-circuit prevention time to are obtained by the equations (60) to (65).

TrG1 = TrP + tp + to (60)
TsG1 = TsM-to (61)
TrG2 = TrS−tp (62)
TrG3 = TrS + tp + to (63)
TsG2 = TsM-to (64)
TrG4 = TrP-tp (65)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 18A is obtained by Expression (66).

Vu = {Vr × (TrG1 + TrG2 + TrG3 + TrG4) +
Vs × (TsG1 + TsG2)} /
(TrG1 + TsG1 + TrG2 + TrG3 + TsG2 + TrG4)
= {Vr * (TrP + to + TrS) + Vs * (TsM-to)} * fc
... (66)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Expression (67).

ΔVu = Vu−Vu *
= {Vr * to + Vs * (-to)} * fc
= Vrs × to × fc (67)

Since the line voltage Vrs is a line voltage of the AC power supply 2 connected to the load 3 as a virtual DC voltage, the product of the line voltage connected to the load 3, the open prevention time to, and the control frequency fc is the output voltage. The error is ΔVu.
FIG. 18B shows the behavior of the pulse pattern of the gate control signals TURF to TUTR and the time-series voltage VuT when the load current flows from the load 3 to the AC power supply 2. The times TrH1, TsH1, TrH2, TrH3, TsH2, and TrH4 for connecting the voltage of the AC power supply 2 to the U phase of the load 3 are respectively the voltages of the AC power supply 2 in the voltage behavior of the time series voltage command VuT *. The phase connection times TrP, TsM, TrS, the short-circuit prevention time tp, and the open-circuit prevention time to are obtained by the equations (68) to (73).

TrH1 = TrP + tp (68)
TsH1 = TsM + to (69)
TrH2 = TrS-tp-to (70)
TrH3 = TrS + tp (71)
TsH2 = TsM + to (72)
TrH4 = TrP-tp-to (73)

  Since the average voltage Vu is an average value of the time-series voltage VuT, the average voltage Vu in two consecutive control periods in FIG. 18B is obtained by Expression (74).

Vu = {Vr × (TrH1 + TrH2 + TrH3 + TrH4) +
Vs × (TsH1 + TsH2)} /
(TrH1 + TsH1 + TrH2 + TrH3 + TsH2 + TrH4)
= {Vr × (TrP−to + TrS) + Vs × (TsM + to)} × fc
... (74)

  Therefore, the voltage error ΔVu between the average voltage Vu and the voltage command value Vu * is expressed by Expression (75).

ΔVu = Vu−Vu *
= {Vs × to + Vr × (−to)} × fc
= −Vrs × to × fc (75)

In other words, when the polarity of the load current is reversed, the polarity of the output voltage error is also reversed.
Such calculation of the output voltage error can be similarly performed for the output voltage errors ΔVv and ΔVw regarding the other phases of the load 3. The same can be done even when the polarity of the voltages Vr, Vs and Vt of the AC power supply 2 is different, or when the line voltage of the AC power supply 2 connected to the load is different in the control cycle.
The output voltage command correction values Vu2 *, Vv2 *, Vw2 * obtained by correcting the output voltage command values Vu1 *, Vv1 *, Vw1 * output by the voltage command means 5 with the output voltage errors ΔVu, ΔVv, ΔVw are: It is calculated | required by Formula (76)-Formula (78).

Vu2 * = Vu1 * + (line voltage connected to load) × to × fc × sgn (Iu) (76)
Vv2 * = Vv1 * + (line voltage connected to load) × to × fc × sgn (Iv) (77)
Vw2 * = Vw1 * + (line voltage connected to load) × to × fc × sgn (Iw) (78)

In the above calculation, the output voltage error is calculated as an average error of two consecutive control cycles. However, such a calculation is performed every two control cycles even if every calculation cycle is performed. However, there is no problem even if the calculation interval is not set.
This formula is for the first embodiment when the line voltage of the AC power source connected to the load is single in one control cycle. At this time, the average value of the line voltage connected to the load is Since it is the line voltage itself, it is synonymous with the equation of the output voltage command correction value obtained in the first embodiment, and the configuration of the output voltage error correction means 8 may be the same as in the first embodiment. Further, in the case of the second embodiment or the third embodiment, the same output voltage command correction value can be obtained even when the line voltage of the AC power supply 2 connected to the load 3 is single in one control cycle. The configuration of the error correction means 8 may be the same as that of each embodiment.

  Even if such a multi-relative multi-phase power converter is controlled so that the two phases of the AC power supply 2 connected to the load 3 are fixed within the control cycle, the line voltage between the two phases is controlled. The output voltage error can be accurately corrected by correcting the output voltage command value using the product of the open prevention time and the control frequency as the output voltage error.

1 is a block diagram of a multi-relative multi-phase power conversion device according to Embodiment 1 of the present invention. FIG. 2 is a configuration diagram of a main circuit according to the first embodiment. FIG. 3 is a configuration diagram of a switch according to the first embodiment. It is a figure of the part connected to the U phase of the load of the 3 relative 3 phase power converter device of FIG. It is the timing chart which showed the commutation operation | movement according to the state of load current when load current is flowing into load from AC power supply. It is the timing chart which showed the commutation operation | movement according to the state of load current when load current is flowing into AC power supply from load. 5 is a timing chart showing a commutation operation according to the state of the AC power supply when the line voltage between the R phase and the S phase of the AC power supply of FIG. 4 is positive. 6 is a timing chart showing a commutation operation according to the state of the AC power supply when the line voltage between the R phase and the S phase of the AC power supply of FIG. 4 is negative. FIG. 3 is a configuration diagram of output voltage error correction means according to the first embodiment. Example of pulse pattern and voltage behavior when performing commutation operation according to the state of load current at the time of commutation of load current in modulation system that supplies power to load by modulating pulse width of virtual DC voltage It is the timing chart which showed. It shows the behavior of the pulse pattern of the gate control signal and the time-series voltage when performing a commutation operation according to the state of the load current. It is a block diagram of the output voltage error correction | amendment means concerning Embodiment 2 of this invention. The behavior of the pulse pattern of the gate control signal and the time-series voltage when performing the commutation operation according to the state of the load current in the second embodiment is shown. It is a block diagram of the main circuit concerning Embodiment 3 of this invention. A pulse pattern for performing a commutation operation according to the state of the load current when the load current is commutated in the modulation method in which the virtual DC voltage is pulse-width modulated and the power is supplied to the load with respect to the third embodiment. It shows the behavior of turn and time series voltage. The behavior of the pulse pattern of the gate control signal and the time-series voltage when performing the commutation operation according to the state of the load current in the third embodiment is shown. It is a timing chart which showed the commutation operation when the line voltage between RS of AC power supply is negative when performing commutation operation according to the state of AC power supply about Embodiment 4 of this invention. The behavior of the pulse pattern of the gate control signal and the time series voltage when performing the commutation operation according to the state of the load current in the fourth embodiment is shown.

Explanation of symbols

  1 multi-relative multi-phase power converter, 2 AC power supply, 3 load, 4 4C main circuit, 5 voltage command means, 6 voltage detector, 7 current detector, 8 output voltage error correction means, 9 gate control means, 11UR -11WT switch, 12URF-12UTR semiconductor switch element group, 13a, 13b intermediate connection point, 21 line voltage extractor, 22 average value calculator, 2323B multiplier, 24 current polarity parameter calculator, 25 multiplier, 26 voltage correction , 31 polarity inverter, 33 DC circuit, 34P, 34N terminal, 35PR-35NT switch, 36UB-36WB half bridge circuit, 37UP, 37UN IGBT.

Claims (4)

A main circuit comprising a plurality of switches connected between an AC power source and a load and selectively controlled to directly convert AC power of the AC power source into predetermined AC power, and a predetermined output voltage command Gate control means for generating an on / off signal for turning on and off the switch based on the value and the carrier of the control frequency, and providing a dead time so that the load end is not opened or the power supply is not short-circuited when the load current is commutated. In the multi-relative multi-phase power converter,
An output voltage error correcting means for correcting the output voltage command value by an output voltage error over two consecutive control periods obtained based on the polarity of the load current ;
The output voltage error correction means is configured such that when one pair of two phases or two pairs of two phases of the multiple phases of the AC power supply are connected to the load in one control cycle, the pair of two-phase line voltages Alternatively, the output voltage error is obtained by multiplying a product of an average value of the two pairs of two-phase line voltages, the dead time, and the control frequency by a parameter indicating the polarity of the load current. A multi-relative multi-phase power converter. When the output voltage error correction means performs the load current commutation operation according to the state of the load current, the dead time time is set as an opening prevention time provided so that the load end is not opened. The multi-relative multi-phase power converter according to claim 1 . When the output voltage error correction means performs the commutation operation of the load current according to the state of the AC power supply, the dead time time is set as a short-circuit prevention time provided so that a power supply short-circuit does not occur. The multi-relative multi-phase power converter according to claim 1 , wherein A plurality of switches connected between an AC power source and a DC circuit and selectively controlled to convert AC power of the AC power source into DC power, and connected between the DC circuit and a load. Based on a main circuit consisting of a half-bridge circuit that is controlled to convert power to predetermined AC power, a predetermined output voltage command value and a carrier with a control frequency, and short-circuiting the power supply during load current commutation In a multi-relative multi-phase power converter comprising: a gate control unit that generates an on / off signal for controlling the half-bridge circuit by providing a dead time time so as not to occur
When the same pair of two phases or the same two pairs of two phases of the multiple phases of the AC power supply are connected to the DC circuit in two consecutive control cycles, the pair of two-phase line voltages or the two The output voltage command value is determined by the output voltage error obtained by multiplying the product of the average value of the line voltage of the pair of two phases, the dead time and the control frequency by the parameter indicating the polarity of the load current. An output voltage error correcting means for correcting the multi-relative multi-phase power converter.

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