JP2001136750A - Pwm pulse generating circuit of three-level npc inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high quality PWM pulse generator of a three-level NPC inverter by adding a simplified circuit to the PWM pulse generating circuit of two-level. SOLUTION: In this PWM pulse generating circuit of three-level NPC inverter for connecting in series four switching element per phase, providing two rectifying elements for clamping to the neutral point and generating the PWM pulse signal of four switches from a command voltage, a comparator 4 for generating a PWM pulse phase, a first switch 7 for distributing the PWM pulse signal to the four switch elements and a control signal (3) for controlling such distribution are provided. Thereby, when the modulation rate of the command voltage 1 is small, the control signal and command voltage are switched for each period of carrier and the pulse for outputting a positive bus voltage to a phase voltage output terminal, and the pulse for outputting a negative bus voltage are switched and outputted for each period of carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device such as a three-level NPC inverter for performing variable speed driving of a motor and system linkage.

[0002]

2. Description of the Related Art The main circuit of a conventional three-level NPC (neutral potential clamp system) inverter has a configuration as shown in FIG. In FIG. 10, reference numerals 102 and 103 denote voltage dividing capacitors for dividing the DC power supply 101 into E / 2 to generate three voltage levels of a positive voltage, a neutral point voltage (zero potential), and a negative voltage. Is the capacitor 1
Rectifier element for deriving neutral point voltage
Reference numerals 0 to 133 denote four series-connected switching elements such as IGBTs that constitute a switching arm for one U-phase provided with reflux diodes 106 to 109, respectively. A similar configuration is V
And a W-phase switching arm, and the PWM pulse is supplied to the U-phase, V-phase, and W-phase switching elements 130, respectively.
ON / OFF drive is performed. The PWM pulse applied to the three-level NPC inverter is generally created by comparing the command voltage with the triangular wave carrier. The method of generating the output voltage is as follows. There are a unipolar modulation method for inverting the period, a double carrier unipolar method using two triangular wave carriers as shown in FIG. 8, and a bipolar modulation method using two wave command voltages as shown in FIG. In each of FIGS. 7 to 9, (a) is a waveform diagram of a triangular wave carrier to be compared with a command voltage, (b) is a waveform diagram of a phase voltage, and (c) is a three-phase output inverter. Voltage waveforms are shown. The unipolar modulation of FIG.
As shown in (a), one command voltage is compared with one triangular wave carrier, and the switching element is turned on while the command voltage exceeds the triangular wave carrier. As a result, a waveform diagram of the phase voltage in the case of the three-phase output inverter as shown in (b) and a waveform of the line voltage as shown in (c) are obtained. According to this, even in a portion where the line output voltage is high as in the line voltage waveform (c), switching is performed to zero voltage, and the quality of the line output voltage is poor. In the double carrier unipolar modulation shown in FIG. 8, one command voltage is compared with two triangular wave carriers having different levels as shown in FIG. 8A, and the switching element is turned on while the command voltage exceeds the triangular wave carrier. is there. by this,
A waveform diagram of the phase voltage in the case of the three-phase output inverter as shown in (b) and a waveform of the line voltage as shown in (c) are obtained. The double carrier unipolar modulation shown in FIG. 8 does not switch to zero voltage in a portion where the line output voltage is high as compared with the unipolar modulation shown in FIG. 7, thus improving the quality of the line output voltage. However, there is a disadvantage in that the circuit for generating the PWM pulse requires two triangular wave carriers having different levels and the circuit becomes complicated. In the bipolar modulation shown in FIG. 9, two command voltages are compared with one triangular wave carrier as shown in FIG. 9A, and each switching element is turned on while each command voltage exceeds the triangular wave carrier. As a result, a waveform diagram of the phase voltage in the case of the three-phase output inverter as shown in (b) and a waveform of the line voltage as shown in (c) are obtained. The bipolar modulation of FIG. 9 does not switch to a high voltage in a portion where the line output voltage is high as compared with the unipolar modulation of FIG. 7, thus improving the quality of the line output voltage at a low modulation rate. . However, as shown in the figure, two command voltages are required, which is also P
The circuit for generating the WM pulse has become complicated.

[0003]

As described above, in each of the prior arts described above, in the PWM pulse generating method of the three-level NPC inverter, the unipolar modulation is performed by the line output voltage as shown in the line voltage waveform of FIG. Is switched to zero voltage even in the high part, and the quality of the line-to-line output voltage is poor. On the other hand, the double-carrier unipolar modulation does not switch to zero voltage in a portion where the line output voltage is high as compared with the unipolar modulation as shown in FIG. 8, and the quality of the line output voltage is good. The circuit becomes complicated because two triangular wave carriers of different levels are required. Further, as shown in FIG. 9, the bipolar modulation requires two command voltages, which also complicates the PWM pulse generation circuit. As described above, the unipolar modulation has a poor quality of the line output voltage, and the double carrier modulation and the double carrier modulation have a problem that the circuit scale is large. Therefore, an object of the present invention is to provide a PWM pulse generating circuit of a three-level NPC inverter that can provide a high-quality inverter output voltage with a low-cost and simplified circuit configuration.

[0004]

In order to achieve the above-mentioned object, the present invention has four switch elements connected in series per phase, has two rectifying elements for clamping to a neutral point, and has two rectifying elements. In a PWM pulse generation circuit of a three-level NPC inverter for generating PWM pulse signals of the four switches, a comparator for generating one PWM pulse per phase and a first distributing a PWM pulse signal to the four switch elements And a control signal for controlling the distribution thereof, and when the modulation rate of the command voltage is small, the control signal and the command voltage are switched every carrier cycle, and the positive bus voltage is applied to the phase voltage output terminal. It is characterized in that a pulse to be output and a pulse to output a negative bus voltage can be switched and output every carrier cycle. The PWM pulse generating circuit of a three-level NPC inverter according to claim 1, wherein an inverter for inverting a PWM pulse, a second switch for switching whether to pass the PWM pulse through the inverter or not. A signal generator for generating a switching signal of the second switching device;
When the modulation rate of the command voltage is large, the PWM pulse is generated by passing the PWM pulse through the inverter and generating the PWM pulse of the four switch elements. According to this configuration, a simple switch circuit is added to a two-level PWM pulse generating circuit to generate a PWM pulse of a three-level NPC inverter. When the modulation rate is small, the control signal and the command voltage are converted. Switching is performed at each carrier cycle, and the positive bus voltage and the negative bus voltage of the phase voltage output can be switched and output at each carrier cycle.On the other hand, when the modulation rate is high, an inverter is provided and the switch switching signal is output. When switching is not performed every carrier cycle, the PWM pulse is passed through an inverter to switch to double carrier unipolar modulation, whereby a high-quality PWM pulse generating circuit of a three-level NPC inverter can be configured with a simple circuit configuration. .

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PWM pulse generation circuit of a three-level NPC inverter according to a first embodiment of the present invention. FIG. 2 shows the P shown in FIG.
FIG. 9 is a waveform chart when the modulation rate of the WM pulse generation circuit is smaller than a reference value 1. FIG. 3 is a waveform diagram when the modulation factor of the PWM generation circuit shown in FIG. 1 is larger than the reference value 1. The reference value 1 is usually set to 0.5 as a PWM pulse switching point, but may be changed according to the situation. In FIG. 1, 1 is a voltage command including information such as an output voltage and an output frequency, and 2 is a switch controller that outputs a switch switching signal (3). Reference numeral 3 denotes a triangular-wave carrier generator, which compares the generated carrier with a command voltage 1 by a comparator 4 to generate a two-level PWM pulse. 5,6
Is a resistor, and 7 is a first switch for switching a PWM pulse in response to a switch switching signal (3) from the switch controller 2. 8 and 9 are inverters (inverters for inversion),
S1 to S4 are three-level NPs as shown in FIG.
I constituting the switching arm of each phase of the C inverter
Represents a drive signal of a PWM pulse applied to the GBT,
S1 is a drive signal applied to the element 130 connected to the positive bus, S2 is a drive signal applied to the element 131, taking the U phase (or V phase, W phase) of FIG. 10 as an example. S
3 is a drive signal applied to the lower arm element 132, S4
Is a drive signal applied to the element 133. As described above, the circuit in FIG. 1 has a configuration in which the switch 7 and the switch controller 2 are added to the circuit for one phase (circuit surrounded by a dotted line) of a general two-level PWM pulse generator.

Next, the operation will be described. First, FIG.
When the modulation ratio of the voltage command is smaller than the reference value 1 by using the circuit shown in FIG. 2, a switch switching signal (3) for command voltages S1 and S2 is given as shown in FIG. When the switch switching signal (3) is H, the switch 7 is connected to the A side, and when L is L, the switch 7 is connected to the B side. The two-level (type composed of two switch elements) PWM pulse generator of FIG. 1 is used to generate a voltage command 1 for the pulse-like upper voltage command S1 and the lower voltage command S2 shown in FIG. 3 to generate a PWM pulse. The switch switching signal (3) is a voltage command S1, S2
And the upper voltage command S1 is switched by the switch A
Since the lower voltage command S2 corresponds to the switch B, as shown in FIG. 2, the driving signal S1 is a passing pulse when the switch 7 is A, and the driving signal S2 is a passing pulse when the switch 7 is B. Is output as a negative pulse through the inverter 9. The drive signal S3 is output as a negative pulse obtained by inverting the polarity of the signal of S1 when the switch 7 is set to A through the inverter 8. As the drive signal S4, the pulse when the switch 7 is at B is output as it is. In this manner, the signals of the lower arm S3 and S4 for the lower arm of the three-level NPC inverter are generated using the switch 7 and the inverter in a complementary manner, so that the positive bus voltage P, Three levels of the neutral point voltage C and the negative bus voltage N can be output. As described above, the command voltage is changed in synchronization with the switch switching signal, the command voltage is also switched for each carrier, and the pulse width is adjusted so that the average value of the phase output voltage becomes a desired voltage during low modulation. With the simple circuit configuration as shown in FIG. 1, the phase output pulse can output a pulse in which three levels of the positive bus voltage P, the neutral point voltage C, and the negative bus voltage N are alternately output. Further, by adjusting the time for outputting the positive bus voltage and the time for outputting the negative bus voltage by the command voltage, the average value of the phase voltage output can be finely controlled. As described above, according to the embodiment of the present invention, it is possible to generate a PWM pulse for a three-level NPC inverter equivalent to that of the bipolar system simply by adding a simple switch circuit to a circuit for generating a two-level PWM pulse. . In contrast to the conventional bipolar modulation shown in FIG. 9, the phase output voltage outputs three positive bus voltage, neutral point voltage, and negative bus voltage during one cycle of the triangular wave carrier. Since the output pulse of the embodiment of the present invention outputs a positive bus voltage, a neutral point voltage, and a negative bus voltage during two cycles of the triangular wave carrier, the bipolar modulation shown in FIG. There is also an advantage that the number of times of switching per cycle is smaller than that of the first embodiment, and the switching loss is reduced.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram of a PWM pulse generating circuit of a three-level NPC inverter according to a second embodiment of the present invention. FIG. 5 is a waveform diagram of the PWM pulse generation circuit shown in FIG. FIG. 6 is an explanatory diagram of the operation of the PWM pulse generation circuit shown in FIG. In FIG. 4, 10
Is a PWM pulse inverter, 11 is a carrier synchronous clock inverter, and 12 is a switch for the inverter 10 which is a second switch. 13 is a delay unit for the switch switching signal (3),
14 is a DFF circuit, 15 is an inverted XOR circuit, 16 is O
This is an R circuit. The configuration added in the second embodiment to FIG. 1 has been described above, and is the portion within the dotted line. The same components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.
Next, the operation will be described. In the circuit of FIG. 1 of the previous embodiment, for example, when the modulation ratio of the voltage command is increased as shown in FIG. 3, the output pulses (S1 to S1) as shown in FIG.
In step S4), the carrier cycle and the switch switching signal become asynchronous, which is equivalent to the unipolar modulation shown in FIG. 7, and the quality of the line voltage deteriorates. The second embodiment improves this. S in FIG.
1 to S4 correspond to the drive signals of the respective switch elements of the respective phase switch arms of the three-level NPC inverter as in FIG. The drive signals S1 to S4 are converted from the two-level signals S1 and S2 by switches and inverters to S3 and S4.
4 is the same as that of the first embodiment, and furthermore, in the second embodiment, a synchronous / asynchronous determination circuit for the triangular wave carrier and the switch switching signal, and an asynchronous circuit In this case, an inverter 10 for inverting the drive signals S2 and S4 is provided. The signal generator that detects the synchronous / asynchronous state of the triangular wave carrier and the switch switching signal and outputs the switching signal of the switch 12 has a configuration shown by a dotted line in FIG. 4 and is synchronized with the triangular wave carrier as shown in FIG. A synchronous clock A is generated, a switch switching signal B from the switch controller 2 is passed through a delay unit 13, and a slightly delayed switch switching signal C signal and a triangular carrier cycle clock A are inverted and delayed by an inverter 11. Clock to DFF circuit 1
In addition to 4, the switch switching signal D delayed by one carrier is output. The D signal and the switch signal B are added to the XOR gate circuit 15 to obtain a gate output signal E, which is then inverted.
An asynchronous section is detected from the output signal F obtained by adding the signal E and the switch switching signal B to the gate circuit 16, and a switching signal of the switch 12 is obtained. The output signal F of this signal generator is
The switch range includes a synchronous range in which the switch switching signal B changes alternately every clock and an asynchronous range in which the switch switch signal B does not change every clock.
And the drive signals S1 to S4 operate as shown in FIG. On the other hand, in the case of the asynchronous range, the control unit
To the H side to switch to the voltage command shown in FIG. 6 (change the lower voltage command). The PWM pulse is inverted through inverter 10, which results in S2 being inverted by inverter 10 and inverter 9
, The inversion process is not performed and only S4 is performed. That is, the processing of FIG. 4 means that the single-carrier unipolar modulation in FIGS. 1 and 3 is switched to the double-carrier unipolar modulation that does not require the inversion of S2 of FIG. In this period, synchronization is ensured, and the waveform between lines is improved. As described above, according to the second embodiment, the synchronous state in which the switch switching signal alternately changes every cycle of the clock synchronized with the triangular carrier, and the asynchronous state in which the carrier and the switch switch signal do not alternately change. Detects and generates a drive signal of a three-level NPC inverter by inversion / complementation by a two-level single unipolar system at the time of synchronization, and changes a voltage command at the time of asynchronous to switch to a two-carrier unipolar system in which S2 is not inverted as a result. By simply adding a simple switching circuit to the two-level PWM pulse generation circuit, a high-quality PWM pulse of a three-level NPC inverter can be generated regardless of whether the modulation ratio of the voltage command is low or high.

[0008]

As described above, according to the present invention,
Four switch elements are connected in series per phase, and two rectifying elements are provided for clamping to a neutral point, and a PWM pulse signal of the four switches is generated from a command voltage.
In a PWM pulse generating circuit of a three-level NPC inverter, a comparator for generating one PWM pulse per phase, a first switch for distributing a PWM pulse signal to the four switch elements, and control for controlling the distribution When the modulation ratio of the command voltage is small, the control signal and the command voltage are switched every carrier cycle, and the pulse for outputting the positive bus voltage and the pulse for outputting the negative bus voltage to the phase voltage output terminal are provided. Since the output can be switched every cycle, a simple circuit can be added to the two-level PWM pulse generator to generate a three-level NPC inverter PWM pulse of the same quality as that of the bipolar modulation. Also, the PW of the three-level NPC inverter
In the M pulse generation circuit, an inverter for inverting the PWM pulse, a second switch for switching whether the PWM pulse is passed or not, and a signal generator for generating a switching signal of the second switch are provided. When the modulation rate of the command voltage is large, the PWM pulse is passed through the inverter to generate the PWM pulses of the four switch elements. Therefore, when the modulation rate of the voltage command is high, the double carrier unipolar is used. A PWM pulse of a three-level NPC inverter of the same quality as the modulation can be generated, and a low-cost and high-quality three-level N can be generated with a simple circuit even when the voltage command is low or high.
A PWM pulse for the PC inverter can be generated.

[Brief description of the drawings]

FIG. 1 shows a three-level NP according to a first embodiment of the present invention.
It is a block diagram of a PWM pulse generation circuit of a C inverter.

FIG. 2 is a waveform diagram of the PWM pulse generation circuit shown in FIG.

FIG. 3 is a waveform chart when the modulation rate of the PWM pulse generation circuit shown in FIG. 1 is large.

FIG. 4 shows a three-level NP according to a second embodiment of the present invention.
It is a block diagram of a PWM pulse generation circuit of a C inverter.

FIG. 5 is a waveform diagram of the PWM pulse generation circuit shown in FIG.

6 is an operation explanatory diagram of the PWM pulse generation circuit shown in FIG.

FIG. 7 is a waveform diagram of a conventional unipolar modulation.

FIG. 8 is a waveform diagram of conventional double carrier unipolar modulation.

FIG. 9 is a waveform diagram of a conventional bipolar modulation.

FIG. 10 is a main circuit diagram of a conventional three-level NPC inverter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage command 2 Switch controller 3 Carrier generator 4 Comparator 5, 6 Resistance 7, 12 Switch 8-11 Inverter 13 Delayer 14 DFF 15 XOR circuit 16 OR circuit

Claims (2)

[Claims] 1. A three-level NPC inverter having four switch elements connected in series per phase, two rectifier elements for clamping to a neutral point, and generating a PWM pulse signal of the four switches from a command voltage. A PWM pulse generating circuit comprising: a comparator for generating one PWM pulse per phase; a first switch for distributing a PWM pulse signal to the four switch elements; and a control signal for controlling the distribution. When the modulation rate of the command voltage is small, the control signal and the command voltage are switched every carrier cycle, and a pulse for outputting a positive bus voltage and a pulse for outputting a negative bus voltage to a phase voltage output terminal are output from the carrier. 3-level NPC characterized by being able to switch and output every cycle
Inverter PWM pulse generation circuit. 2. The PWM pulse generating circuit for a three-level NPC inverter according to claim 1, wherein an inverter for inverting a PWM pulse, and a second switch for switching whether to pass the PWM pulse through the inverter. And a signal generator for generating a switching signal of the second switching device.
A PWM pulse generating circuit for a three-level NPC inverter, wherein a PWM pulse of the four switch elements is generated by passing a WM pulse through the inverter.