JP2005295661A - Driving circuit for power semiconductor element and power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a driving circuit for a power semiconductor for that can easily correct the slippage of switching timing even in the case that a plurality of power semiconductor elements are connected in parallel. <P>SOLUTION: The driving circuit for a power semiconductor element for power is composed of a power semiconductor element 26, a current detecting means 28 which detects a current flowing in the power semiconductor element, a drive command generating means 20 which outputs a drive command to a gate terminal, a current detection period setting means 29 which outputs a current detection period setting signal based on an output signal from the drive command generating means 20, timing connection necessity determination means 2 and 4 each of which determines the necessity of the correction of the timing of turn-off or turn-on operation based on a plurality of output signals taken from the current detecting means 28 at different timings by the current detection period setting signals, latching means 10 and 17 which retain the output of the timing correction necessity determination means 2 and 4, delay time deciding means 11 and 18 each of which decides the amount of the correction of the timing of turn-off or turn-on operation based on the retention signal, and delay time generating means 12 and 19 which output signals generated based upon the delay time selected by the delay time deciding means 11 and 18 to the gate terminal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power semiconductor element drive circuit and a power conversion device, and more particularly to a power semiconductor element drive circuit and a power conversion device for correcting a shift in switching timing between a plurality of power semiconductor elements connected in parallel. Is.

  When configuring a large-capacity power conversion device by connecting power semiconductor elements in parallel, they are connected in parallel due to differences in the characteristics of the power semiconductor elements or the electronic components used in the drive circuit of the power semiconductor elements. There may be a difference in the timing of the switching operation between the power semiconductor elements.

  In the conventional power conversion device, as shown in page 7, lines 4 to 39 of Patent Document 1, the power self-extinguishing semiconductor element is in parallel in both the turn-on operation and the turn-off operation. Compared with the state of the collector current of other connected power semiconductor elements, the switching timing shift is corrected by adjusting and controlling each power semiconductor element based on the result.

  Further, as shown in page 3, lines 20 to 70 of Patent Document 2, the current detection value detected in the vicinity of the turn-off command signal input time point and the current maximum value detected during the period when the turn-off command signal is input. Is greater than the reference value Se of the comparator, a set-reset flip-flop (SRFF) outputs a Hi signal, and a driving method is used that shortens the time until this signal is received and turned off by the variable delay circuit. It was.

JP-A-11-262243 JP 2002-369498 A

  In the power semiconductor element drive circuit disclosed in Patent Document 1, the collector current between a plurality of power semiconductor elements connected in parallel is directly compared, and a transient current is applied to the power semiconductor element that has been delayed in switching operation. As the number of parallel connections is increased to 3 parallels and 4 parallels, the circuit configuration and the configuration of the power conversion device become more complicated and larger in order to correct the switching timing deviation using the concentration of was there.

  Further, in the power semiconductor element driving circuit disclosed in Patent Document 2, the difference between the current detection value detected in the vicinity of the turn-off command signal input time and the current maximum value detected during the period when the turn-off command signal is input. However, if the value is larger than the reference value Se of the comparator, the SRFF outputs a Hi signal, and if the SRFF outputs a Hi signal, the time until the variable delay circuit functions and turns off is shortened. When the timing of turn-off operation shifts between multiple power semiconductor elements connected in parallel, current is transiently concentrated on the power semiconductor elements that are turned off late, and the output signal of the subtractor is the set value of the comparator. The SRFF that has become larger than Se and receives the Hi signal output from the comparator outputs the Hi signal. Since the reset signal of the SRFF is given by the ON command of the command signal S, the timing shift at the n-th turn-off operation must be corrected at the same n-th turn-off operation. However, since the timing has already shifted when the comparator outputs the Hi signal, it is impossible to actually advance the timing of the turn-off operation when the SRFF functions. In addition, there is a problem that the timing shift cannot be corrected during the turn-on operation.

  The present invention has been made to solve the above-described problems. Driving a power semiconductor element capable of easily correcting a deviation in switching timing even when a plurality of power semiconductor elements are connected in parallel. An object of the present invention is to provide a power conversion device that is configured by connecting a plurality of power semiconductor elements driven by a drive circuit for such a power semiconductor element in parallel.

A power semiconductor element drive circuit according to the present invention is a power semiconductor element drive circuit comprising a gate terminal, an emitter terminal, and a collector terminal, and a current detection means for detecting a current flowing through the power semiconductor element; Drive command generation means for outputting a drive command to the gate terminal, current detection period setting means for outputting a current detection period setting signal based on an output signal from the drive command generation means, and the current detection period setting signal, respectively. Based on a plurality of output signals from the current detection means fetched at different timings, the timing correction necessity judgment means for judging whether or not to correct the timing of the turn-off or turn-on operation, and the output of the timing correction necessity judgment means are output. A latch means for holding, and a turn-off or turn-on based on a signal held by the latch means. Comprising a delay time determining means for determining a correction amount of the timing of turn-on operation, the delay time generating means for outputting the generated signal based on the delay time selected by the delay time determination means and to said gate terminal.
The power semiconductor element drive circuit according to the present invention is a power semiconductor element drive circuit comprising a gate terminal, an emitter terminal, and a collector terminal, and outputs a drive command to the gate terminal. And a gate voltage detection period setting means for outputting a gate voltage detection period setting signal based on an output signal from the drive command generation means, and from the gate terminal fetched at different timings by the gate voltage detection period setting signal. Timing correction necessity determination means for determining whether or not to correct the timing of turn-off or turn-on operation based on a plurality of gate voltages, latch means for holding the output of the timing correction necessity determination means, and held by the latch means Correction of turn-off or turn-on operation timing based on the received signal And a delay time determining means for determining a.

  Since the drive circuit for the power semiconductor element according to the present invention has the above-described configuration, even when a plurality of power semiconductor elements are connected in parallel, the operation state of other power semiconductor elements is not referred to. In addition, it is possible to easily correct the deviation of the switching timing for each drive circuit of the power semiconductor element and keep the state where the amount of timing deviation is small. Further, the drive circuit for the power semiconductor element can be reduced in size.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a main part of a drive circuit for a power semiconductor device according to the first embodiment. A power semiconductor element (hereinafter, an IGBT (Insulated Gate Bipolar Transistor) will be described as an example) 26 is connected to a free wheel diode 27 in antiparallel, and a gate resistor 25 is connected to the gate terminal. A current sensor (current detection means) 28 for detecting a current flowing through the circuit 26 is provided. The power semiconductor element 26 is driven by an output from a drive command generation circuit (drive command generation means) 20 via a delay circuit 44 for generating the delay time ta, the drive pulse shaping circuit 1, and the gate amplifier 45.

  The first timing correction necessity determination circuit (timing correction necessity determination means) 2 includes two current detection signal holding circuits (current detection signal holding means) 6a and 6b, a differential amplifier 7, and three comparators 8a and 8b. , 8c, and reference voltages 9a, 9b, 9c of the three comparators, respectively. The current detection signal holding circuit 6a receives the signal S1a from the current detection period setting circuit (current detection period setting means) 29 and takes in the signal from the current sensor 28 in a certain period in the vicinity of the turn-off command time, and drives the drive command generation circuit 20 The signal is held until the reset signal R1 from the current detection period setting circuit 29 output in synchronization with the ON command is input. Further, the current detection signal holding circuit 6b receives the signal S1b from the current detection period setting circuit 29, takes in the signal from the current sensor 28 in a certain period longer than S1a from the same timing as S1a, and turns on the drive command generation circuit 20 The signal is held until the reset signal R1 from the current detection period setting circuit 29 output in synchronization with the command is input. In addition, as a signal taken in, the current peak value within the said fixed period is mentioned, for example.

  The voltage signals held in the current detection signal holding circuits 6 a and 6 b are input to the differential amplifier (difference calculating means) 7. The differential amplifier 7 has Vout1 = G1 (V6b−V6a) where the voltage signals held in the current detection signal holding circuits 6a and 6b are V6a and V6b, respectively, and the gain of the differential amplifier 7 is G1 (> 0). Is output. The output signal Vout1 of the differential amplifier 7 is input to the non-inverting input terminals of the three comparators (comparing means) 8a, 8b, 8c. Further, reference voltages 9a, 9b, 9c inputted to the inverting input terminals of the comparators 8a, 8b, 8c are set to V9a, V9b, V9c (V9a <V9b <V9c), respectively.

  When the drive circuit of other power semiconductor elements connected in parallel is turned off first, or there is no deviation of the off timing or the delay of the off timing is very small, Vout1 <V9a <V9b <V9c The devices 8a, 8b, 8c all output Lo signals. When the delay of the off timing becomes large to some extent and V9a <Vout1 <V9b <V9c, the comparator 8a outputs the Hi signal and both the comparators 8b and 8c output the Lo signal. When V9a <V9b <Vout1 <V9c, the comparators 8a and 8b output the Hi signal, and the comparator 8c outputs the Lo signal. When V9a <V9b <V9c <Vout1, the comparators 8a, 8b, and 8c all output Hi signals.

  The first timing deviation adjusting circuit (timing deviation adjusting means) 3 includes latch circuits (latch means) 10a, 10b, 10c, delay time determining circuit (delay time determining means) 11, delay circuits (delay time generating means) 12a, 12b. , 12c. The latch circuits 10a, 10b, and 10c latch the output signals of the comparators 8a, 8b, and 8c, respectively, and input them to the control terminals 11A, 11B, and 11C of the delay time determination circuit 11, respectively. The delay circuits 12a, 12b, and 12c are provided between the drive command generation circuit 20 and the selection terminals 11D0, 11D1, and 11D3 of the delay time determination circuit 11, respectively. The delay times are ta1, tb1, and tc1 (tc1 <tb1 <ta1 = ta). The drive command generation circuit 20 is directly connected to the selection terminal 11D7 of the delay time determination circuit 11. The delay time determination circuit 11 selects an appropriate circuit from the selection terminals 11D0, 11D1, 11D3, and 11D7 according to the signals of the control terminals 11A, 11B, and 11C, and outputs a signal from the output terminal 11Y.

  FIG. 2 shows the input / output relationship of the delay time determination circuit 11 in the drive circuit for the power semiconductor element according to the first embodiment. The output signal Vout1 of the differential amplifier 7 of the first timing correction necessity determination circuit 2 and the output signal of the delay time determination circuit 11 according to the magnitude relationship between the reference voltages V9a, V9b, V9c of the comparators 8a, 8b, 8c. 11Y is different. When Vout1 <V9a <V9b <V9c, the selection terminal 11D0 is selected. When V9a <Vout1 <V9b <V9c, the selection terminal 11D1 is selected. When V9a <V9b <Vout1 <V9c, the selection terminal 11D3 is selected. In the case of <Vout1, the selection terminal 11D7 is selected by the delay time determination circuit 11 and a signal is output from the output terminal 11Y.

  FIG. 3 shows a correction time chart regarding the off-timing deviation in the drive circuit for the power semiconductor element according to the first embodiment. Here, the operation logic at the time of the n-th and (n + 1) -th switching operations of the power semiconductor element drive circuit delayed in turn-off timing among the plurality of power semiconductor element drive circuits connected in parallel is shown. ing. At the n-th turn-off operation, the output signal Vout1 of the differential amplifier 7 and the reference voltages V9a, V9b, V9c of the comparators 8a, 8b, 8c become V9a <V9b <Vout1 <V9c, and the Hi signals are output from the comparators 8a and 8b. Is output, and the Lo signal is output from the comparator 8c. Both the control terminals 11A and 11B of the delay time determination circuit 11 are latched by the Hi signal, and the control terminal 11C of the delay time determination circuit 11 holds the state of the Lo signal. As a result, the delay time determination circuit 11 selects 11D3 and advances the (n + 1) th turn-off timing. When Vout1 <V9a <V9b <V9c at the (n + 1) th turn-off operation, the output signals of the comparators 8a, 8b, and 8c are all Lo, but the output signals of the comparators 8a and 8b are latch circuit 10a, Since the control terminals 11A and 11B of the delay time determination circuit 11 both maintain the Hi state, the delay time determination circuit 11 maintains the state in which 11D3 is selected.

  The second timing correction necessity determination circuit 4 includes two current detection signal holding circuits 13a, 13b, a differential amplifier 14, three comparators 15a, 15b, 15c, and reference voltages 16a, 16b, 16c for the three comparators, respectively. It is comprised by. The current detection signal holding circuit 13a receives the signal S2a from the current detection period setting circuit 29, takes in the signal from the current sensor 28 in a certain period after the turn-on command, and outputs it in synchronization with the off command of the drive command generation circuit 20 The signal is held until the reset signal R2 is input from the current detection period setting circuit. Further, the current detection signal holding circuit 13b receives the signal S2b from the current detection period setting circuit 29, takes in the signal from the current sensor 28 for a certain period longer than S2a from the same timing as S2a, and turns off the drive command generation circuit 20 The signal is held until the reset signal R2 from the current detection period setting circuit 29 output in synchronization with the command is input. In addition, as a signal taken in, the current peak value within the said fixed period is mentioned, for example.

  The voltage signals held in the current detection signal holding circuits 13 a and 13 b are input to the differential amplifier 14. When the voltage signals held in the current detection signal holding circuits 13a and 13b are V13a and V13b, respectively, and the gain of the differential amplifier is G2 (> 0), the differential amplifier 14 outputs Vout2 = G2 (V13b−V13a). Is done. The output signal Vout2 from the differential amplifier 14 is input to the non-inverting input terminals of the three comparators 15a, 15b, and 15c. The reference voltages 16a, 16b, and 16c input to the inverting input terminals of the comparators 15a, 15b, and 15c are set as V16a, V16b, and V16c (V16a <V16b <V16c), respectively.

  The comparator is turned on before the drive circuit of other power semiconductor elements connected in parallel, or there is no deviation of the on timing, or the delay of the on timing is very small and Vout2 <V16a <V16b <V16c. 15a, 15b, and 15c all output Lo signals. When the on-timing delay becomes large to some extent and V16a <Vout2 <V16b <V16c, the comparator 15a outputs the Hi signal and both the comparators 15b and 15c output the Lo signal. When V16a <V16b <Vout2 <V16c, the comparators 15a and 15b output the Hi signal and the comparator 15c outputs the Lo signal. When V16a <V16b <V16c <Vout2, the comparators 15a, 15b, and 15c all output a Hi signal.

  The second timing deviation adjusting circuit 5 is composed of latch circuits 17a, 17b and 17c, a delay time determining circuit 18, and delay circuits 19a, 19b and 19c. The latch circuits 17a, 17b, and 17c latch the output signals of the comparators 15a, 15b, and 15c, respectively, and input them to the control terminals 18A, 18B, and 18C of the delay time determination circuit 18, respectively. The delay circuits 19a, 19b, and 19c are respectively provided between the drive command generation circuit 20 and the selection terminals 18D0, 18D1, and 18D3 of the delay time determination circuit 18, and the respective delay times are ta2, tb2, and tc2 (tc2 <tb2 <ta2 = ta1). = Ta). The drive command generation circuit 20 is directly connected to the selection terminal 18D7 of the delay time determination circuit 18. The delay time determination circuit 18 selects an appropriate circuit from the selection terminals 18D0, 18D1, 18D3, and 18D7 according to the signals of the control terminals 18A, 18B, and 18C, and outputs a signal from the output terminal 18Y.

  FIG. 4 shows a correction time chart regarding the on-timing deviation in the drive circuit for the power semiconductor element according to the first embodiment. Here, the operation logic at the time of the n-th and (n + 1) -th switching operations of the power semiconductor element drive circuit delayed in turn-on timing among the plurality of power semiconductor element drive circuits connected in parallel is shown. ing. At the n-th turn-on operation, the output signal Vout2 of the differential amplifier 14 and the reference voltages V16a, V16b, and V16c are V16a <V16b <Vout2 <V16c, and the Hi signal is output from the comparators 15a and 15b. The 18 control terminals 18A and 18B are both latched by the Hi signal. As a result, the delay time determination circuit 18 selects 18D3 and advances the (n + 1) th turn-on timing. When Vout2 <V16a <V16b <V16c in the (n + 1) th turn-on operation, the output signals of the comparators 15a and 15b become Lo, but the output signals of the comparators 15a and 15b are connected to the latch circuits 17a and 17b, respectively. Therefore, both the control terminals 18A and 18B of the delay time determination circuit 18 maintain the Hi state, and the delay time determination circuit 18 maintains the state where 18D3 is selected.

  The drive pulse shaping circuit (drive pulse shaping means) 1 includes an AND circuit 21, an OR circuit 22, and EXOR circuits 23 and 24. The logic of the drive pulse shaping circuit 1 is shown in FIG. The AND circuit 21 performs an AND operation on the output signal 11Y of the delay time determination circuit 11 in the first timing deviation adjustment circuit 3 and the signal output from the drive command generation circuit 20 via the delay circuit 44, and the AND circuit 21 The output signal outputs a correction signal for the turn-off timing deviation. The EXOR circuit 23 performs an EXOR operation on the output signal of the AND circuit 21 and the output signal of the delay circuit 44, and outputs a signal obtained by extracting only the correction width of the turn-off timing. The OR circuit 22 performs an OR operation on the output signal 18Y of the delay time determination circuit 18 in the second timing shift adjustment circuit 5 and the signal output from the drive command generation circuit 20 via the delay circuit 44, and thereby counteracts the turn-on timing shift. Output a correction signal. Further, the EXOR circuit 24 performs an EXOR operation of the output signal of the EXOR 23 and the OR circuit 22 and outputs a signal in which both timing differences during the turn-on operation and the turn-off operation are corrected. The output signal of the EXOR circuit 24 is input to the gate terminal of the power semiconductor element 26 via the gate amplifier 45 and the gate resistor 25.

  According to the above-described configuration, the delay time determination circuits 11 and 18 control the control signal in accordance with the amount of timing deviation from the drive circuit of another power semiconductor element connected in parallel during the turn-on operation and the turn-off operation, respectively. In addition, since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Moreover, since this operation is performed for each drive circuit of each power semiconductor element without referring to any operation of the drive circuit for other power semiconductor elements, a plurality of power semiconductor elements are connected in parallel. Even in this case, the deviation of the switching timing can be easily corrected for each drive circuit of each power semiconductor element. In addition, since the wiring between the drive circuits of each power semiconductor element can be reduced as compared with the prior art, the drive circuit of the power semiconductor element itself and the power conversion device can be downsized.

  In the present embodiment, the case where the timing correction means for both the turn-off operation and the turn-on operation is provided is described as an example. However, when only one of the timing corrections is performed, the configuration described below And it is sufficient. When only the correction with respect to the turn-off timing is performed, the first timing correction necessity determination circuit 2 and the first timing deviation adjustment circuit 3 are used, and the drive pulse shaping circuit 1 may be configured only by the AND circuit 21. When only the correction for the turn-on timing is performed, the second timing correction necessity determination circuit 4 and the second timing deviation adjustment circuit 5 are used, and the drive pulse shaping circuit 1 may be configured only by the OR circuit 22. Incidentally, the configuration corresponding to only one of the timing corrections can be similarly applied to all the embodiments described below.

  Note that the outputs of the differential amplifiers 7 and 14 that are components of the first timing correction necessity determination circuit 2 and the second timing correction necessity determination circuit 4 are all connected to the non-inverting input terminals of three comparators. Although connected, the number of comparators is not limited to three, and may be one or two, or four or more. Such a configuration can be similarly applied to Embodiments 2 to 11 described below.

  Further, S1b and S2b start capturing signals from the current sensor 28 at the same timing as S1a and S2a, respectively. However, the signals from the current sensor 28 in a certain period after completion of signal capturing from S1a and S2a, respectively. May be taken in.

  The power unit 103a in which a plurality of power semiconductor elements driven by the power semiconductor element drive circuit described above are connected in parallel is used as one phase, and the power unit 103a and the power units 103b and 103c having the same internal configuration are used as a three-phase structure. FIG. 6 shows the inverter and the load motor 101. By using a power conversion device in which a plurality of power semiconductor elements driven by the power semiconductor element drive circuit are connected in parallel, current imbalance and loss unbalance between the power semiconductor elements connected in parallel can be improved. The power converter can be driven efficiently. In addition, the entire power conversion device can be reduced in size.

Example 1.
FIG. 7 shows a test result obtained by actually operating the drive circuit for the power semiconductor element according to the first embodiment. 2 shows a waveform of a current flowing through the power semiconductor element when a switching operation is performed by delaying one switching timing (only the turn-off timing) of the power semiconductor elements connected in parallel by 160 ns. The horizontal axis is 100 μs / div in time and the vertical axis is 200 A / div in current. In the first turn-off operation, the driving circuit of one power semiconductor element is delayed in switching timing. In the subsequent second turn-off operation, the timing deviation is corrected. Further, in the third turn-off operation, the state in which the deviation of the switching timing is corrected is maintained.

  Since the power semiconductor element drive circuit according to the first embodiment includes the latch circuits 10 and 17, once it is determined that timing correction is necessary, the correction amount can be maintained unless the power supply of the drive circuit itself is turned off. Is possible. Therefore, as described above, the state in which the deviation of the switching timing is corrected is maintained even in the third turn-off operation, and the state in which the amount of timing deviation is small can be maintained. FIG. 7 shows a test result of the correction with respect to the turn-off timing, but it is possible to similarly correct the deviation of the turn-on timing.

Embodiment 2. FIG.
The main part of the drive circuit for the power semiconductor device according to the second embodiment is shown in FIG. In the first embodiment, when the switching timing shift at the time of the turn-on operation is turned on later than the other power semiconductor element drive circuits connected in parallel, the timing is increased by advancing the next turn-on operation timing. A method for correcting the deviation was shown. However, a method may be used in which the timing deviation is corrected by delaying the next turn-on operation timing when it is first turned on compared to the drive circuits for other power semiconductor elements connected in parallel.

  Compared to the case of the first embodiment, the second timing correction necessity determination circuit 4, the second timing deviation adjustment circuit 5, the configuration of the drive pulse shaping circuit 1, and the signal S 2 b output from the current detection period setting circuit 29 The operation timing is different. The outputs of the comparators 15a, 15b, and 15c in the second timing correction necessity determination circuit 4 are respectively AND circuits (AND means) 43a, 43b, and 43c, and the latch circuit 17a in the second timing deviation adjustment circuit 5, 17b and 17c. The signal S2b from the current detection period setting circuit 29 is input to one input terminal of the AND circuits 43a, 43b, and 43c. The signal S2b outputs a Hi signal for a certain period after the signal capture from S2a is completed. The operation of the current detection period holding circuits 13a and 13b is the same as that of the first embodiment. When the voltage signal held in the current detection signal holding circuits 13a and 13b is V13a and V13b and the gain of the differential amplifier is G2 (> 0), the differential amplifier 14 has Vout2 = G2 (V13a−V13b). Shall be output. The reference voltage input to the inverting input terminals of the comparators 15a, 15b, and 15c is set as V16a <V16b <V16c as in the first embodiment. Since the AND circuits 43a, 43b, and 43c exist, the comparators 15a, 15b, and 15c output the latch circuits 17a, 17b, and 17c only during the S2b signal input period.

  When the output circuit is turned on later than the drive circuit of the other power semiconductor elements connected in parallel, or there is no deviation of the on timing, or the advance of the on timing is very small, VAND2 <V16a <V16b <V16c, the AND circuit 43a 43b and 43c all output Lo signals. When the on-timing progresses to some extent and V16a <Vout2 <V16b <V16c, the AND circuit 43a outputs the Hi signal, and the AND circuits 43b and 43c both output the Lo signal. When V16a <V16b <Vout2 <V16c, the AND circuits 43a and 43b output the Hi signal, and the AND circuit 43c outputs the Lo signal. When V16a <V16b <V16c <Vout2, the AND circuits 43a, 43b, and 43c all output Hi signals.

  The components of the second timing shift adjustment circuit 5 are the same as those in the first embodiment, but the delay times are ta2, tb2, tc2, and td2 (ta = ta1 = ta2 <tb2 <tc2 <td2), respectively. The delay circuits 19a, 19b2, 19c, and 19d shown are connected to the selection terminals 18D0, 18D1, 18D3, and 18D7 of the delay time determination circuit 18, respectively. An appropriate circuit is selected from the selection terminals 18D0, 18D1, 18D3, and 18D7 according to the signals of the control terminals 18A, 18B, and 18C of the delay time determination circuit 18, and a signal is output from the output terminal 18Y.

  The drive pulse shaping circuit 1 is composed of AND circuits 30, 31, and 32, and outputs a signal in which timing deviations during both the turn-on operation and the turn-off operation are corrected. The output signal of the AND circuit 32 is input to the gate terminal of the power semiconductor element 26 via the gate amplifier 45 and the gate resistor 25.

  FIG. 9 shows a correction time chart related to the on-timing deviation in the drive circuit for the power semiconductor element according to the second embodiment. Here, the operation logic at the time of the n-th and (n + 1) -th switching operations of the power semiconductor element drive circuit having a fast turn-on timing among a plurality of power semiconductor element drive circuits connected in parallel is shown. Yes. At the n-th turn-on operation, the output signal Vout2 of the differential amplifier 14 and the reference voltages 16a, 16b, and 16c of the comparator 15 become V16a <V16b <Vout2 <V16c, and the Hi signal is output from the comparators 15a and 15b. Both the control terminals 18A and 18B of the delay time determination circuit 18 are latched by the Hi signal. As a result, the delay time determination circuit 18 selects 18D3 and delays the (n + 1) th turn-on timing. In the (n + 1) -th turn-on operation, when Vout2 <V16a <V16b <V16c, the output signals of the comparators 15a and 15b become Lo, but the output signals of the comparators 15a and 15b are output from the AND circuits 43a, 43b and 43c. Are connected to the latch circuits 17a and 17b, respectively, so that the control terminals 18A and 18B of the delay time determining circuit 18 are both in the Hi signal state, that is, the delay time determining circuit 18 is kept in the state of selecting 18D3. The With such a configuration, the shift in the turn timing in the n-th switching operation can be corrected by delaying the (n + 1) th turn-on timing.

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. An optimum pulse width can be selected, and the latch circuits 10 and 17 are provided, so that it is possible to keep a state where the amount of timing deviation is small. In addition, since the wiring between the drive circuits of each power semiconductor element can be reduced as compared with the prior art, the drive circuit of the power semiconductor element itself and the power conversion device can be downsized.

Embodiment 3 FIG.
The main part of the drive circuit for the power semiconductor device according to the third embodiment is shown in FIG. The first timing shift adjustment circuit 3 and the second timing shift adjustment circuit 5 in FIG. 1 may be configured as shown in FIG. In other words, the first timing shift adjustment circuit 3 includes latch circuits 10a, 10b, and 10c, resistors 34, 35a, 35b, and 35c, and switches 33a, 33b, and 33c. The resistors 35a, 35b, and 35c are connected to the switches 33a, 33b, and 33c. The gate resistor 34 is connected in parallel via 33c. The switches 33a, 33b, and 33c are all controlled to be turned on when a Hi signal is input. Reference numerals 39 and 40 denote semiconductor switches for driving the power semiconductor element 26.

  Since such a drive circuit configuration is adopted, when Vout1 <V9a <V9b <V9c, the off-gate resistance is only the resistor 34, and when V9a <Vout1 <V9b <V9c, the switch 33a is turned on, and the off-gate resistance is the resistor 34. And a resistor 35a connected in parallel. Further, when V9a <V9b <Vout1 <V9c, the switches 33a and 33b are turned on, and the off-gate resistance is a combined resistance in which the resistor 34 and the resistors 35a and 35b are connected in parallel. When V9a <V9b <V9c <Vout1, The switches 33a, 33b, and 33c are turned on, and the off-gate resistance is a combined resistance in which the resistor 34 and the resistors 35a, 35b, and 35c are connected in parallel. Thus, the gate resistance can be reduced with respect to an increase in the turn-off timing shift width.

  FIG. 11 shows a correction time chart regarding the off-timing deviation in the drive circuit for the power semiconductor element according to the third embodiment. Here, the operation logic at the time of the n-th and (n + 1) -th switching operations of the power semiconductor element drive circuit delayed in turn-off timing among the plurality of power semiconductor element drive circuits connected in parallel is shown. ing. At the n-th turn-off operation, the output signal Vout1 of the differential amplifier 7 and the reference voltages V9a, V9b, V9c of the comparators 8a, 8b, 8c become V9a <V9b <Vout1 <V9c, and the Hi signals are output from the comparators 8a and 8b. Is output, the Lo signal is output from the comparator 8c, and the switches 33a and 33b are turned on. The off-gate resistance becomes a combined resistance of the resistor 34 and the resistors 35a and 35b, and the (n + 1) th turn-off speed is increased. In the (n + 1) -th turn-off operation, if Vout1 <V9a <V9b <V9c, the outputs of the comparators 8a, 8b, and 8c are all Lo signals, but the output signals of the comparators 8a and 8b are latch circuits 10a, Since the switches 33a and 33b are kept on because they are connected to 10b, the state where the turn-off speed is high is maintained.

  The second timing shift adjustment circuit 5 is composed of latch circuits 17a, 17b, 17c, resistors 37, 38a, 38b, 38c, and switches 36a, 36b, 36c. The resistors 38a, 38b, 38c are connected to the switches 36a, 36b, 36c. The gate resistor 37 is connected in parallel. The switches 36a, 36b, and 36c are controlled so that they are turned on when the output signals of the latch circuits 17a, 17b, and 17c are Hi signals. The operation is the same as that of the first timing deviation adjusting circuit 3, and the gate resistance is controlled to be reduced when the turn-on timing deviation width is increased.

  FIG. 12 shows a correction time chart regarding the on-timing deviation in the drive circuit for the power semiconductor element according to the third embodiment. Here, the operation logic at the time of the n-th and (n + 1) -th switching operations of the power semiconductor element drive circuit delayed in turn-on timing among the plurality of power semiconductor element drive circuits connected in parallel is shown. ing. At the n-th turn-on operation, the output signal Vout2 of the differential amplifier 14 and the reference voltages V16a, V16b, and V16c are V16a <V16b <Vout2 <V16c, and the Hi signal is output from the comparators 15a and 15b. Outputs a Lo signal, and switches 36a and 36b are turned on. The on-gate resistance becomes a combined resistance of the resistor 37 and the resistors 38a and 38b, and the (n + 1) th turn-on speed is increased. In the (n + 1) th turn-on operation, if Vout2 <V16a <V16b <V16c, the output signals of the comparators 15a and 15b become Lo, but the output signals of the comparators 15a and 15b are connected to the latch circuits 17a and 17b, respectively. Therefore, the fast turn-on speed is maintained.

  Note that S1b and S2b start capturing signals from the current sensor 28 at the same timing as S1a and S2a, respectively, but the signals from the current sensor 28 in a certain period after completion of signal capturing from S1a and S2a, respectively. May be taken in.

  According to the above-described configuration, the gate resistance can be selected according to the amount of timing deviation from the drive circuit of the other power semiconductor elements connected in parallel in each of the turn-on operation and the turn-off operation. Since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Furthermore, since the delay time determination circuits 11 and 18 and the drive pulse shaping circuit 1 in the first and second embodiments are not necessary, the circuit configuration can be made compact.

Embodiment 4 FIG.
The main part of the drive circuit for the power semiconductor device according to the fourth embodiment is shown in FIG. The second timing deviation adjusting circuit 5 in FIG. 10 may have a configuration as shown in FIG. Similarly to the second embodiment, when the on timing correction method is turned on first in comparison with the drive circuit of another power semiconductor element connected in parallel during the n-th turn-on operation, (n + 1) The shift of the on timing is corrected by delaying the turn-on operation of the second time. Compared with the drive circuit for the power semiconductor element shown in FIG. 10, the configurations of the second timing correction necessity determination circuit 4 and the second timing deviation adjustment circuit 5 are different. The configuration and operation of the second timing correction necessity determination circuit 4 are the same as those in the second embodiment. Regarding the second timing deviation adjusting circuit 5, the output signals of the latch circuits 17a, 17b, and 17c are connected to the switches 36a, 36b, and 36c through NOT circuits 41a, 41b, and 41c, respectively. With such a configuration, the on-gate resistance can be increased as the on-timing deviation increases, and the on-timing deviation can be corrected.

  FIG. 14 shows a correction time chart regarding off-timing deviation in the drive circuit for the power semiconductor element according to the fourth embodiment, and FIG. 15 shows a correction time chart concerning on-timing deviation.

  According to the above-described configuration, the gate resistance can be selected according to the amount of timing deviation from the drive circuit of the other power semiconductor elements connected in parallel in each of the turn-on operation and the turn-off operation. Since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Furthermore, since the delay time determination circuits 11 and 18 and the drive pulse shaping circuit 1 in the first and second embodiments are not necessary, the circuit configuration can be simplified.

Embodiment 5 FIG.
The main part of the drive circuit for the power semiconductor device according to the fifth embodiment is shown in FIG. The first timing correction necessity determination circuit 2 and the second timing correction necessity determination circuit 4 in FIG. 1 may be configured as shown in FIG. That is, the current detection signal holding circuits 6 and 13 and the differential amplifiers 7 and 14 are replaced with current change rate detection circuits (current change rate detection means) 42-1 and 42-2. Among the plurality of power semiconductor element drive circuits connected in parallel, in the power semiconductor element drive circuit whose turn-off timing is delayed, the current increases rapidly during the turn-off operation. The current change rate is detected by the current change rate detection means 42-1, and compared with the reference values 9a, 9b, 9c of the comparator 8. As for the shift in the turn-on timing, in the power semiconductor element drive circuit that is turned on late, the current change rate after the turn-on operation is higher than that in the case where there is no timing shift. The current change rate is detected by the current change rate detection means 42-2 and compared with the reference values 16a, 16b, and 16c of the comparator 15. The subsequent operation is the same as that of the driving circuit for the power semiconductor element according to the first embodiment. Based on the delay of the nth turn-off timing, the (n + 1) th turnoff timing is advanced, and based on the delay of the nth turn-on timing. (N + 1) turn-on timing is advanced.

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. The optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep the state where the timing deviation amount is small.

Embodiment 6 FIG.
The main part of the drive circuit for the power semiconductor element according to the sixth embodiment is shown in FIG. In the fifth embodiment, the current change rate detecting means is a differential operation means for the output signal of the current detecting means for detecting the current flowing through the power semiconductor element, but a method for directly detecting the current change rate as shown in FIG. May be used. Although the current flowing through the power semiconductor element changes with time, a magnetic field is generated when the current changes with time. Therefore, in the power semiconductor element drive circuit according to the sixth embodiment, magnetic field detection means 48 such as a search coil or a loop antenna is used as the current change rate detection means. The operation setting of the magnetic field detection period setting circuit (magnetic field detection period setting means) 49 for setting the period for detecting the magnetic field is the same as that of the current detection period setting circuit 29 described above. This is the same as described in the first embodiment.

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. The optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep the state where the timing deviation amount is small.

Embodiment 7 FIG.
The main part of the drive circuit for the power semiconductor device according to the seventh embodiment is shown in FIG. Similar to the fifth embodiment, the current change rate is used as a means for detecting a timing shift. However, as in the case of the second embodiment, the current change rate is compared with the drive circuit of another power semiconductor element connected in parallel. FIG. 18 shows a method of correcting the timing shift during the turn-on operation by selecting the optimum circuit by the delay time determination circuit 18 when the switch is turned on first and delaying the next turn-on operation. .

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. The optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep the state where the timing deviation amount is small.

Embodiment 8 FIG.
The main part of the drive circuit for the power semiconductor device according to the eighth embodiment is shown in FIG. Similar to the fifth and sixth embodiments, the current change rate is used as a timing shift detection means, but the timing adjustment circuit corrects the timing shift by switching the gate resistance as shown in FIG. A method of correcting timing deviation by increasing the switching operation speed by reducing the on-gate and off-gate resistance when the turn-on and turn-off operations are delayed compared to the drive circuit of other power semiconductor elements connected in parallel This is shown in FIG. Further, as described in the sixth embodiment, a magnetic field detection unit may be used as the current change rate detection unit.

  According to the above-described configuration, the gate resistance can be selected according to the amount of timing deviation from the drive circuit of another power semiconductor element connected in parallel in each of the turn-on operation and the turn-off operation. Since the latch circuits 10 and 17 are provided, it is possible to keep a state in which the amount of timing deviation is small. Furthermore, since the delay time determination circuits 11 and 18 and the drive pulse shaping circuit 1 in the first and second embodiments are not necessary, the circuit configuration can be simplified.

Embodiment 9 FIG.
The main part of the drive circuit for the power semiconductor device according to the ninth embodiment is shown in FIG. As in the seventh embodiment, the current change rate is used as a means for detecting the timing deviation, and the timing deviation is corrected by changing the gate resistance, but the turn-on timing is corrected for other power connected in parallel. FIG. 20 shows a method of correcting the timing deviation by slowing the turn-on operation speed by increasing the on-gate resistance at the next turn-on operation when it is first turned on compared to the driving circuit of the semiconductor element. It is. Further, as described in the sixth embodiment, a magnetic field detection unit may be used as the current change rate detection unit.

  According to the above-described configuration, the gate resistance can be selected according to the amount of timing deviation from the drive circuit of the other power semiconductor elements connected in parallel in each of the turn-on operation and the turn-off operation. Since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Furthermore, since the delay time determination circuits 11 and 18 and the drive pulse shaping circuit 1 in the first and second embodiments are not necessary, the circuit configuration can be simplified.

Embodiment 10 FIG.
In the first to ninth embodiments, a current sensor is used as means for detecting a switching timing shift. However, the power semiconductor element drive circuit of the tenth embodiment shown in FIG. 21 detects a switching timing shift. A gate voltage is used as the means. The power semiconductor element drive circuit according to the first embodiment shown in FIG. 1 is different from the current sensor detection circuit in that the current sensor is not used as a detection means and a gate voltage detection period setting circuit (gate voltage detection period). The only difference is that the setting means) 50 is used, and the other operations are the same.

  FIG. 22 and FIG. 23 show the relationship between the collector current and the gate voltage in the power semiconductor element drive circuit of the tenth embodiment. FIG. 22 shows the relationship between the collector current flowing through the power semiconductor element 26 and the gate voltage when the switching timing is aligned. Usually, there is a period (mirror period) in which the gate voltage is constant in each of the turn-on operation and the turn-off operation. In the turn-on operation, the gate current charges the input capacitance between the gate and the emitter of the IGBT, and when the gate voltage reaches the threshold value, the IGBT is turned on and the collector current increases. When the collector current reaches the same current value as the inductive load current, the collector voltage decreases and the feedback capacitance between the gate and the collector is discharged. Since most of the output current supplied from the gate drive circuit is the discharge current of the feedback capacitor, the gate voltage is a constant voltage.

  Normally, during the turn-on operation, the recovery current flows through a diode connected in parallel to the power semiconductor element on the opposite arm side in the off state, so that the collector current has a maximum value in the turn-on transient state. At this time, the gate voltage also has a maximum value. On the other hand, during the turn-off operation, the gate voltage is below the threshold value due to the discharge of the input capacitance between the gate and the emitter, but the collector voltage rises, so the feedback capacitance between the gate and the collector needs to be charged. It becomes. Since the collector current does not decrease unless the collector voltage reaches the power supply voltage, the gate voltage is constant at the threshold voltage of the collector current immediately before the turn-off operation. The output current of the drive circuit during this mirror period becomes the charging current of the feedback capacitor. In this way, there is a period in which the gate voltage has a constant value called a mirror period during the turn-on operation and the turn-off operation.

  FIG. 23 is a diagram showing the relationship between the collector current and the gate voltage of the power semiconductor element that operates with the switching timing of the turn-on operation and the turn-off operation delayed from those of other power semiconductor elements connected in parallel. For power semiconductor devices with delayed turn-on timing, the maximum value of the collector current associated with the recovery of the diode is no longer observed. Therefore, the peak value of the gate voltage is detected and held at two timings during the turn-on operation. It is possible to determine the presence or absence of deviation. When the turn-off timing is delayed, the collector current that has been flowing through other power semiconductor elements connected in parallel is shared, current concentration occurs in the transient state of the turn-off operation, and the collector current has a maximum value. It will be. At this time, since the gate voltage also has a maximum value, the peak value of the gate voltage may be detected and held at two timings during the turn-off operation to determine whether or not there is a shift in the turn-off timing.

  As described above, the switching timing can be corrected by applying the gate voltage as the detecting means as the means for detecting the deviation of the switching timing between the plurality of power semiconductor elements connected in parallel. The driving circuit for the power semiconductor element shown in FIG. 21 differs from the first embodiment only in that it uses a gate voltage detection period setting circuit 50 instead of the timing deviation detection means and the current detection period setting circuit 29. As for the operation, when the turn-on timing and turn-off timing of other power semiconductor elements connected in parallel are delayed as in the first embodiment, the next turn-on timing and turn-off timing are determined using the delay time determination circuits 11 and 18. It is to be advanced.

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. An optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Furthermore, since a current sensor is not necessary, a small-sized power conversion device can be configured at low cost.

Embodiment 11 FIG.
FIG. 24 shows the main part of the drive circuit for the power semiconductor device according to the eleventh embodiment. In the tenth embodiment, the delay time determination circuits 11 and 18 are used to correct the deviation of the turn-on and turn-off timing. However, as in the third embodiment, a plurality of on-gate resistors and off-gate resistors are connected in parallel. By reducing the on-gate resistance and the off-gate resistance according to the outputs of the latch circuits 10 and 17, the turn-on timing of the power semiconductor element that is turned on or turned off later than other power semiconductor elements connected in parallel can be obtained. The turn-off timing can be advanced.

  According to the above-described configuration, the gate resistance can be selected according to the amount of timing deviation from the drive circuit of the other power semiconductor elements connected in parallel in each of the turn-on operation and the turn-off operation. Since the latch circuits 10 and 17 are provided, it is possible to keep a state where the amount of timing deviation is small. Furthermore, since the delay time determination circuits 11 and 18 and the drive pulse shaping circuit 1 in the first and second embodiments are not necessary, the circuit configuration can be simplified.

Embodiment 12 FIG.
FIG. 25 shows the main part of the drive circuit for the power semiconductor device according to the twelfth embodiment. In the description up to the eleventh embodiment, the example in which the timing correction is performed accurately by providing a plurality of comparators in the timing correction necessity determination circuit has been described. However, if there is only one comparator, the correction for timing deviation is performed. Since only one step can be set, a plurality of comparators are provided to set a plurality of correction steps. In order to perform timing correction with high accuracy in this way, comparators are provided as many as the number of correction stages.

  In the power semiconductor element drive circuit according to the twelfth embodiment, the timing shift detection circuits 2 and 4 each have one comparator, and instead, the timing shift adjustment circuits 3 and 5 output signals from the comparators, respectively. There is a feature in that counters (counting means) 46 and 47 for counting are provided. In the drive circuit shown in FIG. 25, the current sensor 28 is used as means for detecting the deviation of the switching timing, and the output signals from the counters 46 and 47 are respectively input to the delay time determination circuits 11 and 18, and finally, The drive pulse shaping means 1 corrects the switching timing deviation.

  FIG. 26 shows the relationship between the output signals of the comparators 7 and 14 and the output signals of the counters 46 and 47 in the power semiconductor element drive circuit according to the twelfth embodiment. Here, it is assumed that the counters 46 and 47 operate as a falling detection circuit. The output signals of the comparators 7 and 14 are connected to the CK terminals of the counters 46 and 47, and the output signals of the comparators 7 and 14 input to the CK terminals of the counters 46 and 47 change from the Hi signal to the Lo signal. The state of the output terminal Q1 of the counters 46 and 47 changes. Similarly, when the Q1 signal changes from the Hi signal to the Lo signal, the state of the counter output terminal Q2 changes, and when the Q2 signal changes from the Hi signal to the Lo signal, the state of the counter output terminal Q3 changes.

  Since the control terminals A, B, and C of the delay time determination circuits 11 and 18 are connected to the output terminals Q1, Q2, and Q3 of the counters 46 and 47, the delay time depends on the output from the comparators 46 and 47. The states of the control terminals A, B and C of the decision circuits 11 and 18 change.

  For example, when the difference in switching timing is extremely small and no signal is output from the comparators 7 and 14, all the terminals Q1, Q2 and Q3 remain outputting Lo signals from the counters 46 and 47. At this time, since the control terminals A, B, and C are all in the Lo state in the delay time determination circuits 11 and 18, the output terminal Y of the delay time determination circuits 11 and 18 is connected to the selection terminal D0. When the Hi signal is output from the comparators 7 and 14 due to the deviation of the switching timing, only the Q1 Hi signal is output from the counters 46 and 47 and the state is maintained, and the Lo is output from the Q2 and Q3 terminals. A signal is output. In this case, only the control terminal A of the delay time determination circuits 11 and 18 becomes Hi, and the control terminal B and the control terminal C are in the Lo state. At this time, the output terminal Y of the delay time determination circuits 11 and 18 is connected to the D1 terminal. Further, even if the timing of the switching timing is large to some extent and the timing is corrected once, in the next switching operation and when the comparators 7 and 14 output the Hi signal, the output terminal Q1 of the counters 46 and 47 is Lo. And the output terminal Q2 becomes Hi. In this case, the output terminal Q3 remains in the Lo state, the control terminals of the delay time determination circuits 11 and 18 are in the Hi state only, the control terminals A and C are in the Lo state, and the delay time is reached. The output terminals Y of the decision circuits 11 and 18 are connected to the selection terminal D2. When there is a third output signal from the comparators 7 and 14, the output terminals of the counters 46 and 47 remain Q in the Hi state, Q2 in the Hi state, and Q3 in the Lo state. At this time, the control terminals A, B, and C of the delay time determination circuits 11 and 18 are in the Hi state and the control terminal C is in the Lo state, and the output terminal Y of the delay time determination circuits 11 and 18 is Connected to the selection terminal D3. In FIG. 25, the output terminals of the delay time determining circuits 11 and 18 only show a total of four terminals D0 to D3. However, since there are three control terminals A, B, and C, the actual output terminals are 8 from D0 to D7. Terminal exists. When the Hi signal is output seven times from the comparator, the output terminal Y of the delay time determining circuit is connected to the D7 terminal. In this case, it is needless to say that each of the delay circuits 12 and 19 needs to have seven circuits.

  As described in the first to eleventh embodiments, the optimum pulse width of the control signal cannot be selected by a single output signal from the comparator, but the output from the comparators 7 and 14 for each switching operation. In response to the signal, the delay time determination circuits 11 and 18 determine the states of the control terminals A, B and C, and can select an appropriate circuit from D0, D1, D2 and D3, and turn on the switching timing shift. It is possible to correct for time and / or turn-off operation.

  In the present embodiment, the number of comparators can be reduced, and the counter itself also serves as a latch circuit, so that a dedicated latch circuit is not necessary. As a result, the number of circuit components is reduced, and a small power semiconductor element drive circuit can be provided at low cost.

As described in the second embodiment, as a method for correcting the turn-on timing, the power semiconductor that has been turned on earlier than the drive circuit of another power semiconductor element in which the n-th turn-on operation is connected in parallel is used. A method of delaying the (n + 1) -th turn-on operation of the element driving circuit may be used.
Embodiment 13 FIG.
FIG. 27 shows the main part of the drive circuit for the power semiconductor device according to the thirteenth embodiment. In the twelfth embodiment, an example in which a current sensor is used as a means for detecting a deviation in switching timing has been described. However, in the power semiconductor element drive circuit according to the thirteenth embodiment, the first circuit is the same as in the fifth embodiment. Instead of the current detection signal holding circuits 6 and 13 and the differential amplifiers 7 and 14 in the timing shift detection circuit 2 and the second timing shift detection circuit 4, current change rate calculation circuits (current change rate calculation means) 42-1 and 42 are used. -2 is used. The timing deviation correction method is the same as in the twelfth embodiment.

  As described in the seventh embodiment, as a method for correcting the turn-on timing, the power semiconductor that has been turned on earlier than the drive circuit of another power semiconductor element to which the n-th turn-on operation is connected in parallel is used. A method of delaying the (n + 1) th turn-on operation of the element driving circuit may be used.

  According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. The optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep the state where the timing deviation amount is small.

Embodiment 14 FIG.
FIG. 28 shows the main part of the drive circuit for the power semiconductor element according to the fourteenth embodiment. The means for detecting the deviation of the switching timing is different from the twelfth and thirteenth embodiments, and the feature is that the magnetic field detecting means 48 such as a search coil or a loop antenna is used as the current change rate detecting means as in the sixth embodiment. There is. In place of the above-described current detection period setting means, a magnetic field detection period setting circuit (magnetic field detection period setting means) 49 for outputting a magnetic field detection period setting signal based on an output signal from the magnetic field detection means 48 using a change in magnetic field. Is used. The timing deviation correction method is the same as in the twelfth and thirteenth embodiments. According to the above-described configuration, the delay time determination circuits 11 and 18 can control the control signal in accordance with the amount of timing deviation from the drive circuit of other power semiconductor elements connected in parallel during the turn-on operation and the turn-off operation. The optimum pulse width can be selected as appropriate, and since the latch circuits 10 and 17 are provided, it is possible to keep the state where the timing deviation amount is small.

Embodiment 15 FIG.
FIG. 29 shows the main part of the drive circuit for the power semiconductor device according to the fifteenth embodiment. The delay time determination circuits 11 and 18 and the drive pulse shaping means 1 are not used, but the feature is that the switching timing deviation is corrected by switching the on-gate resistance and the off-gate resistance. The first timing deviation adjusting circuit 3 includes resistors 34, 35a, 35b, 35c and switches 33a, 33b, 33c. Here, the resistance values of the resistors 35a, 35b, and 35c are set as 35c <35b <35a. The second timing deviation adjusting circuit 5 includes resistors 34, 38a, 38b, 38c and switches 36a, 36b, 36c. Here, the resistance values of the resistors 38a, 38b, and 38c are set to 38c <38b <38a.

  FIG. 30 shows the operations of the counters 46 and 47 when the counters 46 and 47 are used as the fall detection circuit in the power semiconductor element drive circuit according to the present embodiment. When there is an output signal once from the comparators 8 and 15, only the Q1 Hi signal is outputted and held from the counters 46 and 47, and the Lo signal is outputted from the Q2 and Q3 terminals. Thereafter, when there is a second output signal from the comparators 8 and 15, the Lo signal is output from Q1 and Q3, and the Hi signal is output from Q2. When there is a third output signal from the comparators 8 and 15, the Lo signal is output from Q1 and Q2, and the Hi signal is output from Q3. FIG. 30 shows an example in which the output signals from the comparators 8 and 15 are three times, and only three output terminals Q1, Q2 and Q3 are shown for the counters 46 and 47. Originally, the number of output terminals depends on the counters 46 and 47, and the number of output terminals is not limited to three. The operation of timing correction for the turn-off operation using such counters 46 and 47 will be described.

  When there is an output signal from the comparator 8 once in accordance with the deviation of the turn-off timing, the output terminal of the counter 46 is the terminal Q2 and the terminal Q3 both outputs the Lo signal, and only the terminal Q1 outputs and holds the Hi signal. 33a holds the ON state. For this reason, the off-gate resistance is a parallel combined resistance of the resistors 34 and 35a, so that it is smaller than the uncorrected off-gate resistance. When there is an output signal from the comparator 8 again in the next turn-off operation, the Lo signal is output from Q1 and Q3, and the Hi signal is output from Q2, and only the switch 33b is turned on. Therefore, the off-gate resistance becomes a parallel combined resistance of the resistors 34 and 35b, and the off-gate resistance can be further reduced.

  In the next turn-off operation, if there is an output signal from the comparator 8, the Lo signal is output from Q1 and Q2, and the Hi signal is output from Q3, so that only the switch 33c is turned on. Therefore, the off-gate resistance is a combined resistance of the resistors 34 and 35c, and the off-gate resistance can be further reduced. In this way, by counting the number of output signals from the comparator with the counter, the value of the off-gate resistance can be reduced, and correction for the deviation in turn-off timing can be performed. Correction for a shift in turn-on timing can be realized by a similar operation.

  As described in the fourth embodiment, as a method for correcting the turn-on timing, the n-th turn-on operation of the power semiconductor element that has been turned on earlier than the drive circuit of another power semiconductor element that is connected in parallel is used. A method of delaying the (n + 1) th turn-on speed of the driving circuit may be used. In addition to the current sensor 28, the current change rate detecting means 42 and the magnetic field detecting means 48 described in the thirteenth or fourteenth embodiment may be used as means for detecting the switching timing deviation.

Embodiment 16 FIG.
FIG. 31 shows the main part of the drive circuit for the power semiconductor device according to the sixteenth embodiment. As described in the tenth and eleventh embodiments, the gate voltage is used as means for detecting the switching timing shift. As a timing correction method, the timing correction is performed using the counters 46 and 47, the delay circuit selection means, and the drive pulse shaping circuit 1, and the operation thereof is the same as that described in the other embodiments. It is.

Embodiment 17. FIG.
FIG. 32 shows the main part of the drive circuit for the power semiconductor device according to the seventeenth embodiment. As described in the tenth and eleventh embodiments, the gate voltage is used as means for detecting the switching timing deviation. As a timing correction method, the counters 46 and 47 are used, and the timing correction is performed by switching the gate resistance. The operation is the same as that described in the other embodiments.

FIG. 3 is a circuit configuration diagram showing a main part of the drive circuit for the power semiconductor element according to the first embodiment. FIG. 3 is a diagram showing an input / output relationship of a delay time determination circuit in the power semiconductor element drive circuit according to the first embodiment; 3 is a time chart showing the operation of the drive circuit for the power semiconductor element according to the first embodiment. 3 is a time chart showing the operation of the drive circuit for the power semiconductor element according to the first embodiment. FIG. 4 is a diagram illustrating an operation of a logic circuit that is a part of the drive circuit for the power semiconductor element according to the first embodiment. 1 is a power conversion device in which a plurality of power semiconductor element drive circuits according to Embodiment 1 are connected in parallel. 4 is an operation experiment result of the power semiconductor element drive circuit according to the first embodiment. FIG. 5 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a second embodiment. 5 is a time chart showing the operation of the drive circuit for the power semiconductor element according to the second embodiment. FIG. 6 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a third embodiment. 10 is a time chart showing the operation of the drive circuit for the power semiconductor element according to the third embodiment. 10 is a time chart showing the operation of the drive circuit for the power semiconductor element according to the third embodiment. FIG. 6 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a fourth embodiment. 10 is a time chart showing the operation of the drive circuit for the power semiconductor device according to the fourth embodiment. 10 is a time chart showing the operation of the drive circuit for the power semiconductor device according to the fourth embodiment. FIG. 9 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a fifth embodiment. FIG. 10 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a sixth embodiment. FIG. 10 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a seventh embodiment. FIG. 10 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to an eighth embodiment. FIG. 20 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a ninth embodiment. FIG. 22 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a tenth embodiment. It is a figure which shows the relationship between the collector current and gate voltage in the drive circuit of the semiconductor device for electric power which concerns on Embodiment 10. FIG. It is a figure which shows the relationship between the collector current and gate voltage in the drive circuit of the semiconductor device for electric power which concerns on Embodiment 10. FIG. FIG. 22 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to an eleventh embodiment. FIG. 20 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a twelfth embodiment. FIG. 23 is a diagram illustrating a relationship between an output signal of a comparator and an output signal of a counter in the power semiconductor element drive circuit according to the twelfth embodiment. FIG. 38 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a thirteenth embodiment. FIG. 25 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a fourteenth embodiment. FIG. 22 is a circuit configuration diagram showing a main part of a power semiconductor element drive circuit according to a fifteenth embodiment; FIG. 23 is a diagram illustrating a relationship between an output signal of a comparator and an output signal of a counter in the power semiconductor element drive circuit according to the fifteenth embodiment. FIG. 18 is a circuit configuration diagram showing a main part of a drive circuit for a power semiconductor element according to a sixteenth embodiment. FIG. 23 is a circuit configuration diagram showing a main part of a power semiconductor element drive circuit according to a seventeenth embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drive pulse shaping circuit, 2 First timing correction necessity judgment circuit, 3 First timing deviation adjustment circuit, 4 Second timing correction necessity judgment circuit, 5 Second timing deviation adjustment circuit, 6a, 6b Current Detection signal holding circuit, 7 differential amplifier, 8a, 8b, 8c comparator, 9a, 9b, 9c reference voltage, 10a, 10b, 10c latch circuit, 11 delay time determining circuit, 12a, 12b, 12c delay circuit, 13a, 13b current detection signal holding circuit, 14 differential amplifier, 15a, 15b, 15c comparator, 16a, 16b, 16c reference voltage, 17a, 17b, 17c latch circuit, 18 delay time determination circuit, 19a, 19b, 19c delay circuit, 20 drive command generation circuit, 21 AND circuit, 22 OR circuit, 23, 24 EXOR circuit, 25 gate resistance 26 power semiconductor element, 27 freewheeling diode, 28 current sensor, 29 current detection period setting circuit, 30, 31, 32 AND circuit, 33a, 33b, 33c switch, 34, 35a, 35b, 35c resistor, 36a, 36b, 36c Switch, 37 gate resistance, 38a, 38b, 38c resistance, 39, 40 semiconductor switch, 41a, 41b, 41c NOT circuit, 42-1, 42-2 current change rate detection means, 43a, 43b, 43c AND circuit, 44 delay Circuit, 45 gate amplifier, 46, 47 counter, 48 magnetic field detection means, 49 magnetic field detection period setting circuit (magnetic field detection period setting means) 50 gate voltage detection period setting circuit (gate voltage detection period setting means).

Claims (12)

A drive circuit for a power semiconductor device comprising a gate terminal, an emitter terminal and a collector terminal,
Current detecting means for detecting a current flowing through the power semiconductor element;
Drive command generating means for outputting a drive command to the gate terminal;
Current detection period setting means for outputting a current detection period setting signal based on an output signal from the drive command generation means;
Timing correction necessity determination means for determining whether or not to correct the timing of turn-off or turn-on operation based on a plurality of output signals from the current detection means fetched at different timings by the current detection period setting signal;
Latch means for holding the output of the timing correction necessity determination means;
Delay time determining means for determining a correction amount of the timing of turn-off or turn-on operation based on the signal held by the latch means;
Delay time generating means for outputting a signal generated based on the delay time selected by the delay time determining means to the gate terminal;
A drive circuit for a power semiconductor element, comprising: A drive circuit for a power semiconductor device comprising a gate terminal, an emitter terminal and a collector terminal,
Drive command generating means for outputting a drive command to the gate terminal;
Gate voltage detection period setting means for outputting a gate voltage detection period setting signal based on an output signal from the drive command generation means;
Timing correction necessity determination means for determining whether or not to correct the timing of turn-off or turn-on operation based on a plurality of gate voltages from the gate terminal captured at different timings according to the gate voltage detection period setting signal;
Latch means for holding the output of the timing correction necessity determination means;
Delay time determining means for determining a correction amount of the timing of turn-off or turn-on operation based on the signal held by the latch means;
A drive circuit for a power semiconductor element, comprising: 3. The power semiconductor device according to claim 1, wherein the timing correction necessity determination unit, the latch unit, and the delay time determination unit are provided separately for turn-off and turn-on operations, respectively. Driving circuit. The timing correction necessity determination means compares the calculation result with a predetermined value, and a difference calculation means for calculating a difference between signals from the current detection means fetched at two different timings at the time of turn-off or turn-on operation command. 4. A drive circuit for a power semiconductor device according to claim 1, further comprising a comparison unit. The timing correction necessity determination means compares the calculation result with a predetermined value, a difference calculation means for calculating a difference between signals from the gate voltage detection means fetched at two different timings at the time of turn-off or turn-on operation command The power semiconductor element drive circuit according to claim 2, further comprising: a comparison unit configured to perform the comparison. A logical operation is performed based on each output signal from the delay time determining means provided for the turn-off and turn-on operation timings and a drive command signal from the drive command generating means via the delay means, and the logical operation result is 6. The drive circuit for a power semiconductor device according to claim 3, further comprising drive pulse shaping means for outputting to the gate terminal. The comparison means provided for the turn-on operation performs an AND operation using the comparator and the output signal of each comparator as one input and the output signal from the current detection period setting means as the other input. 4. A drive circuit for a power semiconductor device according to claim 3, further comprising: an AND circuit that outputs a calculation result to the latch means. 4. The drive circuit for a power semiconductor device according to claim 1, wherein the comparison means is composed of a single comparator, and the latch means is composed of a counter. 4. The electric power according to claim 1, wherein the delay time determining means is configured by gate resistance determining means for determining an optimum gate resistance in accordance with an output signal of the latch means. Semiconductor device drive circuit. The timing correction necessity determination unit includes a current change rate detection unit that detects a current change rate based on an output signal from the current detection unit, and a comparator that compares the current change rate with a predetermined value. 4. The drive circuit for a power semiconductor device according to claim 1, wherein the drive circuit is a power semiconductor device drive circuit. Magnetic field detection means for detecting a magnetic field generated by a current flowing through the power semiconductor element and outputting a magnetic field detection period setting signal based on an output signal from the magnetic field detection means instead of the current detection period setting means 2. The power semiconductor element driving circuit according to claim 1, wherein period setting means is used. 12. A power converter comprising a plurality of power semiconductor elements driven by the power semiconductor element drive circuit according to claim 1 connected in parallel.

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