JP5108433B2 - Wiring board for electronic component inspection equipment - Google Patents

Description

  The present invention relates to, for example, a wiring board used in an electronic component inspection apparatus such as a probe card, and more particularly to an electronic component inspection apparatus capable of accurately inspecting electrical characteristics of each electronic component formed on a large diameter Si wafer or the like. The present invention relates to a wiring board to be used.

A probe card, which is a kind of electronic component inspection device, has a large number of fine probes on its surface, and by bringing such probes into contact with electrodes for each electronic component such as a semiconductor chip formed on a Si wafer. It is used to inspect the electrical characteristics of electronic parts.
By the way, the Si wafer tends to increase in diameter to 300 mm or more. Accordingly, due to the difference in thermal expansion coefficient between the Si wafer and the probe card, the electrical connection between the electrode and the probe becomes insufficient in some electronic components. There is a risk that the physical characteristics cannot be accurately inspected.

For this reason, for example, a measurement wiring substrate having a plurality of insulating substrates and a wiring layer disposed between them, and a plurality of measurement terminals (probes) provided on each of a plurality of pads formed on the surface thereof An average thermal expansion coefficient of the wiring board at −40 to + 400 ° C. is 2 × 10 ⁻⁵ / ° C. to 5 × 10 ⁻⁶ / ° C., and the elongation of the wiring board and the semiconductor wafer is increased in the temperature range. A probe card having a difference of 0.02% or less has been proposed (see, for example, Patent Document 1).
JP 2006-284541 A (pages 1 to 13 and FIGS. 1 to 4)

The wiring board for measurement used in the probe card of Patent Document 1 includes at least one kind of ZnO, CaO, SrO, BaO, and ZrO _{2 in} the insulating substrate, the content is 15% by mass or less, and the cordier A sintered body containing a light crystal phase is used. However, since the wiring layer formed between these insulating substrates is affected by the firing shrinkage due to the firing shrinkage that occurs when firing on such an insulating substrate, a high-density and fine-pitch wiring is formed. It becomes difficult.
As a result, a large number of signals detected from the electronic component to be inspected cannot be accurately processed via the plurality of measurement terminals, and there is a concern that the inspection accuracy and the inspection efficiency are lowered.

  The present invention solves the problems described in the background art, and is used in an electronic component inspection apparatus such as a probe card. For example, even an electronic component formed on a large diameter Si wafer or the like is electrically It is an object to provide a wiring board for an electronic component inspection apparatus capable of accurately and efficiently inspecting characteristics.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the present invention is conceived by forming a build-up layer including a plurality of resin insulation layers and wiring layers on both surfaces of a core substrate made of a ceramic material having a low coefficient of thermal expansion. It has been done.
That is, the wiring board for an electronic component inspection apparatus according to the present invention (Claim 1) is a single layer and a ceramic layer having a thermal expansion coefficient of 3.0 to 4.5 × 10 ⁻⁶ / ° C. at −40 to + 150 ° C., And a core substrate having a plurality of through conductors penetrating between the front surface and the back surface of the ceramic layer, a plurality of resin insulation layers formed above the front surface and the back surface of the core substrate, and a wiring formed therebetween seen including a front and back side buildup layer comprising a layer, a ceramic layer of the core substrate is made of machinable Bull ceramic, and the machinable Bull ceramics, a mixture of SiO ₂ and Al ₂ O _3, or The ceramic layer forming the core substrate is a mixture of AlN and BN, and is thicker than the resin insulating layer .

According to this, the single-layer ceramic layer forming the core substrate having a plurality of through conductors has a thermal expansion coefficient of about 3 × 10 ⁻⁶ at −40 to + 150 ° C. of a Si wafer having a large number of electronic components. Approx. For this reason, a plurality of probes attached to the surface of the buildup layer formed on the surface side of the core substrate and electrodes for each of a large number of electronic components formed on the Si wafer even when subjected to a thermal change in the above temperature range It is easy to ensure the electrical connection with. Furthermore , since the wiring layer formed between the resin insulation layers of the front surface side buildup layer and the rear surface side buildup layer is wired with a high density and a fine pitch, a large number of signals detected from each probe are detected. In addition, it is possible to output from the back side pad of the back side buildup layer to an external circuit board or the like while performing an accurate electrical process. Therefore, even if a large number of electronic parts are formed on a Si wafer having a large diameter of 300 mm or more, the electrical characteristics can be inspected accurately and efficiently.
Moreover, the ceramic layer of the core substrate is made of a machinable ceramic, and the machinable ceramic is a mixture of SiO ₂ and Al ₂ O ₃ or a mixture of AlN and BN. A machinable ceramic having a thermal expansion coefficient in the temperature range of about 4.5 × 10 ⁻⁶ / ° C., AlN of about 4.3 × 10 ⁻⁶ / ° C., or mullite of about 4.2 × 10 ⁻⁶ / ° C. It is formed by the ceramic layer which consists of . For this reason, since the thermal expansion coefficient of the Si wafer having a thermal expansion coefficient in the temperature range of about 3.0 × 10 ⁻⁶ / ° C. is approximately similar, many electronic components formed on the Si wafer can be inspected. It becomes possible to carry out accurately and reliably .
In addition, since the thickness of the ceramic layer forming the core substrate is thicker than the thickness of the resin insulating layer, the thermal expansion coefficient of the entire inspection apparatus wiring board can be approximated to the thermal expansion coefficient of the Si wafer, It is also possible to easily maintain the strength and shape of the entire inspection apparatus wiring board .

Note that the through conductor formed in the core substrate includes a via conductor formed so that the entire through hole penetrating between the front surface and the back surface of the core substrate has a substantially cylindrical shape, or the through hole. The shape of the through-hole conductor formed in a generally cylindrical shape along the inner wall is filled with resin, metal, or the like.
Further, the ceramic layer of the core substrate is pre-fired with a green sheet made of the material described below, and then a through hole is formed by drilling, a conductive paste is filled in the through hole, and the paste is cured. Therefore, a plurality of through conductors are formed with high positional accuracy. Alternatively, a plurality of green sheets can be formed in the same manner by forming through-holes and filling the inside with a conductive paste, followed by lamination and firing.

Note that the pre-Symbol machinable Bull ceramic, machining, especially cutting points to ceramic easily Hodokoseru, for example, mica utilizing significant cleavage of crystals contained in the ceramic material a ceramic, or selective destruction of the grain boundary Also included are aluminum titanate ceramics using

In a further, the present invention, the resin insulating layer forming the back and front sides built-up layer is made of a heat-resistant resin, the electronic component inspection apparatus for circuit board (claim 2) is also included. According to this, even if the heat necessary for attaching the probe (probing) is applied to each of the plurality of front surface side pads formed on the surface of the front surface side buildup layer, the front surface side buildup layer and the rear surface side build are applied. It can prevent or suppress damage to the up layer.
An example of the heat-resistant resin is polyimide (PI).

Further, in the present invention, the front surface side and the back surface side built-up layer include a via conductor connecting the wiring layers located between the plurality of resin insulation layers, and the front surface side and the back surface side of the front surface side build-up layer. formed on the back surface of the built-up layer, and having a plurality of surface side or the back side pad electrically connected to the wiring layer and via conductors, electronic component testing apparatus for printed circuit board (claim 3) are also included.
According to this, a fine pitch wiring layer is formed in a predetermined pattern between a plurality of resin insulation layers made of polyimide or the like, and between these and between the front side or back side pads via via conductors. It is possible to conduct. Therefore, since electrical processing such as voltage amplification and waveform rectification can be reliably and efficiently performed on signals detected from a large number of electronic components on the Si wafer, accurate and efficient inspection can be performed.
In addition, the form which is a part of wiring formed in the surface of a surface side built-up layer is also contained in the said surface side pad. The build-up layer is manufactured by a semitractive method, an additive method, a semi-additive method, or the like.

In addition, the present invention includes an electronic component inspection device wiring board (Claim 4 ) in which probes are respectively attached to the plurality of front surface side pads formed on the surface of the front surface side built-up layer.
According to this, since the probe is attached to each front surface side pad of the front surface side built-up layer, for example, it is possible to perform reliable electrical connection with the electrode for each of a large number of electronic components formed on the Si wafer. In addition, reliable inspection is possible.

In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a schematic view showing a cross section of a wiring board for an electronic component inspection apparatus (hereinafter simply referred to as a wiring board for inspection apparatus) 1 according to an embodiment of the present invention and a usage state thereof.
As shown in FIG. 1, the inspection apparatus wiring board 1 includes a single-layer ceramic layer S having a front surface 3 and a back surface 4, and a plurality of through conductors penetrating between the front surface 3 and the back surface 4 of the ceramic layer S. 5 and a plurality of resin insulation layers j1 to j3 and j4 to j6 formed between the core substrate 2 and the front surface 3 and the back surface 4 of the core substrate 2, and wiring layers 11, 12, 14 and 15, and front and back side build-up layers BU 1 and BU 2. The thicknesses of the resin insulation layers j1 to j3 and j4 to j6 are about 20 to 30% of the thickness of the wiring board 1 for the inspection apparatus, respectively, and the ceramic layer S is about 40 to 40% in total thickness. It accounts for 60%.

Ceramic layer S of the core substrate 2, machinable Brucella mission click a thickness of about 4~5mm or Rannahli, thermal expansion coefficient of -40 to + 0.99 ° C. (hereinafter, simply referred to as CTE) is 3.0 to 4.5 × 10 ⁻⁶ / ° C. Incidentally, the upper Symbol machinable Bull ceramic, a mixture of SiO ₂ and _Al 2 _{O 3,} or consist of a mixture of AlN and BN, these CTE is about 4.5 × ^{10 -6} / ℃.
As shown in FIG. 1, the ceramic layer S of the core substrate 2 is formed with a plurality of through holes h penetrating between the front surface 3 and the back surface 4, and substantially cylindrical along the inner wall surface of the through hole h. A through conductor 5 having a shape is formed, and a filling resin 7 is filled inside. Wiring layers 8 and 9 for sealing the filling resin 7 are formed on the front surface 3 and the back surface 4 of each through conductor 5. The through conductor 5 and the wiring layers 8 and 9 are made of Ag or Cu, or an alloy based on any of these.

Further, as shown in FIG. 1, the surface side buildup layer BU1 includes resin insulating layers j1 to j3 made of a heat resistant resin such as polyimide (hereinafter simply referred to as PI), and a predetermined pattern between them. And the plurality of front surface side pads 13 formed on the surface 12 of the buildup layer BU1 formed by the uppermost resin insulation layer j3. The wiring layers 10, 11, the surface-side pad 13, and the wiring layer 8 can be electrically connected via a substantially inverted conical via conductor V or a smaller via conductor v. The surface-side pad 13 may be a part of the wiring formed on the surface 12 of the surface-side buildup layer BU1.
Further, as shown in FIG. 1, the back-side buildup layer BU2 is also composed of resin insulation layers j4 to j6 made of heat-resistant resin such as PI, and wiring layers 14, 15 formed in a predetermined pattern therebetween. And a plurality of back surface side pads 17 exposed from the bottom surface of the opening k provided in the lowermost resin insulating layer j6 and exposed from the wiring layer 15 to the back surface 16 side of the buildup layer BU2. The wiring layers 14 and 15 and the wiring layer 9 can be electrically connected via a substantially conical via conductor V.

The wiring layers 10, 11, 14, 15 and the via conductors V and v including the front and back pads 13 and 19 are made of Cu or Ag, or an alloy based on any of these. The back-side pad 17 is electrically connected to an external circuit board (not shown) and the like, and is used for input of a power supply current and output of a test signal.
As shown in FIG. 1, a plurality of surface-side pads 13 located on the surface 12 of the surface-side buildup layer BU1 have electrodes for a large number of electronic components (not shown) formed on the Si wafer 20 to be inspected. Probes 19 that come into contact with and can be electrically connected to d are attached individually.

FIG. 2 is a schematic view showing a cross section of a wiring board 1a for an inspection apparatus, which is a modified form of the wiring board 1, and a usage state thereof.
As shown in FIG. 2, the wiring board 1a for an inspection apparatus also includes a core substrate 2a having the same ceramic layer S and a front side and back side buildup having the same resin insulating layers j1 to j3 and j4 to j6. Layers BU1 and BU2.
The present wiring board 1a is different from the wiring board 1 in that the entire wiring board 1a has a substantially cylindrical through conductor 6 in each of a plurality of through holes h that penetrate the ceramic layer S of the core board 2a. . The core substrate S is obtained by laminating a plurality of green sheets and firing them into a single layer, as indicated by a one-dot chain line in FIG.

According to the inspection apparatus wiring boards 1 and 1a as described above, the single ceramic layer S forming the core board 2 and 2a having the plurality of through conductors 5 and 6 is formed of Si having a large number of electronic components. The thermal expansion coefficient of the wafer 20 at −40 to + 150 ° C. is approximately 3 × 10 ⁻⁶ / ° C. For this reason, even when subjected to a thermal change in the above temperature range, a plurality of probes 19 attached to the surface 12 side of the buildup layer BU1 formed on the surface 3 of the core substrate 2 and the Si wafer 20 are formed. It is easy to ensure electrical connection with the electrode d for each of a large number of electronic components.

Furthermore, since the wiring layers 10, 11, 14, and 15 formed between the resin insulating layers j1 to j6 of the front surface side and back surface side buildup layers BU1 and BU2 are wired with high density and fin pitch, A large number of signals detected from each probe 19 can be output from the back surface side pads 17 of the back surface side buildup layers BU2 and BU4 to an external circuit board or the like while performing accurate electrical processing.
In addition, according to the wiring boards 1 and 1a, the thickness of the core boards 2 and 2a occupies about 40 to 60% of the total thickness of the wiring boards 1 and 1a. Since j1 to j6 are made of a heat-resistant resin such as PI, it is possible to reliably withstand probing when the probe 19 is attached. Therefore, even if electronic parts are formed in large numbers on a Si wafer having a large diameter of 300 mm or more, their electrical characteristics can be inspected accurately and efficiently.

The inspection apparatus wiring board 1 was manufactured as follows.
In advance, a ceramic slurry is prepared by mixing a required amount of a machinable ceramic (a mixture of SiO ₂ and Al ₂ O ₃ or a mixture of AlN and BN ), a resin binder, a solvent, and the like. A green sheet having a thickness of about 5 mm was formed from the ceramic slurry by a doctor blade method.
Next, the green sheet is fired at a predetermined temperature, and as shown in the schematic cross-sectional view of FIG. 3, it has a front surface 3 and a back surface 4, a thickness of about 5 mm, and a CTE at −40 to + 150 ° C. A ceramic layer S of 3.0 to 4.5 × 10 ⁻⁶ / ° C. was obtained.

Next, the ceramic layer S was drilled with a small-diameter drill to form a plurality of through holes h penetrating between the front surface 3 and the back surface 4 as shown in FIG.
Further, electroless Ag plating and electrolytic Ag plating, or electroless Cu plating and electrolytic Cu plating are applied to the vicinity of each through hole h of the ceramic layer S, and ring pieces 5a are formed at both ends as shown in FIG. A plurality of through conductors 5 having a substantially cylindrical shape and a hollow portion along the axial direction are formed.
Next, as shown in FIG. 6, for example, a filling resin 7 made of an epoxy resin or the like is printed and filled in each hollow portion of each through conductor 5.
Next, the front surface 3 and the back surface 4 of the ceramic layer S are polished with a grindstone or a belt sander, and as shown in FIG. Formed every h.

In addition, after the conductive paste containing Ag powder or Cu powder is directly printed and filled in the through hole h to form the through conductor 6, the same polishing may be performed.
Further, as shown in FIG. 8, a conductive paste containing Ag powder or Cu powder is screen-printed for each position where both end faces of each through conductor 5 are exposed on the front and back surfaces 3 and 4 of the ceramic layer S. Then, the wiring layers 8 and 9 were formed.
The through conductor 5, the wiring layers 8 and 9, and the filling resin 7 were heated (cured) at a predetermined temperature (about 200 ° C.) to be cured.
As a result, as shown in FIG. 8, the core substrate 2 shown in FIG. 1 was obtained.

On the other hand, in order to obtain the build-up layers BU1 and BU2, as shown in FIG. 9, photosensitive resin insulating layers j1 and j4 made of PI film having a copper foil c attached to the outer surface were prepared. The same applies to the resin insulating layers j2, j3, j5, and j6.
Next, a predetermined number of positions in the copper foil c and the resin insulating layers j1 and j4 were irradiated with laser from the copper foil c side to form a plurality of substantially frustoconical via holes H as shown in FIG.
Further, each via hole H is individually filled with a conductive paste containing Ag powder or Cu powder using a squeegee (not shown). As shown in FIG. A substantially frustoconical packing body g was formed. In this state, the resin insulating layers j1 and j4 including the filler g were heated to cure the filler g.

Next, after a predetermined pattern of plating resist (not shown) is formed on the cured filler g and copper foil c, the uncovered portion is removed by contact with an etching solution. The plating resist was stripped with a stripping solution.
As a result, a substantially frustoconical via conductor V was formed in each via hole H as shown in FIG. At the same time, wiring layers 10 and 14 having a predetermined pattern connected to any via conductor V were formed on the surfaces of the resin insulating layers j1 and j4.
The resin insulating layers j2, j3, and j5 were subjected to the same process as described above to form the via conductor V, the wiring layers 11 and 15, and the back surface side pad 13. Further, the resin insulating layer j6 was drilled at a predetermined position.

Further, the resin insulation layers j1 to j3 are laminated and pressure-bonded to form a surface side buildup layer BU1 as shown in the upper part of FIG. 13, and the resin insulation layers j4 to j6 are laminated and pressure-bonded. As shown in the lower part of FIG. 13, the back side buildup layer BU2 was formed. At this time, the back side pad 17 exposed on the back side 16 was formed on the back side buildup layer BU2.
Next, as shown by the arrows in FIG. 13, the buildup layer BU1 is laminated on the front surface 3 of the core substrate 2, and the buildup layer BU2 is laminated and pressure-bonded on the back surface 4 (lower in the drawing) of the core substrate 2. . At this time, the wiring layers 8 and 9 of the core substrate 2 and the via conductors V adjacent to the front and back side buildup layers BU1 and BU2 were connected.
As a result, the inspection apparatus wiring substrate 1 shown in FIG. 1 in which the built-up layers BU1 and BU2 were laminated on both surfaces of the core substrate 2 could be obtained.
And the principal part of the electronic component inspection apparatus was able to be formed by attaching the probe 19 on each pad 13 of the built-up layer BU1.
Furthermore, an electronic circuit inspection device such as a probe card can be formed by connecting an external circuit board (not shown) to each pad 17 of the back side built-up layer BU2.

According to the manufacturing method of the inspection apparatus wiring board 1 as described above, the single ceramic layer S forming the core substrate 2 is pre-fired after the low thermal expansion coefficient green sheet is fired, A plurality of through holes h are formed with high positional accuracy, and a through conductor 5 in the form of a via conductor or a through hole conductor is formed for each through hole h. Since the build-up layers BU1 and BU2 having the wiring layers 10, 11, 14, and 15 are formed above the front surface 3 and the back surface 4 of the low thermal expansion core substrate 2, each pad 13 on the front surface 12 side is made highly accurate. Can be formed. Therefore, the wiring board 1 for an inspection apparatus that can secure the electrical connection between the probe 19 attached to each pad 13 and the electrode d for each electronic component formed on the Si wafer 20 with the least influence of temperature change. Can be reliably manufactured.
In addition, the signals detected from the probes 19 are transmitted to the back surface 16 via the wiring layers 10, 11, 14, 15 in the buildup layers BU 1, BU 2, the via conductors v, V, the through conductor 5 of the core substrate 2, and the like. It is possible to reliably provide the inspection apparatus wiring board 1 that can output from the side pad 19 to an external circuit board or the like.

14 and 15 are schematic cross-sectional views showing a process for manufacturing the core substrate 2a.
As shown in FIG. 14, a plurality of green sheets s1 to s3 are formed by the same material and method as described above, a plurality of through holes h are formed in these, and then a conductive paste 6a containing Ag powder or Cu powder is formed. Each through hole h was filled individually using a squeegee (not shown).
Next, the green sheets s1 to s3 are laminated and pressure-bonded and then fired to obtain the core substrate 2a shown in FIG. In addition, the position where each of the through holes h is to be formed is set in consideration of the shrinkage amount at the time of firing.
Then, the same steps as described above are performed above the front surface 3 and the back surface 4 of the core substrate 2a to form the front surface side and the back surface side buildup layers BU1 and BU2, so that the inspection apparatus shown in FIG. It is also possible to obtain the wiring board 1a.

The present invention is not limited to the above embodiments.
For example, instead of the pad 13 positioned on the surface 12 of the build-up layer BU1, the surface-side pad is exposed to the surface 12 side from the opening provided in the uppermost resin insulating layer j3. It is good also as a thing made into a part of.
The resin insulation layers j1 to j6 are not limited to the PI, and may be any resin having heat resistance that can withstand probing.
Further, the back side buildup layer BU2 can be formed with a cavity opened on the back side 16 side, and various electronic components can be mounted in the cavity.

Schematic which shows the cross section etc. of the wiring board for test | inspection apparatuses of this invention. Schematic which shows the wiring board for inspection apparatuses of the deformation | transformation form of the said wiring board. Schematic which shows one manufacturing process for obtaining the wiring board for test | inspection apparatuses of FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows the manufacturing process following FIG. Schematic which shows one manufacturing process for obtaining the wiring board for test | inspection apparatuses of FIG. Schematic which shows the manufacturing process following FIG.

Explanation of symbols

1, 1a …………………… Wiring board for inspection equipment 2, 2a ………………… Core board 3, 12 ………………… Front surface 4, 16 ………………… Back surface 5 , 6 …………………… Penetration conductor 10,11,14,15… Wiring layer 13,17 ……………… Pad 19 ……………………… Probe 20 ……………… ……… Si wafer (electronic parts)
S ………………………… Ceramic layer BU1, BU2 ………… Build-up layer j1 to j6 ……………… Resin insulation layer v, V …………………… Via conductor

Claims (4)

A ceramic layer having a single layer and a thermal expansion coefficient of 3.0 to 4.5 × 10 ⁻⁶ / ° C. at −40 to + 150 ° C., and a plurality of through conductors penetrating between the front surface and the back surface of the ceramic layer A core substrate having,
It is formed above the front and back surfaces of the core substrate, viewed including the back and front sides built-up layer, the including a plurality of resin insulation layers and wiring layers formed between them,
The ceramic layer of the core substrate is made of a machinable ceramic, and the machinable ceramic is a mixture of SiO ₂ and Al ₂ O ₃ or a mixture of AlN and BN .
The thickness of the ceramic layer forming the core substrate is thicker than the thickness of the resin insulation layer .
A wiring board for an electronic component inspection apparatus. The resin insulation layer forming the front surface side and the back surface side built-up layer is made of a heat resistant resin.
The wiring board for an electronic component inspection apparatus according to claim 1. The front-side and back-side built-up layers are formed on via conductors connecting the wiring layers located between the plurality of resin insulation layers, and on the front-side and back-side built-up layers. And having a plurality of front-side or back-side pads that are electrically connected to the wiring layer and the via conductor.
The wiring board for an electronic component inspection apparatus according to claim 1 or 2 . A probe is attached to each of the plurality of surface side pads formed on the surface of the surface side built-up layer,
The wiring board for an electronic component inspection apparatus according to any one of claims 1 to 3.

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