JP5105827B2 - Waveform data generator, waveform generator, and semiconductor test equipment - Google Patents

Description

  The present invention relates to a waveform generator used for semiconductor measurement and related equipment, and more particularly to a waveform data generator for generating a waveform combining straight lines, a waveform generator, and a semiconductor test apparatus using the waveform generator.

  In recent years, in the development of flash memory, a complex linear waveform signal combining a plurality of straight lines, which is different from a conventional analog waveform, such as a multi-step step waveform shown in FIG. It has come to be needed.

  On the other hand, for example, as shown in FIG. 1 of Non-Patent Document 1 in semiconductor reliability testing, the need for complex linear waveform signals different from conventional simple pulse waveforms is increasing in other fields as well. it is conceivable that.

  When trying to generate such a complicated linear waveform with a conventional measuring instrument, the following difficulties are involved. For example, since a pulse generator (hereinafter referred to as PG) can only support a threshold value up to three values, there is a technique for generating a complex linear waveform signal by superimposing a plurality of pulse signals using a large number of PGs. It becomes necessary and the apparatus becomes large and the control becomes complicated, so that it cannot be realized at low cost.

  In addition, in an arbitrary waveform generator (Arbitrary Waveform Generator, hereinafter referred to as AWG) generally mounted on an IC tester, as shown in FIG. In this example, 24 points of information are required to be stored as a pattern of discrete digital data at the sample rate. As can be seen from this, a large memory capacity is required. For this reason, the data transfer time of the pattern from the host computer becomes long, the apparatus itself becomes large and cannot be provided at low cost. An example of such an AWG is described in Patent Document 2.

  On the other hand, in Patent Document 3 and Patent Document 4, as shown in FIG. 8B of this specification, a waveform generator of a method of storing an operation or a position in a memory with attention paid to each vertex of the waveform is disclosed. However, it has not spread to general waveform generators.

U.S. Patent Application Publication No. 2002/0118574 FIG. Japanese Patent Laid-Open No. 1-218201 FIG. 3 US Pat. No. 3,662,160 FIGS. 1-3 U.S. Pat. No. 4,222,108 FIGS. 1-3 Denais, M., 7 others, “On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's”, International Electron Device Meeting (IEDM), IEEE , 2004, 109-112

  In the function generator shown in Patent Document 3, only one ramp waveform can be designated as a block mode for designating waveform repetition. For example, in the case where the waveform of FIG. 8B in this specification is repeated a plurality of times, a plurality of linear data for one cycle must be repeatedly expanded and described. Seems to be scarce.

  In the waveform generator shown in Patent Document 4, first, in order to generate the sweep voltage between the apexes by changing the clock rate, a variable clock generator and a high-speed device corresponding to the variable clock generator are required. The cost of the device cannot be reduced. Next, instructions to be executed and necessary data are stored in the memory, for example, setting of an initial value of amplitude, setting of a comparison value of amplitude, setting of a clock frequency for generating a ramp waveform, and ramp Since it must be described and stored one by one, such as a waveform generation instruction, it is considered that programming is not easy and memory efficiency is somewhat inferior because it includes instructions. Further, since the instruction interpreting part is included, the waveform generator itself is considered to be expensive.

  In view of the above-mentioned problems, the problem to be solved by the present invention is to repeatedly generate a waveform combining a plurality of straight lines, or repeatedly generate a plurality of patterns of waveforms combining a plurality of these straight lines, and store them in a memory. It is to provide a technique related to a waveform generator that is efficient and low in apparatus cost.

  Furthermore, another problem to be solved by the present invention is to provide a technique related to a waveform generator that generates a waveform combining a plurality of straight lines, which is inexpensive but operates at high speed.

  Still another problem to be solved by the present invention is to provide a technique related to a waveform generator that stores waveform data obtained by combining a plurality of generated straight lines as data of straight line segments.

  Yet another problem to be solved by the present invention is that a high-accuracy waveform generator that operates at a low cost but operates at a fixed point that handles the slope of each straight line in a combined waveform of a plurality of generated lines. Is to provide the technology.

  In order to achieve the above object, the waveform data generator according to the present invention is a sequence data which repeats a plurality of times a waveform parameter of a plurality of straight line segments and a waveform of one cycle connecting some of the plurality of straight line segments. And a digital-analog converter data that repeats the waveform of one cycle a plurality of times, and performs calculation based on each of the waveform parameters relating to the plurality of line segments according to the sequence data from the memory. A data generator. The waveform data generator includes an aspect in which the memory and the data generator are provided on an FPGA.

  Another waveform data generator according to the present invention includes a waveform memory that stores waveform parameters of a plurality of straight line segments, and sequence data that repeats a waveform of one period connecting a plurality of straight line segments a plurality of times. A sequence memory that stores data, a sequencer that reads out the sequence data from the sequence memory, and accesses the waveform memory to repeat the waveform of one cycle a plurality of times based on the sequence data, and receives from the sequencer and the waveform memory And a line segment data generator for generating data for a digital-analog converter that performs a calculation for generating a line segment waveform based on the series of waveform parameters and repeats the waveform of one cycle a plurality of times.

  Further, the waveform data generator includes, in the waveform memory, an inclination of each of the plurality of straight line segments, an offset value of a start point of each of the plurality of straight line segments, and the plurality of straight line lines. An aspect storing the time for defining the length of each minute, the inclination of each of the line segments of the plurality of straight lines, an aspect expressed in a fixed point, and the inclination of each of the line segments of the plurality of straight lines And the line segment data generator calculates the product of the slope and the time parameter by performing a fixed-point operation. Further, there is a mode in which the number of significant digits after the decimal point is selected by a selector whose control input is a parameter for designating the number of significant digits after the decimal point corresponding to the inclination. Further, the waveform data generator may include an increment or decrement for each of the plurality of straight line segments and an offset value of a start point of each of the plurality of straight line segments in the waveform memory. And a mode for storing a time for defining the length of each of the plurality of straight line segments, and an increase or decrease for each of the plurality of straight line segments is expressed in a fixed point. In the aspect in which the parameter that specifies the number of significant digits after the decimal point of the slope is stored in the waveform memory in accordance with the increment or decrement of each of the plurality of straight line segments, and the line segment data generator, An aspect of performing an operation of adding the increment or decrement for each clock, the waveform memory, the sequence memory, the sequencer, and the line segment data generator are provided on the FPGA. Including embodiments wherein.

  Furthermore, a waveform generator according to the present invention includes any one of the waveform data generators described above and a digital-analog converter connected to the output of the waveform data generator to generate an electrical signal.

  Furthermore, a semiconductor test apparatus according to the present invention comprises the waveform signal generator including the waveform generator described above, an amplifier connected to the output of the waveform generator, a waveform processor, and a storage device. A controller for controlling the generator. According to another aspect of the present invention, there is provided a flash memory test semiconductor test apparatus including flash memory test data in the storage device.

  As described above, according to the present invention, it is possible to repeatedly generate a waveform combining a plurality of straight lines or a plurality of patterns of a waveform combining the plurality of straight lines, and to store in a memory efficiently and to reduce the apparatus cost. Inexpensive waveform generators and related devices can be provided.

  In addition, by using the present invention, it is possible to provide a waveform generator that generates a waveform that combines a plurality of straight lines and that operates at high speed while being inexpensive, and a related device.

  Furthermore, by using the present invention, a low-cost, high-accuracy waveform generator and related devices that handle the slope of each straight line in a combined waveform of a plurality of generated lines with a fixed point. Can be provided.

  With reference to FIG. 13, a waveform generator 2100 which is a basic embodiment of a waveform generator according to the present invention will be described.

  The waveform generator 2100 includes a waveform data generator 2102 for generating digital data of a waveform obtained by connecting a plurality of straight line segments, and a digital-analog converter (converting the digital data of the waveform into an analog signal) DAC) 2104.

  The waveform data generator 2102 includes a sequencer 2110, a waveform memory 2126, a sequence memory 2118, and a line segment data generator 2130. The waveform memory 2126 includes a waveform parameter table 2128 in which information such as parameters for defining or expressing each line segment necessary for generating waveform data is stored for each line segment. Here, the waveform parameter that defines the straight line segment does not store the coordinate information of a plurality of points forming the line segment, but represents the line segment by a mathematical expression (such as a linear function or a class expression). It points to each parameter.

  The sequence memory 2118 uses one or a plurality of pieces of information of a plurality of line segments stored in the waveform memory 2126 to form a waveform for any one period (this is referred to as one sequence in this specification). A sequence table 2119 is provided that stores information on how many times the waveform is repeated and then what sequence of waveforms is to be repeated next (this is referred to as sequence data in this specification).

  A line segment data generator 2130 generates and generates digital data of points on a specified line segment at each time from various parameters of a given line segment and a clock signal input (not shown). The data is output to the DAC 2104.

  The sequencer 2110 accesses the sequence memory 2118 via the buses 2131 and 2132, obtains the reference address of the waveform data of the line segment in the sequence waveform to be generated from the information stored in the sequence table, The waveform memory 2126 is accessed via the bus 2134 based on the above, and the corresponding waveform parameter is output from the waveform memory 2126 to the line segment data generator 2130 via the bus 2138. The sequencer 2110 further includes a t counter 2124, and manages, transfers, or controls the time in the line segment data generator 2130 via the bus 2140 based on information obtained from the waveform memory 2126 via the bus 2136. . The sequencer 2110 further includes a loop counter 2114 that manages the number of repetitions of the sequence being generated therein, and a cycle counter 2116 that manages whether the line segment data generator 2130 has generated one cycle of data. The line data generator 2130 is controlled via 2140.

  With the above configuration, the waveform generator 2100 according to the basic embodiment of the present invention includes the line segment parameter information stored in the waveform memory 2126 and the sequence memory 2118 in the waveform data generator 2102. Based on the information about each sequence, the line segment data generator 2130 generates line segment data for each time, thereby outputting digital data to the DAC 2104. The DAC 2104 converts the received digital data into an analog signal according to a clock signal (not shown). It operates to convert to and output.

  Here, since the information stored in the waveform memory 2126 is line segment parameter information, it is possible to save the memory capacity, and the sequence memory 2118 uses a sequence such as line segment information and the number of repetitions used in one sequence. Since the information is stored, it is possible to flexibly and easily generate a repetition of a plurality of sequences while saving the memory capacity.

  Next, a first example based on the basic embodiment of the waveform generator according to the present invention will be described with reference to FIGS.

  First, a method for storing waveform data in a memory according to this embodiment will be described with reference to FIG.

  The waveform shown in FIG. 3 is a waveform obtained by repeating the same waveform as that shown in FIGS. 8A and 8B four times. Here, with respect to the first period, points A to J are shown at the start and end points of each period and at each vertex. In the present invention, one period of this waveform is divided into a plurality of straight line segments, that is, a straight line AB, a straight line BC, a straight line CD, a straight line DE, a straight line EF, a straight line FG, and a straight line G. Divide into nine line segments, -H, straight line HI, and straight line I-J. Next, for each line segment, a linear function with respect to time t expressed by the following equation (1):

  f (t) = a * t + b (1)

As parameters, the slope a, the offset value b at the start point of this line segment, and the time value t that defines the length of time from the start point to the end point of the line segment, respectively, p_a, p_b, p_t is calculated and stored in the waveform memory (126 in FIG. 1).

  Specifically, as illustrated in FIG. 4, in the waveform parameter table (128 in FIG. 1) in the waveform memory 126, for each WPADD indicating the entry label of each line segment data, the decimal part of the parameter p_a described later is displayed. Parameter bit_sel indicating the number of significant digits, parameter p_a indicating the slope, parameter p_b indicating the offset value at the start point of this line segment, time value p_t for defining the length of the line segment, and whether this time value p_t is the shortest clock cycle It is stored as an indicator IsMin indicating whether or not. Here, the parameter bit_sel takes a value of 0 or 1, and IsMin takes a value of TRUE or FALSE. Each parameter is in fixed-point notation.

  Referring to FIG. 4, the waveform parameter data of each line segment for one period in FIG. 3 is the data of the entry label ADDR_A indicating the data of the line segment AB, the parameter bit_sel value is sel_1, and the parameter p_a is 0. 0, the parameter p_b is 0.5, the parameter p_t is t_A, IsMin is stored as FALSE, and the data of the entry label ADDR_B for the following line segment B-C includes the value of the parameter bit_sel of sel_0, the parameter p_a of 1. 0, parameter p_b is 0.5, parameter p_t is t_B, and IsMin is FALSE. In this manner, the data of nine entries from the line segment AB to the line segment IJ are stored in the waveform parameter table 128 of the waveform memory 126.

  Next, with reference to FIG. 5, the storage method in the memory of the present invention will be described by taking as an example the case of repeating one cycle of FIG. 3 four times. Such repetition information is stored in a sequence table (119 in FIG. 1) provided in the sequence memory (118 in FIG. 1). In this specification, one sequence refers to a series of line segments for one period of the waveform, and in the waveform of FIG. 3, the first one period from line segment AB to line segment I-J is the 1 sequence. It corresponds to a sequence. In the sequence table 119, one sequence of data is stored for each SPADDR that is the entry label of each sequence. That is, when the output of this sequence is switched to the next sequence, base indicating the address of the waveform parameter table of the output line segment, start indicating the address of the waveform parameter table of the first line segment of this sequence, An end indicating the address of the waveform parameter table of the last line segment, period_len indicating the clock period of this one sequence, and loop_num indicating the number of repetitions of this sequence are stored.

  Referring to FIG. 5, the waveform of FIG. 3 shows that in the data of the first sequence entry label SPADDR1, ADDR_A indicating line segment AB as the base address and ADDR_A indicating line segment AB as the start address are end ADDR_I indicating the line segment I-J is stored as an address, a value LEN1 is stored as period_len, and 4 is stored as loop_num. When 0 is stored in loop_num, a continuous output mode is entered, and waveform output is continued until a stop command is received.

  Since the waveform of FIG. 3 can be described by data for one sequence, only one sequence is illustrated in FIG. 5, but data of a plurality of sequences can be described in the sequence table.

  Next, the waveform generator 100 of the present invention for generating the linear waveform of FIG. 3 from the data of FIGS. 4 and 5 will be described with reference to FIG.

  The waveform generator 100 includes a waveform data generator 102 and a digital-analog converter (DAC) 104. The waveform data generator 102 and the DAC 104 operate by being supplied with clock signals (not shown).

  The waveform data generator 102 includes a sequencer 110 that controls sequence repetition, a sequence memory 118 that stores sequence information, and an address generator that generates an address for generating a waveform and a time parameter t based on the sequence information within the sequencer 110. Line data generation for generating data dac_data to be provided to the DAC 104 from the waveform parameter from the waveform controller 126 and the waveform memory 126 that outputs waveform parameters based on information from the sequencer 110 and the time parameter t from the sequencer 110 A device 130 is provided and operates under the control of a controller (not shown).

More specifically, the sequencer 110 includes a state machine 122 , a loop counter 114 that stores the number of repetitions of the sequence, a period counter 116 that counts the clock period for one sequence, and an address generator 120. The sequencer 110 accesses the sequence memory 118 that stores the sequence table 119, and starts waveform data from the waveform specified by the start address to the waveform specified by the end address in the order of the sequence in which the entry label exists in the SPADDR. The addresses are output in order to the address generator 120 and are repeated as many times as specified in loop_num.

  At the time of switching each sequence, a predetermined delay time occurs due to the loading of the next sequence, and during that time, the waveform specified by the base address is output. It is also possible to provide a function to specify the additional delay time so that this delay time becomes equal to period_len and continue the output of the waveform specified by the base address, thereby keeping the output signal at a predetermined period.

  The address generator 120 in the sequencer 110 includes a state machine 122 and a t counter 124 that counts the time t for the line segment. The address generator 120 accesses the waveform parameter table 128 stored in the waveform memory 126 according to the start address wptbl_addr of the waveform data received from the sequencer 110, reads the parameter p_t and the shortest clock period indicator IsMin, and updates them for each clock. The time t is output to the line segment data generator 130. Here, when the waveform parameter p_t is 1, which is the shortest clock period, the indicator IsMin allows the address generator 120 to receive the waveform data start address, access the waveform memory 126, and read the parameter p_t into the t counter 124. This is provided in order to keep up with a delay time in circuit operation. First, when the value of the indicator IsMin is TRUE, the address generator 120 operates the t counter 124 assuming that the parameter p_t is 1, and when the indicator IsMin is FALSE, the address generator 120 reads the parameter p_t and sets the t counter 124. Make it work.

  Thus, by providing the shortest clock period indicator IsMin, the waveform data generator 102 can be realized at low cost.

  The line segment data generator 130 receives from the waveform memory 126 the parameters p_a, p_b, and bit_sel of the waveform data designated by the address generator 120 in the sequencer 110, and from the address generator 120 during the line segment at each clock. The time value t is received, and the calculation of the above-described equation (1) is performed therefrom. As a result, the DAC conversion code dac_data is output to the DAC 104 at a timing according to a clock signal (not shown). The DAC 104 generates a signal dac_out according to dac_data at a timing according to a clock signal (not shown).

  As described above, according to the waveform generator 100 of the present invention, signals forming a given line segment can be sequentially output at a timing according to a predetermined clock signal. That is, the line B-C in FIG. 3 will be described. First, the signal of the voltage at the point B is output from the DAC 104, and the slope p_a of the line B-C and the time increased by one clock at the next clock. The output of the voltage signal indicating the sum of the product of the parameter t indicating the value and the offset value p_b at the start point of the line segment BC from the DAC 104 is repeated. Generate a waveform signal.

  Next, the operation of the line segment data generator 130 will be described in more detail with reference to FIG.

  The waveform parameter p_a is given to the terminal 202 and inputted to the multiplier 214 via the flip-flop (FF) 212. A parameter t indicating a time value in the line segment is given to the terminal 204, input to the multiplier 214 via the FF 230, multiplied by the waveform parameter p_a, and output to the selector 218 via the FF 216. On the other hand, the parameter bit_sel for selecting the number of digits of the decimal part is given to the terminal 206, and is output to the control terminal of the selector 218 via the FFs 232 to 236 having the same number of stages as the delay time of the FF 216. The selector 218 selects a bit according to the control input from the FF 236 with respect to the output from the FF 216 and outputs the selected bit to the FF 220.

  Here, the waveform parameter p_a, which is the inclination of each line segment, is expressed as a 32-bit signed fixed-point numerical value. However, p_a takes a wide range of values, and depending on the numerical value, sufficient resolution cannot be ensured. Therefore, two types of digits for the integer part and the decimal part are prepared, and the type is indicated by the parameter bit_sel. As an example, when p_a is 1 or more, p_a is represented by a code 1 bit, an integer part 14 bits, and a decimal part 17 bits. Otherwise, p_a is represented by a code 1 bit, an integer part 0 bits, and a decimal part 31 bits. The The selector 218 appropriately selects the bit width of the decimal part for the multiplication result based on the information of bit_sel. Note that since the multiplier 214 performs fixed-point arithmetic, the arithmetic can be performed at high speed and the circuit scale can be reduced.

  The multiplication result once stored in the FF 220 is rounded off by the fraction adjustment circuit 222, and the decimal part of the DAC conversion code calculated by the multiplier is rounded off and output to the adder 226 via the FF 224.

  On the other hand, the waveform parameter p_b is given to the terminal 208 and added to the previous multiplication result of p_a and t in the adder 226 via the FFs 238 to 242 having the same number of stages as the delay time from the FF 212 to the FF 224. The result of the adder 226 is output to the DOUT terminal 210 via the FF 228. The operation of the line segment data generator 130 described above operates according to the clock signal.

  Next, a linear waveform pattern as shown in FIG. 6 will be considered. The waveform shown in FIG. 6 is a waveform pattern in which the staircase waveform X is repeated p times, then a plurality of ramp waveforms Y having various peak values and slopes are repeated q times, and a waveform Z including a plurality of staircase waveforms is repeated r times. is there. With the above configuration, the linear waveform pattern as shown in FIG. 6 can be easily described in the waveform memory and the sequence memory. Thus, it will be easily understood that the waveform generator according to the present invention can flexibly cope with complicated linear waveform patterns required in recent semiconductor measurements.

  Returning to FIG. 1, the waveform data generator 102 of the waveform generator 100 according to the present invention, that is, the sequencer 110, the sequence memory 118, the waveform memory 126, and the line segment data generator 130 are configured as described above. Can be implemented on an FPGA (Field Programmable Gate Array). As an FPGA, for example, a Virtex (registered trademark) series manufactured by Xilinx (registered trademark) having an operating frequency of about 100 MHz can be used. By mounting these on the FPGA, for example, the multiplier 214 and the adder 226 can use general-purpose cells of the FPGA, and a high-speed waveform generator can be configured at a low device cost. Further, since the memory capacity required for the linear waveform pattern can be extremely reduced by the waveform storing method in the memory employed in the present invention, it is mounted on a chip having no large-scale memory such as an FPGA. Note also that it has become possible. In addition to the FPGA, it is also possible to mount with a gate array, ASIC, custom LSI, or glue logic.

  FIG. 7 shows a result of comparing the merits and demerits in hardware and control between the waveform data generator 102 according to the present invention and the corresponding part of the conventional AWG, with respect to the waveforms in FIG. As is apparent from this, the present invention achieves a moderate degree of waveform freedom with much less memory and the number of FPGA gates than AWG, and additional hardware such as a memory module and a memory power supply than before. Not only is software unnecessary, but it can save a lot of data transfer time from the host computer in terms of control.

  Furthermore, the waveform parameter p_a indicating the slope is expressed in a fixed-point notation, and the parameter bit_sel for selecting the number of digits of the decimal part is provided, thereby simplifying the circuit and increasing the calculation speed as well as sufficient resolution. It is also possible to secure a waveform and generate a highly accurate waveform.

  Next, a second example based on the basic embodiment of the waveform generator according to the present invention will be described with reference to FIGS.

  In the second embodiment, each line segment is expressed by the following mathematical expression (2).

f (t) = b (when t = 0) and f (t) = f (t−1) + delta (where 1 ≦ t ≦ Te) (2)

Here, t is a positive integer. Te is the value of t at the end point of this line segment. That is, the increment or decrement delta at each time of the line segment, the offset value b at the start point of the line segment, and the time value t that defines the length of time from the start point to the end point of the line segment, that is, Te, Calculated as delta, p_b, and p_t, and stored in the waveform memory (1126 in FIG. 10).

  Specifically, as illustrated in FIG. 12, in the waveform parameter table (1128 in FIG. 10) in the waveform memory 1126, for each WPADD indicating the entry label of each line segment data, Parameter bit_sel indicating the number of significant digits, parameter delta indicating the slope, parameter p_b indicating the offset value at the start point of this line segment, time value p_t for defining the length of the line segment, and whether this time value p_t is the shortest clock cycle It is stored as an indicator IsMin indicating whether or not. Here, the parameter bit_sel takes a value of 0 or 1, and IsMin takes a value of TRUE or FALSE. Each parameter is in fixed-point notation.

  Referring to FIG. 12, the waveform parameter data of each line segment for one period in FIG. 3 is the data of the entry label ADDR_A indicating the data of the line segment AB, the parameter bit_sel value is sel_1, and the parameter delta is 0. 0.0, parameter p_b is 0.5, parameter p_t is t_A, IsMin is stored as FALSE, and the data of the entry label ADDR_B for the subsequent line segment B-C includes a parameter bit_sel value of sel_1, a parameter delta of 0. 5, parameter p_b is stored as 0.5, parameter p_t is stored as t_B, and IsMin is stored as FALSE. As described above, the data of nine entries from the line segment AB to the line segment IJ are stored in the waveform parameter table 1128 of the waveform memory 1126.

  The description method of the sequence table for storing the sequence information using the waveform parameter table of FIG. 12 is the same as that of FIG.

  Next, the waveform generator 1100 of the present invention for generating the linear waveform of FIG. 3 from the data of FIGS. 12 and 5 will be described with reference to FIG. Note that the same reference numerals are given to the same components as described above.

  The waveform generator 1100 includes a waveform data generator 1102 and a digital-analog converter (DAC) 104. The waveform data generator 1102 and the DAC 104 operate by being supplied with clock signals (not shown).

  The waveform data generator 1102 includes a sequencer 1110 that controls sequence repetition, a sequence memory 118 that stores sequence information, and an address generator that generates an address for generating a waveform and a time parameter t based on the sequence information in the sequencer 1110. A line for generating data dac_data to be given to the DAC 104 based on the waveform parameter from the waveform memory 1126, the waveform memory 1126 for outputting the waveform parameter based on the information from the device 1120 and the sequencer 1110, and the time control signal load_enable from the sequencer 1110 A minute data generator 1130 is provided and operates under the control of a controller not shown here.

  More specifically, the sequencer 1110 includes a state machine 1112, a loop counter 114 that stores a repeated count number of the sequence, a period counter 116 that counts a clock period for one sequence, and an address generator 1120. The sequencer 1110 accesses the sequence memory 118 that stores the sequence table 119, and starts waveform data from the waveform specified by the start address to the waveform specified by the end address in the order of the sequence in which the entry label exists in the SPADDR. The addresses are output in order to the address generator 1120, which is repeated the number of times specified in loop_num.

  The address generator 1120 in the sequencer 1110 includes a t counter 1124 that counts the time t for the state machine 1122 and the line segment. The address generator 1120 accesses the waveform parameter table 1128 stored in the waveform memory 1126 according to the waveform data start address wptbl_addr received from the sequencer 1110, reads the parameter p_t and the shortest clock period indicator IsMin, and sets the t counter 1124. When the waveform parameter for the new line segment is output, the time control signal load_enable indicating it is output to the line segment data generator 1130. Here, when the waveform parameter p_t is 1, which is the shortest clock period, the indicator IsMin allows the address generator 1120 to receive the waveform data start address, access the waveform memory 1126, and read the parameter p_t into the t counter 1124. This is provided in order to keep up with a delay time in circuit operation. First, when the value of the indicator IsMin is TRUE, the address generator 1120 operates the t counter 1124 on the assumption that the parameter p_t is 1. When the indicator IsMin is FALSE, the address generator 1120 reads the parameter p_t and sets the t counter 1124. Make it work.

  Thus, by providing the shortest clock period indicator IsMin, the waveform data generator 1102 can be realized at low cost.

  The line segment data generator 1130 receives from the waveform memory 1126 the parameters delta, p_b, bit_sel of the waveform data designated by the address generator 1120 in the sequencer 1110, and starts a new line segment from the address generator 1120. The time control signal load_enable to be notified is received, the calculation of the above equation (2) is performed from them, and as a result, the DAC conversion code dac_data is output to the DAC 104 at a timing according to a clock signal (not shown). The DAC 104 generates a signal dac_out according to dac_data at a timing according to a clock signal (not shown).

  As described above, according to the waveform generator 1100 of the present invention, as in the description of the first embodiment, signals that form a given line segment are sequentially output at a timing according to a predetermined clock signal. be able to.

  Next, the operation of the line segment data generator 1130 will be described in more detail with reference to FIG.

  The waveform parameter delta is given to the terminal 1202 and inputted to the selector 1214 via the flip-flop (FF) 1212. On the other hand, the parameter bit_sel for selecting the number of digits of the decimal part is given to the terminal 1204 and outputted to the control terminal of the selector 1214 via the FF 1230. The selector 1214 selects a bit according to the control input from the FF 1230 with respect to the output from the FF 1212, and outputs the selected bit to the accumulator 1218 via the FF 1216.

  Here, the waveform parameter delta, which is an increment or decrement for each clock of each line segment, is expressed as a 32-bit signed fixed-point numerical value. However, since delta takes a wide range of values and a sufficient resolution cannot be ensured depending on the numerical value, two types of digits of the integer part and the decimal part are prepared, and the type is indicated by the parameter bit_sel. As an example, when delta is 1 or more, delta is represented by a code of 1 bit, an integer part of 14 bits, and a decimal part of 17 bits. Otherwise, delta is represented by a code of 1 bit, an integer part of 0 bits, and a decimal part of 31 bits. The The selector 1214 appropriately selects the bit width of the decimal part for delta based on the information of bit_sel. Note that the accumulator 1218 performs fixed-point arithmetic, so that arithmetic can be performed at high speed and the circuit scale can be kept small.

  The waveform parameter p_b is supplied to the terminal 1206 and is supplied to the accumulator 1218 through the number of stages FF1232 to FF1234 that generate a delay time equal to that from the FF1212 to the FF1216.

  The time control signal load_enable is supplied to a terminal 1208, and is supplied as a reset input signal to the accumulator 1218 via the FF 1238 to FF 1240 having the same number of stages as to generate a delay time equal to that of the FF 1216.

  When the time control signal load_enable is asserted, the accumulator clears the value in the accumulator and loads the parameter p_b. When the load_enable is not asserted, the accumulator displays the FF 1216 select operation result every time the clock signal is engraved. It is added to the value of the accumulator 1218.

  The contents of the accumulator 1218 are temporarily stored in the FF 1226 according to the clock signal. The fraction adjustment circuit 1222 rounds off the decimal point of the conversion code for DAC, and outputs it to the DOUT terminal 1210 via the FF 1228.

  Returning to FIG. 10, with the configuration as described above, the waveform data generator 1102 of the waveform generator 1100 according to the present invention, that is, the sequencer 1110, the sequence memory 118, the waveform memory 1126, and the line segment data generator 1130. Can be implemented on an FPGA (Field Programmable Gate Array). By mounting these on the FPGA, a high-speed waveform generator can be configured at a low device cost. Further, since the memory capacity required for the linear waveform pattern can be extremely reduced by the waveform storing method in the memory employed in the present invention, it is mounted on a chip having no large-scale memory such as an FPGA. Note also that it has become possible. In addition to the FPGA, it is also possible to mount with a gate array, ASIC, custom LSI, or glue logic.

  As another embodiment using the waveform generator according to the present invention, FIG. 9 shows a semiconductor test apparatus 900 for measuring a wafer on which a device under test (DUT) using the waveform generator according to the present invention is mounted. The description will be given with reference.

  The semiconductor test apparatus 900 includes a plurality of waveform signal generators 902 to 904 including the above-described waveform generator 100 and an amplifier (Amp) 906 that is provided at the output thereof and provides a signal having a necessary amplitude, and A controller 910 is included that controls the waveform signal generators 902-904 via control lines 916. The controller 910 includes a processing unit or processor 912 and a storage unit or memory 914. The processor 912 is a device having a data processing function, and various microprocessors (CPU, MPU), DSP, control gate array, etc. manufactured by Intel (registered trademark), etc. can be used. It is a memory | storage means which can store the data for control, for example, various storage devices containing rewritable memories, such as RAM and flash memory, or various storage media may be included. The controller 910 can be a computer such as a PC or various control devices.

  In addition to the control program for the waveform signal generators 902 to 904, the storage device 914 stores in advance the data to be loaded into the waveform memory and sequence memory of each waveform data generator 102 in each waveform signal generator. It can also be transferred to each waveform signal generator via the control line 916 before the start of the test. In that case, the storage device 914 stores waveform parameter data and sequence data for semiconductor testing.

  A contact probe 922 such as a probe needle is connected to the output terminal OUTPUT 907 of the waveform signal generator 902, and the semiconductor test apparatus 900 can probe the DUT 928 on the wafer 920, apply a waveform signal, and perform a test. . Here, the wafer 920 and the contact probe 922 preferably include a mode in which alignment is controlled using a wafer prober 926. Note that the output terminals 908 and 909 of the other waveform signal generators 903 and 904 can be similarly connected and tested.

  Further, in FIG. 9, the DUT 928 is a DUT equipped with a flash memory, and the storage device 914 stores waveform parameter data and sequence data of a waveform suitable for the flash memory test described in Patent Document 1, for example. The semiconductor measuring device 900 may be a flash memory test semiconductor test device.

  By providing such a configuration, it is possible to provide a test for applying a complicated linear waveform pattern, which has been difficult in the past, in a semiconductor test at high speed and high accuracy at a low cost. The semiconductor test apparatus 900 can also be used for a wafer test such as a reliability test of an electronic device such as a semiconductor, a pulse IV measurement related to a MOSFET, or the like, or a test of a device other than a wafer.

  Further, although the waveform generator 100 is described as an example in FIG. 9, the waveform generator 1100 can be used instead.

  Although the present invention has been described with respect to the embodiments of the present invention, various modifications and changes can be made based on the idea of the present invention. For example, the waveform memory may be divided into a plurality of parts depending on the data output destination. Also, clock signal distribution means may be added as appropriate. In addition, if you add a table in the sequence memory to register the line segments used in each sequence in addition to the information for the first and last line segments referenced in each sequence, Since the sequence information can be stored even if the parameters are not stored continuously, the waveform memory can be saved. In addition, by making the clock supplied to the waveform data generator faster than the clock supplied to the DAC, it is possible to absorb the delay time required for data loading. In the second embodiment, the offset is not always loaded into the accumulator at the starting point of each line segment, but is loaded only at the beginning of one sequence, and thereafter, only the increment or decrement is added to the accumulator. Can be changed to do just that, and the content stored in memory can be reduced accordingly. In the second embodiment, the t counter may not be provided in the sequencer, and p_t and IsMin may be read into the line segment data generator instead of the sequencer, and the t counter may be mounted there.

It is a block diagram of the waveform generator of 1st Example by this invention. It is a block diagram explaining the line segment data generator 130 of FIG. It is the figure which showed the example of the waveform produced | generated by this invention. It is a figure explaining the outline | summary of the waveform parameter table of FIG. It is a figure explaining the outline | summary of the sequence table of FIG. It is the figure which showed another example of the waveform produced | generated by this invention. It is a figure which shows the table | surface which compared the performance of the applicable part of the waveform data generator by this invention, and the conventional AWG. It is a figure explaining the memory storage method of the linear waveform by a prior art. 1 is a block diagram showing a semiconductor test apparatus according to the present invention. It is a block diagram of the waveform generator of 2nd Example by this invention. It is a block diagram explaining the line segment data generator 1130 of FIG. It is a figure explaining the outline | summary of the waveform parameter table of FIG. It is a block diagram which shows basic embodiment of the waveform generator by this invention.

Explanation of symbols

100, 2100 Waveform generator 102, 2102 Waveform data generator 104, 2104 Digital-analog converter 110, 2110 Sequencer 118, 2118 Sequence memory 119, 2119 Sequence table 120 Address generator 126, 2126 Waveform memory 128, 2128 Waveform parameter table 130, 2130 line segment data generator

Claims (15)

Waveform memory that stores waveform parameters for multiple line segments,
A sequence memory storing sequence data in which a waveform of one cycle connecting a plurality of straight line segments is repeated a plurality of times;
A sequencer that reads the sequence data from the sequence memory and accesses the waveform memory so as to repeat the waveform of the one cycle a plurality of times based on the sequence data;
A line segment data generator for generating data for a digital-to-analog converter that performs an operation for generating a line segment waveform based on the waveform parameter received from the sequencer and the waveform memory and repeats the waveform of one cycle a plurality of times; Prepared ,
The waveform memory defines the slope of each of the plurality of straight line segments, the offset value of the start point of each of the plurality of straight line segments, and the length of each of the plurality of straight line segments. Time and is stored,
The inclination of each of the plurality of straight line segments is expressed in a fixed point.
A waveform data generator characterized in that a parameter that specifies the number of significant digits after the decimal point of the slope is stored in the waveform memory in accordance with the slope of each of the plurality of straight line segments . In the line segment data generator, the product of the slope and the time parameter is calculated by performing a fixed-point operation, and the result is obtained by a selector having a parameter that specifies the number of significant digits after the decimal point corresponding to the slope as a control input. 2. The waveform data generator according to claim 1 , wherein the number of significant digits after the decimal point is selected. The waveform memory further stores, for each of the plurality of straight line segments, a shortest clock period indicator that indicates whether a time value that defines the length of the line segment is a shortest clock period. Or the waveform data generator of 2. The line segment data generator, for each of the plurality of straight line segments, when the value of the shortest clock period indicator is a value indicating the shortest clock period, the time value stored in the waveform memory 4. The waveform data generator according to claim 3, wherein the waveform data generator generates the data by assuming that the time for defining the length of the line segment is the shortest clock period without using a line. Waveform memory that stores waveform parameters for multiple line segments,
A sequence memory storing sequence data in which a waveform of one cycle connecting a plurality of straight line segments is repeated a plurality of times;
A sequencer that reads the sequence data from the sequence memory and accesses the waveform memory so as to repeat the waveform of the one cycle a plurality of times based on the sequence data;
A line segment data generator for generating data for a digital-to-analog converter that performs a calculation to generate a line segment waveform based on the waveform parameters received from the sequencer and the waveform memory, and repeats the waveform of one cycle a plurality of times;
With
The waveform memory includes an increment or decrement for each clock of each of the plurality of straight line segments, an offset value of a start point of each of the plurality of straight line segments, and the plurality of straight line segments. storing the time and which rules the length of each of the,
The increment or decrement of each of the plurality of straight line segments is represented by a fixed point,
Waveform data generation characterized in that a parameter that specifies the number of significant digits after the decimal point of the increment or decrement is stored in the waveform memory in accordance with the increment or decrement of each of the plurality of straight line segments vessel. 6. The waveform data generator according to claim 5 , wherein the line segment data generator performs an operation of adding the increment or decrement every clock. The waveform memory further includes, for each of the plurality of straight line segments, a shortest clock period indicator that indicates whether a time value that defines a length of the line segment is a shortest clock period. 6. The waveform data generator according to 6. The line segment data generator, for each of the plurality of straight line segments, when the value of the shortest clock period indicator is a value indicating the shortest clock period, the time value stored in the waveform memory The waveform data generator according to claim 7, wherein the data is generated on the assumption that a time for defining the length of the line segment is a predetermined shortest value without using a line. Said waveform memory, said sequence memory, and said sequencer, said line segment data generator, the waveform data generator according to any one of claims 1, characterized in that provided on the FPGA 8. A waveform data generator according to any one of claims 1 to 8 ,
A waveform generator comprising a digital-analog converter connected to the output of the waveform data generator for generating an electrical signal. A waveform signal generator comprising: the waveform generator of claim 10; and an amplifier connected to the output of the waveform generator;
A semiconductor test apparatus comprising a controller that includes a waveform processor and a storage device and controls the waveform signal generator. 12. The semiconductor test apparatus for flash memory testing according to claim 11 , wherein the memory device is provided with data for flash memory test. A waveform data generator according to claim 9;
A digital-to-analog converter connected to the output of the waveform data generator for generating an electrical signal;
Waveform generator with A waveform signal generator comprising: the waveform generator of claim 13; and an amplifier connected to the output of the waveform generator;
A controller comprising a waveform processor and a storage device for controlling the waveform signal generator;
A semiconductor test apparatus. The flash memory test semiconductor test apparatus according to claim 14, wherein the storage device includes flash memory test data.

Images